sys/net/i4b/layer1/ifpnp/i4b_ifpnp_avm.c

   1 /*
   2  *   Copyright (c) 1999, 2000 Udo Schweigert. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpnp_avm.c: AVM Fritz!Card PnP hardware driver
  34  *      ---------------------------------------------------
  35  *
  36  * $FreeBSD: src/sys/i4b/layer1/ifpnp/i4b_ifpnp_avm.c,v 1.5.2.1 2001/08/10 14:08:37 obrien Exp $
  37  *
  38  *      last edit-date: [Fri Jan 12 17:05:28 2001]
  39  *
  40  *---------------------------------------------------------------------------*/
  41
  42 #include "use_ifpnp.h"
  43 #include "opt_i4b.h"
  44
  45 #if (NIFPNP > 0)
  46
  47 #include <sys/param.h>
  48 #include <sys/kernel.h>
  49 #include <sys/systm.h>
  50 #include <sys/mbuf.h>
  51 #include <sys/bus.h>
  52 #include <sys/rman.h>
  53 #include <sys/socket.h>
  54 #include <sys/thread2.h>
  55
  56 #include <bus/isa/isavar.h>
  57
  58 #include <net/if.h>
  59 #include <net/i4b/include/machine/i4b_debug.h>
  60 #include <net/i4b/include/machine/i4b_ioctl.h>
  61 #include <net/i4b/include/machine/i4b_trace.h>
  62
  63 #include "../../include/i4b_global.h"
  64 #include "../../include/i4b_mbuf.h"
  65
  66 #include "../i4b_l1.h"
  67 #include "../isic/i4b_isic.h"
  68 #include "../isic/i4b_isac.h"
  69 #include "../isic/i4b_hscx.h"
  70
  71 #include "i4b_ifpnp_ext.h"
  72
  73 /* prototypes */
  74 static void avm_pnp_intr(void *);
  75 static void hscx_write_reg(int, u_int, struct l1_softc *, u_int);
  76 static void hscx_write_reg_val(int, u_int, u_int8_t, struct l1_softc *);
  77 static u_int hscx_read_reg(int, u_int, struct l1_softc *);
  78 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  79 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  80 static void avm_pnp_hscx_int_handler(struct l1_softc *);
  81 static void avm_pnp_hscx_intr(int, u_int, u_int, struct l1_softc *);
  82 static void avm_pnp_init_linktab(struct l1_softc *);
  83 static void avm_pnp_bchannel_setup(int, int, int, int);
  84 static void avm_pnp_bchannel_start(int, int);
  85 static void avm_pnp_hscx_init(struct l1_softc *, int, int);
  86 static void avm_pnp_bchannel_stat(int, int, bchan_statistics_t *);
  87 static void avm_pnp_set_linktab(int, int, drvr_link_t *);
  88 static isdn_link_t * avm_pnp_ret_linktab(int, int);
  89 static int avm_pnp_probe(device_t);
  90 static int avm_pnp_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
  91 int avm_pnp_attach(device_t);
  92 static void ifpnp_isac_intr(struct l1_softc *sc);
  93
  94 static device_method_t avm_pnp_methods[] = {
  95         /* Device interface */
  96         DEVMETHOD(device_probe,         avm_pnp_probe),
  97         DEVMETHOD(device_attach,        avm_pnp_attach),
  98         { 0, 0 }
  99 };
 100
 101 static driver_t avm_pnp_driver = {
 102         "ifpnp",
 103         avm_pnp_methods,
 104         sizeof(struct l1_softc)
 105 };
 106
 107 static devclass_t avm_pnp_devclass;
 108
 109 DRIVER_MODULE(avm_pnp, isa, avm_pnp_driver, avm_pnp_devclass, NULL, NULL);
 110
 111 /* jump table for multiplex routines */
 112
 113 struct i4b_l1mux_func avm_pnp_l1mux_func = {
 114         avm_pnp_ret_linktab,
 115         avm_pnp_set_linktab,
 116         ifpnp_mph_command_req,
 117         ifpnp_ph_data_req,
 118         ifpnp_ph_activate_req,
 119 };
 120
 121 struct l1_softc *ifpnp_scp[IFPNP_MAXUNIT];
 122
 123 /*---------------------------------------------------------------------------*
 124  *      AVM PnP Fritz!Card special registers
 125  *---------------------------------------------------------------------------*/
 126
 127 /*
 128  *      register offsets from i/o base
 129  */
 130 #define CLASS_OFFSET            0x00
 131 #define REVISION_OFFSET         0x01
 132 #define STAT0_OFFSET            0x02
 133 #define STAT1_OFFSET            0x03
 134 #define ADDR_REG_OFFSET         0x04
 135 /*#define MODREG_OFFSET         0x06
 136 #define VERREG_OFFSET           0x07*/
 137
 138 /* these 2 are used to select an ISAC register set */
 139 #define ISAC_LO_REG_OFFSET      0x04
 140 #define ISAC_HI_REG_OFFSET      0x06
 141
 142 /* offset higher than this goes to the HI register set */
 143 #define MAX_LO_REG_OFFSET       0x2f
 144
 145 /* mask for the offset */
 146 #define ISAC_REGSET_MASK        0x0f
 147
 148 /* the offset from the base to the ISAC registers */
 149 #define ISAC_REG_OFFSET         0x10
 150
 151 /* the offset from the base to the ISAC FIFO */
 152 #define ISAC_FIFO               0x02
 153
 154 /* not really the HSCX, but sort of */
 155 #define HSCX_FIFO               0x00
 156 #define HSCX_STAT               0x04
 157
 158 /*
 159  *      AVM PnP Status Latch 0 read only bits
 160  */
 161 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active low */
 162 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active low */
 163 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active low */
 164 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 165 /* actually active LOW */
 166 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 167
 168 /*
 169  *      AVM Status Latch 0 write only bits
 170  */
 171 #define ASL_RESET_ALL           0x01  /* reset siemens IC's, active 1 */
 172 #define ASL_TIMERDISABLE        0x02  /* active high */
 173 #define ASL_TIMERRESET          0x04  /* active high */
 174 #define ASL_ENABLE_INT          0x08  /* active high */
 175 #define ASL_TESTBIT             0x10  /* active high */
 176
 177 /*
 178  *      AVM Status Latch 1 write only bits
 179  */
 180 #define ASL1_INTSEL              0x0f  /* active high */
 181 #define ASL1_ENABLE_IOM          0x80  /* active high */
 182
 183 /*
 184  * "HSCX" mode bits
 185  */
 186 #define  HSCX_MODE_ITF_FLG      0x01
 187 #define  HSCX_MODE_TRANS        0x02
 188 #define  HSCX_MODE_CCR_7        0x04
 189 #define  HSCX_MODE_CCR_16       0x08
 190 #define  HSCX_MODE_TESTLOOP     0x80
 191
 192 /*
 193  * "HSCX" status bits
 194  */
 195 #define  HSCX_STAT_RME          0x01
 196 #define  HSCX_STAT_RDO          0x10
 197 #define  HSCX_STAT_CRCVFRRAB    0x0E
 198 #define  HSCX_STAT_CRCVFR       0x06
 199 #define  HSCX_STAT_RML_MASK     0x3f00
 200
 201 /*
 202  * "HSCX" interrupt bits
 203  */
 204 #define  HSCX_INT_XPR           0x80
 205 #define  HSCX_INT_XDU           0x40
 206 #define  HSCX_INT_RPR           0x20
 207 #define  HSCX_INT_MASK          0xE0
 208
 209 /*
 210  * "HSCX" command bits
 211  */
 212 #define  HSCX_CMD_XRS           0x80
 213 #define  HSCX_CMD_XME           0x01
 214 #define  HSCX_CMD_RRS           0x20
 215 #define  HSCX_CMD_XML_MASK      0x3f00
 216
 217 /*
 218  * to prevent deactivating the "HSCX" when both channels are active we
 219  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 220  * flag in avm_pnp_bchannel_setup upon active and cleared upon deactivation.
 221  * It is set high to allow room for new flags.
 222  */
 223 #define HSCX_AVMA1PP_ACTIVE     0x1000
 224
 225 /*---------------------------------------------------------------------------*
 226  *      AVM read fifo routines
 227  *---------------------------------------------------------------------------*/
 228
 229 static void
 230 avm_pnp_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 231 {
 232         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 233         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 234
 235         switch (what) {
 236                 case ISIC_WHAT_ISAC:
 237                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 238                         bus_space_read_multi_1(btag, bhandle,  ISAC_REG_OFFSET, buf, size);
 239                         break;
 240                 case ISIC_WHAT_HSCXA:
 241                         hscx_read_fifo(0, buf, size, sc);
 242                         break;
 243                 case ISIC_WHAT_HSCXB:
 244                         hscx_read_fifo(1, buf, size, sc);
 245                         break;
 246         }
 247 }
 248
 249 static void
 250 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 251 {
 252         u_int8_t *ip;
 253         size_t cnt;
 254         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 255         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 256
 257         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 258         ip = (u_int8_t *)buf;
 259         cnt = 0;
 260         while (cnt++ < len)
 261         {
 262                 *ip++ = bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET);
 263         }
 264 }
 265
 266 /*---------------------------------------------------------------------------*
 267  *      AVM write fifo routines
 268  *---------------------------------------------------------------------------*/
 269 static void
 270 avm_pnp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 271 {
 272         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 273         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 274
 275         switch (what) {
 276                 case ISIC_WHAT_ISAC:
 277                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 278                         bus_space_write_multi_1(btag, bhandle,  ISAC_REG_OFFSET, (u_int8_t*)buf, size);
 279                         break;
 280                 case ISIC_WHAT_HSCXA:
 281                         hscx_write_fifo(0, buf, size, sc);
 282                         break;
 283                 case ISIC_WHAT_HSCXB:
 284                         hscx_write_fifo(1, buf, size, sc);
 285                         break;
 286         }
 287 }
 288
 289 static void
 290 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 291 {
 292         u_int8_t *ip;
 293         size_t cnt;
 294         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 295         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 296         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 297
 298         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 299         sc->avma1pp_txl = 0;
 300
 301         if (Bchan->out_mbuf_cur == NULL)
 302         {
 303           if (Bchan->bprot != BPROT_NONE)
 304                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 305         }
 306         if (len != sc->sc_bfifolen)
 307                 sc->avma1pp_txl = len;
 308
 309         hscx_write_reg(chan, HSCX_STAT, sc, 3);
 310
 311         ip = (u_int8_t *)buf;
 312         cnt = 0;
 313         while (cnt++ < len)
 314         {
 315                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET, *ip++);
 316         }
 317 }
 318
 319 /*---------------------------------------------------------------------------*
 320  *      AVM write register routines
 321  *---------------------------------------------------------------------------*/
 322
 323 static void
 324 avm_pnp_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 325 {
 326         u_char reg_bank;
 327         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 328         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 329
 330         switch (what) {
 331                 case ISIC_WHAT_ISAC:
 332                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 333                         /* set the register bank */
 334                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 335                         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
 336                         break;
 337                 case ISIC_WHAT_HSCXA:
 338                         hscx_write_reg_val(0, offs, data, sc);
 339                         break;
 340                 case ISIC_WHAT_HSCXB:
 341                         hscx_write_reg_val(1, offs, data, sc);
 342                         break;
 343         }
 344 }
 345
 346 static void
 347 hscx_write_reg(int chan, u_int off, struct l1_softc *sc, u_int which)
 348 {
 349         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 350         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 351
 352         /* point at the correct channel */
 353         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 354         if (which & 4)
 355                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off + 2, sc->avma1pp_prot);
 356         if (which & 2)
 357                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off + 1, sc->avma1pp_txl);
 358         if (which & 1)
 359                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off, sc->avma1pp_cmd);
 360 }
 361
 362 static void
 363 hscx_write_reg_val(int chan, u_int off, u_int8_t val, struct l1_softc *sc)
 364 {
 365         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 366         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 367
 368         /* point at the correct channel */
 369         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 370         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off, val);
 371 }
 372
 373 /*---------------------------------------------------------------------------*
 374  *      AVM read register routines
 375  *---------------------------------------------------------------------------*/
 376 static u_int8_t
 377 avm_pnp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 378 {
 379         u_char reg_bank;
 380         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 381         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 382
 383         switch (what) {
 384                 case ISIC_WHAT_ISAC:
 385                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 386                         /* set the register bank */
 387                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 388                         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET +
 389                                 (offs & ISAC_REGSET_MASK)));
 390                 case ISIC_WHAT_HSCXA:
 391                         return hscx_read_reg(0, offs, sc);
 392                 case ISIC_WHAT_HSCXB:
 393                         return hscx_read_reg(1, offs, sc);
 394         }
 395         return 0;
 396 }
 397
 398 static u_int
 399 hscx_read_reg(int chan, u_int off, struct l1_softc *sc)
 400 {
 401         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 402         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 403
 404         /* point at the correct channel */
 405         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 406         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET + off));
 407 }
 408
 409
 410 static struct ifpnp_ids {
 411         u_long vend_id;
 412         char *id_str;
 413 } ifpnp_ids[] = {
 414         { 0x0009cd06,           "AVM Fritz!Card PnP"            },
 415         { 0, 0 }
 416 };
 417
 418 /*---------------------------------------------------------------------------*
 419  *      avm_pnp_probe - probe for a card
 420  *---------------------------------------------------------------------------*/
 421 static int
 422 avm_pnp_probe(device_t dev)
 423 {
 424         struct ifpnp_ids *ids;                  /* pnp id's */
 425         char *string = NULL;                            /* the name */
 426         u_int32_t vend_id = isa_get_vendorid(dev);      /* vendor id */
 427
 428         /* search table of knowd id's */
 429
 430         for(ids = ifpnp_ids; ids->vend_id != 0; ids++)
 431         {
 432                 if(vend_id == ids->vend_id)
 433                 {
 434                         string = ids->id_str;
 435                         break;
 436                 }
 437         }
 438
 439         if(string)              /* set name if we have one */
 440         {
 441                 device_set_desc(dev, string);   /* set description */
 442                 return 0;
 443         }
 444         else
 445         {
 446                 return ENXIO;
 447         }
 448 }
 449
 450 /*---------------------------------------------------------------------------*
 451  *      avm_pnp_attach - attach Fritz!Card PnP
 452  *---------------------------------------------------------------------------*/
 453 int
 454 avm_pnp_attach(device_t dev)
 455 {
 456         struct l1_softc *sc;
 457         u_int v;
 458         int unit, error = 0;
 459         u_int16_t vid;
 460         void *ih = 0;
 461         bus_space_handle_t bhandle;
 462         bus_space_tag_t btag;
 463
 464         crit_enter();
 465
 466         vid = isa_get_vendorid(dev);
 467         sc = device_get_softc(dev);
 468         unit = device_get_unit(dev);
 469         bzero(sc, sizeof(struct l1_softc));
 470
 471         /* probably not really required */
 472         if(unit > IFPNP_MAXUNIT) {
 473                 kprintf("avm_pnp%d: Error, unit > IFPNP_MAXUNIT!\n", unit);
 474                 crit_exit();
 475                 return(ENXIO);
 476         }
 477
 478         ifpnp_scp[unit] = sc;
 479
 480
 481         /* get io_base */
 482         if(!(sc->sc_resources.io_base[0] =
 483                         bus_alloc_resource(dev, SYS_RES_IOPORT,
 484                                                 &sc->sc_resources.io_rid[0],
 485                                                 0UL, ~0UL, 1, RF_ACTIVE ) ))
 486         {
 487                 kprintf("avm_pnp_attach: Couldn't get my io_base.\n");
 488                 return ENXIO;
 489         }
 490         if (sc->sc_resources.io_base[0] == NULL) {
 491                 kprintf("avm_pnp%d: couldn't map IO port\n", unit);
 492                 error = ENXIO;
 493                 goto fail;
 494         }
 495
 496         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 497         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 498
 499         /* will not be used for pnp devices */
 500         sc->sc_port = rman_get_start(sc->sc_resources.io_base[0]);
 501
 502         /* get irq, release io_base if we don't get it */
 503
 504         if(!(sc->sc_resources.irq =
 505                         bus_alloc_resource(dev, SYS_RES_IRQ,
 506                                            &sc->sc_resources.irq_rid,
 507                                            0UL, ~0UL, 1, RF_ACTIVE)))
 508         {
 509                 kprintf("avm_pnp%d: Could not get irq.\n",unit);
 510                 error = ENXIO;
 511                 goto fail;
 512         }
 513
 514         /* not needed */
 515         sc->sc_irq = rman_get_start(sc->sc_resources.irq);
 516         bus_setup_intr(dev, sc->sc_resources.irq, 0,
 517                        (void(*)(void*))avm_pnp_intr, sc,
 518                        &ih, NULL);
 519         sc->sc_unit = unit;
 520
 521         /* end of new-bus stuff */
 522
 523         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 524
 525         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 526         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 527
 528         /* setup access routines */
 529
 530         sc->clearirq = NULL;
 531         sc->readreg = avm_pnp_read_reg;
 532         sc->writereg = avm_pnp_write_reg;
 533
 534         sc->readfifo = avm_pnp_read_fifo;
 535         sc->writefifo = avm_pnp_write_fifo;
 536
 537         /* setup card type */
 538
 539         sc->sc_cardtyp = CARD_TYPEP_AVM_PNP;
 540
 541         /* setup IOM bus type */
 542
 543         sc->sc_bustyp = BUS_TYPE_IOM2;
 544
 545         /* set up some other miscellaneous things */
 546         sc->sc_ipac = 0;
 547         sc->sc_bfifolen = HSCX_FIFO_LEN;
 548
 549         /* reset the card */
 550         /* the Linux driver does this to clear any pending ISAC interrupts */
 551         v = 0;
 552         v = ISAC_READ(I_STAR);
 553         v = ISAC_READ(I_MODE);
 554         v = ISAC_READ(I_ADF2);
 555         v = ISAC_READ(I_ISTA);
 556         if (v & ISAC_ISTA_EXI)
 557         {
 558                  v = ISAC_READ(I_EXIR);
 559         }
 560         v = ISAC_READ(I_CIRR);
 561         ISAC_WRITE(I_MASK, 0xff);
 562         /* the Linux driver does this to clear any pending HSCX interrupts */
 563         v = hscx_read_reg(0, HSCX_STAT, sc);
 564         v = hscx_read_reg(1, HSCX_STAT, sc);
 565
 566         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
 567         DELAY(SEC_DELAY/100); /* 10 ms */
 568         bus_space_write_1(btag, bhandle, STAT1_OFFSET, ASL1_ENABLE_IOM|sc->sc_irq);
 569         DELAY(SEC_DELAY/100); /* 10 ms */
 570         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
 571         DELAY(SEC_DELAY/100); /* 10 ms */
 572
 573          kprintf("ifpnp%d: AVM Fritz!Card PnP Class %#x Revision %d \n", unit,
 574                         bus_space_read_1(btag, bhandle, CLASS_OFFSET),
 575                         bus_space_read_1(btag, bhandle, REVISION_OFFSET));
 576
 577          kprintf("ifpnp%d: ISAC %s (IOM-%c)\n", unit,
 578                 "2085 Version A1/A2 or 2086/2186 Version 1.1",
 579                  sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
 580
 581
 582         /* init the ISAC */
 583         ifpnp_isac_init(sc);
 584
 585         /* init the "HSCX" */
 586         avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 587
 588         avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 589
 590         /* can't use the normal B-Channel stuff */
 591         avm_pnp_init_linktab(sc);
 592
 593         /* set trace level */
 594
 595         sc->sc_trace = TRACE_OFF;
 596
 597         sc->sc_state = ISAC_IDLE;
 598
 599         sc->sc_ibuf = NULL;
 600         sc->sc_ib = NULL;
 601         sc->sc_ilen = 0;
 602
 603         sc->sc_obuf = NULL;
 604         sc->sc_op = NULL;
 605         sc->sc_ol = 0;
 606         sc->sc_freeflag = 0;
 607
 608         sc->sc_obuf2 = NULL;
 609         sc->sc_freeflag2 = 0;
 610
 611         callout_init(&sc->sc_T3_timeout);
 612         callout_init(&sc->sc_T4_timeout);
 613
 614         /* init higher protocol layers */
 615
 616         i4b_l1_mph_status_ind(L0IFPNPUNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avm_pnp_l1mux_func);
 617
 618   fail:
 619         crit_exit();
 620         return(error);
 621 }
 622
 623 /*
 624  * this is the real interrupt routine
 625  */
 626 static void
 627 avm_pnp_hscx_intr(int h_chan, u_int stat, u_int cnt, struct l1_softc *sc)
 628 {
 629         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 630         int activity = -1;
 631
 632         NDBGL1(L1_H_IRQ, "%#x", stat);
 633
 634         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 635         {
 636                 chan->stat_XDU++;
 637                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 638                 /* abort the transmission */
 639                 sc->avma1pp_txl = 0;
 640                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 641                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 642                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 643                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 644
 645                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 646                 {
 647                         i4b_Bfreembuf(chan->out_mbuf_head);
 648                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 649                 }
 650         }
 651
 652         /*
 653          * The following is based on examination of the Linux driver.
 654          *
 655          * The logic here is different than with a "real" HSCX; all kinds
 656          * of information (interrupt/status bits) are in stat.
 657          *              HSCX_INT_RPR indicates a receive interrupt
 658          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 659          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 660          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 661          *                      CRC/framing errors are only reported in this state.
 662          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 663          *                                      CRC/framing error
 664          */
 665
 666         if(stat & HSCX_INT_RPR)
 667         {
 668                 int fifo_data_len;
 669                 int error = 0;
 670                 /* always have to read the FIFO, so use a scratch buffer */
 671                 u_char scrbuf[HSCX_FIFO_LEN];
 672
 673                 if(stat & HSCX_STAT_RDO)
 674                 {
 675                         chan->stat_RDO++;
 676                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 677                         error++;
 678                 }
 679
 680                 /*
 681                  * check whether we're receiving data for an inactive B-channel
 682                  * and discard it. This appears to happen for telephony when
 683                  * both B-channels are active and one is deactivated. Since
 684                  * it is not really possible to deactivate the channel in that
 685                  * case (the ASIC seems to deactivate _both_ channels), the
 686                  * "deactivated" channel keeps receiving data which can lead
 687                  * to exhaustion of mbufs and a kernel panic.
 688                  *
 689                  * This is a hack, but it's the only solution I can think of
 690                  * without having the documentation for the ASIC.
 691                  * GJ - 28 Nov 1999
 692                  */
 693                  if (chan->state == HSCX_IDLE)
 694                  {
 695                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 696                         error++;
 697                  }
 698
 699                 fifo_data_len = cnt;
 700
 701                 if(fifo_data_len == 0)
 702                         fifo_data_len = sc->sc_bfifolen;
 703
 704                 /* ALWAYS read data from HSCX fifo */
 705
 706                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 707                 chan->rxcount += fifo_data_len;
 708
 709                 /* all error conditions checked, now decide and take action */
 710
 711                 if(error == 0)
 712                 {
 713                         if(chan->in_mbuf == NULL)
 714                         {
 715                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 716                                         panic("L1 avm_pnp_hscx_intr: RME, cannot allocate mbuf!\n");
 717                                 chan->in_cbptr = chan->in_mbuf->m_data;
 718                                 chan->in_len = 0;
 719                         }
 720
 721                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 722                         {
 723                                 /* OK to copy the data */
 724                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 725                                 chan->in_cbptr += fifo_data_len;
 726                                 chan->in_len += fifo_data_len;
 727
 728                                 /* setup mbuf data length */
 729
 730                                 chan->in_mbuf->m_len = chan->in_len;
 731                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 732
 733                                 if(sc->sc_trace & TRACE_B_RX)
 734                                 {
 735                                         i4b_trace_hdr_t hdr;
 736                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 737                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 738                                         hdr.dir = FROM_NT;
 739                                         hdr.count = ++sc->sc_trace_bcount;
 740                                         MICROTIME(hdr.time);
 741                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 742                                 }
 743
 744                                 if (stat & HSCX_STAT_RME)
 745                                 {
 746                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 747                                   {
 748                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 749                                          activity = ACT_RX;
 750
 751                                          /* mark buffer ptr as unused */
 752
 753                                          chan->in_mbuf = NULL;
 754                                          chan->in_cbptr = NULL;
 755                                          chan->in_len = 0;
 756                                   }
 757                                   else
 758                                   {
 759                                                 chan->stat_CRC++;
 760                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 761                                           if (chan->in_mbuf != NULL)
 762                                           {
 763                                                   i4b_Bfreembuf(chan->in_mbuf);
 764                                                   chan->in_mbuf = NULL;
 765                                                   chan->in_cbptr = NULL;
 766                                                   chan->in_len = 0;
 767                                           }
 768                                   }
 769                                 }
 770                         } /* END enough space in mbuf */
 771                         else
 772                         {
 773                                  if(chan->bprot == BPROT_NONE)
 774                                  {
 775                                           /* setup mbuf data length */
 776
 777                                           chan->in_mbuf->m_len = chan->in_len;
 778                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 779
 780                                           if(sc->sc_trace & TRACE_B_RX)
 781                                           {
 782                                                         i4b_trace_hdr_t hdr;
 783                                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 784                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 785                                                         hdr.dir = FROM_NT;
 786                                                         hdr.count = ++sc->sc_trace_bcount;
 787                                                         MICROTIME(hdr.time);
 788                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 789                                                 }
 790
 791                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 792                                                  activity = ACT_RX;
 793
 794                                           /* move rx'd data to rx queue */
 795                                           if(!(IF_QFULL(&chan->rx_queue)))
 796                                           {
 797                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 798                                           }
 799                                           else
 800                                           {
 801                                                 i4b_Bfreembuf(chan->in_mbuf);
 802                                           }
 803                                           /* signal upper layer that data are available */
 804                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 805
 806                                           /* alloc new buffer */
 807
 808                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 809                                                  panic("L1 avm_pnp_hscx_intr: RPF, cannot allocate new mbuf!\n");
 810
 811                                           /* setup new data ptr */
 812
 813                                           chan->in_cbptr = chan->in_mbuf->m_data;
 814
 815                                           /* OK to copy the data */
 816                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 817
 818                                           chan->in_cbptr += fifo_data_len;
 819                                           chan->in_len = fifo_data_len;
 820
 821                                           chan->rxcount += fifo_data_len;
 822                                         }
 823                                  else
 824                                         {
 825                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 826                                           chan->in_cbptr = chan->in_mbuf->m_data;
 827                                           chan->in_len = 0;
 828                                         }
 829                           }
 830                 } /* if(error == 0) */
 831                 else
 832                 {
 833                         /* land here for RDO */
 834                         if (chan->in_mbuf != NULL)
 835                         {
 836                                 i4b_Bfreembuf(chan->in_mbuf);
 837                                 chan->in_mbuf = NULL;
 838                                 chan->in_cbptr = NULL;
 839                                 chan->in_len = 0;
 840                         }
 841                         sc->avma1pp_txl = 0;
 842                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 843                         hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 844                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 845                         hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 846                 }
 847         }
 848
 849
 850         /* transmit fifo empty, new data can be written to fifo */
 851
 852         if(stat & HSCX_INT_XPR)
 853         {
 854                 /*
 855                  * for a description what is going on here, please have
 856                  * a look at isic_bchannel_start() in i4b_bchan.c !
 857                  */
 858
 859                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 860
 861                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 862                 {
 863                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 864
 865                         if(chan->out_mbuf_head == NULL)
 866                         {
 867                                 chan->state &= ~HSCX_TX_ACTIVE;
 868                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 869                         }
 870                         else
 871                         {
 872                                 chan->state |= HSCX_TX_ACTIVE;
 873                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 874                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 875                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 876
 877                                 if(sc->sc_trace & TRACE_B_TX)
 878                                 {
 879                                         i4b_trace_hdr_t hdr;
 880                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 881                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 882                                         hdr.dir = FROM_TE;
 883                                         hdr.count = ++sc->sc_trace_bcount;
 884                                         MICROTIME(hdr.time);
 885                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 886                                 }
 887
 888                                 if(chan->bprot == BPROT_NONE)
 889                                 {
 890                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 891                                                 activity = ACT_TX;
 892                                 }
 893                                 else
 894                                 {
 895                                         activity = ACT_TX;
 896                                 }
 897                         }
 898                 }
 899
 900                 avm_pnp_hscx_fifo(chan, sc);
 901         }
 902
 903         /* call timeout handling routine */
 904
 905         if(activity == ACT_RX || activity == ACT_TX)
 906                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 907 }
 908
 909 /*
 910  * this is the main routine which checks each channel and then calls
 911  * the real interrupt routine as appropriate
 912  */
 913 static void
 914 avm_pnp_hscx_int_handler(struct l1_softc *sc)
 915 {
 916         u_char stat = 0;
 917         u_char cnt = 0;
 918
 919         stat = hscx_read_reg(0, HSCX_STAT, sc);
 920         if (stat & HSCX_INT_RPR)
 921           cnt = hscx_read_reg(0, HSCX_STAT+1, sc);
 922         if (stat & HSCX_INT_MASK)
 923           avm_pnp_hscx_intr(0, stat, cnt, sc);
 924
 925         cnt = 0;
 926         stat = hscx_read_reg(1, HSCX_STAT, sc);
 927         if (stat & HSCX_INT_RPR)
 928           cnt = hscx_read_reg(1, HSCX_STAT+1, sc);
 929         if (stat & HSCX_INT_MASK)
 930           avm_pnp_hscx_intr(1, stat, cnt, sc);
 931 }
 932
 933 static void
 934 avm_pnp_intr(void *xsc)
 935 {
 936         u_char stat;
 937         struct l1_softc *sc;
 938         bus_space_handle_t bhandle;
 939         bus_space_tag_t btag;
 940
 941         sc = xsc;
 942         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 943         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 944
 945         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 946         NDBGL1(L1_H_IRQ, "stat %x", stat);
 947         /* was there an interrupt from this card ? */
 948         if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
 949                 return; /* no */
 950         /* interrupts are low active */
 951         if (!(stat & ASL_IRQ_TIMER))
 952           NDBGL1(L1_H_IRQ, "timer interrupt ???");
 953         if (!(stat & ASL_IRQ_HSCX))
 954         {
 955           NDBGL1(L1_H_IRQ, "HSCX");
 956                 avm_pnp_hscx_int_handler(sc);
 957         }
 958         if (!(stat & ASL_IRQ_ISAC))
 959         {
 960           NDBGL1(L1_H_IRQ, "ISAC");
 961                 ifpnp_isac_intr(sc);
 962         }
 963 }
 964
 965 static void
 966 avm_pnp_hscx_init(struct l1_softc *sc, int h_chan, int activate)
 967 {
 968         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 969
 970         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
 971                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
 972
 973         if (activate == 0)
 974         {
 975                 /* only deactivate if both channels are idle */
 976                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
 977                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
 978                 {
 979                         return;
 980                 }
 981                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
 982                 sc->avma1pp_prot = HSCX_MODE_TRANS;
 983                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
 984                 return;
 985         }
 986         if(chan->bprot == BPROT_RHDLC)
 987         {
 988                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
 989
 990                 /* HDLC Frames, transparent mode 0 */
 991                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
 992                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
 993                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
 994                 sc->avma1pp_cmd = HSCX_CMD_XRS;
 995                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 996                 sc->avma1pp_cmd = 0;
 997         }
 998         else
 999         {
1000                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1001
1002                 /* Raw Telephony, extended transparent mode 1 */
1003                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1004                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1005                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
1006                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1007                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
1008                 sc->avma1pp_cmd = 0;
1009         }
1010 }
1011
1012 static void
1013 avm_pnp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1014 {
1015         struct l1_softc *sc = ifpnp_scp[unit];
1016         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1017
1018         crit_enter();
1019
1020         if(activate == 0)
1021         {
1022                 /* deactivation */
1023                 chan->state = HSCX_IDLE;
1024                 avm_pnp_hscx_init(sc, h_chan, activate);
1025         }
1026
1027         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1028                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1029
1030         /* general part */
1031
1032         chan->unit = sc->sc_unit;       /* unit number */
1033         chan->channel = h_chan;         /* B channel */
1034         chan->bprot = bprot;            /* B channel protocol */
1035         chan->state = HSCX_IDLE;        /* B channel state */
1036
1037         /* receiver part */
1038
1039         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1040
1041         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1042
1043         chan->rxcount = 0;              /* reset rx counter */
1044
1045         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1046
1047         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1048         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1049         chan->in_len = 0;               /* reset mbuf data len */
1050
1051         /* transmitter part */
1052
1053         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1054
1055         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1056
1057         chan->txcount = 0;              /* reset tx counter */
1058
1059         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1060
1061         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1062         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1063         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1064         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1065
1066         if(activate != 0)
1067         {
1068                 /* activation */
1069                 avm_pnp_hscx_init(sc, h_chan, activate);
1070                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1071         }
1072
1073         crit_exit();
1074 }
1075
1076 static void
1077 avm_pnp_bchannel_start(int unit, int h_chan)
1078 {
1079         struct l1_softc *sc = ifpnp_scp[unit];
1080         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1081         int activity = -1;
1082
1083         crit_enter();
1084         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1085         {
1086                 crit_exit();
1087                 return;                         /* yes, leave */
1088         }
1089
1090         /* get next mbuf from queue */
1091
1092         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1093
1094         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1095         {
1096                 crit_exit();
1097                 return;                         /* yes, exit */
1098         }
1099
1100         /* init current mbuf values */
1101
1102         chan->out_mbuf_cur = chan->out_mbuf_head;
1103         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1104         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1105
1106         /* activity indicator for timeout handling */
1107
1108         if(chan->bprot == BPROT_NONE)
1109         {
1110                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1111                         activity = ACT_TX;
1112         }
1113         else
1114         {
1115                 activity = ACT_TX;
1116         }
1117
1118         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1119
1120         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1121         {
1122                 i4b_trace_hdr_t hdr;
1123                 hdr.unit = L0IFPNPUNIT(sc->sc_unit);
1124                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1125                 hdr.dir = FROM_TE;
1126                 hdr.count = ++sc->sc_trace_bcount;
1127                 MICROTIME(hdr.time);
1128                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1129         }
1130
1131         avm_pnp_hscx_fifo(chan, sc);
1132
1133         /* call timeout handling routine */
1134
1135         if(activity == ACT_RX || activity == ACT_TX)
1136                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1137
1138         crit_exit();
1139 }
1140
1141 /*---------------------------------------------------------------------------*
1142  *      return the address of isic drivers linktab
1143  *---------------------------------------------------------------------------*/
1144 static isdn_link_t *
1145 avm_pnp_ret_linktab(int unit, int channel)
1146 {
1147         struct l1_softc *sc = ifpnp_scp[unit];
1148         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1149
1150         return(&chan->isic_isdn_linktab);
1151 }
1152
1153 /*---------------------------------------------------------------------------*
1154  *      set the driver linktab in the b channel softc
1155  *---------------------------------------------------------------------------*/
1156 static void
1157 avm_pnp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1158 {
1159         struct l1_softc *sc = ifpnp_scp[unit];
1160         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1161
1162         chan->isic_drvr_linktab = dlt;
1163 }
1164
1165
1166 /*---------------------------------------------------------------------------*
1167  *      initialize our local linktab
1168  *---------------------------------------------------------------------------*/
1169 static void
1170 avm_pnp_init_linktab(struct l1_softc *sc)
1171 {
1172         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1173         isdn_link_t *lt = &chan->isic_isdn_linktab;
1174
1175         /* make sure the hardware driver is known to layer 4 */
1176         /* avoid overwriting if already set */
1177         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1178         {
1179                 ctrl_types[CTRL_PASSIVE].set_linktab = avm_pnp_set_linktab;
1180                 ctrl_types[CTRL_PASSIVE].get_linktab = avm_pnp_ret_linktab;
1181         }
1182
1183         /* local setup */
1184         lt->unit = sc->sc_unit;
1185         lt->channel = HSCX_CH_A;
1186         lt->bch_config = avm_pnp_bchannel_setup;
1187         lt->bch_tx_start = avm_pnp_bchannel_start;
1188         lt->bch_stat = avm_pnp_bchannel_stat;
1189         lt->tx_queue = &chan->tx_queue;
1190
1191         /* used by non-HDLC data transfers, i.e. telephony drivers */
1192         lt->rx_queue = &chan->rx_queue;
1193
1194         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1195         lt->rx_mbuf = &chan->in_mbuf;
1196
1197         chan = &sc->sc_chan[HSCX_CH_B];
1198         lt = &chan->isic_isdn_linktab;
1199
1200         lt->unit = sc->sc_unit;
1201         lt->channel = HSCX_CH_B;
1202         lt->bch_config = avm_pnp_bchannel_setup;
1203         lt->bch_tx_start = avm_pnp_bchannel_start;
1204         lt->bch_stat = avm_pnp_bchannel_stat;
1205         lt->tx_queue = &chan->tx_queue;
1206
1207         /* used by non-HDLC data transfers, i.e. telephony drivers */
1208         lt->rx_queue = &chan->rx_queue;
1209
1210         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1211         lt->rx_mbuf = &chan->in_mbuf;
1212 }
1213
1214 /*
1215  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1216  */
1217 static void
1218 avm_pnp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1219 {
1220         struct l1_softc *sc = ifpnp_scp[unit];
1221         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1222
1223         crit_enter();
1224
1225         bsp->outbytes = chan->txcount;
1226         bsp->inbytes = chan->rxcount;
1227
1228         chan->txcount = 0;
1229         chan->rxcount = 0;
1230
1231         crit_exit();
1232 }
1233
1234 /*---------------------------------------------------------------------------*
1235  *      fill HSCX fifo with data from the current mbuf
1236  *      Put this here until it can go into i4b_hscx.c
1237  *---------------------------------------------------------------------------*/
1238 static int
1239 avm_pnp_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1240 {
1241         int len;
1242         int nextlen;
1243         int i;
1244         int cmd = 0;
1245         /* using a scratch buffer simplifies writing to the FIFO */
1246         u_char scrbuf[HSCX_FIFO_LEN];
1247
1248         len = 0;
1249
1250         /*
1251          * fill the HSCX tx fifo with data from the current mbuf. if
1252          * current mbuf holds less data than HSCX fifo length, try to
1253          * get the next mbuf from (a possible) mbuf chain. if there is
1254          * not enough data in a single mbuf or in a chain, then this
1255          * is the last mbuf and we tell the HSCX that it has to send
1256          * CRC and closing flag
1257          */
1258
1259         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1260         {
1261                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1262
1263 #ifdef NOTDEF
1264                 kprintf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1265                         chan->out_mbuf_head,
1266                         chan->out_mbuf_cur,
1267                         chan->out_mbuf_cur_ptr,
1268                         chan->out_mbuf_cur_len,
1269                         len,
1270                         nextlen);
1271 #endif
1272
1273                 cmd |= HSCX_CMDR_XTF;
1274                 /* collect the data in the scratch buffer */
1275                 for (i = 0; i < nextlen; i++)
1276                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1277
1278                 len += nextlen;
1279                 chan->txcount += nextlen;
1280
1281                 chan->out_mbuf_cur_ptr += nextlen;
1282                 chan->out_mbuf_cur_len -= nextlen;
1283
1284                 if(chan->out_mbuf_cur_len == 0)
1285                 {
1286                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1287                         {
1288                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1289                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1290
1291                                 if(sc->sc_trace & TRACE_B_TX)
1292                                 {
1293                                         i4b_trace_hdr_t hdr;
1294                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
1295                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1296                                         hdr.dir = FROM_TE;
1297                                         hdr.count = ++sc->sc_trace_bcount;
1298                                         MICROTIME(hdr.time);
1299                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1300                                 }
1301                         }
1302                         else
1303                         {
1304                                 if (chan->bprot != BPROT_NONE)
1305                                         cmd |= HSCX_CMDR_XME;
1306                                 i4b_Bfreembuf(chan->out_mbuf_head);
1307                                 chan->out_mbuf_head = NULL;
1308                         }
1309                 }
1310         }
1311         /* write what we have from the scratch buf to the HSCX fifo */
1312         if (len != 0)
1313                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1314         return(cmd);
1315 }
1316
1317 /*---------------------------------------------------------------------------*
1318  *      ifpnp - ISAC interrupt routine
1319  *---------------------------------------------------------------------------*/
1320 static void
1321 ifpnp_isac_intr(struct l1_softc *sc)
1322 {
1323         u_char isac_irq_stat;
1324
1325         for(;;)
1326         {
1327                 /* get isac irq status */
1328                 isac_irq_stat = ISAC_READ(I_ISTA);
1329
1330                 if(isac_irq_stat)
1331                         ifpnp_isac_irq(sc, isac_irq_stat); /* isac handler */
1332                 else
1333                         break;
1334         }
1335
1336         ISAC_WRITE(I_MASK, 0xff);
1337
1338         DELAY(100);
1339
1340         ISAC_WRITE(I_MASK, ISAC_IMASK);
1341 }
1342
1343 /*---------------------------------------------------------------------------*
1344  *      ifpnp_recover - try to recover from irq lockup
1345  *---------------------------------------------------------------------------*/
1346 void
1347 ifpnp_recover(struct l1_softc *sc)
1348 {
1349         u_char byte;
1350
1351         /* get isac irq status */
1352
1353         byte = ISAC_READ(I_ISTA);
1354
1355         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1356
1357         if(byte & ISAC_ISTA_EXI)
1358                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1359
1360         if(byte & ISAC_ISTA_CISQ)
1361         {
1362                 byte = ISAC_READ(I_CIRR);
1363
1364                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1365
1366                 if(byte & ISAC_CIRR_SQC)
1367                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1368         }
1369
1370         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
1371
1372         ISAC_WRITE(I_MASK, 0xff);
1373         DELAY(100);
1374         ISAC_WRITE(I_MASK, ISAC_IMASK);
1375 }
1376
1377 #endif /* NIFPNP > 0 */