2 * Copyright (c) 1990 The Regents of the University of California.
3 * Copyright (c) 2008 The DragonFly Project.
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz and Don Ahn.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
53 #include "opt_clock.h"
56 #include <sys/param.h>
57 #include <sys/systm.h>
58 #include <sys/eventhandler.h>
60 #include <sys/kernel.h>
62 #include <sys/sysctl.h>
64 #include <sys/systimer.h>
65 #include <sys/globaldata.h>
66 #include <sys/thread2.h>
67 #include <sys/systimer.h>
68 #include <sys/machintr.h>
69 #include <sys/interrupt.h>
71 #include <machine/clock.h>
72 #include <machine/cputypes.h>
73 #include <machine/frame.h>
74 #include <machine/ipl.h>
75 #include <machine/limits.h>
76 #include <machine/md_var.h>
77 #include <machine/psl.h>
78 #include <machine/segments.h>
79 #include <machine/smp.h>
80 #include <machine/specialreg.h>
81 #include <machine/intr_machdep.h>
83 #include <machine_base/apic/ioapic.h>
84 #include <machine_base/apic/ioapic_abi.h>
85 #include <machine_base/icu/icu.h>
86 #include <bus/isa/isa.h>
87 #include <bus/isa/rtc.h>
88 #include <machine_base/isa/timerreg.h>
90 static void i8254_restore(void);
91 static void resettodr_on_shutdown(void *arg __unused);
94 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
95 * can use a simple formula for leap years.
97 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
98 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
101 #define TIMER_FREQ 1193182
104 static uint8_t i8254_walltimer_sel;
105 static uint16_t i8254_walltimer_cntr;
107 int adjkerntz; /* local offset from GMT in seconds */
108 int disable_rtc_set; /* disable resettodr() if != 0 */
112 int64_t tsc_frequency;
114 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
116 enum tstate { RELEASED, ACQUIRED };
117 enum tstate timer0_state;
118 enum tstate timer1_state;
119 enum tstate timer2_state;
121 static int beeping = 0;
122 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
123 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
124 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
125 static int rtc_loaded;
127 static int i8254_cputimer_div;
129 static int i8254_nointr;
130 static int i8254_intr_disable = 1;
131 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
133 static struct callout sysbeepstop_ch;
135 static sysclock_t i8254_cputimer_count(void);
136 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
137 static void i8254_cputimer_destruct(struct cputimer *cputimer);
139 static struct cputimer i8254_cputimer = {
140 SLIST_ENTRY_INITIALIZER,
144 i8254_cputimer_count,
145 cputimer_default_fromhz,
146 cputimer_default_fromus,
147 i8254_cputimer_construct,
148 i8254_cputimer_destruct,
153 static sysclock_t tsc_cputimer_count(void);
154 static void tsc_cputimer_construct(struct cputimer *, sysclock_t);
156 static struct cputimer tsc_cputimer = {
157 SLIST_ENTRY_INITIALIZER,
162 cputimer_default_fromhz,
163 cputimer_default_fromus,
164 tsc_cputimer_construct,
165 cputimer_default_destruct,
170 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
171 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
172 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
174 static struct cputimer_intr i8254_cputimer_intr = {
176 .reload = i8254_intr_reload,
177 .enable = cputimer_intr_default_enable,
178 .config = i8254_intr_config,
179 .restart = cputimer_intr_default_restart,
180 .pmfixup = cputimer_intr_default_pmfixup,
181 .initclock = i8254_intr_initclock,
182 .next = SLIST_ENTRY_INITIALIZER,
184 .type = CPUTIMER_INTR_8254,
185 .prio = CPUTIMER_INTR_PRIO_8254,
186 .caps = CPUTIMER_INTR_CAP_PS
190 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
191 * counting as of this interrupt. We use timer1 in free-running mode (not
192 * generating any interrupts) as our main counter. Each cpu has timeouts
195 * This code is INTR_MPSAFE and may be called without the BGL held.
198 clkintr(void *dummy, void *frame_arg)
200 static sysclock_t sysclock_count; /* NOTE! Must be static */
201 struct globaldata *gd = mycpu;
202 struct globaldata *gscan;
206 * SWSTROBE mode is a one-shot, the timer is no longer running
211 * XXX the dispatcher needs work. right now we call systimer_intr()
212 * directly or via IPI for any cpu with systimers queued, which is
213 * usually *ALL* of them. We need to use the LAPIC timer for this.
215 sysclock_count = sys_cputimer->count();
216 for (n = 0; n < ncpus; ++n) {
217 gscan = globaldata_find(n);
218 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
221 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
224 systimer_intr(&sysclock_count, 0, frame_arg);
234 acquire_timer2(int mode)
236 if (timer2_state != RELEASED)
238 timer2_state = ACQUIRED;
241 * This access to the timer registers is as atomic as possible
242 * because it is a single instruction. We could do better if we
245 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
252 if (timer2_state != ACQUIRED)
254 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
255 timer2_state = RELEASED;
263 DB_SHOW_COMMAND(rtc, rtc)
265 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
266 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
267 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
268 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
273 * Return the current cpu timer count as a 32 bit integer.
277 i8254_cputimer_count(void)
279 static __uint16_t cputimer_last;
284 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
285 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
286 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
287 count = -count; /* -> countup */
288 if (count < cputimer_last) /* rollover */
289 i8254_cputimer.base += 0x00010000;
290 ret = i8254_cputimer.base | count;
291 cputimer_last = count;
297 * This function is called whenever the system timebase changes, allowing
298 * us to calculate what is needed to convert a system timebase tick
299 * into an 8254 tick for the interrupt timer. If we can convert to a
300 * simple shift, multiplication, or division, we do so. Otherwise 64
301 * bit arithmatic is required every time the interrupt timer is reloaded.
304 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
310 * Will a simple divide do the trick?
312 div = (timer->freq + (cti->freq / 2)) / cti->freq;
313 freq = cti->freq * div;
315 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
316 i8254_cputimer_div = div;
318 i8254_cputimer_div = 0;
322 * Reload for the next timeout. It is possible for the reload value
323 * to be 0 or negative, indicating that an immediate timer interrupt
324 * is desired. For now make the minimum 2 ticks.
326 * We may have to convert from the system timebase to the 8254 timebase.
329 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
333 if (i8254_cputimer_div)
334 reload /= i8254_cputimer_div;
336 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
342 if (timer0_running) {
343 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
344 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
345 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
346 if (reload < count) {
347 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
348 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
349 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
354 reload = 0; /* full count */
355 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
356 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
357 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
363 * DELAY(usec) - Spin for the specified number of microseconds.
364 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
365 * but do a thread switch in the loop
367 * Relies on timer 1 counting down from (cputimer_freq / hz)
368 * Note: timer had better have been programmed before this is first used!
371 DODELAY(int n, int doswitch)
373 ssysclock_t delta, ticks_left;
374 sysclock_t prev_tick, tick;
379 static int state = 0;
383 for (n1 = 1; n1 <= 10000000; n1 *= 10)
388 kprintf("DELAY(%d)...", n);
391 * Guard against the timer being uninitialized if we are called
392 * early for console i/o.
394 if (timer0_state == RELEASED)
398 * Read the counter first, so that the rest of the setup overhead is
399 * counted. Then calculate the number of hardware timer ticks
400 * required, rounding up to be sure we delay at least the requested
401 * number of microseconds.
403 prev_tick = sys_cputimer->count();
404 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
410 while (ticks_left > 0) {
411 tick = sys_cputimer->count();
415 delta = tick - prev_tick;
420 if (doswitch && ticks_left > 0)
426 kprintf(" %d calls to getit() at %d usec each\n",
427 getit_calls, (n + 5) / getit_calls);
432 * DELAY() never switches.
441 * Returns non-zero if the specified time period has elapsed. Call
442 * first with last_clock set to 0.
445 CHECKTIMEOUT(TOTALDELAY *tdd)
450 if (tdd->started == 0) {
451 if (timer0_state == RELEASED)
453 tdd->last_clock = sys_cputimer->count();
457 delta = sys_cputimer->count() - tdd->last_clock;
458 us = (u_int64_t)delta * (u_int64_t)1000000 /
459 (u_int64_t)sys_cputimer->freq;
460 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
463 return (tdd->us < 0);
468 * DRIVERSLEEP() does not switch if called with a spinlock held or
469 * from a hard interrupt.
472 DRIVERSLEEP(int usec)
474 globaldata_t gd = mycpu;
476 if (gd->gd_intr_nesting_level || gd->gd_spinlocks) {
484 sysbeepstop(void *chan)
486 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
492 sysbeep(int pitch, int period)
494 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
496 if (sysbeep_enable == 0)
499 * Nobody else is using timer2, we do not need the clock lock
501 outb(TIMER_CNTR2, pitch);
502 outb(TIMER_CNTR2, (pitch>>8));
504 /* enable counter2 output to speaker */
505 outb(IO_PPI, inb(IO_PPI) | 3);
507 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
513 * RTC support routines
524 val = inb(IO_RTC + 1);
531 writertc(u_char reg, u_char val)
537 outb(IO_RTC + 1, val);
538 inb(0x84); /* XXX work around wrong order in rtcin() */
545 return(bcd2bin(rtcin(port)));
549 calibrate_clocks(void)
553 sysclock_t count, prev_count;
554 int sec, start_sec, timeout;
557 kprintf("Calibrating clock(s) ...\n");
558 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
562 /* Read the mc146818A seconds counter. */
564 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
565 sec = rtcin(RTC_SEC);
572 /* Wait for the mC146818A seconds counter to change. */
575 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
576 sec = rtcin(RTC_SEC);
577 if (sec != start_sec)
584 /* Start keeping track of the i8254 counter. */
585 prev_count = sys_cputimer->count();
591 old_tsc = 0; /* shut up gcc */
594 * Wait for the mc146818A seconds counter to change. Read the i8254
595 * counter for each iteration since this is convenient and only
596 * costs a few usec of inaccuracy. The timing of the final reads
597 * of the counters almost matches the timing of the initial reads,
598 * so the main cause of inaccuracy is the varying latency from
599 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
600 * rtcin(RTC_SEC) that returns a changed seconds count. The
601 * maximum inaccuracy from this cause is < 10 usec on 486's.
605 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
606 sec = rtcin(RTC_SEC);
607 count = sys_cputimer->count();
608 tot_count += (int)(count - prev_count);
610 if (sec != start_sec)
617 * Read the cpu cycle counter. The timing considerations are
618 * similar to those for the i8254 clock.
621 tsc_frequency = rdtsc() - old_tsc;
625 kprintf("TSC%s clock: %llu Hz, ",
626 tsc_invariant ? " invariant" : "",
627 (long long)tsc_frequency);
629 kprintf("i8254 clock: %u Hz\n", tot_count);
633 kprintf("failed, using default i8254 clock of %u Hz\n",
634 i8254_cputimer.freq);
635 return (i8254_cputimer.freq);
641 timer0_state = ACQUIRED;
646 * Timer0 is our fine-grained variable clock interrupt
648 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
649 outb(TIMER_CNTR0, 2); /* lsb */
650 outb(TIMER_CNTR0, 0); /* msb */
654 cputimer_intr_register(&i8254_cputimer_intr);
655 cputimer_intr_select(&i8254_cputimer_intr, 0);
659 * Timer1 or timer2 is our free-running clock, but only if another
660 * has not been selected.
662 cputimer_register(&i8254_cputimer);
663 cputimer_select(&i8254_cputimer, 0);
667 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
672 * Should we use timer 1 or timer 2 ?
675 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
676 if (which != 1 && which != 2)
681 timer->name = "i8254_timer1";
682 timer->type = CPUTIMER_8254_SEL1;
683 i8254_walltimer_sel = TIMER_SEL1;
684 i8254_walltimer_cntr = TIMER_CNTR1;
685 timer1_state = ACQUIRED;
688 timer->name = "i8254_timer2";
689 timer->type = CPUTIMER_8254_SEL2;
690 i8254_walltimer_sel = TIMER_SEL2;
691 i8254_walltimer_cntr = TIMER_CNTR2;
692 timer2_state = ACQUIRED;
696 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
699 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
700 outb(i8254_walltimer_cntr, 0); /* lsb */
701 outb(i8254_walltimer_cntr, 0); /* msb */
702 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
707 i8254_cputimer_destruct(struct cputimer *timer)
709 switch(timer->type) {
710 case CPUTIMER_8254_SEL1:
711 timer1_state = RELEASED;
713 case CPUTIMER_8254_SEL2:
714 timer2_state = RELEASED;
725 /* Restore all of the RTC's "status" (actually, control) registers. */
726 writertc(RTC_STATUSB, RTCSB_24HR);
727 writertc(RTC_STATUSA, rtc_statusa);
728 writertc(RTC_STATUSB, rtc_statusb);
732 * Restore all the timers.
734 * This function is called to resynchronize our core timekeeping after a
735 * long halt, e.g. from apm_default_resume() and friends. It is also
736 * called if after a BIOS call we have detected munging of the 8254.
737 * It is necessary because cputimer_count() counter's delta may have grown
738 * too large for nanouptime() and friends to handle, or (in the case of 8254
739 * munging) might cause the SYSTIMER code to prematurely trigger.
745 i8254_restore(); /* restore timer_freq and hz */
746 rtc_restore(); /* reenable RTC interrupts */
751 * Initialize 8254 timer 0 early so that it can be used in DELAY().
759 * Can we use the TSC?
761 if (cpu_feature & CPUID_TSC) {
763 if ((cpu_vendor_id == CPU_VENDOR_INTEL ||
764 cpu_vendor_id == CPU_VENDOR_AMD) &&
765 cpu_exthigh >= 0x80000007) {
768 do_cpuid(0x80000007, regs);
777 * Initial RTC state, don't do anything unexpected
779 writertc(RTC_STATUSA, rtc_statusa);
780 writertc(RTC_STATUSB, RTCSB_24HR);
783 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
784 * generate an interrupt, which we will ignore for now.
786 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
787 * (so it counts a full 2^16 and repeats). We will use this timer
791 freq = calibrate_clocks();
792 #ifdef CLK_CALIBRATION_LOOP
795 "Press a key on the console to abort clock calibration\n");
796 while (cncheckc() == -1)
802 * Use the calibrated i8254 frequency if it seems reasonable.
803 * Otherwise use the default, and don't use the calibrated i586
806 delta = freq > i8254_cputimer.freq ?
807 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
808 if (delta < i8254_cputimer.freq / 100) {
809 #ifndef CLK_USE_I8254_CALIBRATION
812 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
813 freq = i8254_cputimer.freq;
817 * Interrupt timer's freq must be adjusted
818 * before we change the cuptimer's frequency.
820 i8254_cputimer_intr.freq = freq;
821 cputimer_set_frequency(&i8254_cputimer, freq);
825 "%d Hz differs from default of %d Hz by more than 1%%\n",
826 freq, i8254_cputimer.freq);
830 #ifndef CLK_USE_TSC_CALIBRATION
831 if (tsc_frequency != 0) {
834 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
838 if (tsc_present && tsc_frequency == 0) {
840 * Calibration of the i586 clock relative to the mc146818A
841 * clock failed. Do a less accurate calibration relative
842 * to the i8254 clock.
844 u_int64_t old_tsc = rdtsc();
847 tsc_frequency = rdtsc() - old_tsc;
848 #ifdef CLK_USE_TSC_CALIBRATION
850 kprintf("TSC clock: %llu Hz (Method B)\n",
856 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
860 * Sync the time of day back to the RTC on shutdown, but only if
861 * we have already loaded it and have not crashed.
864 resettodr_on_shutdown(void *arg __unused)
866 if (rtc_loaded && panicstr == NULL) {
872 * Initialize the time of day register, based on the time base which is, e.g.
876 inittodr(time_t base)
878 unsigned long sec, days;
889 /* Look if we have a RTC present and the time is valid */
890 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
893 /* wait for time update to complete */
894 /* If RTCSA_TUP is zero, we have at least 244us before next update */
896 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
902 #ifdef USE_RTC_CENTURY
903 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
905 year = readrtc(RTC_YEAR) + 1900;
913 month = readrtc(RTC_MONTH);
914 for (m = 1; m < month; m++)
915 days += daysinmonth[m-1];
916 if ((month > 2) && LEAPYEAR(year))
918 days += readrtc(RTC_DAY) - 1;
919 for (y = 1970; y < year; y++)
920 days += DAYSPERYEAR + LEAPYEAR(y);
921 sec = ((( days * 24 +
922 readrtc(RTC_HRS)) * 60 +
923 readrtc(RTC_MIN)) * 60 +
925 /* sec now contains the number of seconds, since Jan 1 1970,
926 in the local time zone */
928 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
930 y = time_second - sec;
931 if (y <= -2 || y >= 2) {
932 /* badly off, adjust it */
942 kprintf("Invalid time in real time clock.\n");
943 kprintf("Check and reset the date immediately!\n");
947 * Write system time back to RTC
964 /* Disable RTC updates and interrupts. */
965 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
967 /* Calculate local time to put in RTC */
969 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
971 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
972 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
973 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
975 /* We have now the days since 01-01-1970 in tm */
976 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
977 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
979 y++, m = DAYSPERYEAR + LEAPYEAR(y))
982 /* Now we have the years in y and the day-of-the-year in tm */
983 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
984 #ifdef USE_RTC_CENTURY
985 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
991 if (m == 1 && LEAPYEAR(y))
998 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
999 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
1001 /* Reenable RTC updates and interrupts. */
1002 writertc(RTC_STATUSB, rtc_statusb);
1007 i8254_ioapic_trial(int irq, struct cputimer_intr *cti)
1013 * Following code assumes the 8254 is the cpu timer,
1014 * so make sure it is.
1016 KKASSERT(sys_cputimer == &i8254_cputimer);
1017 KKASSERT(cti == &i8254_cputimer_intr);
1019 lastcnt = get_interrupt_counter(irq, mycpuid);
1022 * Force an 8254 Timer0 interrupt and wait 1/100s for
1023 * it to happen, then see if we got it.
1025 kprintf("IOAPIC: testing 8254 interrupt delivery\n");
1027 i8254_intr_reload(cti, 2);
1028 base = sys_cputimer->count();
1029 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1032 if (get_interrupt_counter(irq, mycpuid) - lastcnt == 0)
1038 * Start both clocks running. DragonFly note: the stat clock is no longer
1039 * used. Instead, 8254 based systimers are used for all major clock
1043 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
1045 void *clkdesc = NULL;
1046 int irq = 0, mixed_mode = 0, error;
1048 KKASSERT(mycpuid == 0);
1049 callout_init_mp(&sysbeepstop_ch);
1051 if (!selected && i8254_intr_disable)
1055 * The stat interrupt mask is different without the
1056 * statistics clock. Also, don't set the interrupt
1057 * flag which would normally cause the RTC to generate
1060 rtc_statusb = RTCSB_24HR;
1062 /* Finish initializing 8254 timer 0. */
1063 if (ioapic_enable) {
1064 irq = machintr_legacy_intr_find(0, INTR_TRIGGER_EDGE,
1065 INTR_POLARITY_HIGH);
1068 error = ioapic_conf_legacy_extint(0);
1070 irq = machintr_legacy_intr_find(0,
1071 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
1078 kprintf("IOAPIC: setup mixed mode for "
1079 "irq 0 failed: %d\n", error);
1082 panic("IOAPIC: setup mixed mode for "
1083 "irq 0 failed: %d\n", error);
1088 clkdesc = register_int(irq, clkintr, NULL, "clk",
1090 INTR_EXCL | INTR_CLOCK |
1091 INTR_NOPOLL | INTR_MPSAFE |
1094 register_int(0, clkintr, NULL, "clk", NULL,
1095 INTR_EXCL | INTR_CLOCK |
1096 INTR_NOPOLL | INTR_MPSAFE |
1100 /* Initialize RTC. */
1101 writertc(RTC_STATUSA, rtc_statusa);
1102 writertc(RTC_STATUSB, RTCSB_24HR);
1104 if (ioapic_enable) {
1105 error = i8254_ioapic_trial(irq, cti);
1109 kprintf("IOAPIC: mixed mode for irq %d "
1110 "trial failed: %d\n",
1114 panic("IOAPIC: mixed mode for irq %d "
1115 "trial failed: %d\n", irq, error);
1118 kprintf("IOAPIC: warning 8254 is not connected "
1119 "to the correct pin, try mixed mode\n");
1120 unregister_int(clkdesc, 0);
1121 goto mixed_mode_setup;
1128 i8254_nointr = 1; /* don't try to register again */
1129 cputimer_intr_deregister(cti);
1133 setstatclockrate(int newhz)
1135 if (newhz == RTC_PROFRATE)
1136 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1138 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1139 writertc(RTC_STATUSA, rtc_statusa);
1144 tsc_get_timecount(struct timecounter *tc)
1150 #ifdef KERN_TIMESTAMP
1151 #define KERN_TIMESTAMP_SIZE 16384
1152 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1153 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1154 sizeof(tsc), "LU", "Kernel timestamps");
1160 tsc[i] = (u_int32_t)rdtsc();
1163 if (i >= KERN_TIMESTAMP_SIZE)
1165 tsc[i] = 0; /* mark last entry */
1167 #endif /* KERN_TIMESTAMP */
1174 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1181 if (sys_cputimer == &i8254_cputimer)
1182 count = sys_cputimer->count();
1190 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1191 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1194 static uint64_t tsc_mpsync_target;
1197 tsc_mpsync_test_remote(void *arg __unused)
1202 if (tsc < tsc_mpsync_target)
1207 tsc_mpsync_test(void)
1209 struct globaldata *gd = mycpu;
1210 uint64_t test_end, test_begin;
1213 if (!tsc_invariant) {
1214 /* Not even invariant TSC */
1224 if (cpu_vendor_id != CPU_VENDOR_INTEL) {
1225 /* XXX only Intel works */
1229 kprintf("TSC testing MP synchronization ...\n");
1232 /* Run test for 100ms */
1233 test_begin = rdtsc();
1234 test_end = test_begin + (tsc_frequency / 10);
1236 #define TSC_TEST_TRYMAX 1000000 /* Make sure we could stop */
1238 for (i = 0; i < TSC_TEST_TRYMAX; ++i) {
1239 struct lwkt_cpusync cs;
1242 lwkt_cpusync_init(&cs, gd->gd_other_cpus,
1243 tsc_mpsync_test_remote, NULL);
1244 lwkt_cpusync_interlock(&cs);
1245 tsc_mpsync_target = rdtsc();
1247 lwkt_cpusync_deinterlock(&cs);
1251 kprintf("TSC is not MP synchronized @%u\n", i);
1254 if (tsc_mpsync_target > test_end)
1258 #undef TSC_TEST_TRYMAX
1261 if (tsc_mpsync_target == test_begin) {
1262 kprintf("TSC does not tick?!");
1263 /* XXX disable TSC? */
1269 kprintf("TSC is MP synchronized");
1271 kprintf(", after %u tries", i);
1275 SYSINIT(tsc_mpsync, SI_BOOT2_FINISH_SMP, SI_ORDER_ANY, tsc_mpsync_test, NULL);
1277 #define TSC_CPUTIMER_FREQMAX 128000000 /* 128Mhz */
1279 static int tsc_cputimer_shift;
1282 tsc_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
1285 timer->base = oldclock - tsc_cputimer_count();
1289 tsc_cputimer_count(void)
1294 tsc >>= tsc_cputimer_shift;
1296 return (tsc + tsc_cputimer.base);
1300 tsc_cputimer_register(void)
1308 TUNABLE_INT_FETCH("hw.tsc_cputimer_enable", &enable);
1312 freq = tsc_frequency;
1313 while (freq > TSC_CPUTIMER_FREQMAX) {
1315 ++tsc_cputimer_shift;
1317 kprintf("TSC: cputimer freq %ju, shift %d\n",
1318 (uintmax_t)freq, tsc_cputimer_shift);
1320 tsc_cputimer.freq = freq;
1322 cputimer_register(&tsc_cputimer);
1323 cputimer_select(&tsc_cputimer, 0);
1325 SYSINIT(tsc_cputimer_reg, SI_BOOT2_MACHDEP, SI_ORDER_ANY,
1326 tsc_cputimer_register, NULL);
1328 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1329 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1331 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1332 0, 0, hw_i8254_timestamp, "A", "");
1334 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1335 &tsc_present, 0, "TSC Available");
1336 SYSCTL_INT(_hw, OID_AUTO, tsc_invariant, CTLFLAG_RD,
1337 &tsc_invariant, 0, "Invariant TSC");
1338 SYSCTL_INT(_hw, OID_AUTO, tsc_mpsync, CTLFLAG_RD,
1339 &tsc_mpsync, 0, "TSC is synchronized across CPUs");
1340 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1341 &tsc_frequency, 0, "TSC Frequency");