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d751f32e MD |
1 | /*- |
2 | * Generic routines for LSI Fusion adapters. | |
984263bc MD |
3 | * FreeBSD Version. |
4 | * | |
5 | * Copyright (c) 2000, 2001 by Greg Ansley | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice immediately at the beginning of the file, without modification, | |
12 | * this list of conditions, and the following disclaimer. | |
13 | * 2. The name of the author may not be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | |
17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR | |
20 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
26 | * SUCH DAMAGE. | |
27 | */ | |
d751f32e MD |
28 | /*- |
29 | * Copyright (c) 2002, 2006 by Matthew Jacob | |
30 | * All rights reserved. | |
31 | * | |
32 | * Redistribution and use in source and binary forms, with or without | |
33 | * modification, are permitted provided that the following conditions are | |
34 | * met: | |
35 | * 1. Redistributions of source code must retain the above copyright | |
36 | * notice, this list of conditions and the following disclaimer. | |
37 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
38 | * substantially similar to the "NO WARRANTY" disclaimer below | |
39 | * ("Disclaimer") and any redistribution must be conditioned upon including | |
40 | * a substantially similar Disclaimer requirement for further binary | |
41 | * redistribution. | |
42 | * 3. Neither the names of the above listed copyright holders nor the names | |
43 | * of any contributors may be used to endorse or promote products derived | |
44 | * from this software without specific prior written permission. | |
45 | * | |
46 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
47 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
48 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
49 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
50 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
51 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
52 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
53 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
54 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
55 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
57 | * | |
58 | * Support from Chris Ellsworth in order to make SAS adapters work | |
59 | * is gratefully acknowledged. | |
60 | * | |
61 | * | |
62 | * Support from LSI-Logic has also gone a great deal toward making this a | |
63 | * workable subsystem and is gratefully acknowledged. | |
64 | */ | |
65 | /*- | |
66 | * Copyright (c) 2004, Avid Technology, Inc. and its contributors. | |
67 | * Copyright (c) 2005, WHEEL Sp. z o.o. | |
68 | * Copyright (c) 2004, 2005 Justin T. Gibbs | |
69 | * All rights reserved. | |
70 | * | |
71 | * Redistribution and use in source and binary forms, with or without | |
72 | * modification, are permitted provided that the following conditions are | |
73 | * met: | |
74 | * 1. Redistributions of source code must retain the above copyright | |
75 | * notice, this list of conditions and the following disclaimer. | |
76 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
77 | * substantially similar to the "NO WARRANTY" disclaimer below | |
78 | * ("Disclaimer") and any redistribution must be conditioned upon including | |
79 | * a substantially similar Disclaimer requirement for further binary | |
80 | * redistribution. | |
81 | * 3. Neither the names of the above listed copyright holders nor the names | |
82 | * of any contributors may be used to endorse or promote products derived | |
83 | * from this software without specific prior written permission. | |
84 | * | |
85 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
86 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
87 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
88 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
89 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
90 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
91 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
92 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
93 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
94 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT | |
95 | * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32af04f7 | 96 | * |
f582582c | 97 | * $FreeBSD: head/sys/dev/mpt/mpt.c 241874 2012-10-22 10:42:59Z marius $ |
984263bc MD |
98 | */ |
99 | ||
d751f32e MD |
100 | #include <dev/disk/mpt/mpt.h> |
101 | #include <dev/disk/mpt/mpt_cam.h> /* XXX For static handler registration */ | |
102 | #include <dev/disk/mpt/mpt_raid.h> /* XXX For static handler registration */ | |
103 | ||
104 | #include <dev/disk/mpt/mpilib/mpi.h> | |
105 | #include <dev/disk/mpt/mpilib/mpi_ioc.h> | |
106 | #include <dev/disk/mpt/mpilib/mpi_fc.h> | |
107 | #include <dev/disk/mpt/mpilib/mpi_targ.h> | |
108 | ||
109 | #include <sys/sysctl.h> | |
984263bc MD |
110 | |
111 | #define MPT_MAX_TRYS 3 | |
112 | #define MPT_MAX_WAIT 300000 | |
113 | ||
114 | static int maxwait_ack = 0; | |
115 | static int maxwait_int = 0; | |
116 | static int maxwait_state = 0; | |
117 | ||
d751f32e MD |
118 | static TAILQ_HEAD(, mpt_softc) mpt_tailq = TAILQ_HEAD_INITIALIZER(mpt_tailq); |
119 | mpt_reply_handler_t *mpt_reply_handlers[MPT_NUM_REPLY_HANDLERS]; | |
120 | ||
121 | static mpt_reply_handler_t mpt_default_reply_handler; | |
122 | static mpt_reply_handler_t mpt_config_reply_handler; | |
123 | static mpt_reply_handler_t mpt_handshake_reply_handler; | |
124 | static mpt_reply_handler_t mpt_event_reply_handler; | |
125 | static void mpt_send_event_ack(struct mpt_softc *mpt, request_t *ack_req, | |
126 | MSG_EVENT_NOTIFY_REPLY *msg, uint32_t context); | |
127 | static int mpt_send_event_request(struct mpt_softc *mpt, int onoff); | |
128 | static int mpt_soft_reset(struct mpt_softc *mpt); | |
129 | static void mpt_hard_reset(struct mpt_softc *mpt); | |
6d259fc1 SW |
130 | static int mpt_dma_buf_alloc(struct mpt_softc *mpt); |
131 | static void mpt_dma_buf_free(struct mpt_softc *mpt); | |
d751f32e MD |
132 | static int mpt_configure_ioc(struct mpt_softc *mpt, int, int); |
133 | static int mpt_enable_ioc(struct mpt_softc *mpt, int); | |
134 | ||
135 | /************************* Personality Module Support *************************/ | |
136 | /* | |
137 | * We include one extra entry that is guaranteed to be NULL | |
138 | * to simplify our itterator. | |
139 | */ | |
140 | static struct mpt_personality *mpt_personalities[MPT_MAX_PERSONALITIES + 1]; | |
141 | static __inline struct mpt_personality* | |
142 | mpt_pers_find(struct mpt_softc *, u_int); | |
143 | static __inline struct mpt_personality* | |
144 | mpt_pers_find_reverse(struct mpt_softc *, u_int); | |
145 | ||
146 | static __inline struct mpt_personality * | |
147 | mpt_pers_find(struct mpt_softc *mpt, u_int start_at) | |
984263bc | 148 | { |
d751f32e | 149 | KASSERT(start_at <= MPT_MAX_PERSONALITIES, |
4c42baf4 | 150 | ("mpt_pers_find: starting position out of range")); |
984263bc | 151 | |
d751f32e MD |
152 | while (start_at < MPT_MAX_PERSONALITIES |
153 | && (mpt->mpt_pers_mask & (0x1 << start_at)) == 0) { | |
154 | start_at++; | |
984263bc | 155 | } |
d751f32e | 156 | return (mpt_personalities[start_at]); |
984263bc MD |
157 | } |
158 | ||
d751f32e MD |
159 | /* |
160 | * Used infrequently, so no need to optimize like a forward | |
161 | * traversal where we use the MAX+1 is guaranteed to be NULL | |
162 | * trick. | |
163 | */ | |
164 | static __inline struct mpt_personality * | |
165 | mpt_pers_find_reverse(struct mpt_softc *mpt, u_int start_at) | |
984263bc | 166 | { |
d751f32e MD |
167 | while (start_at < MPT_MAX_PERSONALITIES |
168 | && (mpt->mpt_pers_mask & (0x1 << start_at)) == 0) { | |
169 | start_at--; | |
984263bc | 170 | } |
d751f32e MD |
171 | if (start_at < MPT_MAX_PERSONALITIES) |
172 | return (mpt_personalities[start_at]); | |
173 | return (NULL); | |
984263bc MD |
174 | } |
175 | ||
d751f32e MD |
176 | #define MPT_PERS_FOREACH(mpt, pers) \ |
177 | for (pers = mpt_pers_find(mpt, /*start_at*/0); \ | |
178 | pers != NULL; \ | |
179 | pers = mpt_pers_find(mpt, /*start_at*/pers->id+1)) | |
180 | ||
181 | #define MPT_PERS_FOREACH_REVERSE(mpt, pers) \ | |
182 | for (pers = mpt_pers_find_reverse(mpt, MPT_MAX_PERSONALITIES-1);\ | |
183 | pers != NULL; \ | |
184 | pers = mpt_pers_find_reverse(mpt, /*start_at*/pers->id-1)) | |
185 | ||
186 | static mpt_load_handler_t mpt_stdload; | |
187 | static mpt_probe_handler_t mpt_stdprobe; | |
188 | static mpt_attach_handler_t mpt_stdattach; | |
189 | static mpt_enable_handler_t mpt_stdenable; | |
190 | static mpt_ready_handler_t mpt_stdready; | |
191 | static mpt_event_handler_t mpt_stdevent; | |
192 | static mpt_reset_handler_t mpt_stdreset; | |
193 | static mpt_shutdown_handler_t mpt_stdshutdown; | |
194 | static mpt_detach_handler_t mpt_stddetach; | |
195 | static mpt_unload_handler_t mpt_stdunload; | |
196 | static struct mpt_personality mpt_default_personality = | |
984263bc | 197 | { |
d751f32e MD |
198 | .load = mpt_stdload, |
199 | .probe = mpt_stdprobe, | |
200 | .attach = mpt_stdattach, | |
201 | .enable = mpt_stdenable, | |
202 | .ready = mpt_stdready, | |
203 | .event = mpt_stdevent, | |
204 | .reset = mpt_stdreset, | |
205 | .shutdown = mpt_stdshutdown, | |
206 | .detach = mpt_stddetach, | |
207 | .unload = mpt_stdunload | |
208 | }; | |
209 | ||
210 | static mpt_load_handler_t mpt_core_load; | |
211 | static mpt_attach_handler_t mpt_core_attach; | |
212 | static mpt_enable_handler_t mpt_core_enable; | |
213 | static mpt_reset_handler_t mpt_core_ioc_reset; | |
214 | static mpt_event_handler_t mpt_core_event; | |
215 | static mpt_shutdown_handler_t mpt_core_shutdown; | |
216 | static mpt_shutdown_handler_t mpt_core_detach; | |
217 | static mpt_unload_handler_t mpt_core_unload; | |
218 | static struct mpt_personality mpt_core_personality = | |
984263bc | 219 | { |
d751f32e MD |
220 | .name = "mpt_core", |
221 | .load = mpt_core_load, | |
222 | // .attach = mpt_core_attach, | |
223 | // .enable = mpt_core_enable, | |
224 | .event = mpt_core_event, | |
225 | .reset = mpt_core_ioc_reset, | |
226 | .shutdown = mpt_core_shutdown, | |
227 | .detach = mpt_core_detach, | |
228 | .unload = mpt_core_unload, | |
229 | }; | |
984263bc | 230 | |
d751f32e MD |
231 | /* |
232 | * Manual declaration so that DECLARE_MPT_PERSONALITY doesn't need | |
233 | * ordering information. We want the core to always register FIRST. | |
234 | * other modules are set to SI_ORDER_SECOND. | |
235 | */ | |
236 | static moduledata_t mpt_core_mod = { | |
237 | "mpt_core", mpt_modevent, &mpt_core_personality | |
238 | }; | |
239 | DECLARE_MODULE(mpt_core, mpt_core_mod, SI_SUB_DRIVERS, SI_ORDER_FIRST); | |
240 | MODULE_VERSION(mpt_core, 1); | |
984263bc | 241 | |
d751f32e | 242 | #define MPT_PERS_ATTACHED(pers, mpt) ((mpt)->mpt_pers_mask & (0x1 << pers->id)) |
984263bc | 243 | |
984263bc | 244 | int |
d751f32e | 245 | mpt_modevent(module_t mod, int type, void *data) |
984263bc | 246 | { |
d751f32e MD |
247 | struct mpt_personality *pers; |
248 | int error; | |
984263bc | 249 | |
d751f32e | 250 | pers = (struct mpt_personality *)data; |
984263bc | 251 | |
d751f32e MD |
252 | error = 0; |
253 | switch (type) { | |
254 | case MOD_LOAD: | |
255 | { | |
256 | mpt_load_handler_t **def_handler; | |
257 | mpt_load_handler_t **pers_handler; | |
258 | int i; | |
984263bc | 259 | |
d751f32e MD |
260 | for (i = 0; i < MPT_MAX_PERSONALITIES; i++) { |
261 | if (mpt_personalities[i] == NULL) | |
262 | break; | |
263 | } | |
264 | if (i >= MPT_MAX_PERSONALITIES) { | |
265 | error = ENOMEM; | |
266 | break; | |
267 | } | |
268 | pers->id = i; | |
269 | mpt_personalities[i] = pers; | |
270 | ||
271 | /* Install standard/noop handlers for any NULL entries. */ | |
272 | def_handler = MPT_PERS_FIRST_HANDLER(&mpt_default_personality); | |
273 | pers_handler = MPT_PERS_FIRST_HANDLER(pers); | |
274 | while (pers_handler <= MPT_PERS_LAST_HANDLER(pers)) { | |
275 | if (*pers_handler == NULL) | |
276 | *pers_handler = *def_handler; | |
277 | pers_handler++; | |
278 | def_handler++; | |
279 | } | |
984263bc | 280 | |
d751f32e MD |
281 | error = (pers->load(pers)); |
282 | if (error != 0) | |
283 | mpt_personalities[i] = NULL; | |
284 | break; | |
984263bc | 285 | } |
d751f32e MD |
286 | case MOD_SHUTDOWN: |
287 | break; | |
d751f32e MD |
288 | case MOD_UNLOAD: |
289 | error = pers->unload(pers); | |
290 | mpt_personalities[pers->id] = NULL; | |
291 | break; | |
292 | default: | |
293 | error = EINVAL; | |
294 | break; | |
295 | } | |
296 | return (error); | |
984263bc MD |
297 | } |
298 | ||
4c42baf4 | 299 | static int |
d751f32e | 300 | mpt_stdload(struct mpt_personality *pers) |
984263bc | 301 | { |
4c42baf4 | 302 | |
6d259fc1 | 303 | /* Load is always successful. */ |
d751f32e | 304 | return (0); |
984263bc MD |
305 | } |
306 | ||
4c42baf4 | 307 | static int |
d751f32e | 308 | mpt_stdprobe(struct mpt_softc *mpt) |
984263bc | 309 | { |
4c42baf4 | 310 | |
6d259fc1 | 311 | /* Probe is always successful. */ |
d751f32e MD |
312 | return (0); |
313 | } | |
984263bc | 314 | |
4c42baf4 | 315 | static int |
d751f32e MD |
316 | mpt_stdattach(struct mpt_softc *mpt) |
317 | { | |
4c42baf4 | 318 | |
6d259fc1 | 319 | /* Attach is always successful. */ |
d751f32e MD |
320 | return (0); |
321 | } | |
984263bc | 322 | |
4c42baf4 | 323 | static int |
d751f32e MD |
324 | mpt_stdenable(struct mpt_softc *mpt) |
325 | { | |
4c42baf4 | 326 | |
6d259fc1 | 327 | /* Enable is always successful. */ |
d751f32e | 328 | return (0); |
984263bc MD |
329 | } |
330 | ||
4c42baf4 | 331 | static void |
d751f32e | 332 | mpt_stdready(struct mpt_softc *mpt) |
984263bc | 333 | { |
984263bc | 334 | |
4c42baf4 | 335 | } |
d751f32e | 336 | |
4c42baf4 | 337 | static int |
d751f32e | 338 | mpt_stdevent(struct mpt_softc *mpt, request_t *req, MSG_EVENT_NOTIFY_REPLY *msg) |
984263bc | 339 | { |
4c42baf4 | 340 | |
6d259fc1 | 341 | mpt_lprt(mpt, MPT_PRT_DEBUG, "mpt_stdevent: 0x%x\n", msg->Event & 0xFF); |
d751f32e MD |
342 | /* Event was not for us. */ |
343 | return (0); | |
984263bc MD |
344 | } |
345 | ||
4c42baf4 | 346 | static void |
d751f32e MD |
347 | mpt_stdreset(struct mpt_softc *mpt, int type) |
348 | { | |
4c42baf4 | 349 | |
d751f32e MD |
350 | } |
351 | ||
4c42baf4 | 352 | static void |
d751f32e MD |
353 | mpt_stdshutdown(struct mpt_softc *mpt) |
354 | { | |
4c42baf4 | 355 | |
984263bc MD |
356 | } |
357 | ||
4c42baf4 | 358 | static void |
d751f32e | 359 | mpt_stddetach(struct mpt_softc *mpt) |
984263bc | 360 | { |
4c42baf4 | 361 | |
984263bc MD |
362 | } |
363 | ||
4c42baf4 | 364 | static int |
d751f32e | 365 | mpt_stdunload(struct mpt_personality *pers) |
984263bc | 366 | { |
4c42baf4 | 367 | |
6d259fc1 | 368 | /* Unload is always successful. */ |
d751f32e | 369 | return (0); |
984263bc MD |
370 | } |
371 | ||
372 | /* | |
d751f32e MD |
373 | * Post driver attachment, we may want to perform some global actions. |
374 | * Here is the hook to do so. | |
984263bc | 375 | */ |
d751f32e MD |
376 | |
377 | static void | |
378 | mpt_postattach(void *unused) | |
984263bc | 379 | { |
d751f32e MD |
380 | struct mpt_softc *mpt; |
381 | struct mpt_personality *pers; | |
984263bc | 382 | |
d751f32e MD |
383 | TAILQ_FOREACH(mpt, &mpt_tailq, links) { |
384 | MPT_PERS_FOREACH(mpt, pers) | |
385 | pers->ready(mpt); | |
984263bc | 386 | } |
d751f32e MD |
387 | } |
388 | SYSINIT(mptdev, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, mpt_postattach, NULL); | |
984263bc | 389 | |
d751f32e MD |
390 | /******************************* Bus DMA Support ******************************/ |
391 | void | |
392 | mpt_map_rquest(void *arg, bus_dma_segment_t *segs, int nseg, int error) | |
393 | { | |
394 | struct mpt_map_info *map_info; | |
984263bc | 395 | |
d751f32e MD |
396 | map_info = (struct mpt_map_info *)arg; |
397 | map_info->error = error; | |
398 | map_info->phys = segs->ds_addr; | |
399 | } | |
984263bc | 400 | |
d751f32e MD |
401 | /**************************** Reply/Event Handling ****************************/ |
402 | int | |
403 | mpt_register_handler(struct mpt_softc *mpt, mpt_handler_type type, | |
404 | mpt_handler_t handler, uint32_t *phandler_id) | |
405 | { | |
984263bc | 406 | |
d751f32e MD |
407 | switch (type) { |
408 | case MPT_HANDLER_REPLY: | |
409 | { | |
410 | u_int cbi; | |
411 | u_int free_cbi; | |
412 | ||
413 | if (phandler_id == NULL) | |
414 | return (EINVAL); | |
415 | ||
416 | free_cbi = MPT_HANDLER_ID_NONE; | |
417 | for (cbi = 0; cbi < MPT_NUM_REPLY_HANDLERS; cbi++) { | |
418 | /* | |
419 | * If the same handler is registered multiple | |
420 | * times, don't error out. Just return the | |
421 | * index of the original registration. | |
422 | */ | |
423 | if (mpt_reply_handlers[cbi] == handler.reply_handler) { | |
424 | *phandler_id = MPT_CBI_TO_HID(cbi); | |
425 | return (0); | |
426 | } | |
984263bc | 427 | |
d751f32e MD |
428 | /* |
429 | * Fill from the front in the hope that | |
430 | * all registered handlers consume only a | |
431 | * single cache line. | |
432 | * | |
433 | * We don't break on the first empty slot so | |
434 | * that the full table is checked to see if | |
435 | * this handler was previously registered. | |
436 | */ | |
437 | if (free_cbi == MPT_HANDLER_ID_NONE && | |
438 | (mpt_reply_handlers[cbi] | |
439 | == mpt_default_reply_handler)) | |
440 | free_cbi = cbi; | |
984263bc | 441 | } |
d751f32e MD |
442 | if (free_cbi == MPT_HANDLER_ID_NONE) { |
443 | return (ENOMEM); | |
444 | } | |
445 | mpt_reply_handlers[free_cbi] = handler.reply_handler; | |
446 | *phandler_id = MPT_CBI_TO_HID(free_cbi); | |
447 | break; | |
984263bc | 448 | } |
d751f32e MD |
449 | default: |
450 | mpt_prt(mpt, "mpt_register_handler unknown type %d\n", type); | |
451 | return (EINVAL); | |
452 | } | |
453 | return (0); | |
984263bc MD |
454 | } |
455 | ||
984263bc | 456 | int |
d751f32e MD |
457 | mpt_deregister_handler(struct mpt_softc *mpt, mpt_handler_type type, |
458 | mpt_handler_t handler, uint32_t handler_id) | |
984263bc | 459 | { |
984263bc | 460 | |
d751f32e MD |
461 | switch (type) { |
462 | case MPT_HANDLER_REPLY: | |
463 | { | |
464 | u_int cbi; | |
984263bc | 465 | |
d751f32e MD |
466 | cbi = MPT_CBI(handler_id); |
467 | if (cbi >= MPT_NUM_REPLY_HANDLERS | |
468 | || mpt_reply_handlers[cbi] != handler.reply_handler) | |
469 | return (ENOENT); | |
470 | mpt_reply_handlers[cbi] = mpt_default_reply_handler; | |
471 | break; | |
984263bc | 472 | } |
d751f32e MD |
473 | default: |
474 | mpt_prt(mpt, "mpt_deregister_handler unknown type %d\n", type); | |
475 | return (EINVAL); | |
984263bc | 476 | } |
d751f32e MD |
477 | return (0); |
478 | } | |
984263bc | 479 | |
d751f32e MD |
480 | static int |
481 | mpt_default_reply_handler(struct mpt_softc *mpt, request_t *req, | |
482 | uint32_t reply_desc, MSG_DEFAULT_REPLY *reply_frame) | |
483 | { | |
4c42baf4 | 484 | |
d751f32e MD |
485 | mpt_prt(mpt, |
486 | "Default Handler Called: req=%p:%u reply_descriptor=%x frame=%p\n", | |
487 | req, req->serno, reply_desc, reply_frame); | |
984263bc | 488 | |
d751f32e MD |
489 | if (reply_frame != NULL) |
490 | mpt_dump_reply_frame(mpt, reply_frame); | |
984263bc | 491 | |
d751f32e | 492 | mpt_prt(mpt, "Reply Frame Ignored\n"); |
984263bc | 493 | |
d751f32e MD |
494 | return (/*free_reply*/TRUE); |
495 | } | |
984263bc | 496 | |
d751f32e MD |
497 | static int |
498 | mpt_config_reply_handler(struct mpt_softc *mpt, request_t *req, | |
499 | uint32_t reply_desc, MSG_DEFAULT_REPLY *reply_frame) | |
500 | { | |
d751f32e | 501 | |
4c42baf4 | 502 | if (req != NULL) { |
d751f32e MD |
503 | if (reply_frame != NULL) { |
504 | MSG_CONFIG *cfgp; | |
505 | MSG_CONFIG_REPLY *reply; | |
506 | ||
507 | cfgp = (MSG_CONFIG *)req->req_vbuf; | |
508 | reply = (MSG_CONFIG_REPLY *)reply_frame; | |
509 | req->IOCStatus = le16toh(reply_frame->IOCStatus); | |
510 | bcopy(&reply->Header, &cfgp->Header, | |
511 | sizeof(cfgp->Header)); | |
512 | cfgp->ExtPageLength = reply->ExtPageLength; | |
513 | cfgp->ExtPageType = reply->ExtPageType; | |
514 | } | |
515 | req->state &= ~REQ_STATE_QUEUED; | |
516 | req->state |= REQ_STATE_DONE; | |
517 | TAILQ_REMOVE(&mpt->request_pending_list, req, links); | |
518 | if ((req->state & REQ_STATE_NEED_WAKEUP) != 0) { | |
519 | wakeup(req); | |
520 | } else if ((req->state & REQ_STATE_TIMEDOUT) != 0) { | |
521 | /* | |
522 | * Whew- we can free this request (late completion) | |
523 | */ | |
524 | mpt_free_request(mpt, req); | |
525 | } | |
526 | } | |
527 | ||
528 | return (TRUE); | |
529 | } | |
530 | ||
531 | static int | |
532 | mpt_handshake_reply_handler(struct mpt_softc *mpt, request_t *req, | |
533 | uint32_t reply_desc, MSG_DEFAULT_REPLY *reply_frame) | |
534 | { | |
4c42baf4 | 535 | |
d751f32e MD |
536 | /* Nothing to be done. */ |
537 | return (TRUE); | |
538 | } | |
539 | ||
540 | static int | |
541 | mpt_event_reply_handler(struct mpt_softc *mpt, request_t *req, | |
542 | uint32_t reply_desc, MSG_DEFAULT_REPLY *reply_frame) | |
543 | { | |
544 | int free_reply; | |
545 | ||
546 | KASSERT(reply_frame != NULL, ("null reply in mpt_event_reply_handler")); | |
547 | KASSERT(req != NULL, ("null request in mpt_event_reply_handler")); | |
548 | ||
549 | free_reply = TRUE; | |
550 | switch (reply_frame->Function) { | |
551 | case MPI_FUNCTION_EVENT_NOTIFICATION: | |
552 | { | |
553 | MSG_EVENT_NOTIFY_REPLY *msg; | |
554 | struct mpt_personality *pers; | |
555 | u_int handled; | |
556 | ||
557 | handled = 0; | |
558 | msg = (MSG_EVENT_NOTIFY_REPLY *)reply_frame; | |
559 | msg->EventDataLength = le16toh(msg->EventDataLength); | |
560 | msg->IOCStatus = le16toh(msg->IOCStatus); | |
561 | msg->IOCLogInfo = le32toh(msg->IOCLogInfo); | |
562 | msg->Event = le32toh(msg->Event); | |
563 | MPT_PERS_FOREACH(mpt, pers) | |
564 | handled += pers->event(mpt, req, msg); | |
565 | ||
566 | if (handled == 0 && mpt->mpt_pers_mask == 0) { | |
567 | mpt_lprt(mpt, MPT_PRT_INFO, | |
568 | "No Handlers For Any Event Notify Frames. " | |
569 | "Event %#x (ACK %sequired).\n", | |
6d259fc1 | 570 | msg->Event, msg->AckRequired? "r" : "not r"); |
d751f32e MD |
571 | } else if (handled == 0) { |
572 | mpt_lprt(mpt, | |
573 | msg->AckRequired? MPT_PRT_WARN : MPT_PRT_INFO, | |
574 | "Unhandled Event Notify Frame. Event %#x " | |
575 | "(ACK %sequired).\n", | |
6d259fc1 | 576 | msg->Event, msg->AckRequired? "r" : "not r"); |
d751f32e MD |
577 | } |
578 | ||
579 | if (msg->AckRequired) { | |
580 | request_t *ack_req; | |
581 | uint32_t context; | |
582 | ||
583 | context = req->index | MPT_REPLY_HANDLER_EVENTS; | |
584 | ack_req = mpt_get_request(mpt, FALSE); | |
585 | if (ack_req == NULL) { | |
586 | struct mpt_evtf_record *evtf; | |
587 | ||
588 | evtf = (struct mpt_evtf_record *)reply_frame; | |
589 | evtf->context = context; | |
590 | LIST_INSERT_HEAD(&mpt->ack_frames, evtf, links); | |
591 | free_reply = FALSE; | |
592 | break; | |
593 | } | |
594 | mpt_send_event_ack(mpt, ack_req, msg, context); | |
595 | /* | |
596 | * Don't check for CONTINUATION_REPLY here | |
597 | */ | |
598 | return (free_reply); | |
599 | } | |
600 | break; | |
601 | } | |
602 | case MPI_FUNCTION_PORT_ENABLE: | |
603 | mpt_lprt(mpt, MPT_PRT_DEBUG , "enable port reply\n"); | |
604 | break; | |
605 | case MPI_FUNCTION_EVENT_ACK: | |
606 | break; | |
607 | default: | |
608 | mpt_prt(mpt, "unknown event function: %x\n", | |
609 | reply_frame->Function); | |
610 | break; | |
611 | } | |
612 | ||
613 | /* | |
614 | * I'm not sure that this continuation stuff works as it should. | |
615 | * | |
616 | * I've had FC async events occur that free the frame up because | |
617 | * the continuation bit isn't set, and then additional async events | |
618 | * then occur using the same context. As you might imagine, this | |
619 | * leads to Very Bad Thing. | |
620 | * | |
621 | * Let's just be safe for now and not free them up until we figure | |
622 | * out what's actually happening here. | |
623 | */ | |
624 | #if 0 | |
625 | if ((reply_frame->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY) == 0) { | |
626 | TAILQ_REMOVE(&mpt->request_pending_list, req, links); | |
627 | mpt_free_request(mpt, req); | |
628 | mpt_prt(mpt, "event_reply %x for req %p:%u NOT a continuation", | |
629 | reply_frame->Function, req, req->serno); | |
630 | if (reply_frame->Function == MPI_FUNCTION_EVENT_NOTIFICATION) { | |
631 | MSG_EVENT_NOTIFY_REPLY *msg = | |
632 | (MSG_EVENT_NOTIFY_REPLY *)reply_frame; | |
633 | mpt_prtc(mpt, " Event=0x%x AckReq=%d", | |
634 | msg->Event, msg->AckRequired); | |
635 | } | |
636 | } else { | |
637 | mpt_prt(mpt, "event_reply %x for %p:%u IS a continuation", | |
638 | reply_frame->Function, req, req->serno); | |
639 | if (reply_frame->Function == MPI_FUNCTION_EVENT_NOTIFICATION) { | |
640 | MSG_EVENT_NOTIFY_REPLY *msg = | |
641 | (MSG_EVENT_NOTIFY_REPLY *)reply_frame; | |
642 | mpt_prtc(mpt, " Event=0x%x AckReq=%d", | |
643 | msg->Event, msg->AckRequired); | |
644 | } | |
645 | mpt_prtc(mpt, "\n"); | |
646 | } | |
647 | #endif | |
648 | return (free_reply); | |
649 | } | |
650 | ||
651 | /* | |
652 | * Process an asynchronous event from the IOC. | |
653 | */ | |
654 | static int | |
655 | mpt_core_event(struct mpt_softc *mpt, request_t *req, | |
656 | MSG_EVENT_NOTIFY_REPLY *msg) | |
657 | { | |
4c42baf4 | 658 | |
d751f32e | 659 | mpt_lprt(mpt, MPT_PRT_DEBUG, "mpt_core_event: 0x%x\n", |
6d259fc1 | 660 | msg->Event & 0xFF); |
d751f32e MD |
661 | switch(msg->Event & 0xFF) { |
662 | case MPI_EVENT_NONE: | |
663 | break; | |
664 | case MPI_EVENT_LOG_DATA: | |
665 | { | |
666 | int i; | |
667 | ||
6d259fc1 | 668 | /* Some error occurred that LSI wants logged */ |
d751f32e | 669 | mpt_prt(mpt, "EvtLogData: IOCLogInfo: 0x%08x\n", |
6d259fc1 | 670 | msg->IOCLogInfo); |
d751f32e MD |
671 | mpt_prt(mpt, "\tEvtLogData: Event Data:"); |
672 | for (i = 0; i < msg->EventDataLength; i++) | |
6d259fc1 | 673 | mpt_prtc(mpt, " %08x", msg->Data[i]); |
d751f32e MD |
674 | mpt_prtc(mpt, "\n"); |
675 | break; | |
676 | } | |
677 | case MPI_EVENT_EVENT_CHANGE: | |
678 | /* | |
679 | * This is just an acknowledgement | |
680 | * of our mpt_send_event_request. | |
681 | */ | |
682 | break; | |
683 | case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE: | |
684 | break; | |
685 | default: | |
686 | return (0); | |
687 | break; | |
688 | } | |
689 | return (1); | |
690 | } | |
691 | ||
692 | static void | |
693 | mpt_send_event_ack(struct mpt_softc *mpt, request_t *ack_req, | |
694 | MSG_EVENT_NOTIFY_REPLY *msg, uint32_t context) | |
695 | { | |
696 | MSG_EVENT_ACK *ackp; | |
697 | ||
698 | ackp = (MSG_EVENT_ACK *)ack_req->req_vbuf; | |
699 | memset(ackp, 0, sizeof (*ackp)); | |
700 | ackp->Function = MPI_FUNCTION_EVENT_ACK; | |
701 | ackp->Event = htole32(msg->Event); | |
702 | ackp->EventContext = htole32(msg->EventContext); | |
703 | ackp->MsgContext = htole32(context); | |
704 | mpt_check_doorbell(mpt); | |
705 | mpt_send_cmd(mpt, ack_req); | |
706 | } | |
707 | ||
708 | /***************************** Interrupt Handling *****************************/ | |
709 | void | |
710 | mpt_intr(void *arg) | |
711 | { | |
712 | struct mpt_softc *mpt; | |
713 | uint32_t reply_desc; | |
714 | int ntrips = 0; | |
715 | ||
716 | mpt = (struct mpt_softc *)arg; | |
717 | mpt_lprt(mpt, MPT_PRT_DEBUG2, "enter mpt_intr\n"); | |
718 | MPT_LOCK_ASSERT(mpt); | |
719 | ||
720 | while ((reply_desc = mpt_pop_reply_queue(mpt)) != MPT_REPLY_EMPTY) { | |
721 | request_t *req; | |
722 | MSG_DEFAULT_REPLY *reply_frame; | |
723 | uint32_t reply_baddr; | |
724 | uint32_t ctxt_idx; | |
725 | u_int cb_index; | |
726 | u_int req_index; | |
6d259fc1 | 727 | u_int offset; |
d751f32e MD |
728 | int free_rf; |
729 | ||
730 | req = NULL; | |
731 | reply_frame = NULL; | |
732 | reply_baddr = 0; | |
6d259fc1 | 733 | offset = 0; |
d751f32e | 734 | if ((reply_desc & MPI_ADDRESS_REPLY_A_BIT) != 0) { |
d751f32e | 735 | /* |
6d259fc1 | 736 | * Ensure that the reply frame is coherent. |
d751f32e MD |
737 | */ |
738 | reply_baddr = MPT_REPLY_BADDR(reply_desc); | |
739 | offset = reply_baddr - (mpt->reply_phys & 0xFFFFFFFF); | |
740 | bus_dmamap_sync_range(mpt->reply_dmat, | |
741 | mpt->reply_dmap, offset, MPT_REPLY_SIZE, | |
742 | BUS_DMASYNC_POSTREAD); | |
743 | reply_frame = MPT_REPLY_OTOV(mpt, offset); | |
744 | ctxt_idx = le32toh(reply_frame->MsgContext); | |
745 | } else { | |
746 | uint32_t type; | |
747 | ||
748 | type = MPI_GET_CONTEXT_REPLY_TYPE(reply_desc); | |
749 | ctxt_idx = reply_desc; | |
750 | mpt_lprt(mpt, MPT_PRT_DEBUG1, "Context Reply: 0x%08x\n", | |
751 | reply_desc); | |
752 | ||
753 | switch (type) { | |
754 | case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT: | |
755 | ctxt_idx &= MPI_CONTEXT_REPLY_CONTEXT_MASK; | |
756 | break; | |
757 | case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET: | |
758 | ctxt_idx = GET_IO_INDEX(reply_desc); | |
759 | if (mpt->tgt_cmd_ptrs == NULL) { | |
760 | mpt_prt(mpt, | |
761 | "mpt_intr: no target cmd ptrs\n"); | |
762 | reply_desc = MPT_REPLY_EMPTY; | |
763 | break; | |
764 | } | |
765 | if (ctxt_idx >= mpt->tgt_cmds_allocated) { | |
766 | mpt_prt(mpt, | |
767 | "mpt_intr: bad tgt cmd ctxt %u\n", | |
768 | ctxt_idx); | |
769 | reply_desc = MPT_REPLY_EMPTY; | |
770 | ntrips = 1000; | |
771 | break; | |
772 | } | |
773 | req = mpt->tgt_cmd_ptrs[ctxt_idx]; | |
774 | if (req == NULL) { | |
775 | mpt_prt(mpt, "no request backpointer " | |
776 | "at index %u", ctxt_idx); | |
777 | reply_desc = MPT_REPLY_EMPTY; | |
778 | ntrips = 1000; | |
779 | break; | |
780 | } | |
781 | /* | |
782 | * Reformulate ctxt_idx to be just as if | |
783 | * it were another type of context reply | |
784 | * so the code below will find the request | |
785 | * via indexing into the pool. | |
786 | */ | |
787 | ctxt_idx = | |
788 | req->index | mpt->scsi_tgt_handler_id; | |
789 | req = NULL; | |
790 | break; | |
791 | case MPI_CONTEXT_REPLY_TYPE_LAN: | |
792 | mpt_prt(mpt, "LAN CONTEXT REPLY: 0x%08x\n", | |
793 | reply_desc); | |
794 | reply_desc = MPT_REPLY_EMPTY; | |
795 | break; | |
796 | default: | |
797 | mpt_prt(mpt, "Context Reply 0x%08x?\n", type); | |
798 | reply_desc = MPT_REPLY_EMPTY; | |
799 | break; | |
800 | } | |
801 | if (reply_desc == MPT_REPLY_EMPTY) { | |
802 | if (ntrips++ > 1000) { | |
803 | break; | |
804 | } | |
805 | continue; | |
806 | } | |
807 | } | |
808 | ||
809 | cb_index = MPT_CONTEXT_TO_CBI(ctxt_idx); | |
810 | req_index = MPT_CONTEXT_TO_REQI(ctxt_idx); | |
811 | if (req_index < MPT_MAX_REQUESTS(mpt)) { | |
812 | req = &mpt->request_pool[req_index]; | |
813 | } else { | |
814 | mpt_prt(mpt, "WARN: mpt_intr index == %d (reply_desc ==" | |
815 | " 0x%x)\n", req_index, reply_desc); | |
816 | } | |
817 | ||
6d259fc1 SW |
818 | bus_dmamap_sync(mpt->request_dmat, mpt->request_dmap, |
819 | BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); | |
d751f32e MD |
820 | free_rf = mpt_reply_handlers[cb_index](mpt, req, |
821 | reply_desc, reply_frame); | |
822 | ||
823 | if (reply_frame != NULL && free_rf) { | |
6d259fc1 SW |
824 | bus_dmamap_sync_range(mpt->reply_dmat, |
825 | mpt->reply_dmap, offset, MPT_REPLY_SIZE, | |
826 | BUS_DMASYNC_PREREAD); | |
d751f32e MD |
827 | mpt_free_reply(mpt, reply_baddr); |
828 | } | |
829 | ||
830 | /* | |
831 | * If we got ourselves disabled, don't get stuck in a loop | |
832 | */ | |
833 | if (mpt->disabled) { | |
834 | mpt_disable_ints(mpt); | |
835 | break; | |
836 | } | |
837 | if (ntrips++ > 1000) { | |
838 | break; | |
839 | } | |
840 | } | |
841 | mpt_lprt(mpt, MPT_PRT_DEBUG2, "exit mpt_intr\n"); | |
842 | } | |
843 | ||
844 | /******************************* Error Recovery *******************************/ | |
845 | void | |
846 | mpt_complete_request_chain(struct mpt_softc *mpt, struct req_queue *chain, | |
847 | u_int iocstatus) | |
848 | { | |
849 | MSG_DEFAULT_REPLY ioc_status_frame; | |
850 | request_t *req; | |
851 | ||
852 | memset(&ioc_status_frame, 0, sizeof(ioc_status_frame)); | |
853 | ioc_status_frame.MsgLength = roundup2(sizeof(ioc_status_frame), 4); | |
854 | ioc_status_frame.IOCStatus = iocstatus; | |
855 | while((req = TAILQ_FIRST(chain)) != NULL) { | |
856 | MSG_REQUEST_HEADER *msg_hdr; | |
857 | u_int cb_index; | |
858 | ||
6d259fc1 SW |
859 | bus_dmamap_sync(mpt->request_dmat, mpt->request_dmap, |
860 | BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); | |
d751f32e MD |
861 | msg_hdr = (MSG_REQUEST_HEADER *)req->req_vbuf; |
862 | ioc_status_frame.Function = msg_hdr->Function; | |
863 | ioc_status_frame.MsgContext = msg_hdr->MsgContext; | |
864 | cb_index = MPT_CONTEXT_TO_CBI(le32toh(msg_hdr->MsgContext)); | |
865 | mpt_reply_handlers[cb_index](mpt, req, msg_hdr->MsgContext, | |
866 | &ioc_status_frame); | |
6d259fc1 SW |
867 | if (mpt_req_on_pending_list(mpt, req) != 0) |
868 | TAILQ_REMOVE(chain, req, links); | |
d751f32e MD |
869 | } |
870 | } | |
871 | ||
872 | /********************************* Diagnostics ********************************/ | |
873 | /* | |
874 | * Perform a diagnostic dump of a reply frame. | |
875 | */ | |
876 | void | |
877 | mpt_dump_reply_frame(struct mpt_softc *mpt, MSG_DEFAULT_REPLY *reply_frame) | |
878 | { | |
4c42baf4 | 879 | |
d751f32e MD |
880 | mpt_prt(mpt, "Address Reply:\n"); |
881 | mpt_print_reply(reply_frame); | |
882 | } | |
883 | ||
884 | /******************************* Doorbell Access ******************************/ | |
885 | static __inline uint32_t mpt_rd_db(struct mpt_softc *mpt); | |
886 | static __inline uint32_t mpt_rd_intr(struct mpt_softc *mpt); | |
887 | ||
888 | static __inline uint32_t | |
889 | mpt_rd_db(struct mpt_softc *mpt) | |
890 | { | |
4c42baf4 | 891 | |
d751f32e MD |
892 | return mpt_read(mpt, MPT_OFFSET_DOORBELL); |
893 | } | |
894 | ||
895 | static __inline uint32_t | |
896 | mpt_rd_intr(struct mpt_softc *mpt) | |
897 | { | |
4c42baf4 | 898 | |
d751f32e MD |
899 | return mpt_read(mpt, MPT_OFFSET_INTR_STATUS); |
900 | } | |
901 | ||
902 | /* Busy wait for a door bell to be read by IOC */ | |
903 | static int | |
904 | mpt_wait_db_ack(struct mpt_softc *mpt) | |
905 | { | |
906 | int i; | |
4c42baf4 | 907 | |
d751f32e MD |
908 | for (i=0; i < MPT_MAX_WAIT; i++) { |
909 | if (!MPT_DB_IS_BUSY(mpt_rd_intr(mpt))) { | |
910 | maxwait_ack = i > maxwait_ack ? i : maxwait_ack; | |
911 | return (MPT_OK); | |
912 | } | |
913 | DELAY(200); | |
914 | } | |
915 | return (MPT_FAIL); | |
916 | } | |
917 | ||
918 | /* Busy wait for a door bell interrupt */ | |
919 | static int | |
920 | mpt_wait_db_int(struct mpt_softc *mpt) | |
921 | { | |
922 | int i; | |
4c42baf4 | 923 | |
d751f32e MD |
924 | for (i = 0; i < MPT_MAX_WAIT; i++) { |
925 | if (MPT_DB_INTR(mpt_rd_intr(mpt))) { | |
926 | maxwait_int = i > maxwait_int ? i : maxwait_int; | |
927 | return MPT_OK; | |
928 | } | |
929 | DELAY(100); | |
930 | } | |
931 | return (MPT_FAIL); | |
932 | } | |
933 | ||
934 | /* Wait for IOC to transition to a give state */ | |
935 | void | |
936 | mpt_check_doorbell(struct mpt_softc *mpt) | |
937 | { | |
938 | uint32_t db = mpt_rd_db(mpt); | |
4c42baf4 | 939 | |
d751f32e MD |
940 | if (MPT_STATE(db) != MPT_DB_STATE_RUNNING) { |
941 | mpt_prt(mpt, "Device not running\n"); | |
942 | mpt_print_db(db); | |
943 | } | |
944 | } | |
945 | ||
946 | /* Wait for IOC to transition to a give state */ | |
947 | static int | |
948 | mpt_wait_state(struct mpt_softc *mpt, enum DB_STATE_BITS state) | |
949 | { | |
950 | int i; | |
951 | ||
952 | for (i = 0; i < MPT_MAX_WAIT; i++) { | |
953 | uint32_t db = mpt_rd_db(mpt); | |
954 | if (MPT_STATE(db) == state) { | |
955 | maxwait_state = i > maxwait_state ? i : maxwait_state; | |
956 | return (MPT_OK); | |
957 | } | |
958 | DELAY(100); | |
959 | } | |
960 | return (MPT_FAIL); | |
961 | } | |
962 | ||
963 | ||
964 | /************************* Intialization/Configuration ************************/ | |
965 | static int mpt_download_fw(struct mpt_softc *mpt); | |
966 | ||
967 | /* Issue the reset COMMAND to the IOC */ | |
968 | static int | |
969 | mpt_soft_reset(struct mpt_softc *mpt) | |
970 | { | |
4c42baf4 | 971 | |
d751f32e MD |
972 | mpt_lprt(mpt, MPT_PRT_DEBUG, "soft reset\n"); |
973 | ||
974 | /* Have to use hard reset if we are not in Running state */ | |
975 | if (MPT_STATE(mpt_rd_db(mpt)) != MPT_DB_STATE_RUNNING) { | |
976 | mpt_prt(mpt, "soft reset failed: device not running\n"); | |
977 | return (MPT_FAIL); | |
978 | } | |
979 | ||
980 | /* If door bell is in use we don't have a chance of getting | |
981 | * a word in since the IOC probably crashed in message | |
982 | * processing. So don't waste our time. | |
983 | */ | |
984 | if (MPT_DB_IS_IN_USE(mpt_rd_db(mpt))) { | |
985 | mpt_prt(mpt, "soft reset failed: doorbell wedged\n"); | |
986 | return (MPT_FAIL); | |
987 | } | |
988 | ||
989 | /* Send the reset request to the IOC */ | |
990 | mpt_write(mpt, MPT_OFFSET_DOORBELL, | |
991 | MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET << MPI_DOORBELL_FUNCTION_SHIFT); | |
992 | if (mpt_wait_db_ack(mpt) != MPT_OK) { | |
993 | mpt_prt(mpt, "soft reset failed: ack timeout\n"); | |
994 | return (MPT_FAIL); | |
995 | } | |
996 | ||
997 | /* Wait for the IOC to reload and come out of reset state */ | |
998 | if (mpt_wait_state(mpt, MPT_DB_STATE_READY) != MPT_OK) { | |
999 | mpt_prt(mpt, "soft reset failed: device did not restart\n"); | |
1000 | return (MPT_FAIL); | |
1001 | } | |
1002 | ||
1003 | return MPT_OK; | |
1004 | } | |
1005 | ||
1006 | static int | |
1007 | mpt_enable_diag_mode(struct mpt_softc *mpt) | |
1008 | { | |
1009 | int try; | |
1010 | ||
1011 | try = 20; | |
1012 | while (--try) { | |
1013 | ||
1014 | if ((mpt_read(mpt, MPT_OFFSET_DIAGNOSTIC) & MPI_DIAG_DRWE) != 0) | |
1015 | break; | |
1016 | ||
1017 | /* Enable diagnostic registers */ | |
1018 | mpt_write(mpt, MPT_OFFSET_SEQUENCE, 0xFF); | |
1019 | mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_1ST_KEY_VALUE); | |
1020 | mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_2ND_KEY_VALUE); | |
1021 | mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_3RD_KEY_VALUE); | |
1022 | mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_4TH_KEY_VALUE); | |
1023 | mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_5TH_KEY_VALUE); | |
1024 | ||
1025 | DELAY(100000); | |
1026 | } | |
1027 | if (try == 0) | |
1028 | return (EIO); | |
1029 | return (0); | |
1030 | } | |
1031 | ||
1032 | static void | |
1033 | mpt_disable_diag_mode(struct mpt_softc *mpt) | |
1034 | { | |
4c42baf4 | 1035 | |
d751f32e MD |
1036 | mpt_write(mpt, MPT_OFFSET_SEQUENCE, 0xFFFFFFFF); |
1037 | } | |
1038 | ||
1039 | /* This is a magic diagnostic reset that resets all the ARM | |
1040 | * processors in the chip. | |
1041 | */ | |
1042 | static void | |
1043 | mpt_hard_reset(struct mpt_softc *mpt) | |
1044 | { | |
1045 | int error; | |
1046 | int wait; | |
1047 | uint32_t diagreg; | |
1048 | ||
1049 | mpt_lprt(mpt, MPT_PRT_DEBUG, "hard reset\n"); | |
1050 | ||
4c42baf4 SW |
1051 | if (mpt->is_1078) { |
1052 | mpt_write(mpt, MPT_OFFSET_RESET_1078, 0x07); | |
1053 | DELAY(1000); | |
1054 | return; | |
1055 | } | |
1056 | ||
d751f32e MD |
1057 | error = mpt_enable_diag_mode(mpt); |
1058 | if (error) { | |
1059 | mpt_prt(mpt, "WARNING - Could not enter diagnostic mode !\n"); | |
1060 | mpt_prt(mpt, "Trying to reset anyway.\n"); | |
1061 | } | |
1062 | ||
1063 | diagreg = mpt_read(mpt, MPT_OFFSET_DIAGNOSTIC); | |
1064 | ||
1065 | /* | |
1066 | * This appears to be a workaround required for some | |
1067 | * firmware or hardware revs. | |
1068 | */ | |
1069 | mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, diagreg | MPI_DIAG_DISABLE_ARM); | |
1070 | DELAY(1000); | |
1071 | ||
1072 | /* Diag. port is now active so we can now hit the reset bit */ | |
1073 | mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, diagreg | MPI_DIAG_RESET_ADAPTER); | |
1074 | ||
1075 | /* | |
1076 | * Ensure that the reset has finished. We delay 1ms | |
1077 | * prior to reading the register to make sure the chip | |
1078 | * has sufficiently completed its reset to handle register | |
1079 | * accesses. | |
1080 | */ | |
1081 | wait = 5000; | |
1082 | do { | |
1083 | DELAY(1000); | |
1084 | diagreg = mpt_read(mpt, MPT_OFFSET_DIAGNOSTIC); | |
1085 | } while (--wait && (diagreg & MPI_DIAG_RESET_ADAPTER) == 0); | |
1086 | ||
1087 | if (wait == 0) { | |
1088 | mpt_prt(mpt, "WARNING - Failed hard reset! " | |
1089 | "Trying to initialize anyway.\n"); | |
1090 | } | |
1091 | ||
1092 | /* | |
1093 | * If we have firmware to download, it must be loaded before | |
1094 | * the controller will become operational. Do so now. | |
1095 | */ | |
1096 | if (mpt->fw_image != NULL) { | |
1097 | ||
1098 | error = mpt_download_fw(mpt); | |
1099 | ||
1100 | if (error) { | |
1101 | mpt_prt(mpt, "WARNING - Firmware Download Failed!\n"); | |
1102 | mpt_prt(mpt, "Trying to initialize anyway.\n"); | |
1103 | } | |
1104 | } | |
1105 | ||
1106 | /* | |
1107 | * Reseting the controller should have disabled write | |
1108 | * access to the diagnostic registers, but disable | |
1109 | * manually to be sure. | |
1110 | */ | |
1111 | mpt_disable_diag_mode(mpt); | |
1112 | } | |
1113 | ||
1114 | static void | |
1115 | mpt_core_ioc_reset(struct mpt_softc *mpt, int type) | |
1116 | { | |
4c42baf4 | 1117 | |
d751f32e MD |
1118 | /* |
1119 | * Complete all pending requests with a status | |
1120 | * appropriate for an IOC reset. | |
1121 | */ | |
1122 | mpt_complete_request_chain(mpt, &mpt->request_pending_list, | |
1123 | MPI_IOCSTATUS_INVALID_STATE); | |
1124 | } | |
1125 | ||
d751f32e MD |
1126 | /* |
1127 | * Reset the IOC when needed. Try software command first then if needed | |
1128 | * poke at the magic diagnostic reset. Note that a hard reset resets | |
1129 | * *both* IOCs on dual function chips (FC929 && LSI1030) as well as | |
1130 | * fouls up the PCI configuration registers. | |
1131 | */ | |
1132 | int | |
1133 | mpt_reset(struct mpt_softc *mpt, int reinit) | |
1134 | { | |
1135 | struct mpt_personality *pers; | |
1136 | int ret; | |
1137 | int retry_cnt = 0; | |
1138 | ||
1139 | /* | |
1140 | * Try a soft reset. If that fails, get out the big hammer. | |
1141 | */ | |
1142 | again: | |
1143 | if ((ret = mpt_soft_reset(mpt)) != MPT_OK) { | |
1144 | int cnt; | |
1145 | for (cnt = 0; cnt < 5; cnt++) { | |
1146 | /* Failed; do a hard reset */ | |
1147 | mpt_hard_reset(mpt); | |
1148 | ||
1149 | /* | |
1150 | * Wait for the IOC to reload | |
1151 | * and come out of reset state | |
1152 | */ | |
1153 | ret = mpt_wait_state(mpt, MPT_DB_STATE_READY); | |
1154 | if (ret == MPT_OK) { | |
1155 | break; | |
1156 | } | |
1157 | /* | |
1158 | * Okay- try to check again... | |
1159 | */ | |
1160 | ret = mpt_wait_state(mpt, MPT_DB_STATE_READY); | |
1161 | if (ret == MPT_OK) { | |
1162 | break; | |
1163 | } | |
1164 | mpt_prt(mpt, "mpt_reset: failed hard reset (%d:%d)\n", | |
1165 | retry_cnt, cnt); | |
1166 | } | |
1167 | } | |
1168 | ||
1169 | if (retry_cnt == 0) { | |
1170 | /* | |
1171 | * Invoke reset handlers. We bump the reset count so | |
1172 | * that mpt_wait_req() understands that regardless of | |
1173 | * the specified wait condition, it should stop its wait. | |
1174 | */ | |
1175 | mpt->reset_cnt++; | |
1176 | MPT_PERS_FOREACH(mpt, pers) | |
1177 | pers->reset(mpt, ret); | |
1178 | } | |
1179 | ||
1180 | if (reinit) { | |
1181 | ret = mpt_enable_ioc(mpt, 1); | |
1182 | if (ret == MPT_OK) { | |
1183 | mpt_enable_ints(mpt); | |
1184 | } | |
1185 | } | |
1186 | if (ret != MPT_OK && retry_cnt++ < 2) { | |
1187 | goto again; | |
1188 | } | |
1189 | return ret; | |
1190 | } | |
1191 | ||
1192 | /* Return a command buffer to the free queue */ | |
1193 | void | |
1194 | mpt_free_request(struct mpt_softc *mpt, request_t *req) | |
1195 | { | |
1196 | request_t *nxt; | |
1197 | struct mpt_evtf_record *record; | |
6d259fc1 | 1198 | uint32_t offset, reply_baddr; |
d751f32e MD |
1199 | |
1200 | if (req == NULL || req != &mpt->request_pool[req->index]) { | |
4c42baf4 | 1201 | panic("mpt_free_request: bad req ptr"); |
d751f32e MD |
1202 | } |
1203 | if ((nxt = req->chain) != NULL) { | |
1204 | req->chain = NULL; | |
1205 | mpt_free_request(mpt, nxt); /* NB: recursion */ | |
1206 | } | |
1207 | KASSERT(req->state != REQ_STATE_FREE, ("freeing free request")); | |
1208 | KASSERT(!(req->state & REQ_STATE_LOCKED), ("freeing locked request")); | |
1209 | MPT_LOCK_ASSERT(mpt); | |
1210 | KASSERT(mpt_req_on_free_list(mpt, req) == 0, | |
1211 | ("mpt_free_request: req %p:%u func %x already on freelist", | |
1212 | req, req->serno, ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); | |
1213 | KASSERT(mpt_req_on_pending_list(mpt, req) == 0, | |
1214 | ("mpt_free_request: req %p:%u func %x on pending list", | |
1215 | req, req->serno, ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); | |
1216 | #ifdef INVARIANTS | |
1217 | mpt_req_not_spcl(mpt, req, "mpt_free_request", __LINE__); | |
1218 | #endif | |
1219 | ||
1220 | req->ccb = NULL; | |
1221 | if (LIST_EMPTY(&mpt->ack_frames)) { | |
1222 | /* | |
1223 | * Insert free ones at the tail | |
1224 | */ | |
1225 | req->serno = 0; | |
1226 | req->state = REQ_STATE_FREE; | |
1227 | #ifdef INVARIANTS | |
1228 | memset(req->req_vbuf, 0xff, sizeof (MSG_REQUEST_HEADER)); | |
1229 | #endif | |
1230 | TAILQ_INSERT_TAIL(&mpt->request_free_list, req, links); | |
1231 | if (mpt->getreqwaiter != 0) { | |
1232 | mpt->getreqwaiter = 0; | |
1233 | wakeup(&mpt->request_free_list); | |
1234 | } | |
1235 | return; | |
1236 | } | |
1237 | ||
1238 | /* | |
1239 | * Process an ack frame deferred due to resource shortage. | |
1240 | */ | |
1241 | record = LIST_FIRST(&mpt->ack_frames); | |
1242 | LIST_REMOVE(record, links); | |
1243 | req->state = REQ_STATE_ALLOCATED; | |
1244 | mpt_assign_serno(mpt, req); | |
1245 | mpt_send_event_ack(mpt, req, &record->reply, record->context); | |
6d259fc1 SW |
1246 | offset = (uint32_t)((uint8_t *)record - mpt->reply); |
1247 | reply_baddr = offset + (mpt->reply_phys & 0xFFFFFFFF); | |
1248 | bus_dmamap_sync_range(mpt->reply_dmat, mpt->reply_dmap, offset, | |
1249 | MPT_REPLY_SIZE, BUS_DMASYNC_PREREAD); | |
d751f32e MD |
1250 | mpt_free_reply(mpt, reply_baddr); |
1251 | } | |
1252 | ||
1253 | /* Get a command buffer from the free queue */ | |
1254 | request_t * | |
1255 | mpt_get_request(struct mpt_softc *mpt, int sleep_ok) | |
1256 | { | |
1257 | request_t *req; | |
1258 | ||
1259 | retry: | |
1260 | MPT_LOCK_ASSERT(mpt); | |
1261 | req = TAILQ_FIRST(&mpt->request_free_list); | |
1262 | if (req != NULL) { | |
1263 | KASSERT(req == &mpt->request_pool[req->index], | |
4c42baf4 | 1264 | ("mpt_get_request: corrupted request free list")); |
d751f32e MD |
1265 | KASSERT(req->state == REQ_STATE_FREE, |
1266 | ("req %p:%u not free on free list %x index %d function %x", | |
1267 | req, req->serno, req->state, req->index, | |
1268 | ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); | |
1269 | TAILQ_REMOVE(&mpt->request_free_list, req, links); | |
1270 | req->state = REQ_STATE_ALLOCATED; | |
1271 | req->chain = NULL; | |
1272 | mpt_assign_serno(mpt, req); | |
d751f32e MD |
1273 | } else if (sleep_ok != 0) { |
1274 | mpt->getreqwaiter = 1; | |
6d259fc1 | 1275 | mpt_sleep(mpt, &mpt->request_free_list, 0, "mptgreq", 0); |
d751f32e MD |
1276 | goto retry; |
1277 | } | |
1278 | return (req); | |
1279 | } | |
1280 | ||
1281 | /* Pass the command to the IOC */ | |
1282 | void | |
1283 | mpt_send_cmd(struct mpt_softc *mpt, request_t *req) | |
1284 | { | |
4c42baf4 | 1285 | |
d751f32e MD |
1286 | if (mpt->verbose > MPT_PRT_DEBUG2) { |
1287 | mpt_dump_request(mpt, req); | |
1288 | } | |
1289 | bus_dmamap_sync(mpt->request_dmat, mpt->request_dmap, | |
6d259fc1 | 1290 | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); |
d751f32e MD |
1291 | req->state |= REQ_STATE_QUEUED; |
1292 | KASSERT(mpt_req_on_free_list(mpt, req) == 0, | |
1293 | ("req %p:%u func %x on freelist list in mpt_send_cmd", | |
1294 | req, req->serno, ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); | |
1295 | KASSERT(mpt_req_on_pending_list(mpt, req) == 0, | |
1296 | ("req %p:%u func %x already on pending list in mpt_send_cmd", | |
1297 | req, req->serno, ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); | |
1298 | TAILQ_INSERT_HEAD(&mpt->request_pending_list, req, links); | |
1299 | mpt_write(mpt, MPT_OFFSET_REQUEST_Q, (uint32_t) req->req_pbuf); | |
1300 | } | |
1301 | ||
1302 | /* | |
1303 | * Wait for a request to complete. | |
1304 | * | |
1305 | * Inputs: | |
1306 | * mpt softc of controller executing request | |
1307 | * req request to wait for | |
1308 | * sleep_ok nonzero implies may sleep in this context | |
1309 | * time_ms timeout in ms. 0 implies no timeout. | |
1310 | * | |
1311 | * Return Values: | |
1312 | * 0 Request completed | |
1313 | * non-0 Timeout fired before request completion. | |
1314 | */ | |
1315 | int | |
1316 | mpt_wait_req(struct mpt_softc *mpt, request_t *req, | |
1317 | mpt_req_state_t state, mpt_req_state_t mask, | |
1318 | int sleep_ok, int time_ms) | |
1319 | { | |
1320 | int error; | |
1321 | int timeout; | |
1322 | u_int saved_cnt; | |
1323 | ||
1324 | /* | |
1325 | * timeout is in ms. 0 indicates infinite wait. | |
1326 | * Convert to ticks or 500us units depending on | |
1327 | * our sleep mode. | |
1328 | */ | |
1329 | if (sleep_ok != 0) { | |
1330 | timeout = (time_ms * hz) / 1000; | |
1331 | } else { | |
1332 | timeout = time_ms * 2; | |
1333 | } | |
1334 | req->state |= REQ_STATE_NEED_WAKEUP; | |
1335 | mask &= ~REQ_STATE_NEED_WAKEUP; | |
1336 | saved_cnt = mpt->reset_cnt; | |
1337 | while ((req->state & mask) != state && mpt->reset_cnt == saved_cnt) { | |
1338 | if (sleep_ok != 0) { | |
6d259fc1 | 1339 | error = mpt_sleep(mpt, req, 0, "mptreq", timeout); |
d751f32e MD |
1340 | if (error == EWOULDBLOCK) { |
1341 | timeout = 0; | |
1342 | break; | |
1343 | } | |
1344 | } else { | |
1345 | if (time_ms != 0 && --timeout == 0) { | |
1346 | break; | |
1347 | } | |
1348 | DELAY(500); | |
1349 | mpt_intr(mpt); | |
1350 | } | |
1351 | } | |
1352 | req->state &= ~REQ_STATE_NEED_WAKEUP; | |
1353 | if (mpt->reset_cnt != saved_cnt) { | |
1354 | return (EIO); | |
1355 | } | |
1356 | if (time_ms && timeout <= 0) { | |
1357 | MSG_REQUEST_HEADER *msg_hdr = req->req_vbuf; | |
1358 | req->state |= REQ_STATE_TIMEDOUT; | |
1359 | mpt_prt(mpt, "mpt_wait_req(%x) timed out\n", msg_hdr->Function); | |
1360 | return (ETIMEDOUT); | |
1361 | } | |
1362 | return (0); | |
1363 | } | |
1364 | ||
1365 | /* | |
1366 | * Send a command to the IOC via the handshake register. | |
1367 | * | |
1368 | * Only done at initialization time and for certain unusual | |
1369 | * commands such as device/bus reset as specified by LSI. | |
1370 | */ | |
1371 | int | |
1372 | mpt_send_handshake_cmd(struct mpt_softc *mpt, size_t len, void *cmd) | |
1373 | { | |
1374 | int i; | |
1375 | uint32_t data, *data32; | |
1376 | ||
1377 | /* Check condition of the IOC */ | |
1378 | data = mpt_rd_db(mpt); | |
1379 | if ((MPT_STATE(data) != MPT_DB_STATE_READY | |
1380 | && MPT_STATE(data) != MPT_DB_STATE_RUNNING | |
1381 | && MPT_STATE(data) != MPT_DB_STATE_FAULT) | |
1382 | || MPT_DB_IS_IN_USE(data)) { | |
1383 | mpt_prt(mpt, "handshake aborted - invalid doorbell state\n"); | |
1384 | mpt_print_db(data); | |
1385 | return (EBUSY); | |
1386 | } | |
1387 | ||
1388 | /* We move things in 32 bit chunks */ | |
1389 | len = (len + 3) >> 2; | |
1390 | data32 = cmd; | |
1391 | ||
1392 | /* Clear any left over pending doorbell interrupts */ | |
1393 | if (MPT_DB_INTR(mpt_rd_intr(mpt))) | |
1394 | mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); | |
1395 | ||
1396 | /* | |
1397 | * Tell the handshake reg. we are going to send a command | |
1398 | * and how long it is going to be. | |
1399 | */ | |
1400 | data = (MPI_FUNCTION_HANDSHAKE << MPI_DOORBELL_FUNCTION_SHIFT) | | |
1401 | (len << MPI_DOORBELL_ADD_DWORDS_SHIFT); | |
1402 | mpt_write(mpt, MPT_OFFSET_DOORBELL, data); | |
1403 | ||
1404 | /* Wait for the chip to notice */ | |
1405 | if (mpt_wait_db_int(mpt) != MPT_OK) { | |
1406 | mpt_prt(mpt, "mpt_send_handshake_cmd: db ignored\n"); | |
1407 | return (ETIMEDOUT); | |
1408 | } | |
1409 | ||
1410 | /* Clear the interrupt */ | |
1411 | mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); | |
1412 | ||
1413 | if (mpt_wait_db_ack(mpt) != MPT_OK) { | |
1414 | mpt_prt(mpt, "mpt_send_handshake_cmd: db ack timed out\n"); | |
1415 | return (ETIMEDOUT); | |
1416 | } | |
1417 | ||
1418 | /* Send the command */ | |
1419 | for (i = 0; i < len; i++) { | |
1420 | mpt_write(mpt, MPT_OFFSET_DOORBELL, htole32(*data32++)); | |
1421 | if (mpt_wait_db_ack(mpt) != MPT_OK) { | |
1422 | mpt_prt(mpt, | |
1423 | "mpt_send_handshake_cmd: timeout @ index %d\n", i); | |
1424 | return (ETIMEDOUT); | |
1425 | } | |
1426 | } | |
1427 | return MPT_OK; | |
1428 | } | |
1429 | ||
1430 | /* Get the response from the handshake register */ | |
1431 | int | |
1432 | mpt_recv_handshake_reply(struct mpt_softc *mpt, size_t reply_len, void *reply) | |
1433 | { | |
1434 | int left, reply_left; | |
1435 | u_int16_t *data16; | |
1436 | uint32_t data; | |
1437 | MSG_DEFAULT_REPLY *hdr; | |
1438 | ||
1439 | /* We move things out in 16 bit chunks */ | |
1440 | reply_len >>= 1; | |
1441 | data16 = (u_int16_t *)reply; | |
1442 | ||
1443 | hdr = (MSG_DEFAULT_REPLY *)reply; | |
1444 | ||
1445 | /* Get first word */ | |
1446 | if (mpt_wait_db_int(mpt) != MPT_OK) { | |
1447 | mpt_prt(mpt, "mpt_recv_handshake_cmd timeout1\n"); | |
1448 | return ETIMEDOUT; | |
1449 | } | |
1450 | data = mpt_read(mpt, MPT_OFFSET_DOORBELL); | |
1451 | *data16++ = le16toh(data & MPT_DB_DATA_MASK); | |
1452 | mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); | |
1453 | ||
1454 | /* Get Second Word */ | |
1455 | if (mpt_wait_db_int(mpt) != MPT_OK) { | |
1456 | mpt_prt(mpt, "mpt_recv_handshake_cmd timeout2\n"); | |
1457 | return ETIMEDOUT; | |
1458 | } | |
1459 | data = mpt_read(mpt, MPT_OFFSET_DOORBELL); | |
1460 | *data16++ = le16toh(data & MPT_DB_DATA_MASK); | |
1461 | mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); | |
1462 | ||
1463 | /* | |
1464 | * With the second word, we can now look at the length. | |
1465 | * Warn about a reply that's too short (except for IOC FACTS REPLY) | |
1466 | */ | |
1467 | if ((reply_len >> 1) != hdr->MsgLength && | |
1468 | (hdr->Function != MPI_FUNCTION_IOC_FACTS)){ | |
d751f32e MD |
1469 | mpt_prt(mpt, "reply length does not match message length: " |
1470 | "got %x; expected %zx for function %x\n", | |
1471 | hdr->MsgLength << 2, reply_len << 1, hdr->Function); | |
d751f32e MD |
1472 | } |
1473 | ||
1474 | /* Get rest of the reply; but don't overflow the provided buffer */ | |
1475 | left = (hdr->MsgLength << 1) - 2; | |
1476 | reply_left = reply_len - 2; | |
1477 | while (left--) { | |
1478 | u_int16_t datum; | |
1479 | ||
1480 | if (mpt_wait_db_int(mpt) != MPT_OK) { | |
1481 | mpt_prt(mpt, "mpt_recv_handshake_cmd timeout3\n"); | |
1482 | return ETIMEDOUT; | |
1483 | } | |
1484 | data = mpt_read(mpt, MPT_OFFSET_DOORBELL); | |
1485 | datum = le16toh(data & MPT_DB_DATA_MASK); | |
1486 | ||
1487 | if (reply_left-- > 0) | |
1488 | *data16++ = datum; | |
1489 | ||
1490 | mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); | |
1491 | } | |
984263bc MD |
1492 | |
1493 | /* One more wait & clear at the end */ | |
1494 | if (mpt_wait_db_int(mpt) != MPT_OK) { | |
d751f32e | 1495 | mpt_prt(mpt, "mpt_recv_handshake_cmd timeout4\n"); |
984263bc MD |
1496 | return ETIMEDOUT; |
1497 | } | |
1498 | mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); | |
1499 | ||
d751f32e MD |
1500 | if ((hdr->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { |
1501 | if (mpt->verbose >= MPT_PRT_TRACE) | |
1502 | mpt_print_reply(hdr); | |
1503 | return (MPT_FAIL | hdr->IOCStatus); | |
1504 | } | |
1505 | ||
1506 | return (0); | |
1507 | } | |
1508 | ||
1509 | static int | |
1510 | mpt_get_iocfacts(struct mpt_softc *mpt, MSG_IOC_FACTS_REPLY *freplp) | |
1511 | { | |
1512 | MSG_IOC_FACTS f_req; | |
1513 | int error; | |
6d259fc1 | 1514 | |
d751f32e MD |
1515 | memset(&f_req, 0, sizeof f_req); |
1516 | f_req.Function = MPI_FUNCTION_IOC_FACTS; | |
1517 | f_req.MsgContext = htole32(MPT_REPLY_HANDLER_HANDSHAKE); | |
1518 | error = mpt_send_handshake_cmd(mpt, sizeof f_req, &f_req); | |
1519 | if (error) { | |
1520 | return(error); | |
1521 | } | |
1522 | error = mpt_recv_handshake_reply(mpt, sizeof (*freplp), freplp); | |
1523 | return (error); | |
1524 | } | |
1525 | ||
1526 | static int | |
1527 | mpt_get_portfacts(struct mpt_softc *mpt, U8 port, MSG_PORT_FACTS_REPLY *freplp) | |
1528 | { | |
1529 | MSG_PORT_FACTS f_req; | |
1530 | int error; | |
6d259fc1 | 1531 | |
d751f32e MD |
1532 | memset(&f_req, 0, sizeof f_req); |
1533 | f_req.Function = MPI_FUNCTION_PORT_FACTS; | |
1534 | f_req.PortNumber = port; | |
1535 | f_req.MsgContext = htole32(MPT_REPLY_HANDLER_HANDSHAKE); | |
1536 | error = mpt_send_handshake_cmd(mpt, sizeof f_req, &f_req); | |
1537 | if (error) { | |
1538 | return(error); | |
1539 | } | |
1540 | error = mpt_recv_handshake_reply(mpt, sizeof (*freplp), freplp); | |
1541 | return (error); | |
1542 | } | |
1543 | ||
1544 | /* | |
1545 | * Send the initialization request. This is where we specify how many | |
1546 | * SCSI busses and how many devices per bus we wish to emulate. | |
1547 | * This is also the command that specifies the max size of the reply | |
1548 | * frames from the IOC that we will be allocating. | |
1549 | */ | |
1550 | static int | |
1551 | mpt_send_ioc_init(struct mpt_softc *mpt, uint32_t who) | |
1552 | { | |
1553 | int error = 0; | |
1554 | MSG_IOC_INIT init; | |
1555 | MSG_IOC_INIT_REPLY reply; | |
1556 | ||
1557 | memset(&init, 0, sizeof init); | |
1558 | init.WhoInit = who; | |
1559 | init.Function = MPI_FUNCTION_IOC_INIT; | |
1560 | init.MaxDevices = 0; /* at least 256 devices per bus */ | |
1561 | init.MaxBuses = 16; /* at least 16 busses */ | |
1562 | ||
1563 | init.MsgVersion = htole16(MPI_VERSION); | |
1564 | init.HeaderVersion = htole16(MPI_HEADER_VERSION); | |
1565 | init.ReplyFrameSize = htole16(MPT_REPLY_SIZE); | |
1566 | init.MsgContext = htole32(MPT_REPLY_HANDLER_HANDSHAKE); | |
1567 | ||
1568 | if ((error = mpt_send_handshake_cmd(mpt, sizeof init, &init)) != 0) { | |
1569 | return(error); | |
1570 | } | |
1571 | ||
1572 | error = mpt_recv_handshake_reply(mpt, sizeof reply, &reply); | |
1573 | return (error); | |
1574 | } | |
1575 | ||
1576 | ||
1577 | /* | |
1578 | * Utiltity routine to read configuration headers and pages | |
1579 | */ | |
1580 | int | |
1581 | mpt_issue_cfg_req(struct mpt_softc *mpt, request_t *req, cfgparms_t *params, | |
1582 | bus_addr_t addr, bus_size_t len, int sleep_ok, int timeout_ms) | |
1583 | { | |
1584 | MSG_CONFIG *cfgp; | |
1585 | SGE_SIMPLE32 *se; | |
1586 | ||
1587 | cfgp = req->req_vbuf; | |
1588 | memset(cfgp, 0, sizeof *cfgp); | |
1589 | cfgp->Action = params->Action; | |
1590 | cfgp->Function = MPI_FUNCTION_CONFIG; | |
1591 | cfgp->Header.PageVersion = params->PageVersion; | |
1592 | cfgp->Header.PageNumber = params->PageNumber; | |
1593 | cfgp->PageAddress = htole32(params->PageAddress); | |
1594 | if ((params->PageType & MPI_CONFIG_PAGETYPE_MASK) == | |
1595 | MPI_CONFIG_PAGETYPE_EXTENDED) { | |
1596 | cfgp->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; | |
1597 | cfgp->Header.PageLength = 0; | |
1598 | cfgp->ExtPageLength = htole16(params->ExtPageLength); | |
1599 | cfgp->ExtPageType = params->ExtPageType; | |
1600 | } else { | |
1601 | cfgp->Header.PageType = params->PageType; | |
1602 | cfgp->Header.PageLength = params->PageLength; | |
1603 | } | |
1604 | se = (SGE_SIMPLE32 *)&cfgp->PageBufferSGE; | |
1605 | se->Address = htole32(addr); | |
1606 | MPI_pSGE_SET_LENGTH(se, len); | |
1607 | MPI_pSGE_SET_FLAGS(se, (MPI_SGE_FLAGS_SIMPLE_ELEMENT | | |
1608 | MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER | | |
1609 | MPI_SGE_FLAGS_END_OF_LIST | | |
1610 | ((params->Action == MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT | |
1611 | || params->Action == MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM) | |
1612 | ? MPI_SGE_FLAGS_HOST_TO_IOC : MPI_SGE_FLAGS_IOC_TO_HOST))); | |
1613 | se->FlagsLength = htole32(se->FlagsLength); | |
1614 | cfgp->MsgContext = htole32(req->index | MPT_REPLY_HANDLER_CONFIG); | |
1615 | ||
1616 | mpt_check_doorbell(mpt); | |
1617 | mpt_send_cmd(mpt, req); | |
1618 | return (mpt_wait_req(mpt, req, REQ_STATE_DONE, REQ_STATE_DONE, | |
1619 | sleep_ok, timeout_ms)); | |
1620 | } | |
1621 | ||
1622 | int | |
1623 | mpt_read_extcfg_header(struct mpt_softc *mpt, int PageVersion, int PageNumber, | |
1624 | uint32_t PageAddress, int ExtPageType, | |
1625 | CONFIG_EXTENDED_PAGE_HEADER *rslt, | |
1626 | int sleep_ok, int timeout_ms) | |
1627 | { | |
1628 | request_t *req; | |
1629 | cfgparms_t params; | |
1630 | MSG_CONFIG_REPLY *cfgp; | |
1631 | int error; | |
1632 | ||
1633 | req = mpt_get_request(mpt, sleep_ok); | |
1634 | if (req == NULL) { | |
1635 | mpt_prt(mpt, "mpt_extread_cfg_header: Get request failed!\n"); | |
1636 | return (ENOMEM); | |
1637 | } | |
1638 | ||
1639 | params.Action = MPI_CONFIG_ACTION_PAGE_HEADER; | |
1640 | params.PageVersion = PageVersion; | |
1641 | params.PageLength = 0; | |
1642 | params.PageNumber = PageNumber; | |
1643 | params.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; | |
1644 | params.PageAddress = PageAddress; | |
1645 | params.ExtPageType = ExtPageType; | |
1646 | params.ExtPageLength = 0; | |
1647 | error = mpt_issue_cfg_req(mpt, req, ¶ms, /*addr*/0, /*len*/0, | |
1648 | sleep_ok, timeout_ms); | |
1649 | if (error != 0) { | |
1650 | /* | |
1651 | * Leave the request. Without resetting the chip, it's | |
1652 | * still owned by it and we'll just get into trouble | |
1653 | * freeing it now. Mark it as abandoned so that if it | |
1654 | * shows up later it can be freed. | |
1655 | */ | |
1656 | mpt_prt(mpt, "read_extcfg_header timed out\n"); | |
1657 | return (ETIMEDOUT); | |
1658 | } | |
1659 | ||
1660 | switch (req->IOCStatus & MPI_IOCSTATUS_MASK) { | |
1661 | case MPI_IOCSTATUS_SUCCESS: | |
1662 | cfgp = req->req_vbuf; | |
1663 | rslt->PageVersion = cfgp->Header.PageVersion; | |
1664 | rslt->PageNumber = cfgp->Header.PageNumber; | |
1665 | rslt->PageType = cfgp->Header.PageType; | |
1666 | rslt->ExtPageLength = le16toh(cfgp->ExtPageLength); | |
1667 | rslt->ExtPageType = cfgp->ExtPageType; | |
1668 | error = 0; | |
1669 | break; | |
1670 | case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: | |
1671 | mpt_lprt(mpt, MPT_PRT_DEBUG, | |
1672 | "Invalid Page Type %d Number %d Addr 0x%0x\n", | |
1673 | MPI_CONFIG_PAGETYPE_EXTENDED, PageNumber, PageAddress); | |
1674 | error = EINVAL; | |
1675 | break; | |
1676 | default: | |
1677 | mpt_prt(mpt, "mpt_read_extcfg_header: Config Info Status %x\n", | |
1678 | req->IOCStatus); | |
1679 | error = EIO; | |
1680 | break; | |
1681 | } | |
1682 | mpt_free_request(mpt, req); | |
1683 | return (error); | |
1684 | } | |
1685 | ||
1686 | int | |
1687 | mpt_read_extcfg_page(struct mpt_softc *mpt, int Action, uint32_t PageAddress, | |
1688 | CONFIG_EXTENDED_PAGE_HEADER *hdr, void *buf, size_t len, | |
1689 | int sleep_ok, int timeout_ms) | |
1690 | { | |
1691 | request_t *req; | |
1692 | cfgparms_t params; | |
1693 | int error; | |
1694 | ||
1695 | req = mpt_get_request(mpt, sleep_ok); | |
1696 | if (req == NULL) { | |
1697 | mpt_prt(mpt, "mpt_read_extcfg_page: Get request failed!\n"); | |
1698 | return (-1); | |
1699 | } | |
1700 | ||
1701 | params.Action = Action; | |
1702 | params.PageVersion = hdr->PageVersion; | |
1703 | params.PageLength = 0; | |
1704 | params.PageNumber = hdr->PageNumber; | |
1705 | params.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; | |
1706 | params.PageAddress = PageAddress; | |
1707 | params.ExtPageType = hdr->ExtPageType; | |
1708 | params.ExtPageLength = hdr->ExtPageLength; | |
1709 | error = mpt_issue_cfg_req(mpt, req, ¶ms, | |
1710 | req->req_pbuf + MPT_RQSL(mpt), | |
1711 | len, sleep_ok, timeout_ms); | |
1712 | if (error != 0) { | |
1713 | mpt_prt(mpt, "read_extcfg_page(%d) timed out\n", Action); | |
1714 | return (-1); | |
1715 | } | |
1716 | ||
1717 | if ((req->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { | |
1718 | mpt_prt(mpt, "mpt_read_extcfg_page: Config Info Status %x\n", | |
1719 | req->IOCStatus); | |
1720 | mpt_free_request(mpt, req); | |
1721 | return (-1); | |
1722 | } | |
d751f32e MD |
1723 | memcpy(buf, ((uint8_t *)req->req_vbuf)+MPT_RQSL(mpt), len); |
1724 | mpt_free_request(mpt, req); | |
1725 | return (0); | |
1726 | } | |
1727 | ||
1728 | int | |
1729 | mpt_read_cfg_header(struct mpt_softc *mpt, int PageType, int PageNumber, | |
1730 | uint32_t PageAddress, CONFIG_PAGE_HEADER *rslt, | |
1731 | int sleep_ok, int timeout_ms) | |
1732 | { | |
1733 | request_t *req; | |
1734 | cfgparms_t params; | |
1735 | MSG_CONFIG *cfgp; | |
1736 | int error; | |
1737 | ||
1738 | req = mpt_get_request(mpt, sleep_ok); | |
1739 | if (req == NULL) { | |
1740 | mpt_prt(mpt, "mpt_read_cfg_header: Get request failed!\n"); | |
1741 | return (ENOMEM); | |
1742 | } | |
1743 | ||
1744 | params.Action = MPI_CONFIG_ACTION_PAGE_HEADER; | |
1745 | params.PageVersion = 0; | |
1746 | params.PageLength = 0; | |
1747 | params.PageNumber = PageNumber; | |
1748 | params.PageType = PageType; | |
1749 | params.PageAddress = PageAddress; | |
1750 | error = mpt_issue_cfg_req(mpt, req, ¶ms, /*addr*/0, /*len*/0, | |
1751 | sleep_ok, timeout_ms); | |
1752 | if (error != 0) { | |
1753 | /* | |
1754 | * Leave the request. Without resetting the chip, it's | |
1755 | * still owned by it and we'll just get into trouble | |
1756 | * freeing it now. Mark it as abandoned so that if it | |
1757 | * shows up later it can be freed. | |
1758 | */ | |
1759 | mpt_prt(mpt, "read_cfg_header timed out\n"); | |
1760 | return (ETIMEDOUT); | |
1761 | } | |
1762 | ||
1763 | switch (req->IOCStatus & MPI_IOCSTATUS_MASK) { | |
1764 | case MPI_IOCSTATUS_SUCCESS: | |
1765 | cfgp = req->req_vbuf; | |
1766 | bcopy(&cfgp->Header, rslt, sizeof(*rslt)); | |
1767 | error = 0; | |
1768 | break; | |
1769 | case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: | |
1770 | mpt_lprt(mpt, MPT_PRT_DEBUG, | |
1771 | "Invalid Page Type %d Number %d Addr 0x%0x\n", | |
1772 | PageType, PageNumber, PageAddress); | |
1773 | error = EINVAL; | |
1774 | break; | |
1775 | default: | |
1776 | mpt_prt(mpt, "mpt_read_cfg_header: Config Info Status %x\n", | |
1777 | req->IOCStatus); | |
1778 | error = EIO; | |
1779 | break; | |
1780 | } | |
1781 | mpt_free_request(mpt, req); | |
1782 | return (error); | |
1783 | } | |
1784 | ||
1785 | int | |
1786 | mpt_read_cfg_page(struct mpt_softc *mpt, int Action, uint32_t PageAddress, | |
1787 | CONFIG_PAGE_HEADER *hdr, size_t len, int sleep_ok, | |
1788 | int timeout_ms) | |
1789 | { | |
1790 | request_t *req; | |
1791 | cfgparms_t params; | |
1792 | int error; | |
1793 | ||
1794 | req = mpt_get_request(mpt, sleep_ok); | |
1795 | if (req == NULL) { | |
1796 | mpt_prt(mpt, "mpt_read_cfg_page: Get request failed!\n"); | |
1797 | return (-1); | |
1798 | } | |
1799 | ||
1800 | params.Action = Action; | |
1801 | params.PageVersion = hdr->PageVersion; | |
1802 | params.PageLength = hdr->PageLength; | |
1803 | params.PageNumber = hdr->PageNumber; | |
1804 | params.PageType = hdr->PageType & MPI_CONFIG_PAGETYPE_MASK; | |
1805 | params.PageAddress = PageAddress; | |
1806 | error = mpt_issue_cfg_req(mpt, req, ¶ms, | |
1807 | req->req_pbuf + MPT_RQSL(mpt), | |
1808 | len, sleep_ok, timeout_ms); | |
1809 | if (error != 0) { | |
1810 | mpt_prt(mpt, "read_cfg_page(%d) timed out\n", Action); | |
1811 | return (-1); | |
1812 | } | |
1813 | ||
1814 | if ((req->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { | |
1815 | mpt_prt(mpt, "mpt_read_cfg_page: Config Info Status %x\n", | |
1816 | req->IOCStatus); | |
1817 | mpt_free_request(mpt, req); | |
1818 | return (-1); | |
1819 | } | |
d751f32e MD |
1820 | memcpy(hdr, ((uint8_t *)req->req_vbuf)+MPT_RQSL(mpt), len); |
1821 | mpt_free_request(mpt, req); | |
1822 | return (0); | |
1823 | } | |
1824 | ||
1825 | int | |
1826 | mpt_write_cfg_page(struct mpt_softc *mpt, int Action, uint32_t PageAddress, | |
1827 | CONFIG_PAGE_HEADER *hdr, size_t len, int sleep_ok, | |
1828 | int timeout_ms) | |
1829 | { | |
1830 | request_t *req; | |
1831 | cfgparms_t params; | |
1832 | u_int hdr_attr; | |
1833 | int error; | |
1834 | ||
1835 | hdr_attr = hdr->PageType & MPI_CONFIG_PAGEATTR_MASK; | |
1836 | if (hdr_attr != MPI_CONFIG_PAGEATTR_CHANGEABLE && | |
1837 | hdr_attr != MPI_CONFIG_PAGEATTR_PERSISTENT) { | |
1838 | mpt_prt(mpt, "page type 0x%x not changeable\n", | |
1839 | hdr->PageType & MPI_CONFIG_PAGETYPE_MASK); | |
1840 | return (-1); | |
1841 | } | |
1842 | ||
1843 | #if 0 | |
1844 | /* | |
1845 | * We shouldn't mask off other bits here. | |
1846 | */ | |
1847 | hdr->PageType &= MPI_CONFIG_PAGETYPE_MASK; | |
1848 | #endif | |
1849 | ||
1850 | req = mpt_get_request(mpt, sleep_ok); | |
1851 | if (req == NULL) | |
1852 | return (-1); | |
1853 | ||
1854 | memcpy(((caddr_t)req->req_vbuf) + MPT_RQSL(mpt), hdr, len); | |
1855 | ||
1856 | /* | |
1857 | * There isn't any point in restoring stripped out attributes | |
1858 | * if you then mask them going down to issue the request. | |
1859 | */ | |
1860 | ||
1861 | params.Action = Action; | |
1862 | params.PageVersion = hdr->PageVersion; | |
1863 | params.PageLength = hdr->PageLength; | |
1864 | params.PageNumber = hdr->PageNumber; | |
1865 | params.PageAddress = PageAddress; | |
1866 | #if 0 | |
1867 | /* Restore stripped out attributes */ | |
1868 | hdr->PageType |= hdr_attr; | |
1869 | params.PageType = hdr->PageType & MPI_CONFIG_PAGETYPE_MASK; | |
1870 | #else | |
1871 | params.PageType = hdr->PageType; | |
1872 | #endif | |
1873 | error = mpt_issue_cfg_req(mpt, req, ¶ms, | |
1874 | req->req_pbuf + MPT_RQSL(mpt), | |
1875 | len, sleep_ok, timeout_ms); | |
1876 | if (error != 0) { | |
1877 | mpt_prt(mpt, "mpt_write_cfg_page timed out\n"); | |
1878 | return (-1); | |
984263bc MD |
1879 | } |
1880 | ||
d751f32e MD |
1881 | if ((req->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { |
1882 | mpt_prt(mpt, "mpt_write_cfg_page: Config Info Status %x\n", | |
1883 | req->IOCStatus); | |
1884 | mpt_free_request(mpt, req); | |
1885 | return (-1); | |
1886 | } | |
1887 | mpt_free_request(mpt, req); | |
984263bc MD |
1888 | return (0); |
1889 | } | |
1890 | ||
d751f32e MD |
1891 | /* |
1892 | * Read IOC configuration information | |
1893 | */ | |
984263bc | 1894 | static int |
d751f32e | 1895 | mpt_read_config_info_ioc(struct mpt_softc *mpt) |
984263bc | 1896 | { |
d751f32e MD |
1897 | CONFIG_PAGE_HEADER hdr; |
1898 | struct mpt_raid_volume *mpt_raid; | |
1899 | int rv; | |
1900 | int i; | |
1901 | size_t len; | |
1902 | ||
1903 | rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_IOC, | |
1904 | 2, 0, &hdr, FALSE, 5000); | |
1905 | /* | |
1906 | * If it's an invalid page, so what? Not a supported function.... | |
1907 | */ | |
1908 | if (rv == EINVAL) { | |
1909 | return (0); | |
1910 | } | |
1911 | if (rv) { | |
1912 | return (rv); | |
1913 | } | |
1914 | ||
1915 | mpt_lprt(mpt, MPT_PRT_DEBUG, | |
1916 | "IOC Page 2 Header: Version %x len %x PageNumber %x PageType %x\n", | |
1917 | hdr.PageVersion, hdr.PageLength << 2, | |
1918 | hdr.PageNumber, hdr.PageType); | |
1919 | ||
1920 | len = hdr.PageLength * sizeof(uint32_t); | |
2545bca0 | 1921 | mpt->ioc_page2 = kmalloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); |
d751f32e MD |
1922 | if (mpt->ioc_page2 == NULL) { |
1923 | mpt_prt(mpt, "unable to allocate memory for IOC page 2\n"); | |
1924 | mpt_raid_free_mem(mpt); | |
1925 | return (ENOMEM); | |
1926 | } | |
1927 | memcpy(&mpt->ioc_page2->Header, &hdr, sizeof(hdr)); | |
1928 | rv = mpt_read_cur_cfg_page(mpt, 0, | |
1929 | &mpt->ioc_page2->Header, len, FALSE, 5000); | |
1930 | if (rv) { | |
1931 | mpt_prt(mpt, "failed to read IOC Page 2\n"); | |
1932 | mpt_raid_free_mem(mpt); | |
1933 | return (EIO); | |
1934 | } | |
1935 | mpt2host_config_page_ioc2(mpt->ioc_page2); | |
1936 | ||
1937 | if (mpt->ioc_page2->CapabilitiesFlags != 0) { | |
1938 | uint32_t mask; | |
1939 | ||
1940 | mpt_prt(mpt, "Capabilities: ("); | |
1941 | for (mask = 1; mask != 0; mask <<= 1) { | |
1942 | if ((mpt->ioc_page2->CapabilitiesFlags & mask) == 0) { | |
1943 | continue; | |
1944 | } | |
1945 | switch (mask) { | |
1946 | case MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT: | |
1947 | mpt_prtc(mpt, " RAID-0"); | |
1948 | break; | |
1949 | case MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT: | |
1950 | mpt_prtc(mpt, " RAID-1E"); | |
1951 | break; | |
1952 | case MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT: | |
1953 | mpt_prtc(mpt, " RAID-1"); | |
1954 | break; | |
1955 | case MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT: | |
1956 | mpt_prtc(mpt, " SES"); | |
1957 | break; | |
1958 | case MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT: | |
1959 | mpt_prtc(mpt, " SAFTE"); | |
1960 | break; | |
1961 | case MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT: | |
1962 | mpt_prtc(mpt, " Multi-Channel-Arrays"); | |
1963 | default: | |
1964 | break; | |
1965 | } | |
1966 | } | |
1967 | mpt_prtc(mpt, " )\n"); | |
1968 | if ((mpt->ioc_page2->CapabilitiesFlags | |
1969 | & (MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT | |
1970 | | MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT | |
1971 | | MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT)) != 0) { | |
1972 | mpt_prt(mpt, "%d Active Volume%s(%d Max)\n", | |
1973 | mpt->ioc_page2->NumActiveVolumes, | |
1974 | mpt->ioc_page2->NumActiveVolumes != 1 | |
1975 | ? "s " : " ", | |
1976 | mpt->ioc_page2->MaxVolumes); | |
1977 | mpt_prt(mpt, "%d Hidden Drive Member%s(%d Max)\n", | |
1978 | mpt->ioc_page2->NumActivePhysDisks, | |
1979 | mpt->ioc_page2->NumActivePhysDisks != 1 | |
1980 | ? "s " : " ", | |
1981 | mpt->ioc_page2->MaxPhysDisks); | |
1982 | } | |
1983 | } | |
1984 | ||
1985 | len = mpt->ioc_page2->MaxVolumes * sizeof(struct mpt_raid_volume); | |
2545bca0 | 1986 | mpt->raid_volumes = kmalloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); |
d751f32e MD |
1987 | if (mpt->raid_volumes == NULL) { |
1988 | mpt_prt(mpt, "Could not allocate RAID volume data\n"); | |
1989 | mpt_raid_free_mem(mpt); | |
1990 | return (ENOMEM); | |
1991 | } | |
1992 | ||
1993 | /* | |
1994 | * Copy critical data out of ioc_page2 so that we can | |
1995 | * safely refresh the page without windows of unreliable | |
1996 | * data. | |
1997 | */ | |
1998 | mpt->raid_max_volumes = mpt->ioc_page2->MaxVolumes; | |
1999 | ||
2000 | len = sizeof(*mpt->raid_volumes->config_page) + | |
2001 | (sizeof (RAID_VOL0_PHYS_DISK) * (mpt->ioc_page2->MaxPhysDisks - 1)); | |
2002 | for (i = 0; i < mpt->ioc_page2->MaxVolumes; i++) { | |
2003 | mpt_raid = &mpt->raid_volumes[i]; | |
2004 | mpt_raid->config_page = | |
2545bca0 | 2005 | kmalloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); |
d751f32e MD |
2006 | if (mpt_raid->config_page == NULL) { |
2007 | mpt_prt(mpt, "Could not allocate RAID page data\n"); | |
2008 | mpt_raid_free_mem(mpt); | |
2009 | return (ENOMEM); | |
2010 | } | |
2011 | } | |
2012 | mpt->raid_page0_len = len; | |
2013 | ||
2014 | len = mpt->ioc_page2->MaxPhysDisks * sizeof(struct mpt_raid_disk); | |
2545bca0 | 2015 | mpt->raid_disks = kmalloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); |
d751f32e MD |
2016 | if (mpt->raid_disks == NULL) { |
2017 | mpt_prt(mpt, "Could not allocate RAID disk data\n"); | |
2018 | mpt_raid_free_mem(mpt); | |
2019 | return (ENOMEM); | |
2020 | } | |
2021 | mpt->raid_max_disks = mpt->ioc_page2->MaxPhysDisks; | |
2022 | ||
2023 | /* | |
2024 | * Load page 3. | |
2025 | */ | |
2026 | rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_IOC, | |
2027 | 3, 0, &hdr, FALSE, 5000); | |
2028 | if (rv) { | |
2029 | mpt_raid_free_mem(mpt); | |
2030 | return (EIO); | |
2031 | } | |
2032 | ||
2033 | mpt_lprt(mpt, MPT_PRT_DEBUG, "IOC Page 3 Header: %x %x %x %x\n", | |
2034 | hdr.PageVersion, hdr.PageLength, hdr.PageNumber, hdr.PageType); | |
2035 | ||
2036 | len = hdr.PageLength * sizeof(uint32_t); | |
2545bca0 | 2037 | mpt->ioc_page3 = kmalloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); |
d751f32e MD |
2038 | if (mpt->ioc_page3 == NULL) { |
2039 | mpt_prt(mpt, "unable to allocate memory for IOC page 3\n"); | |
2040 | mpt_raid_free_mem(mpt); | |
2041 | return (ENOMEM); | |
2042 | } | |
2043 | memcpy(&mpt->ioc_page3->Header, &hdr, sizeof(hdr)); | |
2044 | rv = mpt_read_cur_cfg_page(mpt, 0, | |
2045 | &mpt->ioc_page3->Header, len, FALSE, 5000); | |
2046 | if (rv) { | |
2047 | mpt_raid_free_mem(mpt); | |
2048 | return (EIO); | |
2049 | } | |
2050 | mpt2host_config_page_ioc3(mpt->ioc_page3); | |
2051 | mpt_raid_wakeup(mpt); | |
2052 | return (0); | |
984263bc MD |
2053 | } |
2054 | ||
d751f32e MD |
2055 | /* |
2056 | * Enable IOC port | |
2057 | */ | |
984263bc | 2058 | static int |
d751f32e | 2059 | mpt_send_port_enable(struct mpt_softc *mpt, int port) |
984263bc | 2060 | { |
d751f32e MD |
2061 | request_t *req; |
2062 | MSG_PORT_ENABLE *enable_req; | |
2063 | int error; | |
2064 | ||
2065 | req = mpt_get_request(mpt, /*sleep_ok*/FALSE); | |
2066 | if (req == NULL) | |
2067 | return (-1); | |
2068 | ||
2069 | enable_req = req->req_vbuf; | |
2070 | memset(enable_req, 0, MPT_RQSL(mpt)); | |
2071 | ||
2072 | enable_req->Function = MPI_FUNCTION_PORT_ENABLE; | |
2073 | enable_req->MsgContext = htole32(req->index | MPT_REPLY_HANDLER_CONFIG); | |
2074 | enable_req->PortNumber = port; | |
2075 | ||
2076 | mpt_check_doorbell(mpt); | |
2077 | mpt_lprt(mpt, MPT_PRT_DEBUG, "enabling port %d\n", port); | |
2078 | ||
2079 | mpt_send_cmd(mpt, req); | |
2080 | error = mpt_wait_req(mpt, req, REQ_STATE_DONE, REQ_STATE_DONE, | |
4c42baf4 | 2081 | FALSE, (mpt->is_sas || mpt->is_fc)? 300000 : 30000); |
d751f32e MD |
2082 | if (error != 0) { |
2083 | mpt_prt(mpt, "port %d enable timed out\n", port); | |
2084 | return (-1); | |
2085 | } | |
2086 | mpt_free_request(mpt, req); | |
2087 | mpt_lprt(mpt, MPT_PRT_DEBUG, "enabled port %d\n", port); | |
2088 | return (0); | |
984263bc MD |
2089 | } |
2090 | ||
2091 | /* | |
d751f32e | 2092 | * Enable/Disable asynchronous event reporting. |
984263bc MD |
2093 | */ |
2094 | static int | |
d751f32e | 2095 | mpt_send_event_request(struct mpt_softc *mpt, int onoff) |
984263bc | 2096 | { |
d751f32e MD |
2097 | request_t *req; |
2098 | MSG_EVENT_NOTIFY *enable_req; | |
984263bc | 2099 | |
d751f32e MD |
2100 | req = mpt_get_request(mpt, FALSE); |
2101 | if (req == NULL) { | |
2102 | return (ENOMEM); | |
984263bc | 2103 | } |
d751f32e MD |
2104 | enable_req = req->req_vbuf; |
2105 | memset(enable_req, 0, sizeof *enable_req); | |
984263bc | 2106 | |
d751f32e MD |
2107 | enable_req->Function = MPI_FUNCTION_EVENT_NOTIFICATION; |
2108 | enable_req->MsgContext = htole32(req->index | MPT_REPLY_HANDLER_EVENTS); | |
2109 | enable_req->Switch = onoff; | |
984263bc | 2110 | |
d751f32e MD |
2111 | mpt_check_doorbell(mpt); |
2112 | mpt_lprt(mpt, MPT_PRT_DEBUG, "%sabling async events\n", | |
2113 | onoff ? "en" : "dis"); | |
2114 | /* | |
2115 | * Send the command off, but don't wait for it. | |
2116 | */ | |
2117 | mpt_send_cmd(mpt, req); | |
2118 | return (0); | |
984263bc MD |
2119 | } |
2120 | ||
984263bc | 2121 | /* |
d751f32e | 2122 | * Un-mask the interrupts on the chip. |
984263bc | 2123 | */ |
d751f32e MD |
2124 | void |
2125 | mpt_enable_ints(struct mpt_softc *mpt) | |
2126 | { | |
4c42baf4 | 2127 | |
d751f32e MD |
2128 | /* Unmask every thing except door bell int */ |
2129 | mpt_write(mpt, MPT_OFFSET_INTR_MASK, MPT_INTR_DB_MASK); | |
2130 | } | |
984263bc | 2131 | |
d751f32e MD |
2132 | /* |
2133 | * Mask the interrupts on the chip. | |
2134 | */ | |
2135 | void | |
2136 | mpt_disable_ints(struct mpt_softc *mpt) | |
2137 | { | |
4c42baf4 | 2138 | |
d751f32e MD |
2139 | /* Mask all interrupts */ |
2140 | mpt_write(mpt, MPT_OFFSET_INTR_MASK, | |
2141 | MPT_INTR_REPLY_MASK | MPT_INTR_DB_MASK); | |
2142 | } | |
984263bc | 2143 | |
d751f32e MD |
2144 | static void |
2145 | mpt_sysctl_attach(struct mpt_softc *mpt) | |
984263bc | 2146 | { |
26595b18 SW |
2147 | struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(mpt->dev); |
2148 | struct sysctl_oid *tree = device_get_sysctl_tree(mpt->dev); | |
2149 | ||
2150 | SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, | |
d751f32e MD |
2151 | "debug", CTLFLAG_RW, &mpt->verbose, 0, |
2152 | "Debugging/Verbose level"); | |
26595b18 | 2153 | SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, |
d751f32e MD |
2154 | "role", CTLFLAG_RD, &mpt->role, 0, |
2155 | "HBA role"); | |
2156 | #ifdef MPT_TEST_MULTIPATH | |
26595b18 | 2157 | SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, |
d751f32e MD |
2158 | "failure_id", CTLFLAG_RW, &mpt->failure_id, -1, |
2159 | "Next Target to Fail"); | |
2160 | #endif | |
d751f32e | 2161 | } |
984263bc | 2162 | |
d751f32e MD |
2163 | int |
2164 | mpt_attach(struct mpt_softc *mpt) | |
2165 | { | |
2166 | struct mpt_personality *pers; | |
2167 | int i; | |
2168 | int error; | |
984263bc | 2169 | |
d751f32e MD |
2170 | mpt_core_attach(mpt); |
2171 | mpt_core_enable(mpt); | |
984263bc | 2172 | |
d751f32e MD |
2173 | TAILQ_INSERT_TAIL(&mpt_tailq, mpt, links); |
2174 | for (i = 0; i < MPT_MAX_PERSONALITIES; i++) { | |
2175 | pers = mpt_personalities[i]; | |
2176 | if (pers == NULL) { | |
2177 | continue; | |
2178 | } | |
2179 | if (pers->probe(mpt) == 0) { | |
2180 | error = pers->attach(mpt); | |
2181 | if (error != 0) { | |
2182 | mpt_detach(mpt); | |
2183 | return (error); | |
2184 | } | |
2185 | mpt->mpt_pers_mask |= (0x1 << pers->id); | |
2186 | pers->use_count++; | |
2187 | } | |
2188 | } | |
984263bc | 2189 | |
d751f32e MD |
2190 | /* |
2191 | * Now that we've attached everything, do the enable function | |
2192 | * for all of the personalities. This allows the personalities | |
2193 | * to do setups that are appropriate for them prior to enabling | |
2194 | * any ports. | |
2195 | */ | |
2196 | for (i = 0; i < MPT_MAX_PERSONALITIES; i++) { | |
2197 | pers = mpt_personalities[i]; | |
2198 | if (pers != NULL && MPT_PERS_ATTACHED(pers, mpt) != 0) { | |
2199 | error = pers->enable(mpt); | |
2200 | if (error != 0) { | |
2201 | mpt_prt(mpt, "personality %s attached but would" | |
2202 | " not enable (%d)\n", pers->name, error); | |
2203 | mpt_detach(mpt); | |
2204 | return (error); | |
2205 | } | |
984263bc | 2206 | } |
984263bc | 2207 | } |
984263bc MD |
2208 | return (0); |
2209 | } | |
2210 | ||
d751f32e MD |
2211 | int |
2212 | mpt_shutdown(struct mpt_softc *mpt) | |
2213 | { | |
2214 | struct mpt_personality *pers; | |
2215 | ||
2216 | MPT_PERS_FOREACH_REVERSE(mpt, pers) { | |
2217 | pers->shutdown(mpt); | |
2218 | } | |
2219 | return (0); | |
2220 | } | |
984263bc MD |
2221 | |
2222 | int | |
d751f32e | 2223 | mpt_detach(struct mpt_softc *mpt) |
984263bc | 2224 | { |
d751f32e | 2225 | struct mpt_personality *pers; |
984263bc | 2226 | |
d751f32e MD |
2227 | MPT_PERS_FOREACH_REVERSE(mpt, pers) { |
2228 | pers->detach(mpt); | |
2229 | mpt->mpt_pers_mask &= ~(0x1 << pers->id); | |
2230 | pers->use_count--; | |
2231 | } | |
2232 | TAILQ_REMOVE(&mpt_tailq, mpt, links); | |
2233 | return (0); | |
2234 | } | |
984263bc | 2235 | |
4c42baf4 | 2236 | static int |
d751f32e MD |
2237 | mpt_core_load(struct mpt_personality *pers) |
2238 | { | |
2239 | int i; | |
984263bc | 2240 | |
d751f32e MD |
2241 | /* |
2242 | * Setup core handlers and insert the default handler | |
2243 | * into all "empty slots". | |
2244 | */ | |
2245 | for (i = 0; i < MPT_NUM_REPLY_HANDLERS; i++) { | |
2246 | mpt_reply_handlers[i] = mpt_default_reply_handler; | |
2247 | } | |
984263bc | 2248 | |
d751f32e MD |
2249 | mpt_reply_handlers[MPT_CBI(MPT_REPLY_HANDLER_EVENTS)] = |
2250 | mpt_event_reply_handler; | |
2251 | mpt_reply_handlers[MPT_CBI(MPT_REPLY_HANDLER_CONFIG)] = | |
2252 | mpt_config_reply_handler; | |
2253 | mpt_reply_handlers[MPT_CBI(MPT_REPLY_HANDLER_HANDSHAKE)] = | |
2254 | mpt_handshake_reply_handler; | |
2255 | return (0); | |
2256 | } | |
2257 | ||
2258 | /* | |
2259 | * Initialize per-instance driver data and perform | |
2260 | * initial controller configuration. | |
2261 | */ | |
4c42baf4 | 2262 | static int |
d751f32e MD |
2263 | mpt_core_attach(struct mpt_softc *mpt) |
2264 | { | |
2265 | int val, error; | |
2266 | ||
2267 | LIST_INIT(&mpt->ack_frames); | |
2268 | /* Put all request buffers on the free list */ | |
2269 | TAILQ_INIT(&mpt->request_pending_list); | |
2270 | TAILQ_INIT(&mpt->request_free_list); | |
2271 | TAILQ_INIT(&mpt->request_timeout_list); | |
d751f32e MD |
2272 | for (val = 0; val < MPT_MAX_LUNS; val++) { |
2273 | STAILQ_INIT(&mpt->trt[val].atios); | |
2274 | STAILQ_INIT(&mpt->trt[val].inots); | |
2275 | } | |
2276 | STAILQ_INIT(&mpt->trt_wildcard.atios); | |
2277 | STAILQ_INIT(&mpt->trt_wildcard.inots); | |
2278 | #ifdef MPT_TEST_MULTIPATH | |
2279 | mpt->failure_id = -1; | |
2280 | #endif | |
2281 | mpt->scsi_tgt_handler_id = MPT_HANDLER_ID_NONE; | |
2282 | mpt_sysctl_attach(mpt); | |
2283 | mpt_lprt(mpt, MPT_PRT_DEBUG, "doorbell req = %s\n", | |
2284 | mpt_ioc_diag(mpt_read(mpt, MPT_OFFSET_DOORBELL))); | |
2285 | ||
2286 | MPT_LOCK(mpt); | |
2287 | error = mpt_configure_ioc(mpt, 0, 0); | |
2288 | MPT_UNLOCK(mpt); | |
2289 | ||
2290 | return (error); | |
2291 | } | |
2292 | ||
4c42baf4 | 2293 | static int |
d751f32e MD |
2294 | mpt_core_enable(struct mpt_softc *mpt) |
2295 | { | |
4c42baf4 | 2296 | |
d751f32e MD |
2297 | /* |
2298 | * We enter with the IOC enabled, but async events | |
2299 | * not enabled, ports not enabled and interrupts | |
2300 | * not enabled. | |
2301 | */ | |
2302 | MPT_LOCK(mpt); | |
2303 | ||
2304 | /* | |
2305 | * Enable asynchronous event reporting- all personalities | |
2306 | * have attached so that they should be able to now field | |
2307 | * async events. | |
2308 | */ | |
2309 | mpt_send_event_request(mpt, 1); | |
2310 | ||
2311 | /* | |
2312 | * Catch any pending interrupts | |
2313 | * | |
2314 | * This seems to be crucial- otherwise | |
2315 | * the portenable below times out. | |
2316 | */ | |
2317 | mpt_intr(mpt); | |
2318 | ||
2319 | /* | |
2320 | * Enable Interrupts | |
2321 | */ | |
2322 | mpt_enable_ints(mpt); | |
2323 | ||
2324 | /* | |
2325 | * Catch any pending interrupts | |
2326 | * | |
2327 | * This seems to be crucial- otherwise | |
2328 | * the portenable below times out. | |
2329 | */ | |
2330 | mpt_intr(mpt); | |
2331 | ||
2332 | /* | |
2333 | * Enable the port. | |
2334 | */ | |
2335 | if (mpt_send_port_enable(mpt, 0) != MPT_OK) { | |
2336 | mpt_prt(mpt, "failed to enable port 0\n"); | |
2337 | MPT_UNLOCK(mpt); | |
2338 | return (ENXIO); | |
2339 | } | |
2340 | MPT_UNLOCK(mpt); | |
984263bc MD |
2341 | return (0); |
2342 | } | |
2343 | ||
4c42baf4 | 2344 | static void |
d751f32e MD |
2345 | mpt_core_shutdown(struct mpt_softc *mpt) |
2346 | { | |
4c42baf4 | 2347 | |
d751f32e MD |
2348 | mpt_disable_ints(mpt); |
2349 | } | |
2350 | ||
4c42baf4 | 2351 | static void |
d751f32e MD |
2352 | mpt_core_detach(struct mpt_softc *mpt) |
2353 | { | |
6d259fc1 SW |
2354 | int val; |
2355 | ||
d751f32e MD |
2356 | /* |
2357 | * XXX: FREE MEMORY | |
2358 | */ | |
2359 | mpt_disable_ints(mpt); | |
6d259fc1 SW |
2360 | |
2361 | /* Make sure no request has pending timeouts. */ | |
2362 | for (val = 0; val < MPT_MAX_REQUESTS(mpt); val++) { | |
2363 | request_t *req = &mpt->request_pool[val]; | |
f582582c | 2364 | mpt_callout_drain(mpt, &req->callout); |
6d259fc1 SW |
2365 | } |
2366 | ||
2367 | mpt_dma_buf_free(mpt); | |
d751f32e MD |
2368 | } |
2369 | ||
4c42baf4 | 2370 | static int |
d751f32e MD |
2371 | mpt_core_unload(struct mpt_personality *pers) |
2372 | { | |
4c42baf4 | 2373 | |
6d259fc1 | 2374 | /* Unload is always successful. */ |
d751f32e MD |
2375 | return (0); |
2376 | } | |
2377 | ||
2378 | #define FW_UPLOAD_REQ_SIZE \ | |
2379 | (sizeof(MSG_FW_UPLOAD) - sizeof(SGE_MPI_UNION) \ | |
2380 | + sizeof(FW_UPLOAD_TCSGE) + sizeof(SGE_SIMPLE32)) | |
2381 | ||
2382 | static int | |
2383 | mpt_upload_fw(struct mpt_softc *mpt) | |
2384 | { | |
2385 | uint8_t fw_req_buf[FW_UPLOAD_REQ_SIZE]; | |
2386 | MSG_FW_UPLOAD_REPLY fw_reply; | |
2387 | MSG_FW_UPLOAD *fw_req; | |
2388 | FW_UPLOAD_TCSGE *tsge; | |
2389 | SGE_SIMPLE32 *sge; | |
2390 | uint32_t flags; | |
2391 | int error; | |
6d259fc1 | 2392 | |
d751f32e MD |
2393 | memset(&fw_req_buf, 0, sizeof(fw_req_buf)); |
2394 | fw_req = (MSG_FW_UPLOAD *)fw_req_buf; | |
2395 | fw_req->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM; | |
2396 | fw_req->Function = MPI_FUNCTION_FW_UPLOAD; | |
2397 | fw_req->MsgContext = htole32(MPT_REPLY_HANDLER_HANDSHAKE); | |
2398 | tsge = (FW_UPLOAD_TCSGE *)&fw_req->SGL; | |
2399 | tsge->DetailsLength = 12; | |
2400 | tsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT; | |
2401 | tsge->ImageSize = htole32(mpt->fw_image_size); | |
2402 | sge = (SGE_SIMPLE32 *)(tsge + 1); | |
2403 | flags = (MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER | |
2404 | | MPI_SGE_FLAGS_END_OF_LIST | MPI_SGE_FLAGS_SIMPLE_ELEMENT | |
2405 | | MPI_SGE_FLAGS_32_BIT_ADDRESSING | MPI_SGE_FLAGS_IOC_TO_HOST); | |
2406 | flags <<= MPI_SGE_FLAGS_SHIFT; | |
2407 | sge->FlagsLength = htole32(flags | mpt->fw_image_size); | |
2408 | sge->Address = htole32(mpt->fw_phys); | |
6d259fc1 | 2409 | bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, BUS_DMASYNC_PREREAD); |
d751f32e MD |
2410 | error = mpt_send_handshake_cmd(mpt, sizeof(fw_req_buf), &fw_req_buf); |
2411 | if (error) | |
2412 | return(error); | |
2413 | error = mpt_recv_handshake_reply(mpt, sizeof(fw_reply), &fw_reply); | |
6d259fc1 | 2414 | bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, BUS_DMASYNC_POSTREAD); |
d751f32e MD |
2415 | return (error); |
2416 | } | |
2417 | ||
2418 | static void | |
2419 | mpt_diag_outsl(struct mpt_softc *mpt, uint32_t addr, | |
2420 | uint32_t *data, bus_size_t len) | |
2421 | { | |
2422 | uint32_t *data_end; | |
2423 | ||
2424 | data_end = data + (roundup2(len, sizeof(uint32_t)) / 4); | |
2425 | if (mpt->is_sas) { | |
2426 | pci_enable_io(mpt->dev, SYS_RES_IOPORT); | |
2427 | } | |
2428 | mpt_pio_write(mpt, MPT_OFFSET_DIAG_ADDR, addr); | |
2429 | while (data != data_end) { | |
2430 | mpt_pio_write(mpt, MPT_OFFSET_DIAG_DATA, *data); | |
2431 | data++; | |
2432 | } | |
2433 | if (mpt->is_sas) { | |
2434 | pci_disable_io(mpt->dev, SYS_RES_IOPORT); | |
2435 | } | |
2436 | } | |
2437 | ||
2438 | static int | |
2439 | mpt_download_fw(struct mpt_softc *mpt) | |
984263bc | 2440 | { |
d751f32e MD |
2441 | MpiFwHeader_t *fw_hdr; |
2442 | int error; | |
2443 | uint32_t ext_offset; | |
2444 | uint32_t data; | |
984263bc | 2445 | |
4c42baf4 SW |
2446 | if (mpt->pci_pio_reg == NULL) { |
2447 | mpt_prt(mpt, "No PIO resource!\n"); | |
2448 | return (ENXIO); | |
2449 | } | |
2450 | ||
d751f32e MD |
2451 | mpt_prt(mpt, "Downloading Firmware - Image Size %d\n", |
2452 | mpt->fw_image_size); | |
984263bc | 2453 | |
d751f32e MD |
2454 | error = mpt_enable_diag_mode(mpt); |
2455 | if (error != 0) { | |
2456 | mpt_prt(mpt, "Could not enter diagnostic mode!\n"); | |
2457 | return (EIO); | |
2458 | } | |
984263bc | 2459 | |
d751f32e MD |
2460 | mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, |
2461 | MPI_DIAG_RW_ENABLE|MPI_DIAG_DISABLE_ARM); | |
2462 | ||
2463 | fw_hdr = (MpiFwHeader_t *)mpt->fw_image; | |
6d259fc1 | 2464 | bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, BUS_DMASYNC_PREWRITE); |
d751f32e MD |
2465 | mpt_diag_outsl(mpt, fw_hdr->LoadStartAddress, (uint32_t*)fw_hdr, |
2466 | fw_hdr->ImageSize); | |
6d259fc1 | 2467 | bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, BUS_DMASYNC_POSTWRITE); |
d751f32e MD |
2468 | |
2469 | ext_offset = fw_hdr->NextImageHeaderOffset; | |
2470 | while (ext_offset != 0) { | |
2471 | MpiExtImageHeader_t *ext; | |
2472 | ||
2473 | ext = (MpiExtImageHeader_t *)((uintptr_t)fw_hdr + ext_offset); | |
2474 | ext_offset = ext->NextImageHeaderOffset; | |
6d259fc1 SW |
2475 | bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, |
2476 | BUS_DMASYNC_PREWRITE); | |
d751f32e MD |
2477 | mpt_diag_outsl(mpt, ext->LoadStartAddress, (uint32_t*)ext, |
2478 | ext->ImageSize); | |
6d259fc1 SW |
2479 | bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, |
2480 | BUS_DMASYNC_POSTWRITE); | |
984263bc | 2481 | } |
984263bc | 2482 | |
d751f32e MD |
2483 | if (mpt->is_sas) { |
2484 | pci_enable_io(mpt->dev, SYS_RES_IOPORT); | |
2485 | } | |
2486 | /* Setup the address to jump to on reset. */ | |
2487 | mpt_pio_write(mpt, MPT_OFFSET_DIAG_ADDR, fw_hdr->IopResetRegAddr); | |
2488 | mpt_pio_write(mpt, MPT_OFFSET_DIAG_DATA, fw_hdr->IopResetVectorValue); | |
984263bc | 2489 | |
d751f32e MD |
2490 | /* |
2491 | * The controller sets the "flash bad" status after attempting | |
2492 | * to auto-boot from flash. Clear the status so that the controller | |
2493 | * will continue the boot process with our newly installed firmware. | |
2494 | */ | |
2495 | mpt_pio_write(mpt, MPT_OFFSET_DIAG_ADDR, MPT_DIAG_MEM_CFG_BASE); | |
2496 | data = mpt_pio_read(mpt, MPT_OFFSET_DIAG_DATA) | MPT_DIAG_MEM_CFG_BADFL; | |
2497 | mpt_pio_write(mpt, MPT_OFFSET_DIAG_ADDR, MPT_DIAG_MEM_CFG_BASE); | |
2498 | mpt_pio_write(mpt, MPT_OFFSET_DIAG_DATA, data); | |
984263bc | 2499 | |
d751f32e MD |
2500 | if (mpt->is_sas) { |
2501 | pci_disable_io(mpt->dev, SYS_RES_IOPORT); | |
984263bc | 2502 | } |
984263bc | 2503 | |
d751f32e MD |
2504 | /* |
2505 | * Re-enable the processor and clear the boot halt flag. | |
2506 | */ | |
2507 | data = mpt_read(mpt, MPT_OFFSET_DIAGNOSTIC); | |
2508 | data &= ~(MPI_DIAG_PREVENT_IOC_BOOT|MPI_DIAG_DISABLE_ARM); | |
2509 | mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, data); | |
2510 | ||
2511 | mpt_disable_diag_mode(mpt); | |
984263bc MD |
2512 | return (0); |
2513 | } | |
2514 | ||
6d259fc1 SW |
2515 | static int |
2516 | mpt_dma_buf_alloc(struct mpt_softc *mpt) | |
2517 | { | |
2518 | struct mpt_map_info mi; | |
2519 | uint8_t *vptr; | |
2520 | uint32_t pptr, end; | |
2521 | int i, error; | |
2522 | ||
2523 | /* Create a child tag for data buffers */ | |
2524 | if (mpt_dma_tag_create(mpt, mpt->parent_dmat, 1, | |
2525 | 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, | |
2526 | NULL, NULL, (mpt->max_cam_seg_cnt - 1) * PAGE_SIZE, | |
2527 | mpt->max_cam_seg_cnt, BUS_SPACE_MAXSIZE_32BIT, 0, | |
2528 | &mpt->buffer_dmat) != 0) { | |
2529 | mpt_prt(mpt, "cannot create a dma tag for data buffers\n"); | |
2530 | return (1); | |
2531 | } | |
2532 | ||
2533 | /* Create a child tag for request buffers */ | |
2534 | if (mpt_dma_tag_create(mpt, mpt->parent_dmat, PAGE_SIZE, 0, | |
2535 | BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, | |
2536 | NULL, NULL, MPT_REQ_MEM_SIZE(mpt), 1, BUS_SPACE_MAXSIZE_32BIT, 0, | |
2537 | &mpt->request_dmat) != 0) { | |
2538 | mpt_prt(mpt, "cannot create a dma tag for requests\n"); | |
2539 | return (1); | |
2540 | } | |
2541 | ||
2542 | /* Allocate some DMA accessible memory for requests */ | |
2543 | if (bus_dmamem_alloc(mpt->request_dmat, (void **)&mpt->request, | |
2544 | BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &mpt->request_dmap) != 0) { | |
2545 | mpt_prt(mpt, "cannot allocate %d bytes of request memory\n", | |
2546 | MPT_REQ_MEM_SIZE(mpt)); | |
2547 | return (1); | |
2548 | } | |
2549 | ||
2550 | mi.mpt = mpt; | |
2551 | mi.error = 0; | |
2552 | ||
2553 | /* Load and lock it into "bus space" */ | |
2554 | bus_dmamap_load(mpt->request_dmat, mpt->request_dmap, mpt->request, | |
2555 | MPT_REQ_MEM_SIZE(mpt), mpt_map_rquest, &mi, 0); | |
2556 | ||
2557 | if (mi.error) { | |
2558 | mpt_prt(mpt, "error %d loading dma map for DMA request queue\n", | |
2559 | mi.error); | |
2560 | return (1); | |
2561 | } | |
2562 | mpt->request_phys = mi.phys; | |
2563 | ||
2564 | /* | |
2565 | * Now create per-request dma maps | |
2566 | */ | |
2567 | i = 0; | |
2568 | pptr = mpt->request_phys; | |
2569 | vptr = mpt->request; | |
2570 | end = pptr + MPT_REQ_MEM_SIZE(mpt); | |
2571 | while(pptr < end) { | |
2572 | request_t *req = &mpt->request_pool[i]; | |
2573 | req->index = i++; | |
2574 | ||
2575 | /* Store location of Request Data */ | |
2576 | req->req_pbuf = pptr; | |
2577 | req->req_vbuf = vptr; | |
2578 | ||
2579 | pptr += MPT_REQUEST_AREA; | |
2580 | vptr += MPT_REQUEST_AREA; | |
2581 | ||
2582 | req->sense_pbuf = (pptr - MPT_SENSE_SIZE); | |
2583 | req->sense_vbuf = (vptr - MPT_SENSE_SIZE); | |
2584 | ||
2585 | error = bus_dmamap_create(mpt->buffer_dmat, 0, &req->dmap); | |
2586 | if (error) { | |
2587 | mpt_prt(mpt, "error %d creating per-cmd DMA maps\n", | |
2588 | error); | |
2589 | return (1); | |
2590 | } | |
2591 | } | |
2592 | ||
2593 | return (0); | |
2594 | } | |
2595 | ||
2596 | static void | |
2597 | mpt_dma_buf_free(struct mpt_softc *mpt) | |
2598 | { | |
2599 | int i; | |
4c42baf4 | 2600 | |
6d259fc1 SW |
2601 | if (mpt->request_dmat == 0) { |
2602 | mpt_lprt(mpt, MPT_PRT_DEBUG, "already released dma memory\n"); | |
2603 | return; | |
2604 | } | |
2605 | for (i = 0; i < MPT_MAX_REQUESTS(mpt); i++) { | |
2606 | bus_dmamap_destroy(mpt->buffer_dmat, mpt->request_pool[i].dmap); | |
2607 | } | |
2608 | bus_dmamap_unload(mpt->request_dmat, mpt->request_dmap); | |
2609 | bus_dmamem_free(mpt->request_dmat, mpt->request, mpt->request_dmap); | |
2610 | bus_dma_tag_destroy(mpt->request_dmat); | |
2611 | mpt->request_dmat = 0; | |
2612 | bus_dma_tag_destroy(mpt->buffer_dmat); | |
2613 | } | |
2614 | ||
984263bc | 2615 | /* |
d751f32e MD |
2616 | * Allocate/Initialize data structures for the controller. Called |
2617 | * once at instance startup. | |
984263bc MD |
2618 | */ |
2619 | static int | |
d751f32e | 2620 | mpt_configure_ioc(struct mpt_softc *mpt, int tn, int needreset) |
984263bc | 2621 | { |
d751f32e | 2622 | PTR_MSG_PORT_FACTS_REPLY pfp; |
6d259fc1 | 2623 | int error, port, val; |
d751f32e | 2624 | size_t len; |
984263bc | 2625 | |
d751f32e | 2626 | if (tn == MPT_MAX_TRYS) { |
984263bc MD |
2627 | return (-1); |
2628 | } | |
984263bc | 2629 | |
d751f32e MD |
2630 | /* |
2631 | * No need to reset if the IOC is already in the READY state. | |
2632 | * | |
2633 | * Force reset if initialization failed previously. | |
2634 | * Note that a hard_reset of the second channel of a '929 | |
2635 | * will stop operation of the first channel. Hopefully, if the | |
2636 | * first channel is ok, the second will not require a hard | |
2637 | * reset. | |
2638 | */ | |
2639 | if (needreset || MPT_STATE(mpt_rd_db(mpt)) != MPT_DB_STATE_READY) { | |
2640 | if (mpt_reset(mpt, FALSE) != MPT_OK) { | |
2641 | return (mpt_configure_ioc(mpt, tn++, 1)); | |
2642 | } | |
2643 | needreset = 0; | |
984263bc | 2644 | } |
d751f32e MD |
2645 | |
2646 | if (mpt_get_iocfacts(mpt, &mpt->ioc_facts) != MPT_OK) { | |
2647 | mpt_prt(mpt, "mpt_get_iocfacts failed\n"); | |
2648 | return (mpt_configure_ioc(mpt, tn++, 1)); | |
984263bc | 2649 | } |
d751f32e | 2650 | mpt2host_iocfacts_reply(&mpt->ioc_facts); |
984263bc | 2651 | |
d751f32e MD |
2652 | mpt_prt(mpt, "MPI Version=%d.%d.%d.%d\n", |
2653 | mpt->ioc_facts.MsgVersion >> 8, | |
2654 | mpt->ioc_facts.MsgVersion & 0xFF, | |
2655 | mpt->ioc_facts.HeaderVersion >> 8, | |
2656 | mpt->ioc_facts.HeaderVersion & 0xFF); | |
2657 | ||
2658 | /* | |
2659 | * Now that we know request frame size, we can calculate | |
2660 | * the actual (reasonable) segment limit for read/write I/O. | |
2661 | * | |
2662 | * This limit is constrained by: | |
2663 | * | |
2664 | * + The size of each area we allocate per command (and how | |
2665 | * many chain segments we can fit into it). | |
2666 | * + The total number of areas we've set up. | |
2667 | * + The actual chain depth the card will allow. | |
2668 | * | |
2669 | * The first area's segment count is limited by the I/O request | |
2670 | * at the head of it. We cannot allocate realistically more | |
2671 | * than MPT_MAX_REQUESTS areas. Therefore, to account for both | |
2672 | * conditions, we'll just start out with MPT_MAX_REQUESTS-2. | |
2673 | * | |
2674 | */ | |
2675 | /* total number of request areas we (can) allocate */ | |
2676 | mpt->max_seg_cnt = MPT_MAX_REQUESTS(mpt) - 2; | |
2677 | ||
2678 | /* converted to the number of chain areas possible */ | |
2679 | mpt->max_seg_cnt *= MPT_NRFM(mpt); | |
2680 | ||
2681 | /* limited by the number of chain areas the card will support */ | |
2682 | if (mpt->max_seg_cnt > mpt->ioc_facts.MaxChainDepth) { | |
6d259fc1 | 2683 | mpt_lprt(mpt, MPT_PRT_INFO, |
d751f32e MD |
2684 | "chain depth limited to %u (from %u)\n", |
2685 | mpt->ioc_facts.MaxChainDepth, mpt->max_seg_cnt); | |
2686 | mpt->max_seg_cnt = mpt->ioc_facts.MaxChainDepth; | |
984263bc MD |
2687 | } |
2688 | ||
d751f32e MD |
2689 | /* converted to the number of simple sges in chain segments. */ |
2690 | mpt->max_seg_cnt *= (MPT_NSGL(mpt) - 1); | |
2691 | ||
6d259fc1 SW |
2692 | /* |
2693 | * Use this as the basis for reporting the maximum I/O size to CAM. | |
2694 | */ | |
2695 | mpt->max_cam_seg_cnt = min(mpt->max_seg_cnt, (MAXPHYS / PAGE_SIZE) + 1); | |
2696 | ||
2697 | error = mpt_dma_buf_alloc(mpt); | |
2698 | if (error != 0) { | |
2699 | mpt_prt(mpt, "mpt_dma_buf_alloc() failed!\n"); | |
2700 | return (EIO); | |
2701 | } | |
2702 | ||
2703 | for (val = 0; val < MPT_MAX_REQUESTS(mpt); val++) { | |
2704 | request_t *req = &mpt->request_pool[val]; | |
2705 | req->state = REQ_STATE_ALLOCATED; | |
2706 | mpt_callout_init(mpt, &req->callout); | |
2707 | mpt_free_request(mpt, req); | |
2708 | } | |
2709 | ||
2710 | mpt_lprt(mpt, MPT_PRT_INFO, "Maximum Segment Count: %u, Maximum " | |
2711 | "CAM Segment Count: %u\n", mpt->max_seg_cnt, | |
2712 | mpt->max_cam_seg_cnt); | |
2713 | ||
2714 | mpt_lprt(mpt, MPT_PRT_INFO, "MsgLength=%u IOCNumber = %d\n", | |
d751f32e | 2715 | mpt->ioc_facts.MsgLength, mpt->ioc_facts.IOCNumber); |
6d259fc1 | 2716 | mpt_lprt(mpt, MPT_PRT_INFO, |
d751f32e MD |
2717 | "IOCFACTS: GlobalCredits=%d BlockSize=%u bytes " |
2718 | "Request Frame Size %u bytes Max Chain Depth %u\n", | |
2719 | mpt->ioc_facts.GlobalCredits, mpt->ioc_facts.BlockSize, | |
2720 | mpt->ioc_facts.RequestFrameSize << 2, | |
2721 | mpt->ioc_facts.MaxChainDepth); | |
6d259fc1 | 2722 | mpt_lprt(mpt, MPT_PRT_INFO, "IOCFACTS: Num Ports %d, FWImageSize %d, " |
d751f32e | 2723 | "Flags=%#x\n", mpt->ioc_facts.NumberOfPorts, |
6d259fc1 | 2724 | mpt->ioc_facts.FWImageSize, mpt->ioc_facts.Flags); |
d751f32e MD |
2725 | |
2726 | len = mpt->ioc_facts.NumberOfPorts * sizeof (MSG_PORT_FACTS_REPLY); | |
2545bca0 | 2727 | mpt->port_facts = kmalloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); |
d751f32e MD |
2728 | if (mpt->port_facts == NULL) { |
2729 | mpt_prt(mpt, "unable to allocate memory for port facts\n"); | |
2730 | return (ENOMEM); | |
984263bc MD |
2731 | } |
2732 | ||
d751f32e MD |
2733 | |
2734 | if ((mpt->ioc_facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) && | |
2735 | (mpt->fw_uploaded == 0)) { | |
2736 | struct mpt_map_info mi; | |
2737 | ||
2738 | /* | |
2739 | * In some configurations, the IOC's firmware is | |
2740 | * stored in a shared piece of system NVRAM that | |
6d259fc1 | 2741 | * is only accessible via the BIOS. In this |
d751f32e MD |
2742 | * case, the firmware keeps a copy of firmware in |
2743 | * RAM until the OS driver retrieves it. Once | |
2744 | * retrieved, we are responsible for re-downloading | |
2745 | * the firmware after any hard-reset. | |
2746 | */ | |
2747 | mpt->fw_image_size = mpt->ioc_facts.FWImageSize; | |
2748 | error = mpt_dma_tag_create(mpt, mpt->parent_dmat, 1, 0, | |
2749 | BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, | |
2750 | mpt->fw_image_size, 1, mpt->fw_image_size, 0, | |
2751 | &mpt->fw_dmat); | |
2752 | if (error != 0) { | |
6d259fc1 | 2753 | mpt_prt(mpt, "cannot create firmware dma tag\n"); |
d751f32e | 2754 | return (ENOMEM); |
984263bc | 2755 | } |
d751f32e | 2756 | error = bus_dmamem_alloc(mpt->fw_dmat, |
6d259fc1 SW |
2757 | (void **)&mpt->fw_image, BUS_DMA_NOWAIT | |
2758 | BUS_DMA_COHERENT, &mpt->fw_dmap); | |
d751f32e MD |
2759 | if (error != 0) { |
2760 | mpt_prt(mpt, "cannot allocate firmware memory\n"); | |
2761 | bus_dma_tag_destroy(mpt->fw_dmat); | |
2762 | return (ENOMEM); | |
984263bc | 2763 | } |
d751f32e MD |
2764 | mi.mpt = mpt; |
2765 | mi.error = 0; | |
2766 | bus_dmamap_load(mpt->fw_dmat, mpt->fw_dmap, | |
2767 | mpt->fw_image, mpt->fw_image_size, mpt_map_rquest, &mi, 0); | |
2768 | mpt->fw_phys = mi.phys; | |
2769 | ||
2770 | error = mpt_upload_fw(mpt); | |
2771 | if (error != 0) { | |
2772 | mpt_prt(mpt, "firmware upload failed.\n"); | |
2773 | bus_dmamap_unload(mpt->fw_dmat, mpt->fw_dmap); | |
2774 | bus_dmamem_free(mpt->fw_dmat, mpt->fw_image, | |
2775 | mpt->fw_dmap); | |
2776 | bus_dma_tag_destroy(mpt->fw_dmat); | |
2777 | mpt->fw_image = NULL; | |
2778 | return (EIO); | |
2779 | } | |
2780 | mpt->fw_uploaded = 1; | |
2781 | } | |
2782 | ||
2783 | for (port = 0; port < mpt->ioc_facts.NumberOfPorts; port++) { | |
2784 | pfp = &mpt->port_facts[port]; | |
2785 | error = mpt_get_portfacts(mpt, 0, pfp); | |
2786 | if (error != MPT_OK) { | |
2787 | mpt_prt(mpt, | |
2788 | "mpt_get_portfacts on port %d failed\n", port); | |
2545bca0 | 2789 | kfree(mpt->port_facts, M_DEVBUF); |
d751f32e MD |
2790 | mpt->port_facts = NULL; |
2791 | return (mpt_configure_ioc(mpt, tn++, 1)); | |
984263bc | 2792 | } |
d751f32e MD |
2793 | mpt2host_portfacts_reply(pfp); |
2794 | ||
2795 | if (port > 0) { | |
2796 | error = MPT_PRT_INFO; | |
2797 | } else { | |
2798 | error = MPT_PRT_DEBUG; | |
984263bc | 2799 | } |
d751f32e MD |
2800 | mpt_lprt(mpt, error, |
2801 | "PORTFACTS[%d]: Type %x PFlags %x IID %d MaxDev %d\n", | |
2802 | port, pfp->PortType, pfp->ProtocolFlags, pfp->PortSCSIID, | |
2803 | pfp->MaxDevices); | |
2804 | ||
984263bc MD |
2805 | } |
2806 | ||
2807 | /* | |
d751f32e | 2808 | * XXX: Not yet supporting more than port 0 |
984263bc | 2809 | */ |
d751f32e MD |
2810 | pfp = &mpt->port_facts[0]; |
2811 | if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_FC) { | |
2812 | mpt->is_fc = 1; | |
2813 | mpt->is_sas = 0; | |
2814 | mpt->is_spi = 0; | |
2815 | } else if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_SAS) { | |
2816 | mpt->is_fc = 0; | |
2817 | mpt->is_sas = 1; | |
2818 | mpt->is_spi = 0; | |
2819 | } else if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_SCSI) { | |
2820 | mpt->is_fc = 0; | |
2821 | mpt->is_sas = 0; | |
2822 | mpt->is_spi = 1; | |
6d259fc1 SW |
2823 | if (mpt->mpt_ini_id == MPT_INI_ID_NONE) |
2824 | mpt->mpt_ini_id = pfp->PortSCSIID; | |
d751f32e MD |
2825 | } else if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_ISCSI) { |
2826 | mpt_prt(mpt, "iSCSI not supported yet\n"); | |
2827 | return (ENXIO); | |
2828 | } else if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_INACTIVE) { | |
2829 | mpt_prt(mpt, "Inactive Port\n"); | |
2830 | return (ENXIO); | |
2831 | } else { | |
2832 | mpt_prt(mpt, "unknown Port Type %#x\n", pfp->PortType); | |
2833 | return (ENXIO); | |
984263bc MD |
2834 | } |
2835 | ||
d751f32e MD |
2836 | /* |
2837 | * Set our role with what this port supports. | |
2838 | * | |
2839 | * Note this might be changed later in different modules | |
2840 | * if this is different from what is wanted. | |
2841 | */ | |
2842 | mpt->role = MPT_ROLE_NONE; | |
2843 | if (pfp->ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) { | |
2844 | mpt->role |= MPT_ROLE_INITIATOR; | |
984263bc | 2845 | } |
d751f32e MD |
2846 | if (pfp->ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) { |
2847 | mpt->role |= MPT_ROLE_TARGET; | |
984263bc MD |
2848 | } |
2849 | ||
d751f32e MD |
2850 | /* |
2851 | * Enable the IOC | |
2852 | */ | |
2853 | if (mpt_enable_ioc(mpt, 1) != MPT_OK) { | |
2854 | mpt_prt(mpt, "unable to initialize IOC\n"); | |
2855 | return (ENXIO); | |
984263bc | 2856 | } |
984263bc | 2857 | |
d751f32e MD |
2858 | /* |
2859 | * Read IOC configuration information. | |
2860 | * | |
2861 | * We need this to determine whether or not we have certain | |
2862 | * settings for Integrated Mirroring (e.g.). | |
2863 | */ | |
2864 | mpt_read_config_info_ioc(mpt); | |
2865 | ||
984263bc MD |
2866 | return (0); |
2867 | } | |
2868 | ||
984263bc | 2869 | static int |
d751f32e | 2870 | mpt_enable_ioc(struct mpt_softc *mpt, int portenable) |
984263bc | 2871 | { |
d751f32e MD |
2872 | uint32_t pptr; |
2873 | int val; | |
984263bc | 2874 | |
d751f32e MD |
2875 | if (mpt_send_ioc_init(mpt, MPI_WHOINIT_HOST_DRIVER) != MPT_OK) { |
2876 | mpt_prt(mpt, "mpt_send_ioc_init failed\n"); | |
2877 | return (EIO); | |
2878 | } | |
984263bc | 2879 | |
d751f32e | 2880 | mpt_lprt(mpt, MPT_PRT_DEBUG, "mpt_send_ioc_init ok\n"); |
984263bc | 2881 | |
d751f32e MD |
2882 | if (mpt_wait_state(mpt, MPT_DB_STATE_RUNNING) != MPT_OK) { |
2883 | mpt_prt(mpt, "IOC failed to go to run state\n"); | |
2884 | return (ENXIO); | |
2885 | } | |
2886 | mpt_lprt(mpt, MPT_PRT_DEBUG, "IOC now at RUNSTATE\n"); | |
984263bc | 2887 | |
d751f32e MD |
2888 | /* |
2889 | * Give it reply buffers | |
2890 | * | |
2891 | * Do *not* exceed global credits. | |
2892 | */ | |
2893 | for (val = 0, pptr = mpt->reply_phys; | |
2894 | (pptr + MPT_REPLY_SIZE) < (mpt->reply_phys + PAGE_SIZE); | |
2895 | pptr += MPT_REPLY_SIZE) { | |
2896 | mpt_free_reply(mpt, pptr); | |
2897 | if (++val == mpt->ioc_facts.GlobalCredits - 1) | |
2898 | break; | |
984263bc | 2899 | } |
984263bc | 2900 | |
d751f32e MD |
2901 | |
2902 | /* | |
2903 | * Enable the port if asked. This is only done if we're resetting | |
2904 | * the IOC after initial startup. | |
2905 | */ | |
2906 | if (portenable) { | |
2907 | /* | |
2908 | * Enable asynchronous event reporting | |
2909 | */ | |
2910 | mpt_send_event_request(mpt, 1); | |
2911 | ||
2912 | if (mpt_send_port_enable(mpt, 0) != MPT_OK) { | |
6d259fc1 | 2913 | mpt_prt(mpt, "%s: failed to enable port 0\n", __func__); |
d751f32e | 2914 | return (ENXIO); |
984263bc | 2915 | } |
d751f32e MD |
2916 | } |
2917 | return (MPT_OK); | |
984263bc MD |
2918 | } |
2919 | ||
2920 | /* | |
d751f32e | 2921 | * Endian Conversion Functions- only used on Big Endian machines |
984263bc | 2922 | */ |
d751f32e MD |
2923 | #if _BYTE_ORDER == _BIG_ENDIAN |
2924 | void | |
2925 | mpt2host_sge_simple_union(SGE_SIMPLE_UNION *sge) | |
984263bc | 2926 | { |
984263bc | 2927 | |
d751f32e MD |
2928 | MPT_2_HOST32(sge, FlagsLength); |
2929 | MPT_2_HOST32(sge, u.Address64.Low); | |
2930 | MPT_2_HOST32(sge, u.Address64.High); | |
2931 | } | |
984263bc | 2932 | |
d751f32e MD |
2933 | void |
2934 | mpt2host_iocfacts_reply(MSG_IOC_FACTS_REPLY *rp) | |
2935 | { | |
984263bc | 2936 | |
d751f32e MD |
2937 | MPT_2_HOST16(rp, MsgVersion); |
2938 | MPT_2_HOST16(rp, HeaderVersion); | |
2939 | MPT_2_HOST32(rp, MsgContext); | |
2940 | MPT_2_HOST16(rp, IOCExceptions); | |
2941 | MPT_2_HOST16(rp, IOCStatus); | |
2942 | MPT_2_HOST32(rp, IOCLogInfo); | |
2943 | MPT_2_HOST16(rp, ReplyQueueDepth); | |
2944 | MPT_2_HOST16(rp, RequestFrameSize); | |
2945 | MPT_2_HOST16(rp, Reserved_0101_FWVersion); | |
2946 | MPT_2_HOST16(rp, ProductID); | |
2947 | MPT_2_HOST32(rp, CurrentHostMfaHighAddr); | |
2948 | MPT_2_HOST16(rp, GlobalCredits); | |
2949 | MPT_2_HOST32(rp, CurrentSenseBufferHighAddr); | |
2950 | MPT_2_HOST16(rp, CurReplyFrameSize); | |
2951 | MPT_2_HOST32(rp, FWImageSize); | |
2952 | MPT_2_HOST32(rp, IOCCapabilities); | |
2953 | MPT_2_HOST32(rp, FWVersion.Word); | |
2954 | MPT_2_HOST16(rp, HighPriorityQueueDepth); | |
2955 | MPT_2_HOST16(rp, Reserved2); | |
2956 | mpt2host_sge_simple_union(&rp->HostPageBufferSGE); | |
2957 | MPT_2_HOST32(rp, ReplyFifoHostSignalingAddr); | |
2958 | } | |
984263bc | 2959 | |
d751f32e MD |
2960 | void |
2961 | mpt2host_portfacts_reply(MSG_PORT_FACTS_REPLY *pfp) | |
2962 | { | |
984263bc | 2963 | |
d751f32e MD |
2964 | MPT_2_HOST16(pfp, Reserved); |
2965 | MPT_2_HOST16(pfp, Reserved1); | |
2966 | MPT_2_HOST32(pfp, MsgContext); | |
2967 | MPT_2_HOST16(pfp, Reserved2); | |
2968 | MPT_2_HOST16(pfp, IOCStatus); | |
2969 | MPT_2_HOST32(pfp, IOCLogInfo); | |
2970 | MPT_2_HOST16(pfp, MaxDevices); | |
2971 | MPT_2_HOST16(pfp, PortSCSIID); | |
2972 | MPT_2_HOST16(pfp, ProtocolFlags); | |
2973 | MPT_2_HOST16(pfp, MaxPostedCmdBuffers); | |
2974 | MPT_2_HOST16(pfp, MaxPersistentIDs); | |
2975 | MPT_2_HOST16(pfp, MaxLanBuckets); | |
2976 | MPT_2_HOST16(pfp, Reserved4); | |
2977 | MPT_2_HOST32(pfp, Reserved5); | |
984263bc MD |
2978 | } |
2979 | ||
984263bc | 2980 | void |
d751f32e | 2981 | mpt2host_config_page_ioc2(CONFIG_PAGE_IOC_2 *ioc2) |
984263bc | 2982 | { |
d751f32e MD |
2983 | int i; |
2984 | ||
2985 | MPT_2_HOST32(ioc2, CapabilitiesFlags); | |
2986 | for (i = 0; i < MPI_IOC_PAGE_2_RAID_VOLUME_MAX; i++) { | |
2987 | MPT_2_HOST16(ioc2, RaidVolume[i].Reserved3); | |
2988 | } | |
984263bc MD |
2989 | } |
2990 | ||
984263bc | 2991 | void |
d751f32e | 2992 | mpt2host_config_page_ioc3(CONFIG_PAGE_IOC_3 *ioc3) |
984263bc | 2993 | { |
d751f32e MD |
2994 | |
2995 | MPT_2_HOST16(ioc3, Reserved2); | |
984263bc MD |
2996 | } |
2997 | ||
d751f32e MD |
2998 | void |
2999 | mpt2host_config_page_scsi_port_0(CONFIG_PAGE_SCSI_PORT_0 *sp0) | |
984263bc | 3000 | { |
984263bc | 3001 | |
d751f32e MD |
3002 | MPT_2_HOST32(sp0, Capabilities); |
3003 | MPT_2_HOST32(sp0, PhysicalInterface); | |
3004 | } | |
984263bc | 3005 | |
d751f32e MD |
3006 | void |
3007 | mpt2host_config_page_scsi_port_1(CONFIG_PAGE_SCSI_PORT_1 *sp1) | |
3008 | { | |
984263bc | 3009 | |
d751f32e MD |
3010 | MPT_2_HOST32(sp1, Configuration); |
3011 | MPT_2_HOST32(sp1, OnBusTimerValue); | |
3012 | MPT_2_HOST16(sp1, IDConfig); | |
3013 | } | |
984263bc | 3014 | |
d751f32e MD |
3015 | void |
3016 | host2mpt_config_page_scsi_port_1(CONFIG_PAGE_SCSI_PORT_1 *sp1) | |
3017 | { | |
984263bc | 3018 | |
d751f32e MD |
3019 | HOST_2_MPT32(sp1, Configuration); |
3020 | HOST_2_MPT32(sp1, OnBusTimerValue); | |
3021 | HOST_2_MPT16(sp1, IDConfig); | |
3022 | } | |
984263bc | 3023 | |
d751f32e MD |
3024 | void |
3025 | mpt2host_config_page_scsi_port_2(CONFIG_PAGE_SCSI_PORT_2 *sp2) | |
3026 | { | |
3027 | int i; | |
984263bc | 3028 | |
d751f32e MD |
3029 | MPT_2_HOST32(sp2, PortFlags); |
3030 | MPT_2_HOST32(sp2, PortSettings); | |
3031 | for (i = 0; i < sizeof(sp2->DeviceSettings) / | |
3032 | sizeof(*sp2->DeviceSettings); i++) { | |
3033 | MPT_2_HOST16(sp2, DeviceSettings[i].DeviceFlags); | |
3034 | } | |
3035 | } | |
984263bc | 3036 | |
d751f32e MD |
3037 | void |
3038 | mpt2host_config_page_scsi_device_0(CONFIG_PAGE_SCSI_DEVICE_0 *sd0) | |
3039 | { | |
984263bc | 3040 | |
d751f32e MD |
3041 | MPT_2_HOST32(sd0, NegotiatedParameters); |
3042 | MPT_2_HOST32(sd0, Information); | |
3043 | } | |
984263bc | 3044 | |
d751f32e MD |
3045 | void |
3046 | mpt2host_config_page_scsi_device_1(CONFIG_PAGE_SCSI_DEVICE_1 *sd1) | |
3047 | { | |
984263bc | 3048 | |
d751f32e MD |
3049 | MPT_2_HOST32(sd1, RequestedParameters); |
3050 | MPT_2_HOST32(sd1, Reserved); | |
3051 | MPT_2_HOST32(sd1, Configuration); | |
3052 | } | |
984263bc | 3053 | |
d751f32e MD |
3054 | void |
3055 | host2mpt_config_page_scsi_device_1(CONFIG_PAGE_SCSI_DEVICE_1 *sd1) | |
3056 | { | |
984263bc | 3057 | |
d751f32e MD |
3058 | HOST_2_MPT32(sd1, RequestedParameters); |
3059 | HOST_2_MPT32(sd1, Reserved); | |
3060 | HOST_2_MPT32(sd1, Configuration); | |
3061 | } | |
984263bc | 3062 | |
d751f32e MD |
3063 | void |
3064 | mpt2host_config_page_fc_port_0(CONFIG_PAGE_FC_PORT_0 *fp0) | |
3065 | { | |
984263bc | 3066 | |
d751f32e MD |
3067 | MPT_2_HOST32(fp0, Flags); |
3068 | MPT_2_HOST32(fp0, PortIdentifier); | |
3069 | MPT_2_HOST32(fp0, WWNN.Low); | |
3070 | MPT_2_HOST32(fp0, WWNN.High); | |
3071 | MPT_2_HOST32(fp0, WWPN.Low); | |
3072 | MPT_2_HOST32(fp0, WWPN.High); | |
3073 | MPT_2_HOST32(fp0, SupportedServiceClass); | |
3074 | MPT_2_HOST32(fp0, SupportedSpeeds); | |
3075 | MPT_2_HOST32(fp0, CurrentSpeed); | |
3076 | MPT_2_HOST32(fp0, MaxFrameSize); | |
3077 | MPT_2_HOST32(fp0, FabricWWNN.Low); | |
3078 | MPT_2_HOST32(fp0, FabricWWNN.High); | |
3079 | MPT_2_HOST32(fp0, FabricWWPN.Low); | |
3080 | MPT_2_HOST32(fp0, FabricWWPN.High); | |
3081 | MPT_2_HOST32(fp0, DiscoveredPortsCount); | |
3082 | MPT_2_HOST32(fp0, MaxInitiators); | |
3083 | } | |
984263bc | 3084 | |
d751f32e MD |
3085 | void |
3086 | mpt2host_config_page_fc_port_1(CONFIG_PAGE_FC_PORT_1 *fp1) | |
3087 | { | |
984263bc | 3088 | |
d751f32e MD |
3089 | MPT_2_HOST32(fp1, Flags); |
3090 | MPT_2_HOST32(fp1, NoSEEPROMWWNN.Low); | |
3091 | MPT_2_HOST32(fp1, NoSEEPROMWWNN.High); | |
3092 | MPT_2_HOST32(fp1, NoSEEPROMWWPN.Low); | |
3093 | MPT_2_HOST32(fp1, NoSEEPROMWWPN.High); | |
3094 | } | |
984263bc | 3095 | |
d751f32e MD |
3096 | void |
3097 | host2mpt_config_page_fc_port_1(CONFIG_PAGE_FC_PORT_1 *fp1) | |
3098 | { | |
984263bc | 3099 | |
d751f32e MD |
3100 | HOST_2_MPT32(fp1, Flags); |
3101 | HOST_2_MPT32(fp1, NoSEEPROMWWNN.Low); | |
3102 | HOST_2_MPT32(fp1, NoSEEPROMWWNN.High); | |
3103 | HOST_2_MPT32(fp1, NoSEEPROMWWPN.Low); | |
3104 | HOST_2_MPT32(fp1, NoSEEPROMWWPN.High); | |
3105 | } | |
984263bc | 3106 | |
d751f32e MD |
3107 | void |
3108 | mpt2host_config_page_raid_vol_0(CONFIG_PAGE_RAID_VOL_0 *volp) | |
3109 | { | |
3110 | int i; | |
984263bc | 3111 | |
d751f32e MD |
3112 | MPT_2_HOST16(volp, VolumeStatus.Reserved); |
3113 | MPT_2_HOST16(volp, VolumeSettings.Settings); | |
3114 | MPT_2_HOST32(volp, MaxLBA); | |
3115 | MPT_2_HOST32(volp, MaxLBAHigh); | |
3116 | MPT_2_HOST32(volp, StripeSize); | |
3117 | MPT_2_HOST32(volp, Reserved2); | |
3118 | MPT_2_HOST32(volp, Reserved3); | |
3119 | for (i = 0; i < MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX; i++) { | |
3120 | MPT_2_HOST16(volp, PhysDisk[i].Reserved); | |
984263bc | 3121 | } |
d751f32e | 3122 | } |
984263bc | 3123 | |
d751f32e MD |
3124 | void |
3125 | mpt2host_config_page_raid_phys_disk_0(CONFIG_PAGE_RAID_PHYS_DISK_0 *rpd0) | |
3126 | { | |
3127 | ||
3128 | MPT_2_HOST32(rpd0, Reserved1); | |
3129 | MPT_2_HOST16(rpd0, PhysDiskStatus.Reserved); | |
3130 | MPT_2_HOST32(rpd0, MaxLBA); | |
3131 | MPT_2_HOST16(rpd0, ErrorData.Reserved); | |
3132 | MPT_2_HOST16(rpd0, ErrorData.ErrorCount); | |
3133 | MPT_2_HOST16(rpd0, ErrorData.SmartCount); | |
3134 | } | |
3135 | ||
3136 | void | |
3137 | mpt2host_mpi_raid_vol_indicator(MPI_RAID_VOL_INDICATOR *vi) | |
3138 | { | |
3139 | ||
3140 | MPT_2_HOST16(vi, TotalBlocks.High); | |
3141 | MPT_2_HOST16(vi, TotalBlocks.Low); | |
3142 | MPT_2_HOST16(vi, BlocksRemaining.High); | |
3143 | MPT_2_HOST16(vi, BlocksRemaining.Low); | |
984263bc | 3144 | } |
d751f32e | 3145 | #endif |