2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/ioapic_abi.h>
60 #include <machine_base/apic/lapic.h>
61 #include <machine_base/apic/ioapic.h>
62 #include <machine/psl.h>
63 #include <machine/segments.h>
64 #include <machine/tss.h>
65 #include <machine/specialreg.h>
66 #include <machine/globaldata.h>
67 #include <machine/pmap_inval.h>
69 #include <machine/md_var.h> /* setidt() */
70 #include <machine_base/icu/icu.h> /* IPIs */
71 #include <machine/intr_machdep.h> /* IPIs */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
83 * this code MUST be enabled here and in mpboot.s.
84 * it follows the very early stages of AP boot by placing values in CMOS ram.
85 * it NORMALLY will never be needed and thus the primitive method for enabling.
88 #if defined(CHECK_POINTS)
89 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
90 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
92 #define CHECK_INIT(D); \
93 CHECK_WRITE(0x34, (D)); \
94 CHECK_WRITE(0x35, (D)); \
95 CHECK_WRITE(0x36, (D)); \
96 CHECK_WRITE(0x37, (D)); \
97 CHECK_WRITE(0x38, (D)); \
98 CHECK_WRITE(0x39, (D));
100 #define CHECK_PRINT(S); \
101 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
110 #else /* CHECK_POINTS */
112 #define CHECK_INIT(D)
113 #define CHECK_PRINT(S)
115 #endif /* CHECK_POINTS */
118 * Values to send to the POST hardware.
120 #define MP_BOOTADDRESS_POST 0x10
121 #define MP_PROBE_POST 0x11
122 #define MPTABLE_PASS1_POST 0x12
124 #define MP_START_POST 0x13
125 #define MP_ENABLE_POST 0x14
126 #define MPTABLE_PASS2_POST 0x15
128 #define START_ALL_APS_POST 0x16
129 #define INSTALL_AP_TRAMP_POST 0x17
130 #define START_AP_POST 0x18
132 #define MP_ANNOUNCE_POST 0x19
134 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
135 int current_postcode;
137 /** XXX FIXME: what system files declare these??? */
138 extern struct region_descriptor r_gdt, r_idt;
140 int mp_naps; /* # of Applications processors */
143 u_int32_t cpu_apic_versions[MAXCPU];
145 extern int64_t tsc_offsets[];
147 #ifdef SMP /* APIC-IO */
148 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
152 * APIC ID logical/physical mapping structures.
153 * We oversize these to simplify boot-time config.
155 int cpu_num_to_apic_id[NAPICID];
156 int apic_id_to_logical[NAPICID];
158 /* AP uses this during bootstrap. Do not staticize. */
162 /* Hotwire a 0->4MB V==P mapping */
163 extern pt_entry_t *KPTphys;
166 * SMP page table page. Setup by locore to point to a page table
167 * page from which we allocate per-cpu privatespace areas io_apics,
170 extern pt_entry_t *SMPpt;
172 struct pcb stoppcbs[MAXCPU];
175 * Local data and functions.
178 static u_int boot_address;
179 static int mp_finish;
180 static int mp_finish_lapic;
182 static void mp_enable(u_int boot_addr);
184 static int start_all_aps(u_int boot_addr);
185 static void install_ap_tramp(u_int boot_addr);
186 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
187 static int smitest(void);
189 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
190 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
191 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
192 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
198 * Calculate usable address in base memory for AP trampoline code.
201 mp_bootaddress(u_int basemem)
203 POSTCODE(MP_BOOTADDRESS_POST);
205 base_memory = basemem;
207 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
208 if ((base_memory - boot_address) < bootMP_size)
209 boot_address -= 4096; /* not enough, lower by 4k */
215 * Startup the SMP processors.
220 POSTCODE(MP_START_POST);
221 mp_enable(boot_address);
226 * Print various information about the SMP system hardware and setup.
233 POSTCODE(MP_ANNOUNCE_POST);
235 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
236 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
237 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
238 for (x = 1; x <= mp_naps; ++x) {
239 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
240 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
244 kprintf(" Warning: APIC I/O disabled\n");
248 * AP cpu's call this to sync up protected mode.
250 * WARNING! We must ensure that the cpu is sufficiently initialized to
251 * be able to use to the FP for our optimized bzero/bcopy code before
252 * we enter more mainstream C code.
254 * WARNING! %fs is not set up on entry. This routine sets up %fs.
260 int x, myid = bootAP;
262 struct mdglobaldata *md;
263 struct privatespace *ps;
265 ps = &CPU_prvspace[myid];
267 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
268 gdt_segs[GPROC0_SEL].ssd_base =
269 (int) &ps->mdglobaldata.gd_common_tss;
270 ps->mdglobaldata.mi.gd_prvspace = ps;
272 for (x = 0; x < NGDT; x++) {
273 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
276 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
277 r_gdt.rd_base = (int) &gdt[myid * NGDT];
278 lgdt(&r_gdt); /* does magic intra-segment return */
283 mdcpu->gd_currentldt = _default_ldt;
285 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
286 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
288 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
290 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
291 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
292 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
293 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
294 md->gd_common_tssd = *md->gd_tss_gdt;
298 * Set to a known state:
299 * Set by mpboot.s: CR0_PG, CR0_PE
300 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
303 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
305 pmap_set_opt(); /* PSE/4MB pages, etc */
307 /* set up CPU registers and state */
310 /* set up FPU state on the AP */
311 npxinit(__INITIAL_NPXCW__);
313 /* set up SSE registers */
317 /*******************************************************************
318 * local functions and data
322 * start the SMP system
325 mp_enable(u_int boot_addr)
327 POSTCODE(MP_ENABLE_POST);
331 /* Initialize BSP's local APIC */
334 /* start each Application Processor */
335 start_all_aps(boot_addr);
341 MachIntrABI.finalize();
345 mp_set_cpuids(int cpu_id, int apic_id)
347 CPU_TO_ID(cpu_id) = apic_id;
348 ID_TO_CPU(apic_id) = cpu_id;
352 ioapic_map(vm_paddr_t pa)
354 KKASSERT(pa < 0x100000000LL);
355 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
359 * start each AP in our list
362 start_all_aps(u_int boot_addr)
370 u_long mpbioswarmvec;
371 struct mdglobaldata *gd;
372 struct privatespace *ps;
376 POSTCODE(START_ALL_APS_POST);
378 /* install the AP 1st level boot code */
379 install_ap_tramp(boot_addr);
382 /* save the current value of the warm-start vector */
383 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
384 outb(CMOS_REG, BIOS_RESET);
385 mpbiosreason = inb(CMOS_DATA);
387 /* setup a vector to our boot code */
388 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
389 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
390 outb(CMOS_REG, BIOS_RESET);
391 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
394 * If we have a TSC we can figure out the SMI interrupt rate.
395 * The SMI does not necessarily use a constant rate. Spend
396 * up to 250ms trying to figure it out.
399 if (cpu_feature & CPUID_TSC) {
400 set_apic_timer(275000);
401 smilast = read_apic_timer();
402 for (x = 0; x < 20 && read_apic_timer(); ++x) {
403 smicount = smitest();
404 if (smibest == 0 || smilast - smicount < smibest)
405 smibest = smilast - smicount;
408 if (smibest > 250000)
411 smibest = smibest * (int64_t)1000000 /
412 get_apic_timer_frequency();
416 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
417 1000000 / smibest, smibest);
420 /* set up temporary P==V mapping for AP boot */
421 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
422 kptbase = (uintptr_t)(void *)KPTphys;
423 for (x = 0; x < NKPT; x++) {
424 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
425 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
430 for (x = 1; x <= mp_naps; ++x) {
432 /* This is a bit verbose, it will go away soon. */
434 /* first page of AP's private space */
435 pg = x * i386_btop(sizeof(struct privatespace));
437 /* allocate new private data page(s) */
438 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
439 MDGLOBALDATA_BASEALLOC_SIZE);
440 /* wire it into the private page table page */
441 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
442 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
443 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
445 pg += MDGLOBALDATA_BASEALLOC_PAGES;
447 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
448 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
449 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
450 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
452 /* allocate and set up an idle stack data page */
453 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
454 for (i = 0; i < UPAGES; i++) {
455 SMPpt[pg + 4 + i] = (pt_entry_t)
456 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
459 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
460 bzero(gd, sizeof(*gd));
461 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
463 /* prime data page for it to use */
464 mi_gdinit(&gd->mi, x);
466 gd->gd_CMAP1 = &SMPpt[pg + 0];
467 gd->gd_CMAP2 = &SMPpt[pg + 1];
468 gd->gd_CMAP3 = &SMPpt[pg + 2];
469 gd->gd_PMAP1 = &SMPpt[pg + 3];
470 gd->gd_CADDR1 = ps->CPAGE1;
471 gd->gd_CADDR2 = ps->CPAGE2;
472 gd->gd_CADDR3 = ps->CPAGE3;
473 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
476 * Per-cpu pmap for get_ptbase().
478 gd->gd_GDADDR1= (unsigned *)
479 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
480 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
482 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
483 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
486 * Setup the AP boot stack
488 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
491 /* attempt to start the Application Processor */
492 CHECK_INIT(99); /* setup checkpoints */
493 if (!start_ap(gd, boot_addr, smibest)) {
494 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
495 CHECK_PRINT("trace"); /* show checkpoints */
496 /* better panic as the AP may be running loose */
497 kprintf("panic y/n? [y] ");
501 CHECK_PRINT("trace"); /* show checkpoints */
503 /* record its version info */
504 cpu_apic_versions[x] = cpu_apic_versions[0];
507 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
510 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
511 for (shift = 0; (1 << shift) <= ncpus; ++shift)
514 ncpus2_shift = shift;
516 ncpus2_mask = ncpus2 - 1;
518 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
519 if ((1 << shift) < ncpus)
521 ncpus_fit = 1 << shift;
522 ncpus_fit_mask = ncpus_fit - 1;
524 /* build our map of 'other' CPUs */
525 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
526 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
527 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
529 /* fill in our (BSP) APIC version */
530 cpu_apic_versions[0] = lapic->version;
532 /* restore the warmstart vector */
533 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
534 outb(CMOS_REG, BIOS_RESET);
535 outb(CMOS_DATA, mpbiosreason);
538 * NOTE! The idlestack for the BSP was setup by locore. Finish
539 * up, clean out the P==V mapping we did earlier.
541 for (x = 0; x < NKPT; x++)
546 * Wait all APs to finish initializing LAPIC
550 kprintf("SMP: Waiting APs LAPIC initialization\n");
551 if (cpu_feature & CPUID_TSC)
552 tsc0_offset = rdtsc();
555 while (smp_lapic_mask != smp_startup_mask) {
557 if (cpu_feature & CPUID_TSC)
558 tsc0_offset = rdtsc();
560 while (try_mplock() == 0)
563 /* number of APs actually started */
568 * load the 1st level AP boot code into base memory.
571 /* targets for relocation */
572 extern void bigJump(void);
573 extern void bootCodeSeg(void);
574 extern void bootDataSeg(void);
575 extern void MPentry(void);
577 extern u_int mp_gdtbase;
580 install_ap_tramp(u_int boot_addr)
583 int size = *(int *) ((u_long) & bootMP_size);
584 u_char *src = (u_char *) ((u_long) bootMP);
585 u_char *dst = (u_char *) boot_addr + KERNBASE;
586 u_int boot_base = (u_int) bootMP;
591 POSTCODE(INSTALL_AP_TRAMP_POST);
593 for (x = 0; x < size; ++x)
597 * modify addresses in code we just moved to basemem. unfortunately we
598 * need fairly detailed info about mpboot.s for this to work. changes
599 * to mpboot.s might require changes here.
602 /* boot code is located in KERNEL space */
603 dst = (u_char *) boot_addr + KERNBASE;
605 /* modify the lgdt arg */
606 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
607 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
609 /* modify the ljmp target for MPentry() */
610 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
611 *dst32 = ((u_int) MPentry - KERNBASE);
613 /* modify the target for boot code segment */
614 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
615 dst8 = (u_int8_t *) (dst16 + 1);
616 *dst16 = (u_int) boot_addr & 0xffff;
617 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
619 /* modify the target for boot data segment */
620 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
621 dst8 = (u_int8_t *) (dst16 + 1);
622 *dst16 = (u_int) boot_addr & 0xffff;
623 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
628 * This function starts the AP (application processor) identified
629 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
630 * to accomplish this. This is necessary because of the nuances
631 * of the different hardware we might encounter. It ain't pretty,
632 * but it seems to work.
634 * NOTE: eventually an AP gets to ap_init(), which is called just
635 * before the AP goes into the LWKT scheduler's idle loop.
638 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
642 u_long icr_lo, icr_hi;
644 POSTCODE(START_AP_POST);
646 /* get the PHYSICAL APIC ID# */
647 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
649 /* calculate the vector */
650 vector = (boot_addr >> 12) & 0xff;
652 /* We don't want anything interfering */
655 /* Make sure the target cpu sees everything */
659 * Try to detect when a SMI has occurred, wait up to 200ms.
661 * If a SMI occurs during an AP reset but before we issue
662 * the STARTUP command, the AP may brick. To work around
663 * this problem we hold off doing the AP startup until
664 * after we have detected the SMI. Hopefully another SMI
665 * will not occur before we finish the AP startup.
667 * Retries don't seem to help. SMIs have a window of opportunity
668 * and if USB->legacy keyboard emulation is enabled in the BIOS
669 * the interrupt rate can be quite high.
671 * NOTE: Don't worry about the L1 cache load, it might bloat
672 * ldelta a little but ndelta will be so huge when the SMI
673 * occurs the detection logic will still work fine.
676 set_apic_timer(200000);
681 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
682 * and running the target CPU. OR this INIT IPI might be latched (P5
683 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
686 * see apic/apicreg.h for icr bit definitions.
688 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
692 * Setup the address for the target AP. We can setup
693 * icr_hi once and then just trigger operations with
696 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
697 icr_hi |= (physical_cpu << 24);
698 icr_lo = lapic->icr_lo & 0xfff00000;
699 lapic->icr_hi = icr_hi;
702 * Do an INIT IPI: assert RESET
704 * Use edge triggered mode to assert INIT
706 lapic->icr_lo = icr_lo | 0x0000c500;
707 while (lapic->icr_lo & APIC_DELSTAT_MASK)
711 * The spec calls for a 10ms delay but we may have to use a
712 * MUCH lower delay to avoid bricking an AP due to a fast SMI
713 * interrupt. We have other loops here too and dividing by 2
714 * doesn't seem to be enough even after subtracting 350us,
717 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
718 * interrupt was detected we use the full 10ms.
722 else if (smibest < 150 * 4 + 350)
724 else if ((smibest - 350) / 4 < 10000)
725 u_sleep((smibest - 350) / 4);
730 * Do an INIT IPI: deassert RESET
732 * Use level triggered mode to deassert. It is unclear
733 * why we need to do this.
735 lapic->icr_lo = icr_lo | 0x00008500;
736 while (lapic->icr_lo & APIC_DELSTAT_MASK)
738 u_sleep(150); /* wait 150us */
741 * Next we do a STARTUP IPI: the previous INIT IPI might still be
742 * latched, (P5 bug) this 1st STARTUP would then terminate
743 * immediately, and the previously started INIT IPI would continue. OR
744 * the previous INIT IPI has already run. and this STARTUP IPI will
745 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
748 lapic->icr_lo = icr_lo | 0x00000600 | vector;
749 while (lapic->icr_lo & APIC_DELSTAT_MASK)
751 u_sleep(200); /* wait ~200uS */
754 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
755 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
756 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
757 * recognized after hardware RESET or INIT IPI.
759 lapic->icr_lo = icr_lo | 0x00000600 | vector;
760 while (lapic->icr_lo & APIC_DELSTAT_MASK)
763 /* Resume normal operation */
766 /* wait for it to start, see ap_init() */
767 set_apic_timer(5000000);/* == 5 seconds */
768 while (read_apic_timer()) {
769 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
770 return 1; /* return SUCCESS */
773 return 0; /* return FAILURE */
788 while (read_apic_timer()) {
790 for (count = 0; count < 100; ++count)
791 ntsc = rdtsc(); /* force loop to occur */
793 ndelta = ntsc - ltsc;
796 if (ndelta > ldelta * 2)
799 ldelta = ntsc - ltsc;
802 return(read_apic_timer());
806 * Lazy flush the TLB on all other CPU's. DEPRECATED.
808 * If for some reason we were unable to start all cpus we cannot safely
809 * use broadcast IPIs.
812 static cpumask_t smp_invltlb_req;
813 #define SMP_INVLTLB_DEBUG
819 struct mdglobaldata *md = mdcpu;
820 #ifdef SMP_INVLTLB_DEBUG
825 crit_enter_gd(&md->mi);
826 md->gd_invltlb_ret = 0;
827 ++md->mi.gd_cnt.v_smpinvltlb;
828 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
829 #ifdef SMP_INVLTLB_DEBUG
832 if (smp_startup_mask == smp_active_mask) {
833 all_but_self_ipi(XINVLTLB_OFFSET);
835 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
836 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
839 #ifdef SMP_INVLTLB_DEBUG
841 kprintf("smp_invltlb: ipi sent\n");
843 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
844 (smp_active_mask & ~md->mi.gd_cpumask)) {
847 #ifdef SMP_INVLTLB_DEBUG
849 if (++count == 400000000) {
851 kprintf("smp_invltlb: endless loop %08lx %08lx, "
852 "rflags %016lx retry",
853 (long)md->gd_invltlb_ret,
854 (long)smp_invltlb_req,
855 (long)read_eflags());
856 __asm __volatile ("sti");
861 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
865 kprintf("bcpu %d\n", bcpu);
866 xgd = globaldata_find(bcpu);
867 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
876 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
877 crit_exit_gd(&md->mi);
884 * Called from Xinvltlb assembly with interrupts disabled. We didn't
885 * bother to bump the critical section count or nested interrupt count
886 * so only do very low level operations here.
889 smp_invltlb_intr(void)
891 struct mdglobaldata *md = mdcpu;
892 struct mdglobaldata *omd;
896 mask = smp_invltlb_req;
900 cpu = BSFCPUMASK(mask);
901 mask &= ~CPUMASK(cpu);
902 omd = (struct mdglobaldata *)globaldata_find(cpu);
903 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
910 * When called the executing CPU will send an IPI to all other CPUs
911 * requesting that they halt execution.
913 * Usually (but not necessarily) called with 'other_cpus' as its arg.
915 * - Signals all CPUs in map to stop.
916 * - Waits for each to stop.
923 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
924 * from executing at same time.
927 stop_cpus(cpumask_t map)
929 map &= smp_active_mask;
931 /* send the Xcpustop IPI to all CPUs in map */
932 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
934 while ((stopped_cpus & map) != map)
942 * Called by a CPU to restart stopped CPUs.
944 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
946 * - Signals all CPUs in map to restart.
947 * - Waits for each to restart.
955 restart_cpus(cpumask_t map)
957 /* signal other cpus to restart */
958 started_cpus = map & smp_active_mask;
960 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
967 * This is called once the mpboot code has gotten us properly relocated
968 * and the MMU turned on, etc. ap_init() is actually the idle thread,
969 * and when it returns the scheduler will call the real cpu_idle() main
970 * loop for the idlethread. Interrupts are disabled on entry and should
971 * remain disabled at return.
979 * Adjust smp_startup_mask to signal the BSP that we have started
980 * up successfully. Note that we do not yet hold the BGL. The BSP
981 * is waiting for our signal.
983 * We can't set our bit in smp_active_mask yet because we are holding
984 * interrupts physically disabled and remote cpus could deadlock
985 * trying to send us an IPI.
987 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
991 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
992 * non-zero, then get the MP lock.
994 * Note: We are in a critical section.
996 * Note: we are the idle thread, we can only spin.
998 * Note: The load fence is memory volatile and prevents the compiler
999 * from improperly caching mp_finish_lapic, and the cpu from improperly
1002 while (mp_finish_lapic == 0)
1004 while (try_mplock() == 0)
1007 if (cpu_feature & CPUID_TSC) {
1009 * The BSP is constantly updating tsc0_offset, figure out
1010 * the relative difference to synchronize ktrdump.
1012 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1015 /* BSP may have changed PTD while we're waiting for the lock */
1018 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
1022 /* Build our map of 'other' CPUs. */
1023 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1025 /* A quick check from sanity claus */
1026 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
1027 if (mycpu->gd_cpuid != apic_id) {
1028 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
1029 kprintf("SMP: apic_id = %d\n", apic_id);
1030 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1031 panic("cpuid mismatch! boom!!");
1034 /* Initialize AP's local APIC for irq's */
1037 /* LAPIC initialization is done */
1038 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1041 /* Let BSP move onto the next initialization stage */
1045 * Interlock for finalization. Wait until mp_finish is non-zero,
1046 * then get the MP lock.
1048 * Note: We are in a critical section.
1050 * Note: we are the idle thread, we can only spin.
1052 * Note: The load fence is memory volatile and prevents the compiler
1053 * from improperly caching mp_finish, and the cpu from improperly
1056 while (mp_finish == 0)
1058 while (try_mplock() == 0)
1061 /* BSP may have changed PTD while we're waiting for the lock */
1064 /* Set memory range attributes for this CPU to match the BSP */
1065 mem_range_AP_init();
1068 * Once we go active we must process any IPIQ messages that may
1069 * have been queued, because no actual IPI will occur until we
1070 * set our bit in the smp_active_mask. If we don't the IPI
1071 * message interlock could be left set which would also prevent
1074 * The idle loop doesn't expect the BGL to be held and while
1075 * lwkt_switch() normally cleans things up this is a special case
1076 * because we returning almost directly into the idle loop.
1078 * The idle thread is never placed on the runq, make sure
1079 * nothing we've done put it there.
1081 KKASSERT(get_mplock_count(curthread) == 1);
1082 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
1085 * Enable interrupts here. idle_restore will also do it, but
1086 * doing it here lets us clean up any strays that got posted to
1087 * the CPU during the AP boot while we are still in a critical
1090 __asm __volatile("sti; pause; pause"::);
1091 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1093 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1094 lwkt_process_ipiq();
1097 * Releasing the mp lock lets the BSP finish up the SMP init
1100 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1104 * Get SMP fully working before we start initializing devices.
1112 kprintf("Finish MP startup\n");
1114 while (smp_active_mask != smp_startup_mask)
1116 while (try_mplock() == 0)
1119 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
1122 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1125 cpu_send_ipiq(int dcpu)
1127 if (CPUMASK(dcpu) & smp_active_mask)
1128 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1131 #if 0 /* single_apic_ipi_passive() not working yet */
1133 * Returns 0 on failure, 1 on success
1136 cpu_send_ipiq_passive(int dcpu)
1139 if (CPUMASK(dcpu) & smp_active_mask) {
1140 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1141 APIC_DELMODE_FIXED);