sys/net/i4b/layer1/iwic/i4b_iwic_dchan.c

   1 /*
   2  * Copyright (c) 1999, 2000 Dave Boyce. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  *---------------------------------------------------------------------------
  26  *
  27  *      i4b_iwic - isdn4bsd Winbond W6692 driver
  28  *      ----------------------------------------
  29  *
  30  * $FreeBSD: src/sys/i4b/layer1/iwic/i4b_iwic_dchan.c,v 1.4.2.1 2001/08/10 14:08:40 obrien Exp $
  31  * $DragonFly: src/sys/net/i4b/layer1/iwic/i4b_iwic_dchan.c,v 1.2 2003/06/17 04:28:40 dillon Exp $
  32  *
  33  *      last edit-date: [Tue Jan 16 13:20:14 2001]
  34  *
  35  *---------------------------------------------------------------------------*/
  36
  37 #include "iwic.h"
  38 #include "opt_i4b.h"
  39 #include "pci.h"
  40
  41 #if (NIWIC > 0) && (NPCI > 0)
  42
  43 #include <sys/param.h>
  44 #include <sys/systm.h>
  45 #include <sys/mbuf.h>
  46 #include <sys/socket.h>
  47
  48 #include <net/if.h>
  49
  50
  51 #include <machine/i4b_debug.h>
  52 #include <machine/i4b_ioctl.h>
  53 #include <machine/i4b_trace.h>
  54
  55 #include <i4b/layer1/i4b_l1.h>
  56
  57 #include <i4b/include/i4b_global.h>
  58 #include <i4b/include/i4b_l3l4.h>
  59 #include <i4b/include/i4b_mbuf.h>
  60
  61 #include <i4b/layer1/iwic/i4b_iwic.h>
  62 #include <i4b/layer1/iwic/i4b_w6692.h>
  63
  64 #define MAX_DFRAME_LEN  264
  65
  66 static void dchan_receive(struct iwic_softc *sc, int ista);
  67
  68 /*---------------------------------------------------------------------------*
  69  *      initialize D-channel variables and registers
  70  *---------------------------------------------------------------------------*/
  71 void
  72 iwic_dchan_init(struct iwic_softc *sc)
  73 {
  74         sc->sc_dchan.ibuf = NULL;
  75         sc->sc_dchan.rx_count = 0;
  76
  77         sc->sc_dchan.obuf = NULL;
  78         sc->sc_dchan.obuf2 = NULL;
  79         sc->sc_dchan.tx_count = 0;
  80         sc->sc_dchan.tx_ready = 0;
  81
  82         IWIC_WRITE(sc, D_CTL, D_CTL_SRST);
  83
  84         DELAY(5000);
  85
  86         IWIC_WRITE(sc, D_CTL, 0);
  87
  88         IWIC_WRITE(sc, SQX, SQX_SCIE);
  89
  90         IWIC_WRITE(sc, PCTL, 0x00);
  91         IWIC_WRITE(sc, MOCR, 0x00);
  92         IWIC_WRITE(sc, GCR, 0x00);
  93
  94         IWIC_WRITE(sc, D_CMDR, D_CMDR_RRST | D_CMDR_XRST);
  95         IWIC_WRITE(sc, D_MODE, D_MODE_RACT);
  96
  97         IWIC_WRITE(sc, D_SAM, 0xff);
  98         IWIC_WRITE(sc, D_TAM, 0xff);
  99
 100         IWIC_WRITE(sc, D_EXIM, 0x00);
 101 }
 102
 103 /*---------------------------------------------------------------------------*
 104  *      Extended IRQ handler for the D-channel
 105  *---------------------------------------------------------------------------*/
 106 void
 107 iwic_dchan_xirq(struct iwic_softc *sc)
 108 {
 109         int irq_stat;
 110         int stat;
 111
 112         irq_stat = IWIC_READ(sc, D_EXIR);
 113
 114         if (irq_stat & D_EXIR_RDOV)
 115         {
 116                 NDBGL1(L1_I_ERR, "RDOV in state %s", iwic_printstate(sc));
 117                 IWIC_WRITE(sc, D_CMDR, D_CMDR_RRST);
 118         }
 119         if (irq_stat & D_EXIR_XDUN)
 120         {
 121                 NDBGL1(L1_I_ERR, "XDUN in state %s", iwic_printstate(sc));
 122                 sc->sc_dchan.tx_ready = 0;
 123         }
 124         if (irq_stat & D_EXIR_XCOL)
 125         {
 126                 NDBGL1(L1_I_ERR, "XCOL in state %s", iwic_printstate(sc));
 127                 IWIC_WRITE(sc, D_CMDR, D_CMDR_XRST);
 128                 sc->sc_dchan.tx_ready = 0;
 129         }
 130         if (irq_stat & D_EXIR_TIN2)
 131         {
 132                 NDBGL1(L1_I_ERR, "TIN2 in state %s", iwic_printstate(sc));
 133         }
 134         if (irq_stat & D_EXIR_MOC)
 135         {
 136                 stat = IWIC_READ(sc, MOR);
 137                 NDBGL1(L1_I_ERR, "MOC in state %s, byte = 0x%x", iwic_printstate(sc), stat);
 138         }
 139
 140         if (irq_stat & D_EXIR_ISC)
 141         {
 142                 stat = (IWIC_READ(sc, CIR)) & 0x0f;
 143
 144                 switch (stat)
 145                 {
 146                         case CIR_CE:
 147                                 NDBGL1(L1_I_CICO, "rx CE in state %s", iwic_printstate(sc));
 148                                 iwic_next_state(sc, EV_CE);
 149                                 break;
 150                         case CIR_DRD:
 151                                 NDBGL1(L1_I_CICO, "rx DRD in state %s", iwic_printstate(sc));
 152                                 iwic_next_state(sc, EV_INFO0);
 153                                 i4b_l1_mph_status_ind(L0IWICUNIT(sc->sc_unit), STI_L1STAT, LAYER_IDLE, NULL);
 154                                 break;
 155                         case CIR_LD:
 156                                 NDBGL1(L1_I_CICO, "rx LD in state %s", iwic_printstate(sc));
 157                                 iwic_next_state(sc, EV_RSY);
 158                                 break;
 159                         case CIR_ARD:
 160                                 NDBGL1(L1_I_CICO, "rx ARD in state %s", iwic_printstate(sc));
 161                                 iwic_next_state(sc, EV_INFO2);
 162                                 break;
 163                         case CIR_TI:
 164                                 NDBGL1(L1_I_CICO, "rx TI in state %s", iwic_printstate(sc));
 165                                 iwic_next_state(sc, EV_INFO0);
 166                                 break;
 167                         case CIR_ATI:
 168                                 NDBGL1(L1_I_CICO, "rx ATI in state %s", iwic_printstate(sc));
 169                                 iwic_next_state(sc, EV_INFO0);
 170                                 break;
 171                         case CIR_AI8:
 172                                 NDBGL1(L1_I_CICO, "rx AI8 in state %s", iwic_printstate(sc));
 173                                 i4b_l1_mph_status_ind(L0IWICUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
 174                                 iwic_next_state(sc, EV_INFO48);
 175                                 break;
 176                         case CIR_AI10:
 177                                 NDBGL1(L1_I_CICO, "rx AI10 in state %s", iwic_printstate(sc));
 178                                 i4b_l1_mph_status_ind(L0IWICUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
 179                                 iwic_next_state(sc, EV_INFO410);
 180                                 break;
 181                         case CIR_CD:
 182                                 NDBGL1(L1_I_CICO, "rx DIS in state %s", iwic_printstate(sc));
 183                                 iwic_next_state(sc, EV_DIS);
 184                                 break;
 185                         default:
 186                                 NDBGL1(L1_I_ERR, "ERROR, unknown indication 0x%x in state %s", stat, iwic_printstate(sc));
 187                                 iwic_next_state(sc, EV_INFO0);
 188                                 break;
 189                 }
 190         }
 191
 192         if (irq_stat & D_EXIR_TEXP)
 193         {
 194                 NDBGL1(L1_I_ERR, "TEXP in state %s", iwic_printstate(sc));
 195         }
 196
 197         if (irq_stat & D_EXIR_WEXP)
 198         {
 199                 NDBGL1(L1_I_ERR, "WEXP in state %s", iwic_printstate(sc));
 200         }
 201 }
 202
 203 /*---------------------------------------------------------------------------*
 204  *      All receiving and transmitting takes place here.
 205  *---------------------------------------------------------------------------*/
 206 void
 207 iwic_dchan_xfer_irq(struct iwic_softc *sc, int ista)
 208 {
 209         NDBGL1(L1_I_MSG, "ISTA = 0x%x", ista);
 210
 211         if (ista & (ISTA_D_RMR | ISTA_D_RME))
 212         {
 213                 /* Receive message ready */
 214                 dchan_receive(sc, ista);
 215         }
 216         if (ista & ISTA_D_XFR)
 217         {
 218                 /* Transmitter ready */
 219                 sc->sc_dchan.tx_ready = 1;
 220
 221                 iwic_dchan_transmit(sc);
 222         }
 223 }
 224
 225 /*---------------------------------------------------------------------------*
 226  *      disable D-channel
 227  *---------------------------------------------------------------------------*/
 228 void
 229 iwic_dchan_disable(struct iwic_softc *sc)
 230 {
 231         int s;
 232
 233         s = SPLI4B();
 234
 235         if (sc->sc_dchan.obuf)
 236         {
 237                 if (sc->sc_dchan.free_obuf)
 238                         i4b_Dfreembuf(sc->sc_dchan.obuf);
 239                 sc->sc_dchan.obuf = NULL;
 240         }
 241
 242         if (sc->sc_dchan.obuf2)
 243         {
 244                 if (sc->sc_dchan.free_obuf2)
 245                         i4b_Dfreembuf(sc->sc_dchan.obuf2);
 246                 sc->sc_dchan.obuf2 = NULL;
 247         }
 248
 249         splx(s);
 250
 251         IWIC_WRITE(sc, CIX, CIX_DRC);
 252 }
 253
 254 /*---------------------------------------------------------------------------*
 255  *      queue D-channel message for transmission
 256  *---------------------------------------------------------------------------*/
 257 int
 258 iwic_dchan_data_req(struct iwic_softc *sc, struct mbuf *m, int freeflag)
 259 {
 260         int s;
 261
 262         if (!m)
 263                 return 0;
 264
 265         s = SPLI4B();
 266
 267         /* Queue message */
 268
 269         if (sc->sc_dchan.obuf)
 270         {
 271                 if (sc->sc_dchan.obuf2)
 272                 {
 273                         NDBGL1(L1_I_ERR, "no buffer space!");
 274                 }
 275                 else
 276                 {
 277                         sc->sc_dchan.obuf2 = m;
 278                         sc->sc_dchan.free_obuf2 = freeflag;
 279                 }
 280         }
 281         else
 282         {
 283                 sc->sc_dchan.obuf = m;
 284                 sc->sc_dchan.obuf_ptr = m->m_data;
 285                 sc->sc_dchan.obuf_len = m->m_len;
 286                 sc->sc_dchan.free_obuf = freeflag;
 287         }
 288
 289         iwic_dchan_transmit(sc);
 290
 291         splx(s);
 292
 293         return (0);
 294 }
 295
 296 /*---------------------------------------------------------------------------*
 297  *      allocate an mbuf
 298  *---------------------------------------------------------------------------*/
 299 static void
 300 dchan_get_mbuf(struct iwic_softc *sc, int len)
 301 {
 302         sc->sc_dchan.ibuf = i4b_Dgetmbuf(len);
 303
 304         if (!sc->sc_dchan.ibuf)
 305                 panic("dchan_get_mbuf: unable to allocate %d bytes for mbuf!\n", len);
 306
 307         sc->sc_dchan.ibuf_ptr = sc->sc_dchan.ibuf->m_data;
 308         sc->sc_dchan.ibuf_max_len = sc->sc_dchan.ibuf->m_len;
 309         sc->sc_dchan.ibuf_len = 0;
 310 }
 311
 312 /*---------------------------------------------------------------------------*
 313  *      D-channel receive data interrupt
 314  *---------------------------------------------------------------------------*/
 315 static void
 316 dchan_receive(struct iwic_softc *sc, int ista)
 317 {
 318         int command = D_CMDR_RACK;
 319
 320         if (ista & ISTA_D_RMR)
 321         {
 322                 /* Got 64 bytes in FIFO */
 323
 324                 if (!sc->sc_dchan.ibuf)
 325                 {
 326                         dchan_get_mbuf(sc, MAX_DFRAME_LEN);
 327
 328                 }
 329                 else if ((sc->sc_dchan.ibuf_len + MAX_DFRAME_LEN) >
 330                          sc->sc_dchan.ibuf_max_len)
 331                 {
 332                         panic("dchan_receive: not enough space in buffer!\n");
 333                 }
 334
 335                 IWIC_RDDFIFO(sc, sc->sc_dchan.ibuf_ptr, 64);
 336
 337                 sc->sc_dchan.ibuf_ptr += 64;
 338                 sc->sc_dchan.ibuf_len += 64;
 339                 sc->sc_dchan.rx_count += 64;
 340         }
 341         if (ista & ISTA_D_RME)
 342         {
 343                 /* Got end of frame */
 344                 int status;
 345
 346                 status = IWIC_READ(sc, D_RSTA);
 347
 348                 if (status & (D_RSTA_RDOV | D_RSTA_CRCE | D_RSTA_RMB))
 349                 {
 350                         if (status & D_RSTA_RDOV)
 351                                 NDBGL1(L1_I_ERR, "iwic%d: D-channel Receive Data Overflow", sc->sc_unit);
 352                         if (status & D_RSTA_CRCE)
 353                                 NDBGL1(L1_I_ERR, "iwic%d: D-channel CRC Error", sc->sc_unit);
 354                         if (status & D_RSTA_RMB)
 355                                 NDBGL1(L1_I_ERR, "iwic%d: D-channel Receive Message Aborted", sc->sc_unit);
 356                         command |= D_CMDR_RRST;
 357                 }
 358                 else
 359                 {
 360                         int hi, lo;
 361                         int total_frame_len;
 362
 363                         lo = IWIC_READ(sc, D_RBCL);
 364                         hi = IWIC_READ(sc, D_RBCH);
 365                         total_frame_len = D_RBC(hi, lo);
 366                         lo = lo & 0x3f;
 367
 368                         if (lo == 0)
 369                                 lo = IWIC_DCHAN_FIFO_LEN;
 370
 371                         if (!sc->sc_dchan.ibuf)
 372                         {
 373                                 dchan_get_mbuf(sc, lo);
 374                         }
 375                         else if ((sc->sc_dchan.ibuf_len + lo) >
 376                                  sc->sc_dchan.ibuf_max_len)
 377                         {
 378                                 panic("dchan_receive: buffer not long enough");
 379                         }
 380
 381                         IWIC_RDDFIFO(sc, sc->sc_dchan.ibuf_ptr, lo);
 382                         sc->sc_dchan.ibuf_len += lo;
 383                         sc->sc_dchan.rx_count += lo;
 384
 385                         sc->sc_dchan.ibuf->m_len = sc->sc_dchan.ibuf_len;
 386
 387                         if(sc->sc_trace & TRACE_D_RX)
 388                         {
 389                                 i4b_trace_hdr_t hdr;
 390                                 hdr.unit = L0IWICUNIT(sc->sc_unit);
 391                                 hdr.type = TRC_CH_D;
 392                                 hdr.dir = FROM_NT;
 393                                 hdr.count = ++sc->sc_dchan.trace_count;
 394                                 MICROTIME(hdr.time);
 395                                 i4b_l1_trace_ind(&hdr, sc->sc_dchan.ibuf->m_len, sc->sc_dchan.ibuf->m_data);
 396                         }
 397                         i4b_l1_ph_data_ind(L0IWICUNIT(sc->sc_unit), sc->sc_dchan.ibuf);
 398
 399                         sc->sc_dchan.ibuf = NULL;
 400                 }
 401         }
 402         IWIC_WRITE(sc, D_CMDR, command);
 403 }
 404
 405 /*---------------------------------------------------------------------------*
 406  *      transmit D-channel frame
 407  *---------------------------------------------------------------------------*/
 408 void
 409 iwic_dchan_transmit(struct iwic_softc *sc)
 410 {
 411         int cmd;
 412         u_char *ptr;
 413         int len;
 414
 415         if (!sc->sc_dchan.tx_ready)
 416                 return;
 417
 418         if (!sc->sc_dchan.obuf)
 419                 return;
 420
 421         if (sc->sc_I430state != ST_F7)
 422                 return;
 423
 424         ptr = sc->sc_dchan.obuf_ptr;
 425         len = min(sc->sc_dchan.obuf_len, IWIC_DCHAN_FIFO_LEN);
 426
 427         if(sc->sc_trace & TRACE_D_TX)
 428         {
 429                 i4b_trace_hdr_t hdr;
 430                 hdr.unit = L0IWICUNIT(sc->sc_unit);
 431                 hdr.type = TRC_CH_D;
 432                 hdr.dir = FROM_TE;
 433                 hdr.count = ++sc->sc_dchan.trace_count;
 434                 MICROTIME(hdr.time);
 435                 i4b_l1_trace_ind(&hdr, len, ptr);
 436         }
 437
 438         IWIC_WRDFIFO(sc, ptr, len);
 439
 440         sc->sc_dchan.tx_count += len;
 441
 442         if (len < sc->sc_dchan.obuf_len)
 443         {
 444                 sc->sc_dchan.obuf_ptr += len;
 445                 sc->sc_dchan.obuf_len -= len;
 446
 447                 cmd = D_CMDR_XMS;
 448
 449         }
 450         else
 451         {
 452                 if (sc->sc_dchan.free_obuf)
 453                         i4b_Dfreembuf(sc->sc_dchan.obuf);
 454
 455                 sc->sc_dchan.obuf = NULL;
 456                 sc->sc_dchan.obuf_ptr = NULL;
 457                 sc->sc_dchan.obuf_len = 0;
 458
 459                 if (sc->sc_dchan.obuf2)
 460                 {
 461                         sc->sc_dchan.obuf = sc->sc_dchan.obuf2;
 462                         sc->sc_dchan.obuf_ptr = sc->sc_dchan.obuf->m_data;
 463                         sc->sc_dchan.obuf_len = sc->sc_dchan.obuf->m_len;
 464                         sc->sc_dchan.free_obuf = sc->sc_dchan.free_obuf2;
 465
 466                         sc->sc_dchan.obuf2 = NULL;
 467                 }
 468                 cmd = D_CMDR_XMS | D_CMDR_XME;
 469         }
 470         sc->sc_dchan.tx_ready = 0;
 471         IWIC_WRITE(sc, D_CMDR, cmd);
 472 }
 473
 474 #endif  /* (NIWIC > 0) && (NPCI > 0) */