2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <machine/globaldata.h>
34 #include <machine/smp.h>
35 #include <machine/cputypes.h>
36 #include <machine/md_var.h>
37 #include <machine/pmap.h>
38 #include <machine_base/apic/lapic.h>
39 #include <machine_base/apic/ioapic_abi.h>
40 #include <machine/segments.h>
41 #include <sys/thread2.h>
43 #include <machine/intr_machdep.h>
45 #define IOAPIC_COUNT_MAX 16
46 #define IOAPIC_ID_MASK (IOAPIC_COUNT_MAX - 1)
49 extern pt_entry_t *SMPpt;
58 TAILQ_ENTRY(ioapic_info) io_link;
60 TAILQ_HEAD(ioapic_info_list, ioapic_info);
62 struct ioapic_intsrc {
64 enum intr_trigger int_trig;
65 enum intr_polarity int_pola;
69 struct ioapic_info_list ioc_list;
70 struct ioapic_intsrc ioc_intsrc[16]; /* XXX magic number */
73 static void ioapic_setup(const struct ioapic_info *);
74 static int ioapic_alloc_apic_id(int);
75 static void ioapic_set_apic_id(const struct ioapic_info *);
76 static void ioapic_gsi_setup(int);
77 static const struct ioapic_info *
78 ioapic_gsi_search(int);
79 static void ioapic_pin_prog(void *, int, int,
80 enum intr_trigger, enum intr_polarity, uint32_t);
82 static struct ioapic_conf ioapic_conf;
84 static TAILQ_HEAD(, ioapic_enumerator) ioapic_enumerators =
85 TAILQ_HEAD_INITIALIZER(ioapic_enumerators);
90 struct ioapic_info *info;
91 int start_apic_id = 0;
92 struct ioapic_enumerator *e;
96 TAILQ_INIT(&ioapic_conf.ioc_list);
97 /* XXX magic number */
98 for (i = 0; i < 16; ++i)
99 ioapic_conf.ioc_intsrc[i].int_gsi = -1;
101 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
102 error = e->ioapic_probe(e);
108 panic("can't config I/O APIC\n");
110 kprintf("no I/O APIC\n");
121 * Switch to I/O APIC MachIntrABI and reconfigure
122 * the default IDT entries.
124 MachIntrABI = MachIntrABI_IOAPIC;
125 MachIntrABI.setdefault();
127 e->ioapic_enumerate(e);
133 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
136 if (i > IOAPIC_COUNT_MAX) /* XXX magic number */
137 panic("ioapic_config: more than 16 I/O APIC\n");
142 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
145 apic_id = ioapic_alloc_apic_id(start_apic_id);
146 if (apic_id == NAPICID) {
147 kprintf("IOAPIC: can't alloc APIC ID for "
148 "%dth I/O APIC\n", info->io_idx);
151 info->io_apic_id = apic_id;
153 start_apic_id = apic_id + 1;
157 * xAPIC allows I/O APIC's APIC ID to be same
158 * as the LAPIC's APIC ID
160 kprintf("IOAPIC: use xAPIC model to alloc APIC ID "
163 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
164 info->io_apic_id = info->io_idx;
168 * Warning about any GSI holes
170 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
171 const struct ioapic_info *prev_info;
173 prev_info = TAILQ_PREV(info, ioapic_info_list, io_link);
174 if (prev_info != NULL) {
175 if (info->io_gsi_base !=
176 prev_info->io_gsi_base + prev_info->io_npin) {
177 kprintf("IOAPIC: warning gsi hole "
179 prev_info->io_gsi_base +
181 info->io_gsi_base - 1);
187 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
188 kprintf("IOAPIC: idx %d, apic id %d, "
189 "gsi base %d, npin %d\n",
200 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
202 ioapic_abi_fixup_irqmap();
206 MachIntrABI.cleanup();
212 ioapic_enumerator_register(struct ioapic_enumerator *ne)
214 struct ioapic_enumerator *e;
216 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
217 if (e->ioapic_prio < ne->ioapic_prio) {
218 TAILQ_INSERT_BEFORE(e, ne, ioapic_link);
222 TAILQ_INSERT_TAIL(&ioapic_enumerators, ne, ioapic_link);
226 ioapic_add(void *addr, int gsi_base, int npin)
228 struct ioapic_info *info, *ninfo;
231 gsi_end = gsi_base + npin - 1;
232 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
233 if ((gsi_base >= info->io_gsi_base &&
234 gsi_base < info->io_gsi_base + info->io_npin) ||
235 (gsi_end >= info->io_gsi_base &&
236 gsi_end < info->io_gsi_base + info->io_npin)) {
237 panic("ioapic_add: overlapped gsi, base %d npin %d, "
238 "hit base %d, npin %d\n", gsi_base, npin,
239 info->io_gsi_base, info->io_npin);
241 if (info->io_addr == addr)
242 panic("ioapic_add: duplicated addr %p\n", addr);
245 ninfo = kmalloc(sizeof(*ninfo), M_DEVBUF, M_WAITOK | M_ZERO);
246 ninfo->io_addr = addr;
247 ninfo->io_npin = npin;
248 ninfo->io_gsi_base = gsi_base;
249 ninfo->io_apic_id = -1;
252 * Create IOAPIC list in ascending order of GSI base
254 TAILQ_FOREACH_REVERSE(info, &ioapic_conf.ioc_list,
255 ioapic_info_list, io_link) {
256 if (ninfo->io_gsi_base > info->io_gsi_base) {
257 TAILQ_INSERT_AFTER(&ioapic_conf.ioc_list,
258 info, ninfo, io_link);
263 TAILQ_INSERT_HEAD(&ioapic_conf.ioc_list, ninfo, io_link);
267 ioapic_intsrc(int irq, int gsi, enum intr_trigger trig, enum intr_polarity pola)
269 struct ioapic_intsrc *int_src;
272 int_src = &ioapic_conf.ioc_intsrc[irq];
275 /* Don't allow mixed mode */
276 kprintf("IOAPIC: warning intsrc irq %d -> gsi 0\n", irq);
280 if (int_src->int_gsi != -1) {
281 if (int_src->int_gsi != gsi) {
282 kprintf("IOAPIC: warning intsrc irq %d, gsi "
283 "%d -> %d\n", irq, int_src->int_gsi, gsi);
285 if (int_src->int_trig != trig) {
286 kprintf("IOAPIC: warning intsrc irq %d, trig "
288 intr_str_trigger(int_src->int_trig),
289 intr_str_trigger(trig));
291 if (int_src->int_pola != pola) {
292 kprintf("IOAPIC: warning intsrc irq %d, pola "
294 intr_str_polarity(int_src->int_pola),
295 intr_str_polarity(pola));
298 int_src->int_gsi = gsi;
299 int_src->int_trig = trig;
300 int_src->int_pola = pola;
304 ioapic_set_apic_id(const struct ioapic_info *info)
309 id = ioapic_read(info->io_addr, IOAPIC_ID);
312 id |= (info->io_apic_id << 24);
314 ioapic_write(info->io_addr, IOAPIC_ID, id);
319 id = ioapic_read(info->io_addr, IOAPIC_ID);
320 apic_id = (id & APIC_ID_MASK) >> 24;
323 * I/O APIC ID is a 4bits field
325 if ((apic_id & IOAPIC_ID_MASK) !=
326 (info->io_apic_id & IOAPIC_ID_MASK)) {
327 panic("ioapic_set_apic_id: can't set apic id to %d, "
328 "currently set to %d\n", info->io_apic_id, apic_id);
333 ioapic_gsi_setup(int gsi)
335 enum intr_trigger trig;
336 enum intr_polarity pola;
342 ioapic_extpin_setup(ioapic_gsi_ioaddr(gsi),
343 ioapic_gsi_pin(gsi), 0);
348 trig = 0; /* silence older gcc's */
349 pola = 0; /* silence older gcc's */
351 for (irq = 0; irq < 16; ++irq) {
352 const struct ioapic_intsrc *int_src =
353 &ioapic_conf.ioc_intsrc[irq];
355 if (gsi == int_src->int_gsi) {
356 trig = int_src->int_trig;
357 pola = int_src->int_pola;
364 trig = INTR_TRIGGER_EDGE;
365 pola = INTR_POLARITY_HIGH;
367 trig = INTR_TRIGGER_LEVEL;
368 pola = INTR_POLARITY_LOW;
373 ioapic_abi_set_irqmap(irq, gsi, trig, pola);
377 ioapic_gsi_ioaddr(int gsi)
379 const struct ioapic_info *info;
381 info = ioapic_gsi_search(gsi);
382 return info->io_addr;
386 ioapic_gsi_pin(int gsi)
388 const struct ioapic_info *info;
390 info = ioapic_gsi_search(gsi);
391 return gsi - info->io_gsi_base;
394 static const struct ioapic_info *
395 ioapic_gsi_search(int gsi)
397 const struct ioapic_info *info;
399 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
400 if (gsi >= info->io_gsi_base &&
401 gsi < info->io_gsi_base + info->io_npin)
404 panic("ioapic_gsi_search: no I/O APIC\n");
408 ioapic_gsi(int idx, int pin)
410 const struct ioapic_info *info;
412 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
413 if (info->io_idx == idx)
418 if (pin >= info->io_npin)
420 return info->io_gsi_base + pin;
424 ioapic_extpin_setup(void *addr, int pin, int vec)
426 ioapic_pin_prog(addr, pin, vec,
427 INTR_TRIGGER_CONFORM, INTR_POLARITY_CONFORM, IOART_DELEXINT);
431 ioapic_extpin_gsi(void)
437 ioapic_pin_setup(void *addr, int pin, int vec,
438 enum intr_trigger trig, enum intr_polarity pola)
441 * Always clear an I/O APIC pin before [re]programming it. This is
442 * particularly important if the pin is set up for a level interrupt
443 * as the IOART_REM_IRR bit might be set. When we reprogram the
444 * vector any EOI from pending ints on this pin could be lost and
445 * IRR might never get reset.
447 * To fix this problem, clear the vector and make sure it is
448 * programmed as an edge interrupt. This should theoretically
449 * clear IRR so we can later, safely program it as a level
452 ioapic_pin_prog(addr, pin, vec, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH,
454 ioapic_pin_prog(addr, pin, vec, trig, pola, IOART_DELFIXED);
458 ioapic_pin_prog(void *addr, int pin, int vec,
459 enum intr_trigger trig, enum intr_polarity pola, uint32_t del_mode)
461 uint32_t flags, target;
464 KKASSERT(del_mode == IOART_DELEXINT || del_mode == IOART_DELFIXED);
466 select = IOAPIC_REDTBL0 + (2 * pin);
468 flags = ioapic_read(addr, select) & IOART_RESV;
469 flags |= IOART_INTMSET | IOART_DESTPHY;
474 * We only support limited I/O APIC mixed mode,
475 * so even for ExtINT, we still use "fixed"
478 flags |= IOART_DELFIXED;
481 if (del_mode == IOART_DELEXINT) {
482 KKASSERT(trig == INTR_TRIGGER_CONFORM &&
483 pola == INTR_POLARITY_CONFORM);
484 flags |= IOART_TRGREDG | IOART_INTAHI;
487 case INTR_TRIGGER_EDGE:
488 flags |= IOART_TRGREDG;
491 case INTR_TRIGGER_LEVEL:
492 flags |= IOART_TRGRLVL;
495 case INTR_TRIGGER_CONFORM:
496 panic("ioapic_pin_prog: trig conform is not "
500 case INTR_POLARITY_HIGH:
501 flags |= IOART_INTAHI;
504 case INTR_POLARITY_LOW:
505 flags |= IOART_INTALO;
508 case INTR_POLARITY_CONFORM:
509 panic("ioapic_pin_prog: pola conform is not "
514 target = ioapic_read(addr, select + 1) & IOART_HI_DEST_RESV;
515 target |= (CPU_TO_ID(0) << IOART_HI_DEST_SHIFT) &
518 ioapic_write(addr, select, flags | vec);
519 ioapic_write(addr, select + 1, target);
523 ioapic_setup(const struct ioapic_info *info)
527 ioapic_set_apic_id(info);
529 for (i = 0; i < info->io_npin; ++i)
530 ioapic_gsi_setup(info->io_gsi_base + i);
534 ioapic_alloc_apic_id(int start)
537 const struct ioapic_info *info;
538 int apic_id, apic_id16;
540 apic_id = lapic_unused_apic_id(start);
541 if (apic_id == NAPICID) {
542 kprintf("IOAPIC: can't find unused APIC ID\n");
545 apic_id16 = apic_id & IOAPIC_ID_MASK;
548 * Check against other I/O APIC's APIC ID's lower 4bits.
550 * The new APIC ID will have to be different from others
551 * in the lower 4bits, no matter whether xAPIC is used
554 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
555 if (info->io_apic_id == -1) {
559 if ((info->io_apic_id & IOAPIC_ID_MASK) == apic_id16)
565 kprintf("IOAPIC: APIC ID %d has same lower 4bits as "
566 "%dth I/O APIC, keep searching...\n",
567 apic_id, info->io_idx);
571 panic("ioapic_unused_apic_id: never reached\n");