sys/dev/misc/pcic/i82365.c

   1 /*      $NetBSD: i82365.c,v 1.25 1999/10/15 06:07:27 haya Exp $ */
   2 /* $FreeBSD: src/sys/dev/pcic/i82365.c,v 1.16.2.1 2000/05/23 03:57:02 imp Exp $ */
   3
   4 /*
   5  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Marc Horowitz.
  18  * 4. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/malloc.h>
  36 #include <sys/module.h>
  37 #include <sys/kernel.h>
  38 #include <sys/queue.h>
  39 #include <sys/types.h>
  40
  41 #include <sys/bus.h>
  42 #include <machine/bus.h>
  43 #include <sys/rman.h>
  44 #include <machine/resource.h>
  45
  46 #include <machine/clock.h>
  47
  48 #include <sys/proc.h>
  49 #include <sys/wait.h>
  50 #include <sys/kthread.h>
  51 #include <vm/vm.h>
  52
  53 /* We shouldn't need to include the following, but sadly we do for now */
  54 /* XXX */
  55 #include <dev/pccard/pccardreg.h>
  56 #include <dev/pccard/pccardvar.h>
  57
  58 #include <dev/pcic/i82365reg.h>
  59 #include <dev/pcic/i82365var.h>
  60
  61 #include "card_if.h"
  62
  63 #define PCICDEBUG
  64
  65 #ifdef PCICDEBUG
  66 int     pcic_debug = 1;
  67 #define DPRINTF(arg) if (pcic_debug) printf arg;
  68 #define DEVPRINTF(arg) if (pcic_debug) device_printf arg;
  69 #else
  70 #define DPRINTF(arg)
  71 #define DEVPRINTF(arg)
  72 #endif
  73
  74 #define DETACH_FORCE    0x1
  75
  76 #define PCIC_VENDOR_UNKNOWN             0
  77 #define PCIC_VENDOR_I82365SLR0          1
  78 #define PCIC_VENDOR_I82365SLR1          2
  79 #define PCIC_VENDOR_CIRRUS_PD6710       3
  80 #define PCIC_VENDOR_CIRRUS_PD672X       4
  81
  82 /*
  83  * Individual drivers will allocate their own memory and io regions. Memory
  84  * regions must be a multiple of 4k, aligned on a 4k boundary.
  85  */
  86
  87 #define PCIC_MEM_ALIGN  PCIC_MEM_PAGESIZE
  88
  89 static void     pcic_init_socket(struct pcic_handle *);
  90
  91 static void     pcic_intr_socket(struct pcic_handle *);
  92
  93 static void     pcic_deactivate(device_t dev);
  94 static int      pcic_activate(device_t dev);
  95 static void     pcic_intr(void *arg);
  96
  97 static void     pcic_attach_card(struct pcic_handle *);
  98 static void     pcic_detach_card(struct pcic_handle *, int);
  99
 100 static void     pcic_chip_do_mem_map(struct pcic_handle *, int);
 101 static void     pcic_chip_do_io_map(struct pcic_handle *, int);
 102
 103 void    pcic_create_event_thread(void *);
 104 void    pcic_event_thread(void *);
 105
 106 void    pcic_queue_event(struct pcic_handle *, int);
 107
 108 static void     pcic_wait_ready(struct pcic_handle *);
 109
 110 static u_int8_t st_pcic_read(struct pcic_handle *, int);
 111 static void st_pcic_write(struct pcic_handle *, int, u_int8_t);
 112
 113 /* XXX Should really be dynamic XXX */
 114 static struct pcic_handle *handles[20];
 115 static struct pcic_handle **lasthandle = handles;
 116
 117 static struct pcic_handle *
 118 pcic_get_handle(device_t dev, device_t child)
 119 {
 120         if (dev == child)
 121                 return NULL;
 122         while (child && device_get_parent(child) != dev)
 123                 child = device_get_parent(child);
 124         if (child == NULL)
 125                 return NULL;
 126         return ((struct pcic_handle *) device_get_ivars(child));
 127 }
 128
 129 int
 130 pcic_ident_ok(int ident)
 131 {
 132         /* this is very empirical and heuristic */
 133
 134         if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO))
 135                 return (0);
 136
 137         if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) {
 138 #ifdef DIAGNOSTIC
 139                 printf("pcic: does not support memory and I/O cards, "
 140                     "ignored (ident=%0x)\n", ident);
 141 #endif
 142                 return (0);
 143         }
 144         return (1);
 145 }
 146
 147 int
 148 pcic_vendor(struct pcic_handle *h)
 149 {
 150         int reg;
 151
 152         /*
 153          * the chip_id of the cirrus toggles between 11 and 00 after a write.
 154          * weird.
 155          */
 156
 157         pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0);
 158         reg = pcic_read(h, -1);
 159
 160         if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) ==
 161             PCIC_CIRRUS_CHIP_INFO_CHIP_ID) {
 162                 reg = pcic_read(h, -1);
 163                 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) {
 164                         if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS)
 165                                 return (PCIC_VENDOR_CIRRUS_PD672X);
 166                         else
 167                                 return (PCIC_VENDOR_CIRRUS_PD6710);
 168                 }
 169         }
 170
 171         reg = pcic_read(h, PCIC_IDENT);
 172
 173         if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0)
 174                 return (PCIC_VENDOR_I82365SLR0);
 175         else
 176                 return (PCIC_VENDOR_I82365SLR1);
 177
 178         return (PCIC_VENDOR_UNKNOWN);
 179 }
 180
 181 char *
 182 pcic_vendor_to_string(int vendor)
 183 {
 184         switch (vendor) {
 185         case PCIC_VENDOR_I82365SLR0:
 186                 return ("Intel 82365SL Revision 0");
 187         case PCIC_VENDOR_I82365SLR1:
 188                 return ("Intel 82365SL Revision 1");
 189         case PCIC_VENDOR_CIRRUS_PD6710:
 190                 return ("Cirrus PD6710");
 191         case PCIC_VENDOR_CIRRUS_PD672X:
 192                 return ("Cirrus PD672X");
 193         }
 194
 195         return ("Unknown controller");
 196 }
 197
 198 static int
 199 pcic_activate(device_t dev)
 200 {
 201         struct pcic_softc *sc = (struct pcic_softc *)
 202             device_get_softc(dev);
 203         int err;
 204
 205         sc->port_rid = 0;
 206         sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid,
 207             0, ~0, PCIC_IOSIZE, RF_ACTIVE);
 208         if (!sc->port_res) {
 209 #ifdef PCIC_DEBUG
 210                 device_printf(dev, "Cannot allocate ioport\n");
 211 #endif
 212                 return ENOMEM;
 213         }
 214
 215         sc->irq_rid = 0;
 216         sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid,
 217             0, ~0, 1, RF_ACTIVE);
 218         if (!sc->irq_res) {
 219 #ifdef PCIC_DEBUG
 220                 device_printf(dev, "Cannot allocate irq\n");
 221 #endif
 222                 pcic_deactivate(dev);
 223                 return ENOMEM;
 224         }
 225         sc->irq = rman_get_start(sc->irq_res);
 226         if ((err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET, pcic_intr,
 227             sc, &sc->intrhand)) != 0) {
 228                 pcic_deactivate(dev);
 229                 return err;
 230         }
 231
 232         /* XXX This might not be needed in future, get it directly from
 233          * XXX parent */
 234         sc->mem_rid = 0;
 235         sc->mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->mem_rid,
 236             0, ~0, 1 << 13, RF_ACTIVE);
 237         if (!sc->mem_res) {
 238 #ifdef PCIC_DEBUG
 239                 device_printf(dev, "Cannot allocate mem\n");
 240 #endif
 241                 pcic_deactivate(dev);
 242                 return ENOMEM;
 243         }
 244
 245         sc->iot = rman_get_bustag(sc->port_res);
 246         sc->ioh = rman_get_bushandle(sc->port_res);;
 247         sc->memt = rman_get_bustag(sc->mem_res);
 248         sc->memh = rman_get_bushandle(sc->mem_res);;
 249
 250         return (0);
 251 }
 252
 253 static void
 254 pcic_deactivate(device_t dev)
 255 {
 256         struct pcic_softc *sc = device_get_softc(dev);
 257
 258         if (sc->intrhand)
 259                 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
 260         sc->intrhand = 0;
 261         if (sc->port_res)
 262                 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
 263                     sc->port_res);
 264         sc->port_res = 0;
 265         if (sc->irq_res)
 266                 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
 267                     sc->irq_res);
 268         sc->irq_res = 0;
 269         if (sc->mem_res)
 270                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 271                     sc->mem_res);
 272         sc->mem_res = 0;
 273         return;
 274 }
 275
 276 int
 277 pcic_attach(device_t dev)
 278 {
 279         struct pcic_softc *sc = (struct pcic_softc *)
 280             device_get_softc(dev);
 281         struct pcic_handle *h;
 282         int vendor, count, i, reg, error;
 283
 284         sc->dev = dev;
 285
 286         /* Activate our resources */
 287         if ((error = pcic_activate(dev)) != 0)
 288                 return error;
 289
 290         /* now check for each controller/socket */
 291
 292         /*
 293          * this could be done with a loop, but it would violate the
 294          * abstraction...  so? --imp
 295          */
 296
 297         count = 0;
 298
 299         DPRINTF(("pcic ident regs:"));
 300
 301         sc->handle[0].sc = sc;
 302         sc->handle[0].sock = C0SA;
 303         /* initialise pcic_read and pcic_write functions */
 304         sc->handle[0].ph_read = st_pcic_read;
 305         sc->handle[0].ph_write = st_pcic_write;
 306         sc->handle[0].ph_bus_t = sc->iot;
 307         sc->handle[0].ph_bus_h = sc->ioh;
 308         if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) {
 309                 sc->handle[0].flags = PCIC_FLAG_SOCKETP;
 310                 count++;
 311         } else {
 312                 sc->handle[0].flags = 0;
 313         }
 314         sc->handle[0].laststate = PCIC_LASTSTATE_EMPTY;
 315
 316         DPRINTF((" 0x%02x", reg));
 317
 318         sc->handle[1].sc = sc;
 319         sc->handle[1].sock = C0SB;
 320         /* initialise pcic_read and pcic_write functions */
 321         sc->handle[1].ph_read = st_pcic_read;
 322         sc->handle[1].ph_write = st_pcic_write;
 323         sc->handle[1].ph_bus_t = sc->iot;
 324         sc->handle[1].ph_bus_h = sc->ioh;
 325         if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) {
 326                 sc->handle[1].flags = PCIC_FLAG_SOCKETP;
 327                 count++;
 328         } else {
 329                 sc->handle[1].flags = 0;
 330         }
 331         sc->handle[1].laststate = PCIC_LASTSTATE_EMPTY;
 332
 333         DPRINTF((" 0x%02x", reg));
 334
 335         /*
 336          * The CL-PD6729 has only one controller and always returns 0
 337          * if you try to read from the second one. Maybe pcic_ident_ok
 338          * shouldn't accept 0?
 339          */
 340         sc->handle[2].sc = sc;
 341         sc->handle[2].sock = C1SA;
 342         /* initialise pcic_read and pcic_write functions */
 343         sc->handle[2].ph_read = st_pcic_read;
 344         sc->handle[2].ph_write = st_pcic_write;
 345         sc->handle[2].ph_bus_t = sc->iot;
 346         sc->handle[2].ph_bus_h = sc->ioh;
 347         if (pcic_vendor(&sc->handle[0]) != PCIC_VENDOR_CIRRUS_PD672X ||
 348             pcic_read(&sc->handle[2], PCIC_IDENT) != 0) {
 349                 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2],
 350                                                   PCIC_IDENT))) {
 351                         sc->handle[2].flags = PCIC_FLAG_SOCKETP;
 352                         count++;
 353                 } else {
 354                         sc->handle[2].flags = 0;
 355                 }
 356                 sc->handle[2].laststate = PCIC_LASTSTATE_EMPTY;
 357
 358                 DPRINTF((" 0x%02x", reg));
 359
 360                 sc->handle[3].sc = sc;
 361                 sc->handle[3].sock = C1SB;
 362                 /* initialise pcic_read and pcic_write functions */
 363                 sc->handle[3].ph_read = st_pcic_read;
 364                 sc->handle[3].ph_write = st_pcic_write;
 365                 sc->handle[3].ph_bus_t = sc->iot;
 366                 sc->handle[3].ph_bus_h = sc->ioh;
 367                 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3],
 368                                                   PCIC_IDENT))) {
 369                         sc->handle[3].flags = PCIC_FLAG_SOCKETP;
 370                         count++;
 371                 } else {
 372                         sc->handle[3].flags = 0;
 373                 }
 374                 sc->handle[3].laststate = PCIC_LASTSTATE_EMPTY;
 375
 376                 DPRINTF((" 0x%02x\n", reg));
 377         } else {
 378                 sc->handle[2].flags = 0;
 379                 sc->handle[3].flags = 0;
 380         }
 381
 382         if (count == 0)
 383                 panic("pcic_attach: attach found no sockets");
 384
 385         /* establish the interrupt */
 386
 387         /* XXX block interrupts? */
 388
 389         for (i = 0; i < PCIC_NSLOTS; i++) {
 390                 /*
 391                  * this should work, but w/o it, setting tty flags hangs at
 392                  * boot time.
 393                  */
 394                 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
 395                 {
 396                         STAILQ_INIT(&sc->handle[i].events);
 397                         pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0);
 398                         pcic_read(&sc->handle[i], PCIC_CSC);
 399                 }
 400         }
 401
 402         if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) ||
 403             (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) {
 404                 vendor = pcic_vendor(&sc->handle[0]);
 405
 406                 device_printf(dev, "controller 0 (%s) has ",
 407                        pcic_vendor_to_string(vendor));
 408
 409                 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) &&
 410                     (sc->handle[1].flags & PCIC_FLAG_SOCKETP))
 411                         printf("sockets A and B\n");
 412                 else if (sc->handle[0].flags & PCIC_FLAG_SOCKETP)
 413                         printf("socket A only\n");
 414                 else
 415                         printf("socket B only\n");
 416
 417                 if (sc->handle[0].flags & PCIC_FLAG_SOCKETP)
 418                         sc->handle[0].vendor = vendor;
 419                 if (sc->handle[1].flags & PCIC_FLAG_SOCKETP)
 420                         sc->handle[1].vendor = vendor;
 421         }
 422         if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) ||
 423             (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) {
 424                 vendor = pcic_vendor(&sc->handle[2]);
 425
 426                 device_printf(dev, "controller 1 (%s) has ",
 427                        pcic_vendor_to_string(vendor));
 428
 429                 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) &&
 430                     (sc->handle[3].flags & PCIC_FLAG_SOCKETP))
 431                         printf("sockets A and B\n");
 432                 else if (sc->handle[2].flags & PCIC_FLAG_SOCKETP)
 433                         printf("socket A only\n");
 434                 else
 435                         printf("socket B only\n");
 436
 437                 if (sc->handle[2].flags & PCIC_FLAG_SOCKETP)
 438                         sc->handle[2].vendor = vendor;
 439                 if (sc->handle[3].flags & PCIC_FLAG_SOCKETP)
 440                         sc->handle[3].vendor = vendor;
 441         }
 442
 443         for (i = 0; i < PCIC_NSLOTS; i++) {
 444                 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) == 0)
 445                         continue;
 446                 h = &sc->handle[i];
 447                 /* initialize the rest of the handle */
 448                 h->shutdown = 0;
 449                 h->memalloc = 0;
 450                 h->ioalloc = 0;
 451                 h->ih_irq = 0;
 452                 h->sc = sc;
 453                 h->dev = device_add_child(dev, "pccard", -1);
 454                 device_set_ivars(h->dev, h);
 455                 pcic_init_socket(h);
 456         }
 457
 458         /*
 459          * Probe and attach any children as were configured above.
 460          */
 461         error = bus_generic_attach(dev);
 462         if (error)
 463                 pcic_deactivate(dev);
 464         return error;
 465 }
 466
 467 void
 468 pcic_create_event_thread(void *arg)
 469 {
 470         struct pcic_handle *h = arg;
 471         const char *cs;
 472
 473         switch (h->sock) {
 474         case C0SA:
 475                 cs = "0,0";
 476                 break;
 477         case C0SB:
 478                 cs = "0,1";
 479                 break;
 480         case C1SA:
 481                 cs = "1,0";
 482                 break;
 483         case C1SB:
 484                 cs = "1,1";
 485                 break;
 486         default:
 487                 panic("pcic_create_event_thread: unknown pcic socket");
 488         }
 489
 490         if (kthread_create(pcic_event_thread, h, &h->event_thread,
 491             "%s,%s", device_get_name(h->sc->dev), cs)) {
 492                 device_printf(h->sc->dev,
 493                     "cannot create event thread for sock 0x%02x\n", h->sock);
 494                 panic("pcic_create_event_thread");
 495         }
 496 }
 497
 498 void
 499 pcic_event_thread(void *arg)
 500 {
 501         struct pcic_handle *h = arg;
 502         struct pcic_event *pe;
 503         int s;
 504         struct pcic_softc *sc = h->sc;
 505
 506         while (h->shutdown == 0) {
 507                 s = splhigh();
 508                 if ((pe = STAILQ_FIRST(&h->events)) == NULL) {
 509                         splx(s);
 510                         (void) tsleep(&h->events, PWAIT, "pcicev", 0);
 511                         continue;
 512                 } else {
 513                         splx(s);
 514                         /* sleep .25s to be enqueued chatterling interrupts */
 515                         (void) tsleep((caddr_t)pcic_event_thread, PWAIT, "pcicss", hz/4);
 516                 }
 517                 s = splhigh();
 518                 STAILQ_REMOVE_HEAD_UNTIL(&h->events, pe, pe_q);
 519                 splx(s);
 520
 521                 switch (pe->pe_type) {
 522                 case PCIC_EVENT_INSERTION:
 523                         s = splhigh();
 524                         while (1) {
 525                                 struct pcic_event *pe1, *pe2;
 526
 527                                 if ((pe1 = STAILQ_FIRST(&h->events)) == NULL)
 528                                         break;
 529                                 if (pe1->pe_type != PCIC_EVENT_REMOVAL)
 530                                         break;
 531                                 if ((pe2 = STAILQ_NEXT(pe1, pe_q)) == NULL)
 532                                         break;
 533                                 if (pe2->pe_type == PCIC_EVENT_INSERTION) {
 534                                         STAILQ_REMOVE_HEAD_UNTIL(&h->events, pe1, pe_q);
 535                                         free(pe1, M_TEMP);
 536                                         STAILQ_REMOVE_HEAD_UNTIL(&h->events, pe2, pe_q);
 537                                         free(pe2, M_TEMP);
 538                                 }
 539                         }
 540                         splx(s);
 541
 542                         DEVPRINTF((h->dev, "insertion event\n"));
 543                         pcic_attach_card(h);
 544                         break;
 545
 546                 case PCIC_EVENT_REMOVAL:
 547                         s = splhigh();
 548                         while (1) {
 549                                 struct pcic_event *pe1, *pe2;
 550
 551                                 if ((pe1 = STAILQ_FIRST(&h->events)) == NULL)
 552                                         break;
 553                                 if (pe1->pe_type != PCIC_EVENT_INSERTION)
 554                                         break;
 555                                 if ((pe2 = STAILQ_NEXT(pe1, pe_q)) == NULL)
 556                                         break;
 557                                 if (pe2->pe_type == PCIC_EVENT_REMOVAL) {
 558                                         STAILQ_REMOVE_HEAD_UNTIL(&h->events, pe1, pe_q);
 559                                         free(pe1, M_TEMP);
 560                                         STAILQ_REMOVE_HEAD_UNTIL(&h->events, pe2, pe_q);
 561                                         free(pe2, M_TEMP);
 562                                 }
 563                         }
 564                         splx(s);
 565
 566                         DEVPRINTF((h->dev, "removal event\n"));
 567                         pcic_detach_card(h, DETACH_FORCE);
 568                         break;
 569
 570                 default:
 571                         panic("pcic_event_thread: unknown event %d",
 572                             pe->pe_type);
 573                 }
 574                 free(pe, M_TEMP);
 575         }
 576
 577         h->event_thread = NULL;
 578
 579         /* In case parent is waiting for us to exit. */
 580         wakeup(sc);
 581
 582         kthread_exit(0);
 583 }
 584
 585 void
 586 pcic_init_socket(struct pcic_handle *h)
 587 {
 588         int reg;
 589         struct pcic_softc *sc = h->sc;
 590
 591         /*
 592          * queue creation of a kernel thread to handle insert/removal events.
 593          */
 594         *lasthandle++ = h;
 595
 596         /* set up the card to interrupt on card detect */
 597
 598         pcic_write(h, PCIC_CSC_INTR, (sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) |
 599             PCIC_CSC_INTR_CD_ENABLE);
 600         pcic_write(h, PCIC_INTR, 0);
 601         pcic_read(h, PCIC_CSC);
 602
 603         /* unsleep the cirrus controller */
 604
 605         if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) ||
 606             (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) {
 607                 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2);
 608                 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) {
 609                         DEVPRINTF((sc->dev, "socket %02x was suspended\n",
 610                             h->sock));
 611                         reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND;
 612                         pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg);
 613                 }
 614         }
 615         h->laststate = PCIC_LASTSTATE_EMPTY;
 616
 617 #if 0
 618 /* XXX */
 619 /*      Should do this later */
 620 /* maybe as part of interrupt routing verification */
 621         if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) ==
 622             PCIC_IF_STATUS_CARDDETECT_PRESENT) {
 623                 pcic_attach_card(h);
 624                 h->laststate = PCIC_LASTSTATE_PRESENT;
 625         } else {
 626                 h->laststate = PCIC_LASTSTATE_EMPTY;
 627         }
 628 #endif
 629 }
 630
 631 static void
 632 pcic_intr(void *arg)
 633 {
 634         struct pcic_softc *sc = arg;
 635         int i;
 636
 637         DEVPRINTF((sc->dev, "intr\n"));
 638
 639         for (i = 0; i < PCIC_NSLOTS; i++)
 640                 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
 641                         pcic_intr_socket(&sc->handle[i]);
 642 }
 643
 644 static void
 645 pcic_intr_socket(struct pcic_handle *h)
 646 {
 647         int cscreg;
 648
 649         cscreg = pcic_read(h, PCIC_CSC);
 650
 651         cscreg &= (PCIC_CSC_GPI | PCIC_CSC_CD | PCIC_CSC_READY |
 652             PCIC_CSC_BATTWARN | PCIC_CSC_BATTDEAD);
 653
 654         if (cscreg & PCIC_CSC_GPI) {
 655                 DEVPRINTF((h->dev, "%02x GPI\n", h->sock));
 656         }
 657         if (cscreg & PCIC_CSC_CD) {
 658                 int statreg;
 659
 660                 statreg = pcic_read(h, PCIC_IF_STATUS);
 661
 662                 DEVPRINTF((h->dev, "%02x CD %x\n", h->sock, statreg));
 663
 664                 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) ==
 665                     PCIC_IF_STATUS_CARDDETECT_PRESENT) {
 666                         if (h->laststate != PCIC_LASTSTATE_PRESENT) {
 667                                 DEVPRINTF((h->dev,
 668                                     "enqueing INSERTION event\n"));
 669                                 pcic_queue_event(h, PCIC_EVENT_INSERTION);
 670                         }
 671                         h->laststate = PCIC_LASTSTATE_PRESENT;
 672                 } else {
 673                         if (h->laststate == PCIC_LASTSTATE_PRESENT) {
 674                                 /* Deactivate the card now. */
 675                                 DEVPRINTF((h->dev, "detaching card\n"));
 676                                 pcic_detach_card(h, DETACH_FORCE);
 677
 678                                 DEVPRINTF((h->dev,
 679                                     "enqueing REMOVAL event\n"));
 680                                 pcic_queue_event(h, PCIC_EVENT_REMOVAL);
 681                         }
 682                         h->laststate = ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 0)
 683                                 ? PCIC_LASTSTATE_EMPTY : PCIC_LASTSTATE_HALF;
 684                 }
 685         }
 686         if (cscreg & PCIC_CSC_READY) {
 687                 DEVPRINTF((h->dev, "%02x READY\n", h->sock));
 688                 /* shouldn't happen */
 689         }
 690         if (cscreg & PCIC_CSC_BATTWARN) {
 691                 DEVPRINTF((h->dev, "%02x BATTWARN\n", h->sock));
 692         }
 693         if (cscreg & PCIC_CSC_BATTDEAD) {
 694                 DEVPRINTF((h->dev, "%02x BATTDEAD\n", h->sock));
 695         }
 696 }
 697
 698 void
 699 pcic_queue_event(struct pcic_handle *h, int event)
 700 {
 701         struct pcic_event *pe;
 702         int s;
 703
 704         pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT);
 705         if (pe == NULL)
 706                 panic("pcic_queue_event: can't allocate event");
 707
 708         pe->pe_type = event;
 709         s = splhigh();
 710         STAILQ_INSERT_TAIL(&h->events, pe, pe_q);
 711         splx(s);
 712         wakeup(&h->events);
 713 }
 714
 715 static void
 716 pcic_attach_card(struct pcic_handle *h)
 717 {
 718         DPRINTF(("pcic_attach_card h %p h->dev %p %s %s\n", h, h->dev,
 719             device_get_name(h->dev), device_get_name(device_get_parent(h->dev))));
 720         if (!(h->flags & PCIC_FLAG_CARDP)) {
 721                 /* call the MI attach function */
 722                 CARD_ATTACH_CARD(h->dev);
 723
 724                 h->flags |= PCIC_FLAG_CARDP;
 725         } else {
 726                 DPRINTF(("pcic_attach_card: already attached"));
 727         }
 728 }
 729
 730 static void
 731 pcic_detach_card(struct pcic_handle *h, int flags)
 732 {
 733
 734         if (h->flags & PCIC_FLAG_CARDP) {
 735                 h->flags &= ~PCIC_FLAG_CARDP;
 736
 737                 /* call the MI detach function */
 738                 CARD_DETACH_CARD(h->dev, flags);
 739         } else {
 740                 DPRINTF(("pcic_detach_card: already detached"));
 741         }
 742 }
 743
 744 static int
 745 pcic_chip_mem_alloc(struct pcic_handle *h, struct resource *r, bus_size_t size,
 746     struct pccard_mem_handle *pcmhp)
 747 {
 748         bus_space_handle_t memh;
 749         bus_addr_t addr;
 750         bus_size_t sizepg;
 751         int mask;
 752         struct pcic_softc *sc = h->sc;
 753
 754         /* out of sc->memh, allocate as many pages as necessary */
 755
 756         /* convert size to PCIC pages */
 757         sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN;
 758         if (sizepg > PCIC_MAX_MEM_PAGES)
 759                 return (1);
 760
 761         mask = (1 << sizepg) - 1;
 762
 763         addr = rman_get_start(r);
 764         memh = addr;
 765         pcmhp->memt = sc->memt;
 766         pcmhp->memh = memh;
 767         pcmhp->addr = addr;
 768         pcmhp->size = size;
 769         pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE;
 770         return (0);
 771 }
 772
 773 static void
 774 pcic_chip_mem_free(struct pcic_handle *h, struct pccard_mem_handle *pcmhp)
 775 {
 776 }
 777
 778 static struct mem_map_index_st {
 779         int     sysmem_start_lsb;
 780         int     sysmem_start_msb;
 781         int     sysmem_stop_lsb;
 782         int     sysmem_stop_msb;
 783         int     cardmem_lsb;
 784         int     cardmem_msb;
 785         int     memenable;
 786 } mem_map_index[] = {
 787         {
 788                 PCIC_SYSMEM_ADDR0_START_LSB,
 789                 PCIC_SYSMEM_ADDR0_START_MSB,
 790                 PCIC_SYSMEM_ADDR0_STOP_LSB,
 791                 PCIC_SYSMEM_ADDR0_STOP_MSB,
 792                 PCIC_CARDMEM_ADDR0_LSB,
 793                 PCIC_CARDMEM_ADDR0_MSB,
 794                 PCIC_ADDRWIN_ENABLE_MEM0,
 795         },
 796         {
 797                 PCIC_SYSMEM_ADDR1_START_LSB,
 798                 PCIC_SYSMEM_ADDR1_START_MSB,
 799                 PCIC_SYSMEM_ADDR1_STOP_LSB,
 800                 PCIC_SYSMEM_ADDR1_STOP_MSB,
 801                 PCIC_CARDMEM_ADDR1_LSB,
 802                 PCIC_CARDMEM_ADDR1_MSB,
 803                 PCIC_ADDRWIN_ENABLE_MEM1,
 804         },
 805         {
 806                 PCIC_SYSMEM_ADDR2_START_LSB,
 807                 PCIC_SYSMEM_ADDR2_START_MSB,
 808                 PCIC_SYSMEM_ADDR2_STOP_LSB,
 809                 PCIC_SYSMEM_ADDR2_STOP_MSB,
 810                 PCIC_CARDMEM_ADDR2_LSB,
 811                 PCIC_CARDMEM_ADDR2_MSB,
 812                 PCIC_ADDRWIN_ENABLE_MEM2,
 813         },
 814         {
 815                 PCIC_SYSMEM_ADDR3_START_LSB,
 816                 PCIC_SYSMEM_ADDR3_START_MSB,
 817                 PCIC_SYSMEM_ADDR3_STOP_LSB,
 818                 PCIC_SYSMEM_ADDR3_STOP_MSB,
 819                 PCIC_CARDMEM_ADDR3_LSB,
 820                 PCIC_CARDMEM_ADDR3_MSB,
 821                 PCIC_ADDRWIN_ENABLE_MEM3,
 822         },
 823         {
 824                 PCIC_SYSMEM_ADDR4_START_LSB,
 825                 PCIC_SYSMEM_ADDR4_START_MSB,
 826                 PCIC_SYSMEM_ADDR4_STOP_LSB,
 827                 PCIC_SYSMEM_ADDR4_STOP_MSB,
 828                 PCIC_CARDMEM_ADDR4_LSB,
 829                 PCIC_CARDMEM_ADDR4_MSB,
 830                 PCIC_ADDRWIN_ENABLE_MEM4,
 831         },
 832 };
 833
 834 static void
 835 pcic_chip_do_mem_map(struct pcic_handle *h, int win)
 836 {
 837         int reg;
 838
 839         pcic_write(h, mem_map_index[win].sysmem_start_lsb,
 840             (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff);
 841         pcic_write(h, mem_map_index[win].sysmem_start_msb,
 842             ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) &
 843             PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK));
 844
 845 #if 0
 846         /* XXX do I want 16 bit all the time? */
 847         PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT;
 848 #endif
 849
 850         pcic_write(h, mem_map_index[win].sysmem_stop_lsb,
 851             ((h->mem[win].addr + h->mem[win].size) >>
 852             PCIC_SYSMEM_ADDRX_SHIFT) & 0xff);
 853         pcic_write(h, mem_map_index[win].sysmem_stop_msb,
 854             (((h->mem[win].addr + h->mem[win].size) >>
 855             (PCIC_SYSMEM_ADDRX_SHIFT + 8)) &
 856             PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) |
 857             PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2);
 858
 859         pcic_write(h, mem_map_index[win].cardmem_lsb,
 860             (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff);
 861         pcic_write(h, mem_map_index[win].cardmem_msb,
 862             ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) &
 863             PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) |
 864             ((h->mem[win].kind == PCCARD_MEM_ATTR) ?
 865             PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0));
 866
 867         reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
 868         reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16);
 869         pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
 870
 871         DELAY(100);
 872
 873 #ifdef PCICDEBUG
 874         {
 875                 int r1, r2, r3, r4, r5, r6;
 876
 877                 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb);
 878                 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb);
 879                 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb);
 880                 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb);
 881                 r5 = pcic_read(h, mem_map_index[win].cardmem_msb);
 882                 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb);
 883
 884                 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x "
 885                     "%02x%02x\n", win, r1, r2, r3, r4, r5, r6));
 886         }
 887 #endif
 888 }
 889
 890 static int
 891 pcic_chip_mem_map(struct pcic_handle *h, int kind, bus_addr_t card_addr,
 892     bus_size_t size, struct pccard_mem_handle *pcmhp, bus_addr_t *offsetp,
 893     int *windowp)
 894 {
 895         bus_addr_t busaddr;
 896         long card_offset;
 897         int i, win;
 898
 899         win = -1;
 900         for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0]));
 901             i++) {
 902                 if ((h->memalloc & (1 << i)) == 0) {
 903                         win = i;
 904                         h->memalloc |= (1 << i);
 905                         break;
 906                 }
 907         }
 908
 909         if (win == -1)
 910                 return (1);
 911
 912         *windowp = win;
 913         busaddr = pcmhp->addr;
 914
 915         /*
 916          * compute the address offset to the pccard address space for the
 917          * pcic.  this is intentionally signed.  The masks and shifts below
 918          * will cause TRT to happen in the pcic registers.  Deal with making
 919          * sure the address is aligned, and return the alignment offset.
 920          */
 921
 922         *offsetp = card_addr % PCIC_MEM_ALIGN;
 923         card_addr -= *offsetp;
 924
 925         DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr "
 926             "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size,
 927             (u_long) card_addr));
 928
 929         /*
 930          * include the offset in the size, and decrement size by one, since
 931          * the hw wants start/stop
 932          */
 933         size += *offsetp - 1;
 934
 935         card_offset = (((long) card_addr) - ((long) busaddr));
 936
 937         h->mem[win].addr = busaddr;
 938         h->mem[win].size = size;
 939         h->mem[win].offset = card_offset;
 940         h->mem[win].kind = kind;
 941
 942         pcic_chip_do_mem_map(h, win);
 943
 944         return (0);
 945 }
 946
 947 static void
 948 pcic_chip_mem_unmap(struct pcic_handle *h, int window)
 949 {
 950         int reg;
 951
 952         if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0])))
 953                 panic("pcic_chip_mem_unmap: window out of range");
 954
 955         reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
 956         reg &= ~mem_map_index[window].memenable;
 957         pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
 958
 959         h->memalloc &= ~(1 << window);
 960 }
 961
 962 static int
 963 pcic_chip_io_alloc(struct pcic_handle *h, bus_addr_t start, bus_size_t size,
 964     bus_size_t align, struct pccard_io_handle *pcihp)
 965 {
 966         bus_space_tag_t iot;
 967         bus_space_handle_t ioh;
 968         bus_addr_t ioaddr;
 969         int flags = 0;
 970         struct pcic_softc *sc = h->sc;
 971
 972         /*
 973          * Allocate some arbitrary I/O space.
 974          */
 975
 976         iot = sc->iot;
 977
 978         ioaddr = start;
 979         if (start) {
 980                 ioh = start;
 981                 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n",
 982                     (u_long) ioaddr, (u_long) size));
 983         } else {
 984                 flags |= PCCARD_IO_ALLOCATED;
 985                 ioh = start;
 986                 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n",
 987                     (u_long) ioaddr, (u_long) size));
 988         }
 989
 990         pcihp->iot = iot;
 991         pcihp->ioh = ioh;
 992         pcihp->addr = ioaddr;
 993         pcihp->size = size;
 994         pcihp->flags = flags;
 995
 996         return (0);
 997 }
 998
 999 static void
1000 pcic_chip_io_free(struct pcic_handle *h, struct pccard_io_handle *pcihp)
1001 {
1002 }
1003
1004
1005 static struct io_map_index_st {
1006         int     start_lsb;
1007         int     start_msb;
1008         int     stop_lsb;
1009         int     stop_msb;
1010         int     ioenable;
1011         int     ioctlmask;
1012         int     ioctlbits[3];           /* indexed by PCCARD_WIDTH_* */
1013 }               io_map_index[] = {
1014         {
1015                 PCIC_IOADDR0_START_LSB,
1016                 PCIC_IOADDR0_START_MSB,
1017                 PCIC_IOADDR0_STOP_LSB,
1018                 PCIC_IOADDR0_STOP_MSB,
1019                 PCIC_ADDRWIN_ENABLE_IO0,
1020                 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT |
1021                 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK,
1022                 {
1023                         PCIC_IOCTL_IO0_IOCS16SRC_CARD,
1024                         PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
1025                             PCIC_IOCTL_IO0_DATASIZE_8BIT,
1026                         PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
1027                             PCIC_IOCTL_IO0_DATASIZE_16BIT,
1028                 },
1029         },
1030         {
1031                 PCIC_IOADDR1_START_LSB,
1032                 PCIC_IOADDR1_START_MSB,
1033                 PCIC_IOADDR1_STOP_LSB,
1034                 PCIC_IOADDR1_STOP_MSB,
1035                 PCIC_ADDRWIN_ENABLE_IO1,
1036                 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT |
1037                 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK,
1038                 {
1039                         PCIC_IOCTL_IO1_IOCS16SRC_CARD,
1040                         PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE |
1041                             PCIC_IOCTL_IO1_DATASIZE_8BIT,
1042                         PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE |
1043                             PCIC_IOCTL_IO1_DATASIZE_16BIT,
1044                 },
1045         },
1046 };
1047
1048 static void
1049 pcic_chip_do_io_map(struct pcic_handle *h, int win)
1050 {
1051         int reg;
1052
1053         DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n",
1054             win, (long) h->io[win].addr, (long) h->io[win].size,
1055             h->io[win].width * 8));
1056
1057         pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff);
1058         pcic_write(h, io_map_index[win].start_msb,
1059             (h->io[win].addr >> 8) & 0xff);
1060
1061         pcic_write(h, io_map_index[win].stop_lsb,
1062             (h->io[win].addr + h->io[win].size - 1) & 0xff);
1063         pcic_write(h, io_map_index[win].stop_msb,
1064             ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff);
1065
1066         reg = pcic_read(h, PCIC_IOCTL);
1067         reg &= ~io_map_index[win].ioctlmask;
1068         reg |= io_map_index[win].ioctlbits[h->io[win].width];
1069         pcic_write(h, PCIC_IOCTL, reg);
1070
1071         reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
1072         reg |= io_map_index[win].ioenable;
1073         pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
1074 }
1075
1076 static int
1077 pcic_chip_io_map(struct pcic_handle *h, int width, bus_addr_t offset,
1078     bus_size_t size, struct pccard_io_handle *pcihp, int *windowp)
1079 {
1080         bus_addr_t ioaddr = pcihp->addr + offset;
1081         int i, win;
1082 #ifdef PCICDEBUG
1083         static char *width_names[] = { "auto", "io8", "io16" };
1084 #endif
1085 #if 0
1086         struct pcic_softc *sc = h->sc;
1087 #endif
1088
1089         /* XXX Sanity check offset/size. */
1090
1091         win = -1;
1092         for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) {
1093                 if ((h->ioalloc & (1 << i)) == 0) {
1094                         win = i;
1095                         h->ioalloc |= (1 << i);
1096                         break;
1097                 }
1098         }
1099
1100         if (win == -1)
1101                 return (1);
1102
1103         *windowp = win;
1104
1105 #if 0
1106         /* XXX this is pretty gross */
1107         if (sc->iot != pcihp->iot)
1108                 panic("pcic_chip_io_map iot is bogus");
1109 #endif
1110
1111         DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n",
1112                  win, width_names[width], (u_long) ioaddr, (u_long) size));
1113
1114         /* XXX wtf is this doing here? */
1115
1116         printf(" port 0x%lx", (u_long) ioaddr);
1117         if (size > 1)
1118                 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1);
1119
1120         h->io[win].addr = ioaddr;
1121         h->io[win].size = size;
1122         h->io[win].width = width;
1123
1124         pcic_chip_do_io_map(h, win);
1125
1126         return (0);
1127 }
1128
1129 static void
1130 pcic_chip_io_unmap(struct pcic_handle *h, int window)
1131 {
1132         int reg;
1133
1134         if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0])))
1135                 panic("pcic_chip_io_unmap: window out of range");
1136
1137         reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
1138         reg &= ~io_map_index[window].ioenable;
1139         pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
1140
1141         h->ioalloc &= ~(1 << window);
1142 }
1143
1144 static void
1145 pcic_wait_ready(struct pcic_handle *h)
1146 {
1147         int i;
1148
1149         for (i = 0; i < 10000; i++) {
1150                 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY)
1151                         return;
1152                 DELAY(500);
1153 #ifdef PCICDEBUG
1154                 if (pcic_debug) {
1155                         if ((i>5000) && (i%100 == 99))
1156                                 printf(".");
1157                 }
1158 #endif
1159         }
1160
1161 #ifdef DIAGNOSTIC
1162         printf("pcic_wait_ready: ready never happened, status = %02x\n",
1163             pcic_read(h, PCIC_IF_STATUS));
1164 #endif
1165 }
1166
1167 int
1168 pcic_enable_socket(device_t dev, device_t child)
1169 {
1170         struct pcic_handle *h = pcic_get_handle(dev, child);
1171         int cardtype, reg, win;
1172
1173         /* this bit is mostly stolen from pcic_attach_card */
1174
1175         /* power down the socket to reset it, clear the card reset pin */
1176
1177         pcic_write(h, PCIC_PWRCTL, 0);
1178
1179         /*
1180          * wait 300ms until power fails (Tpf).  Then, wait 100ms since
1181          * we are changing Vcc (Toff).
1182          */
1183         DELAY((300 + 100) * 1000);
1184
1185 #ifdef VADEM_POWER_HACK
1186         bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e);
1187         bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37);
1188         printf("prcr = %02x\n", pcic_read(h, 0x02));
1189         printf("cvsr = %02x\n", pcic_read(h, 0x2f));
1190         printf("DANGER WILL ROBINSON!  Changing voltage select!\n");
1191         pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03);
1192         printf("cvsr = %02x\n", pcic_read(h, 0x2f));
1193 #endif
1194
1195         /* power up the socket */
1196
1197         pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV
1198                            | PCIC_PWRCTL_PWR_ENABLE);
1199
1200         /*
1201          * wait 100ms until power raise (Tpr) and 20ms to become
1202          * stable (Tsu(Vcc)).
1203          *
1204          * some machines require some more time to be settled
1205          * (300ms is added here).
1206          */
1207         DELAY((100 + 20 + 300) * 1000);
1208
1209         pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_OE
1210                            | PCIC_PWRCTL_PWR_ENABLE);
1211         pcic_write(h, PCIC_INTR, 0);
1212
1213         /*
1214          * hold RESET at least 10us.
1215          */
1216         DELAY(10);
1217
1218         /* clear the reset flag */
1219
1220         pcic_write(h, PCIC_INTR, PCIC_INTR_RESET);
1221
1222         /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */
1223
1224         DELAY(20000);
1225
1226         /* wait for the chip to finish initializing */
1227
1228 #ifdef DIAGNOSTIC
1229         reg = pcic_read(h, PCIC_IF_STATUS);
1230         if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) {
1231                 printf("pcic_chip_socket_enable: status %x", reg);
1232         }
1233 #endif
1234
1235         pcic_wait_ready(h);
1236
1237         /* zero out the address windows */
1238         pcic_write(h, PCIC_ADDRWIN_ENABLE, 0);
1239
1240         /* set the card type */
1241         CARD_GET_TYPE(h->dev, &cardtype);
1242
1243         reg = pcic_read(h, PCIC_INTR);
1244         reg &= ~(PCIC_INTR_CARDTYPE_MASK | PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
1245         reg |= ((cardtype == PCCARD_IFTYPE_IO) ?
1246                 PCIC_INTR_CARDTYPE_IO :
1247                 PCIC_INTR_CARDTYPE_MEM);
1248         reg |= h->ih_irq;
1249         pcic_write(h, PCIC_INTR, reg);
1250
1251         DEVPRINTF((h->dev, "pcic_chip_socket_enable cardtype %s %02x\n",
1252             ((cardtype == PCCARD_IFTYPE_IO) ? "io" : "mem"), reg));
1253
1254         /* reinstall all the memory and io mappings */
1255
1256         for (win = 0; win < PCIC_MEM_WINS; win++)
1257                 if (h->memalloc & (1 << win))
1258                         pcic_chip_do_mem_map(h, win);
1259
1260         for (win = 0; win < PCIC_IO_WINS; win++)
1261                 if (h->ioalloc & (1 << win))
1262                         pcic_chip_do_io_map(h, win);
1263
1264         return 0;
1265 }
1266
1267 int
1268 pcic_disable_socket(device_t dev, device_t child)
1269 {
1270         struct pcic_handle *h = pcic_get_handle(dev, child);
1271         DPRINTF(("pcic_chip_socket_disable\n"));
1272
1273         /* power down the socket */
1274
1275         pcic_write(h, PCIC_PWRCTL, 0);
1276
1277         /*
1278          * wait 300ms until power fails (Tpf).
1279          */
1280         DELAY(300 * 1000);
1281
1282         return 0;
1283 }
1284
1285 static u_int8_t
1286 st_pcic_read(struct pcic_handle *h, int idx)
1287 {
1288         if (idx != -1) {
1289                 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX,
1290                     h->sock + idx);
1291         }
1292         return bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA);
1293 }
1294
1295 static void
1296 st_pcic_write(struct pcic_handle *h, int idx, u_int8_t data)
1297 {
1298         if (idx != -1) {
1299                 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX,
1300                     h->sock + idx);
1301         }
1302
1303         bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data);
1304 }
1305
1306 int
1307 pcic_activate_resource(device_t dev, device_t child, int type, int rid,
1308     struct resource *r)
1309 {
1310         int err;
1311         int sz;
1312         int win;
1313         bus_addr_t off;
1314         struct pcic_handle *h = pcic_get_handle(dev, child);
1315
1316         sz = rman_get_end(r) - rman_get_start(r) + 1;
1317         switch (type) {
1318         case SYS_RES_IOPORT:
1319                 win = rid;
1320                 err = pcic_chip_io_map(h, 0, 0, sz, &h->io[rid], &win);
1321                 if (err) {
1322                         pcic_chip_io_free(h, &h->io[rid]);
1323                         return err;
1324                 }
1325                 break;
1326         case SYS_RES_MEMORY:
1327                 err = pcic_chip_mem_map(h, 0, 0, sz, &h->mem[rid], &off, &win);
1328                 if (err) {
1329                         pcic_chip_mem_free(h, &h->mem[rid]);
1330                         return err;
1331                 }
1332                 break;
1333         default:
1334                 break;
1335         }
1336         err = bus_generic_activate_resource(device_get_parent(dev), child,
1337             type, rid, r);
1338         return (err);
1339 }
1340
1341 int
1342 pcic_deactivate_resource(device_t dev, device_t child, int type, int rid,
1343     struct resource *r)
1344 {
1345         struct pcic_handle *h = pcic_get_handle(dev, child);
1346         int err = 0;
1347
1348         switch (type) {
1349         case SYS_RES_IOPORT:
1350                 pcic_chip_io_unmap(h, rid);
1351                 break;
1352         case SYS_RES_MEMORY:
1353                 pcic_chip_mem_unmap(h, rid);
1354         default:
1355                 break;
1356         }
1357         err = bus_generic_deactivate_resource(device_get_parent(dev), child,
1358             type, rid, r);
1359         return (err);
1360 }
1361
1362 int
1363 pcic_setup_intr(device_t dev, device_t child, struct resource *irqres,
1364     int flags, driver_intr_t intr, void *arg, void **cookiep)
1365 {
1366         struct pcic_handle *h = pcic_get_handle(dev, child);
1367         int reg;
1368         int irq;
1369         int err;
1370
1371         err = bus_generic_setup_intr(device_get_parent(dev), child, irqres,
1372             flags, intr, arg, cookiep);
1373         if (!err)
1374                 return (err);
1375
1376         irq = rman_get_start(irqres);
1377         reg = pcic_read(h, PCIC_INTR);
1378         reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
1379         reg |= irq;
1380         pcic_write(h, PCIC_INTR, reg);
1381
1382         h->ih_irq = irq;
1383
1384         device_printf(dev, "card irq %d\n", irq);
1385
1386         return 0;
1387 }
1388
1389 int
1390 pcic_teardown_intr(device_t dev, device_t child, struct resource *irq,
1391     void *cookiep)
1392 {
1393         int reg;
1394         struct pcic_handle *h = pcic_get_handle(dev, child);
1395
1396         h->ih_irq = 0;
1397
1398         reg = pcic_read(h, PCIC_INTR);
1399         reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
1400         pcic_write(h, PCIC_INTR, reg);
1401
1402         return (bus_generic_teardown_intr(device_get_parent(dev), child, irq,
1403             cookiep));
1404 }
1405
1406 struct resource *
1407 pcic_alloc_resource(device_t dev, device_t child, int type, int *rid,
1408     u_long start, u_long end, u_long count, u_int flags)
1409 {
1410         int sz;
1411         int err;
1412         struct resource *r;
1413         struct pcic_handle *h = pcic_get_handle(dev, child);
1414
1415         /* Nearly default */
1416         if (type == SYS_RES_MEMORY && start == 0 && end == ~0 && count != 1) {
1417                 start = 0xd0000;        /* XXX */
1418                 end = 0xdffff;
1419         }
1420
1421         r = bus_generic_alloc_resource(dev, child, type, rid, start, end,
1422             count, flags);
1423         if (r == NULL)
1424                 return r;
1425         sz = rman_get_end(r) - rman_get_start(r) + 1;
1426         switch (type) {
1427         case SYS_RES_IOPORT:
1428                 err = pcic_chip_io_alloc(h, rman_get_start(r), sz, 0,
1429                     &h->io[*rid]);
1430                 if (err) {
1431                         bus_generic_release_resource(dev, child, type, *rid,
1432                             r);
1433                         return 0;
1434                 }
1435                 break;
1436         case SYS_RES_MEMORY:
1437                 err = pcic_chip_mem_alloc(h, r, sz, &h->mem[*rid]);
1438                 if (err) {
1439                         bus_generic_release_resource(dev, child, type, *rid,
1440                             r);
1441                         return 0;
1442                 }
1443                 break;
1444         default:
1445                 break;
1446         }
1447         return r;
1448 }
1449
1450 int
1451 pcic_release_resource(device_t dev, device_t child, int type, int rid,
1452     struct resource *r)
1453 {
1454         struct pcic_handle *h = pcic_get_handle(dev, child);
1455
1456         switch (type) {
1457         case SYS_RES_IOPORT:
1458                 pcic_chip_io_free(h, &h->io[rid]);
1459                 break;
1460         case SYS_RES_MEMORY:
1461                 pcic_chip_mem_free(h, &h->mem[rid]);
1462         default:
1463                 break;
1464         }
1465         return bus_generic_release_resource(dev, child, type, rid, r);
1466 }
1467
1468 int
1469 pcic_suspend(device_t dev)
1470 {
1471         /*
1472          * Do nothing for now, maybe in time do what FreeBSD's current
1473          * pccard code does and detach my children.  That's the safest thing
1474          * to do since we don't want to wake up and have different hardware
1475          * in the slots.
1476          */
1477
1478         return 0;
1479 }
1480
1481 int
1482 pcic_resume(device_t dev)
1483 {
1484         /* Need to port pcic_power from newer netbsd versions of this file */
1485
1486         return 0;
1487 }
1488
1489 int
1490 pcic_set_res_flags(device_t dev, device_t child, int type, int rid,
1491     u_int32_t flags)
1492 {
1493         struct pcic_handle *h = pcic_get_handle(dev, child);
1494
1495         DPRINTF(("%p %p %d %d %#x\n", dev, child, type, rid, flags));
1496         if (type != SYS_RES_MEMORY)
1497                 return (EINVAL);
1498         h->mem[rid].kind = PCCARD_MEM_ATTR;
1499         pcic_chip_do_mem_map(h, rid);
1500
1501         return 0;
1502 }
1503
1504 int
1505 pcic_set_memory_offset(device_t dev, device_t child, int rid, u_int32_t offset)
1506 {
1507         return 0;
1508 }
1509
1510 static void
1511 pcic_start_threads(void *arg)
1512 {
1513         struct pcic_handle **walker;
1514         walker = handles;
1515         while (*walker) {
1516                 pcic_create_event_thread(*walker++);
1517         }
1518 }
1519
1520 SYSINIT(pcic, SI_SUB_KTHREAD_IDLE, SI_ORDER_ANY, pcic_start_threads, 0);