2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $
36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
37 * series chips and several workalikes including the following:
39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
41 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
42 * ASIX Electronics AX88140A (www.asix.com.tw)
43 * ASIX Electronics AX88141 (www.asix.com.tw)
44 * ADMtek AL981 (www.admtek.com.tw)
45 * ADMtek AN985 (www.admtek.com.tw)
46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
47 * Accton EN1217 (www.accton.com)
48 * Conexant LANfinity (www.conexant.com)
50 * Datasheets for the 21143 are available at developer.intel.com.
51 * Datasheets for the clone parts can be found at their respective sites.
52 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
53 * The PNIC II is essentially a Macronix 98715A chip; the only difference
54 * worth noting is that its multicast hash table is only 128 bits wide
57 * Written by Bill Paul <wpaul@ee.columbia.edu>
58 * Electrical Engineering Department
59 * Columbia University, New York City
63 * The Intel 21143 is the successor to the DEC 21140. It is basically
64 * the same as the 21140 but with a few new features. The 21143 supports
65 * three kinds of media attachments:
67 * o MII port, for 10Mbps and 100Mbps support and NWAY
68 * autonegotiation provided by an external PHY.
69 * o SYM port, for symbol mode 100Mbps support.
73 * The 100Mbps SYM port and 10baseT port can be used together in
74 * combination with the internal NWAY support to create a 10/100
75 * autosensing configuration.
77 * Note that not all tulip workalikes are handled in this driver: we only
78 * deal with those which are relatively well behaved. The Winbond is
79 * handled separately due to its different register offsets and the
80 * special handling needed for its various bugs. The PNIC is handled
81 * here, but I'm not thrilled about it.
83 * All of the workalike chips use some form of MII transceiver support
84 * with the exception of the Macronix chips, which also have a SYM port.
85 * The ASIX AX88140A is also documented to have a SYM port, but all
86 * the cards I've seen use an MII transceiver, probably because the
87 * AX88140A doesn't support internal NWAY.
90 #include <sys/param.h>
91 #include <sys/systm.h>
92 #include <sys/sockio.h>
94 #include <sys/malloc.h>
95 #include <sys/kernel.h>
96 #include <sys/socket.h>
97 #include <sys/sysctl.h>
100 #include <net/if_arp.h>
101 #include <net/ethernet.h>
102 #include <net/if_dl.h>
103 #include <net/if_media.h>
104 #include <net/if_types.h>
105 #include <net/if_vlan_var.h>
109 #include <vm/vm.h> /* for vtophys */
110 #include <vm/pmap.h> /* for vtophys */
111 #include <machine/clock.h> /* for DELAY */
112 #include <machine/bus_pio.h>
113 #include <machine/bus_memio.h>
114 #include <machine/bus.h>
115 #include <machine/resource.h>
117 #include <sys/rman.h>
119 #include <dev/mii/mii.h>
120 #include <dev/mii/miivar.h>
122 #include <pci/pcireg.h>
123 #include <pci/pcivar.h>
125 #define DC_USEIOSPACE
130 #include <pci/if_dcreg.h>
132 /* "controller miibus0" required. See GENERIC if you get errors here. */
133 #include "miibus_if.h"
136 static const char rcsid[] =
137 "$FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $";
141 * Various supported device vendors/types and their names.
143 static struct dc_type dc_devs[] = {
144 { DC_VENDORID_DEC, DC_DEVICEID_21143,
145 "Intel 21143 10/100BaseTX" },
146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
147 "Davicom DM9009 10/100BaseTX" },
148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
149 "Davicom DM9100 10/100BaseTX" },
150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
151 "Davicom DM9102 10/100BaseTX" },
152 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
153 "Davicom DM9102A 10/100BaseTX" },
154 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
155 "ADMtek AL981 10/100BaseTX" },
156 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
157 "ADMtek AN985 10/100BaseTX" },
158 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
159 "ASIX AX88140A 10/100BaseTX" },
160 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
161 "ASIX AX88141 10/100BaseTX" },
162 { DC_VENDORID_MX, DC_DEVICEID_98713,
163 "Macronix 98713 10/100BaseTX" },
164 { DC_VENDORID_MX, DC_DEVICEID_98713,
165 "Macronix 98713A 10/100BaseTX" },
166 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
167 "Compex RL100-TX 10/100BaseTX" },
168 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
169 "Compex RL100-TX 10/100BaseTX" },
170 { DC_VENDORID_MX, DC_DEVICEID_987x5,
171 "Macronix 98715/98715A 10/100BaseTX" },
172 { DC_VENDORID_MX, DC_DEVICEID_987x5,
173 "Macronix 98715AEC-C 10/100BaseTX" },
174 { DC_VENDORID_MX, DC_DEVICEID_987x5,
175 "Macronix 98725 10/100BaseTX" },
176 { DC_VENDORID_MX, DC_DEVICEID_98727,
177 "Macronix 98727/98732 10/100BaseTX" },
178 { DC_VENDORID_LO, DC_DEVICEID_82C115,
179 "LC82C115 PNIC II 10/100BaseTX" },
180 { DC_VENDORID_LO, DC_DEVICEID_82C168,
181 "82c168 PNIC 10/100BaseTX" },
182 { DC_VENDORID_LO, DC_DEVICEID_82C168,
183 "82c169 PNIC 10/100BaseTX" },
184 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
185 "Accton EN1217 10/100BaseTX" },
186 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
187 "Accton EN2242 MiniPCI 10/100BaseTX" },
188 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
189 "Conexant LANfinity MiniPCI 10/100BaseTX" },
190 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
191 "3Com OfficeConnect 10/100B" },
195 static int dc_probe __P((device_t));
196 static int dc_attach __P((device_t));
197 static int dc_detach __P((device_t));
198 static int dc_suspend __P((device_t));
199 static int dc_resume __P((device_t));
200 static void dc_acpi __P((device_t));
201 static struct dc_type *dc_devtype __P((device_t));
202 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *));
203 static int dc_encap __P((struct dc_softc *, struct mbuf *,
205 static int dc_coal __P((struct dc_softc *, struct mbuf **));
206 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int));
207 static int dc_rx_resync __P((struct dc_softc *));
208 static void dc_rxeof __P((struct dc_softc *));
209 static void dc_txeof __P((struct dc_softc *));
210 static void dc_tick __P((void *));
211 static void dc_tx_underrun __P((struct dc_softc *));
212 static void dc_intr __P((void *));
213 static void dc_start __P((struct ifnet *));
214 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t));
215 static void dc_init __P((void *));
216 static void dc_stop __P((struct dc_softc *));
217 static void dc_watchdog __P((struct ifnet *));
218 static void dc_shutdown __P((device_t));
219 static int dc_ifmedia_upd __P((struct ifnet *));
220 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
222 static void dc_delay __P((struct dc_softc *));
223 static void dc_eeprom_idle __P((struct dc_softc *));
224 static void dc_eeprom_putbyte __P((struct dc_softc *, int));
225 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *));
226 static void dc_eeprom_getword_pnic
227 __P((struct dc_softc *, int, u_int16_t *));
228 static void dc_eeprom_width __P((struct dc_softc *));
229 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int,
232 static void dc_mii_writebit __P((struct dc_softc *, int));
233 static int dc_mii_readbit __P((struct dc_softc *));
234 static void dc_mii_sync __P((struct dc_softc *));
235 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int));
236 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *));
237 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *));
238 static int dc_miibus_readreg __P((device_t, int, int));
239 static int dc_miibus_writereg __P((device_t, int, int, int));
240 static void dc_miibus_statchg __P((device_t));
241 static void dc_miibus_mediainit __P((device_t));
243 static void dc_setcfg __P((struct dc_softc *, int));
244 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t));
245 static u_int32_t dc_crc_be __P((caddr_t));
246 static void dc_setfilt_21143 __P((struct dc_softc *));
247 static void dc_setfilt_asix __P((struct dc_softc *));
248 static void dc_setfilt_admtek __P((struct dc_softc *));
250 static void dc_setfilt __P((struct dc_softc *));
252 static void dc_reset __P((struct dc_softc *));
253 static int dc_list_rx_init __P((struct dc_softc *));
254 static int dc_list_tx_init __P((struct dc_softc *));
256 static void dc_read_srom __P((struct dc_softc *, int));
257 static void dc_parse_21143_srom __P((struct dc_softc *));
258 static void dc_decode_leaf_sia __P((struct dc_softc *,
259 struct dc_eblock_sia *));
260 static void dc_decode_leaf_mii __P((struct dc_softc *,
261 struct dc_eblock_mii *));
262 static void dc_decode_leaf_sym __P((struct dc_softc *,
263 struct dc_eblock_sym *));
264 static void dc_apply_fixup __P((struct dc_softc *, int));
267 #define DC_RES SYS_RES_IOPORT
268 #define DC_RID DC_PCI_CFBIO
270 #define DC_RES SYS_RES_MEMORY
271 #define DC_RID DC_PCI_CFBMA
274 static device_method_t dc_methods[] = {
275 /* Device interface */
276 DEVMETHOD(device_probe, dc_probe),
277 DEVMETHOD(device_attach, dc_attach),
278 DEVMETHOD(device_detach, dc_detach),
279 DEVMETHOD(device_suspend, dc_suspend),
280 DEVMETHOD(device_resume, dc_resume),
281 DEVMETHOD(device_shutdown, dc_shutdown),
284 DEVMETHOD(bus_print_child, bus_generic_print_child),
285 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
288 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
289 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
290 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
291 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
296 static driver_t dc_driver = {
299 sizeof(struct dc_softc)
302 static devclass_t dc_devclass;
305 static int dc_quick=1;
306 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
307 &dc_quick,0,"do not mdevget in dc driver");
310 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
311 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
313 #define DC_SETBIT(sc, reg, x) \
314 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
316 #define DC_CLRBIT(sc, reg, x) \
317 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
319 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
320 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
322 static void dc_delay(sc)
327 for (idx = (300 / 33) + 1; idx > 0; idx--)
328 CSR_READ_4(sc, DC_BUSCTL);
331 static void dc_eeprom_width(sc)
336 /* Force EEPROM to idle state. */
339 /* Enter EEPROM access mode. */
340 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
342 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
344 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
346 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
351 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
353 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
355 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
357 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
361 for (i = 1; i <= 12; i++) {
362 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
364 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
365 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
373 /* Turn off EEPROM access mode. */
381 /* Enter EEPROM access mode. */
382 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
384 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
386 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
388 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
391 /* Turn off EEPROM access mode. */
395 static void dc_eeprom_idle(sc)
400 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
402 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
404 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
406 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
409 for (i = 0; i < 25; i++) {
410 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
412 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
420 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
426 * Send a read command and address to the EEPROM, check for ACK.
428 static void dc_eeprom_putbyte(sc, addr)
434 d = DC_EECMD_READ >> 6;
437 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
439 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
441 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
443 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
448 * Feed in each bit and strobe the clock.
450 for (i = sc->dc_romwidth; i--;) {
451 if (addr & (1 << i)) {
452 SIO_SET(DC_SIO_EE_DATAIN);
454 SIO_CLR(DC_SIO_EE_DATAIN);
457 SIO_SET(DC_SIO_EE_CLK);
459 SIO_CLR(DC_SIO_EE_CLK);
467 * Read a word of data stored in the EEPROM at address 'addr.'
468 * The PNIC 82c168/82c169 has its own non-standard way to read
471 static void dc_eeprom_getword_pnic(sc, addr, dest)
479 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
481 for (i = 0; i < DC_TIMEOUT; i++) {
483 r = CSR_READ_4(sc, DC_SIO);
484 if (!(r & DC_PN_SIOCTL_BUSY)) {
485 *dest = (u_int16_t)(r & 0xFFFF);
494 * Read a word of data stored in the EEPROM at address 'addr.'
496 static void dc_eeprom_getword(sc, addr, dest)
504 /* Force EEPROM to idle state. */
507 /* Enter EEPROM access mode. */
508 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
510 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
512 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
514 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
518 * Send address of word we want to read.
520 dc_eeprom_putbyte(sc, addr);
523 * Start reading bits from EEPROM.
525 for (i = 0x8000; i; i >>= 1) {
526 SIO_SET(DC_SIO_EE_CLK);
528 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
531 SIO_CLR(DC_SIO_EE_CLK);
535 /* Turn off EEPROM access mode. */
544 * Read a sequence of words from the EEPROM.
546 static void dc_read_eeprom(sc, dest, off, cnt, swap)
554 u_int16_t word = 0, *ptr;
556 for (i = 0; i < cnt; i++) {
558 dc_eeprom_getword_pnic(sc, off + i, &word);
560 dc_eeprom_getword(sc, off + i, &word);
561 ptr = (u_int16_t *)(dest + (i * 2));
572 * The following two routines are taken from the Macronix 98713
573 * Application Notes pp.19-21.
576 * Write a bit to the MII bus.
578 static void dc_mii_writebit(sc, bit)
583 CSR_WRITE_4(sc, DC_SIO,
584 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT);
586 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
588 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
589 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
595 * Read a bit from the MII bus.
597 static int dc_mii_readbit(sc)
600 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
601 CSR_READ_4(sc, DC_SIO);
602 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
603 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
604 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
611 * Sync the PHYs by setting data bit and strobing the clock 32 times.
613 static void dc_mii_sync(sc)
618 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
620 for (i = 0; i < 32; i++)
621 dc_mii_writebit(sc, 1);
627 * Clock a series of bits through the MII.
629 static void dc_mii_send(sc, bits, cnt)
636 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
637 dc_mii_writebit(sc, bits & i);
641 * Read an PHY register through the MII.
643 static int dc_mii_readreg(sc, frame)
645 struct dc_mii_frame *frame;
653 * Set up frame for RX.
655 frame->mii_stdelim = DC_MII_STARTDELIM;
656 frame->mii_opcode = DC_MII_READOP;
657 frame->mii_turnaround = 0;
666 * Send command/address info.
668 dc_mii_send(sc, frame->mii_stdelim, 2);
669 dc_mii_send(sc, frame->mii_opcode, 2);
670 dc_mii_send(sc, frame->mii_phyaddr, 5);
671 dc_mii_send(sc, frame->mii_regaddr, 5);
675 dc_mii_writebit(sc, 1);
676 dc_mii_writebit(sc, 0);
680 ack = dc_mii_readbit(sc);
683 * Now try reading data bits. If the ack failed, we still
684 * need to clock through 16 cycles to keep the PHY(s) in sync.
687 for(i = 0; i < 16; i++) {
693 for (i = 0x8000; i; i >>= 1) {
695 if (dc_mii_readbit(sc))
696 frame->mii_data |= i;
702 dc_mii_writebit(sc, 0);
703 dc_mii_writebit(sc, 0);
713 * Write to a PHY register through the MII.
715 static int dc_mii_writereg(sc, frame)
717 struct dc_mii_frame *frame;
724 * Set up frame for TX.
727 frame->mii_stdelim = DC_MII_STARTDELIM;
728 frame->mii_opcode = DC_MII_WRITEOP;
729 frame->mii_turnaround = DC_MII_TURNAROUND;
736 dc_mii_send(sc, frame->mii_stdelim, 2);
737 dc_mii_send(sc, frame->mii_opcode, 2);
738 dc_mii_send(sc, frame->mii_phyaddr, 5);
739 dc_mii_send(sc, frame->mii_regaddr, 5);
740 dc_mii_send(sc, frame->mii_turnaround, 2);
741 dc_mii_send(sc, frame->mii_data, 16);
744 dc_mii_writebit(sc, 0);
745 dc_mii_writebit(sc, 0);
752 static int dc_miibus_readreg(dev, phy, reg)
756 struct dc_mii_frame frame;
758 int i, rval, phy_reg = 0;
760 sc = device_get_softc(dev);
761 bzero((char *)&frame, sizeof(frame));
764 * Note: both the AL981 and AN985 have internal PHYs,
765 * however the AL981 provides direct access to the PHY
766 * registers while the AN985 uses a serial MII interface.
767 * The AN985's MII interface is also buggy in that you
768 * can read from any MII address (0 to 31), but only address 1
769 * behaves normally. To deal with both cases, we pretend
770 * that the PHY is at MII address 1.
772 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
776 * Note: the ukphy probes of the RS7112 report a PHY at
777 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
778 * so we only respond to correct one.
780 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
783 if (sc->dc_pmode != DC_PMODE_MII) {
784 if (phy == (MII_NPHY - 1)) {
788 * Fake something to make the probe
789 * code think there's a PHY here.
791 return(BMSR_MEDIAMASK);
795 return(DC_VENDORID_LO);
796 return(DC_VENDORID_DEC);
800 return(DC_DEVICEID_82C168);
801 return(DC_DEVICEID_21143);
811 if (DC_IS_PNIC(sc)) {
812 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
813 (phy << 23) | (reg << 18));
814 for (i = 0; i < DC_TIMEOUT; i++) {
816 rval = CSR_READ_4(sc, DC_PN_MII);
817 if (!(rval & DC_PN_MII_BUSY)) {
819 return(rval == 0xFFFF ? 0 : rval);
825 if (DC_IS_COMET(sc)) {
828 phy_reg = DC_AL_BMCR;
831 phy_reg = DC_AL_BMSR;
834 phy_reg = DC_AL_VENID;
837 phy_reg = DC_AL_DEVID;
840 phy_reg = DC_AL_ANAR;
843 phy_reg = DC_AL_LPAR;
846 phy_reg = DC_AL_ANER;
849 printf("dc%d: phy_read: bad phy register %x\n",
855 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
862 frame.mii_phyaddr = phy;
863 frame.mii_regaddr = reg;
864 if (sc->dc_type == DC_TYPE_98713) {
865 phy_reg = CSR_READ_4(sc, DC_NETCFG);
866 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
868 dc_mii_readreg(sc, &frame);
869 if (sc->dc_type == DC_TYPE_98713)
870 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
872 return(frame.mii_data);
875 static int dc_miibus_writereg(dev, phy, reg, data)
880 struct dc_mii_frame frame;
883 sc = device_get_softc(dev);
884 bzero((char *)&frame, sizeof(frame));
886 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
889 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
892 if (DC_IS_PNIC(sc)) {
893 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
894 (phy << 23) | (reg << 10) | data);
895 for (i = 0; i < DC_TIMEOUT; i++) {
896 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
902 if (DC_IS_COMET(sc)) {
905 phy_reg = DC_AL_BMCR;
908 phy_reg = DC_AL_BMSR;
911 phy_reg = DC_AL_VENID;
914 phy_reg = DC_AL_DEVID;
917 phy_reg = DC_AL_ANAR;
920 phy_reg = DC_AL_LPAR;
923 phy_reg = DC_AL_ANER;
926 printf("dc%d: phy_write: bad phy register %x\n",
932 CSR_WRITE_4(sc, phy_reg, data);
936 frame.mii_phyaddr = phy;
937 frame.mii_regaddr = reg;
938 frame.mii_data = data;
940 if (sc->dc_type == DC_TYPE_98713) {
941 phy_reg = CSR_READ_4(sc, DC_NETCFG);
942 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
944 dc_mii_writereg(sc, &frame);
945 if (sc->dc_type == DC_TYPE_98713)
946 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
951 static void dc_miibus_statchg(dev)
955 struct mii_data *mii;
958 sc = device_get_softc(dev);
959 if (DC_IS_ADMTEK(sc))
962 mii = device_get_softc(sc->dc_miibus);
963 ifm = &mii->mii_media;
964 if (DC_IS_DAVICOM(sc) &&
965 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
966 dc_setcfg(sc, ifm->ifm_media);
967 sc->dc_if_media = ifm->ifm_media;
969 dc_setcfg(sc, mii->mii_media_active);
970 sc->dc_if_media = mii->mii_media_active;
977 * Special support for DM9102A cards with HomePNA PHYs. Note:
978 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
979 * to be impossible to talk to the management interface of the DM9801
980 * PHY (its MDIO pin is not connected to anything). Consequently,
981 * the driver has to just 'know' about the additional mode and deal
982 * with it itself. *sigh*
984 static void dc_miibus_mediainit(dev)
988 struct mii_data *mii;
992 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
994 sc = device_get_softc(dev);
995 mii = device_get_softc(sc->dc_miibus);
996 ifm = &mii->mii_media;
998 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
999 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL);
1004 #define DC_POLY 0xEDB88320
1005 #define DC_BITS_512 9
1006 #define DC_BITS_128 7
1007 #define DC_BITS_64 6
1009 static u_int32_t dc_crc_le(sc, addr)
1010 struct dc_softc *sc;
1013 u_int32_t idx, bit, data, crc;
1015 /* Compute CRC for the address value. */
1016 crc = 0xFFFFFFFF; /* initial value */
1018 for (idx = 0; idx < 6; idx++) {
1019 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1020 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
1024 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1025 * chips is only 128 bits wide.
1027 if (sc->dc_flags & DC_128BIT_HASH)
1028 return (crc & ((1 << DC_BITS_128) - 1));
1030 /* The hash table on the MX98715BEC is only 64 bits wide. */
1031 if (sc->dc_flags & DC_64BIT_HASH)
1032 return (crc & ((1 << DC_BITS_64) - 1));
1034 return (crc & ((1 << DC_BITS_512) - 1));
1038 * Calculate CRC of a multicast group address, return the lower 6 bits.
1040 static u_int32_t dc_crc_be(addr)
1043 u_int32_t crc, carry;
1047 /* Compute CRC for the address value. */
1048 crc = 0xFFFFFFFF; /* initial value */
1050 for (i = 0; i < 6; i++) {
1052 for (j = 0; j < 8; j++) {
1053 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1057 crc = (crc ^ 0x04c11db6) | carry;
1061 /* return the filter bit position */
1062 return((crc >> 26) & 0x0000003F);
1066 * 21143-style RX filter setup routine. Filter programming is done by
1067 * downloading a special setup frame into the TX engine. 21143, Macronix,
1068 * PNIC, PNIC II and Davicom chips are programmed this way.
1070 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1071 * address (our node address) and a 512-bit hash filter for multicast
1072 * frames. We also sneak the broadcast address into the hash filter since
1075 void dc_setfilt_21143(sc)
1076 struct dc_softc *sc;
1078 struct dc_desc *sframe;
1080 struct ifmultiaddr *ifma;
1084 ifp = &sc->arpcom.ac_if;
1086 i = sc->dc_cdata.dc_tx_prod;
1087 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1088 sc->dc_cdata.dc_tx_cnt++;
1089 sframe = &sc->dc_ldata->dc_tx_list[i];
1090 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1091 bzero((char *)sp, DC_SFRAME_LEN);
1093 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1094 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1095 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1097 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1099 /* If we want promiscuous mode, set the allframes bit. */
1100 if (ifp->if_flags & IFF_PROMISC)
1101 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1103 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1105 if (ifp->if_flags & IFF_ALLMULTI)
1106 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1108 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1110 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1111 ifma = ifma->ifma_link.le_next) {
1112 if (ifma->ifma_addr->sa_family != AF_LINK)
1115 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1116 sp[h >> 4] |= 1 << (h & 0xF);
1119 if (ifp->if_flags & IFF_BROADCAST) {
1120 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr);
1121 sp[h >> 4] |= 1 << (h & 0xF);
1124 /* Set our MAC address */
1125 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1126 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1127 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1129 sframe->dc_status = DC_TXSTAT_OWN;
1130 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1133 * The PNIC takes an exceedingly long time to process its
1134 * setup frame; wait 10ms after posting the setup frame
1135 * before proceeding, just so it has time to swallow its
1145 void dc_setfilt_admtek(sc)
1146 struct dc_softc *sc;
1150 u_int32_t hashes[2] = { 0, 0 };
1151 struct ifmultiaddr *ifma;
1153 ifp = &sc->arpcom.ac_if;
1155 /* Init our MAC address */
1156 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1157 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1159 /* If we want promiscuous mode, set the allframes bit. */
1160 if (ifp->if_flags & IFF_PROMISC)
1161 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1163 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1165 if (ifp->if_flags & IFF_ALLMULTI)
1166 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1168 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1170 /* first, zot all the existing hash bits */
1171 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1172 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1175 * If we're already in promisc or allmulti mode, we
1176 * don't have to bother programming the multicast filter.
1178 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1181 /* now program new ones */
1182 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1183 ifma = ifma->ifma_link.le_next) {
1184 if (ifma->ifma_addr->sa_family != AF_LINK)
1186 if (DC_IS_CENTAUR(sc))
1187 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1189 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1191 hashes[0] |= (1 << h);
1193 hashes[1] |= (1 << (h - 32));
1196 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1197 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1202 void dc_setfilt_asix(sc)
1203 struct dc_softc *sc;
1207 u_int32_t hashes[2] = { 0, 0 };
1208 struct ifmultiaddr *ifma;
1210 ifp = &sc->arpcom.ac_if;
1212 /* Init our MAC address */
1213 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1214 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1215 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1216 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1217 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1218 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1220 /* If we want promiscuous mode, set the allframes bit. */
1221 if (ifp->if_flags & IFF_PROMISC)
1222 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1224 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1226 if (ifp->if_flags & IFF_ALLMULTI)
1227 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1229 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1232 * The ASIX chip has a special bit to enable reception
1233 * of broadcast frames.
1235 if (ifp->if_flags & IFF_BROADCAST)
1236 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1238 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1240 /* first, zot all the existing hash bits */
1241 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1242 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1243 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1244 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1247 * If we're already in promisc or allmulti mode, we
1248 * don't have to bother programming the multicast filter.
1250 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1253 /* now program new ones */
1254 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1255 ifma = ifma->ifma_link.le_next) {
1256 if (ifma->ifma_addr->sa_family != AF_LINK)
1258 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1260 hashes[0] |= (1 << h);
1262 hashes[1] |= (1 << (h - 32));
1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1267 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1268 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1273 static void dc_setfilt(sc)
1274 struct dc_softc *sc;
1276 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1277 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1278 dc_setfilt_21143(sc);
1281 dc_setfilt_asix(sc);
1283 if (DC_IS_ADMTEK(sc))
1284 dc_setfilt_admtek(sc);
1290 * In order to fiddle with the
1291 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
1292 * first have to put the transmit and/or receive logic in the idle state.
1294 static void dc_setcfg(sc, media)
1295 struct dc_softc *sc;
1301 if (IFM_SUBTYPE(media) == IFM_NONE)
1304 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1306 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1308 for (i = 0; i < DC_TIMEOUT; i++) {
1309 isr = CSR_READ_4(sc, DC_ISR);
1310 if (isr & DC_ISR_TX_IDLE ||
1311 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED)
1316 if (i == DC_TIMEOUT)
1317 printf("dc%d: failed to force tx and "
1318 "rx to idle state\n", sc->dc_unit);
1321 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1322 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1323 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1324 if (sc->dc_pmode == DC_PMODE_MII) {
1327 if (DC_IS_INTEL(sc)) {
1328 /* there's a write enable bit here that reads as 1 */
1329 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1330 watchdogreg &= ~DC_WDOG_CTLWREN;
1331 watchdogreg |= DC_WDOG_JABBERDIS;
1332 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1334 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1336 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1337 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1338 if (sc->dc_type == DC_TYPE_98713)
1339 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1340 DC_NETCFG_SCRAMBLER));
1341 if (!DC_IS_DAVICOM(sc))
1342 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1343 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1344 if (DC_IS_INTEL(sc))
1345 dc_apply_fixup(sc, IFM_AUTO);
1347 if (DC_IS_PNIC(sc)) {
1348 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1349 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1350 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1353 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1354 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1355 if (DC_IS_INTEL(sc))
1357 (media & IFM_GMASK) == IFM_FDX ?
1358 IFM_100_TX|IFM_FDX : IFM_100_TX);
1362 if (IFM_SUBTYPE(media) == IFM_10_T) {
1363 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1364 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1365 if (sc->dc_pmode == DC_PMODE_MII) {
1368 /* there's a write enable bit here that reads as 1 */
1369 if (DC_IS_INTEL(sc)) {
1370 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1371 watchdogreg &= ~DC_WDOG_CTLWREN;
1372 watchdogreg |= DC_WDOG_JABBERDIS;
1373 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1375 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1377 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1378 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1379 if (sc->dc_type == DC_TYPE_98713)
1380 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1381 if (!DC_IS_DAVICOM(sc))
1382 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1383 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1384 if (DC_IS_INTEL(sc))
1385 dc_apply_fixup(sc, IFM_AUTO);
1387 if (DC_IS_PNIC(sc)) {
1388 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1389 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1390 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1392 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1393 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1394 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1395 if (DC_IS_INTEL(sc)) {
1396 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1397 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1398 if ((media & IFM_GMASK) == IFM_FDX)
1399 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1401 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1402 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1403 DC_CLRBIT(sc, DC_10BTCTRL,
1404 DC_TCTL_AUTONEGENBL);
1406 (media & IFM_GMASK) == IFM_FDX ?
1407 IFM_10_T|IFM_FDX : IFM_10_T);
1414 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1415 * PHY and we want HomePNA mode, set the portsel bit to turn
1416 * on the external MII port.
1418 if (DC_IS_DAVICOM(sc)) {
1419 if (IFM_SUBTYPE(media) == IFM_homePNA) {
1420 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1423 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1427 if ((media & IFM_GMASK) == IFM_FDX) {
1428 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1429 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1430 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1432 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1433 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1434 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1443 static void dc_reset(sc)
1444 struct dc_softc *sc;
1448 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1450 for (i = 0; i < DC_TIMEOUT; i++) {
1452 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1456 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) {
1458 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1462 if (i == DC_TIMEOUT)
1463 printf("dc%d: reset never completed!\n", sc->dc_unit);
1465 /* Wait a little while for the chip to get its brains in order. */
1468 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1469 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1470 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1473 * Bring the SIA out of reset. In some cases, it looks
1474 * like failing to unreset the SIA soon enough gets it
1475 * into a state where it will never come out of reset
1476 * until we reset the whole chip again.
1478 if (DC_IS_INTEL(sc)) {
1479 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1480 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1481 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1487 static struct dc_type *dc_devtype(dev)
1495 while(t->dc_name != NULL) {
1496 if ((pci_get_vendor(dev) == t->dc_vid) &&
1497 (pci_get_device(dev) == t->dc_did)) {
1498 /* Check the PCI revision */
1499 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1500 if (t->dc_did == DC_DEVICEID_98713 &&
1501 rev >= DC_REVISION_98713A)
1503 if (t->dc_did == DC_DEVICEID_98713_CP &&
1504 rev >= DC_REVISION_98713A)
1506 if (t->dc_did == DC_DEVICEID_987x5 &&
1507 rev >= DC_REVISION_98715AEC_C)
1509 if (t->dc_did == DC_DEVICEID_987x5 &&
1510 rev >= DC_REVISION_98725)
1512 if (t->dc_did == DC_DEVICEID_AX88140A &&
1513 rev >= DC_REVISION_88141)
1515 if (t->dc_did == DC_DEVICEID_82C168 &&
1516 rev >= DC_REVISION_82C169)
1518 if (t->dc_did == DC_DEVICEID_DM9102 &&
1519 rev >= DC_REVISION_DM9102A)
1530 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1531 * IDs against our list and return a device name if we find a match.
1532 * We do a little bit of extra work to identify the exact type of
1533 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1534 * but different revision IDs. The same is true for 98715/98715A
1535 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1536 * cases, the exact chip revision affects driver behavior.
1538 static int dc_probe(dev)
1543 t = dc_devtype(dev);
1546 device_set_desc(dev, t->dc_name);
1553 static void dc_acpi(dev)
1559 unit = device_get_unit(dev);
1561 /* Find the location of the capabilities block */
1562 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF;
1564 r = pci_read_config(dev, cptr, 4) & 0xFF;
1567 r = pci_read_config(dev, cptr + 4, 4);
1568 if (r & DC_PSTATE_D3) {
1569 u_int32_t iobase, membase, irq;
1571 /* Save important PCI config data. */
1572 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1573 membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1574 irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1576 /* Reset the power state. */
1577 printf("dc%d: chip is in D%d power mode "
1578 "-- setting to D0\n", unit, r & DC_PSTATE_D3);
1580 pci_write_config(dev, cptr + 4, r, 4);
1582 /* Restore PCI config data. */
1583 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1584 pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1585 pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1591 static void dc_apply_fixup(sc, media)
1592 struct dc_softc *sc;
1595 struct dc_mediainfo *m;
1603 if (m->dc_media == media)
1611 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1612 reg = (p[0] | (p[1] << 8)) << 16;
1613 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1616 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1617 reg = (p[0] | (p[1] << 8)) << 16;
1618 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1624 static void dc_decode_leaf_sia(sc, l)
1625 struct dc_softc *sc;
1626 struct dc_eblock_sia *l;
1628 struct dc_mediainfo *m;
1630 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1631 bzero(m, sizeof(struct dc_mediainfo));
1632 if (l->dc_sia_code == DC_SIA_CODE_10BT)
1633 m->dc_media = IFM_10_T;
1635 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX)
1636 m->dc_media = IFM_10_T|IFM_FDX;
1638 if (l->dc_sia_code == DC_SIA_CODE_10B2)
1639 m->dc_media = IFM_10_2;
1641 if (l->dc_sia_code == DC_SIA_CODE_10B5)
1642 m->dc_media = IFM_10_5;
1645 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl;
1647 m->dc_next = sc->dc_mi;
1650 sc->dc_pmode = DC_PMODE_SIA;
1655 static void dc_decode_leaf_sym(sc, l)
1656 struct dc_softc *sc;
1657 struct dc_eblock_sym *l;
1659 struct dc_mediainfo *m;
1661 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1662 bzero(m, sizeof(struct dc_mediainfo));
1663 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1664 m->dc_media = IFM_100_TX;
1666 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1667 m->dc_media = IFM_100_TX|IFM_FDX;
1670 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1672 m->dc_next = sc->dc_mi;
1675 sc->dc_pmode = DC_PMODE_SYM;
1680 static void dc_decode_leaf_mii(sc, l)
1681 struct dc_softc *sc;
1682 struct dc_eblock_mii *l;
1685 struct dc_mediainfo *m;
1687 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1688 bzero(m, sizeof(struct dc_mediainfo));
1689 /* We abuse IFM_AUTO to represent MII. */
1690 m->dc_media = IFM_AUTO;
1691 m->dc_gp_len = l->dc_gpr_len;
1694 p += sizeof(struct dc_eblock_mii);
1696 p += 2 * l->dc_gpr_len;
1697 m->dc_reset_len = *p;
1699 m->dc_reset_ptr = p;
1701 m->dc_next = sc->dc_mi;
1707 static void dc_read_srom(sc, bits)
1708 struct dc_softc *sc;
1714 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1715 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1718 static void dc_parse_21143_srom(sc)
1719 struct dc_softc *sc;
1721 struct dc_leaf_hdr *lhdr;
1722 struct dc_eblock_hdr *hdr;
1728 loff = sc->dc_srom[27];
1729 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1732 ptr += sizeof(struct dc_leaf_hdr) - 1;
1734 * Look if we got a MII media block.
1736 for (i = 0; i < lhdr->dc_mcnt; i++) {
1737 hdr = (struct dc_eblock_hdr *)ptr;
1738 if (hdr->dc_type == DC_EBLOCK_MII)
1741 ptr += (hdr->dc_len & 0x7F);
1746 * Do the same thing again. Only use SIA and SYM media
1747 * blocks if no MII media block is available.
1750 ptr += sizeof(struct dc_leaf_hdr) - 1;
1751 for (i = 0; i < lhdr->dc_mcnt; i++) {
1752 hdr = (struct dc_eblock_hdr *)ptr;
1753 switch(hdr->dc_type) {
1755 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1759 dc_decode_leaf_sia(sc,
1760 (struct dc_eblock_sia *)hdr);
1764 dc_decode_leaf_sym(sc,
1765 (struct dc_eblock_sym *)hdr);
1768 /* Don't care. Yet. */
1771 ptr += (hdr->dc_len & 0x7F);
1779 * Attach the interface. Allocate softc structures, do ifmedia
1780 * setup and ethernet/BPF attach.
1782 static int dc_attach(dev)
1786 u_char eaddr[ETHER_ADDR_LEN];
1788 struct dc_softc *sc;
1791 int unit, error = 0, rid, mac_offset;
1795 sc = device_get_softc(dev);
1796 unit = device_get_unit(dev);
1797 bzero(sc, sizeof(struct dc_softc));
1800 * Handle power management nonsense.
1805 * Map control/status registers.
1807 command = pci_read_config(dev, PCIR_COMMAND, 4);
1808 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1809 pci_write_config(dev, PCIR_COMMAND, command, 4);
1810 command = pci_read_config(dev, PCIR_COMMAND, 4);
1812 #ifdef DC_USEIOSPACE
1813 if (!(command & PCIM_CMD_PORTEN)) {
1814 printf("dc%d: failed to enable I/O ports!\n", unit);
1819 if (!(command & PCIM_CMD_MEMEN)) {
1820 printf("dc%d: failed to enable memory mapping!\n", unit);
1827 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid,
1828 0, ~0, 1, RF_ACTIVE);
1830 if (sc->dc_res == NULL) {
1831 printf("dc%d: couldn't map ports/memory\n", unit);
1836 sc->dc_btag = rman_get_bustag(sc->dc_res);
1837 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1839 /* Allocate interrupt */
1841 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1842 RF_SHAREABLE | RF_ACTIVE);
1844 if (sc->dc_irq == NULL) {
1845 printf("dc%d: couldn't map interrupt\n", unit);
1846 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
1851 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET,
1852 dc_intr, sc, &sc->dc_intrhand);
1855 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
1856 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
1857 printf("dc%d: couldn't set up irq\n", unit);
1861 /* Need this info to decide on a chip type. */
1862 sc->dc_info = dc_devtype(dev);
1863 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF;
1865 /* Get the eeprom width, but PNIC has diff eeprom */
1866 if (sc->dc_info->dc_did != DC_DEVICEID_82C168)
1867 dc_eeprom_width(sc);
1869 switch(sc->dc_info->dc_did) {
1870 case DC_DEVICEID_21143:
1871 sc->dc_type = DC_TYPE_21143;
1872 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1873 sc->dc_flags |= DC_REDUCED_MII_POLL;
1874 /* Save EEPROM contents so we can parse them later. */
1875 dc_read_srom(sc, sc->dc_romwidth);
1877 case DC_DEVICEID_DM9009:
1878 case DC_DEVICEID_DM9100:
1879 case DC_DEVICEID_DM9102:
1880 sc->dc_type = DC_TYPE_DM9102;
1881 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS;
1882 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD;
1883 sc->dc_pmode = DC_PMODE_MII;
1884 /* Increase the latency timer value. */
1885 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1886 command &= 0xFFFF00FF;
1887 command |= 0x00008000;
1888 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1890 case DC_DEVICEID_AL981:
1891 sc->dc_type = DC_TYPE_AL981;
1892 sc->dc_flags |= DC_TX_USE_TX_INTR;
1893 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1894 sc->dc_pmode = DC_PMODE_MII;
1895 dc_read_srom(sc, sc->dc_romwidth);
1897 case DC_DEVICEID_AN985:
1898 case DC_DEVICEID_EN2242:
1899 case DC_DEVICEID_3CSOHOB:
1900 sc->dc_type = DC_TYPE_AN985;
1901 sc->dc_flags |= DC_64BIT_HASH;
1902 sc->dc_flags |= DC_TX_USE_TX_INTR;
1903 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1904 sc->dc_pmode = DC_PMODE_MII;
1905 dc_read_srom(sc, sc->dc_romwidth);
1907 case DC_DEVICEID_98713:
1908 case DC_DEVICEID_98713_CP:
1909 if (revision < DC_REVISION_98713A) {
1910 sc->dc_type = DC_TYPE_98713;
1912 if (revision >= DC_REVISION_98713A) {
1913 sc->dc_type = DC_TYPE_98713A;
1914 sc->dc_flags |= DC_21143_NWAY;
1916 sc->dc_flags |= DC_REDUCED_MII_POLL;
1917 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1919 case DC_DEVICEID_987x5:
1920 case DC_DEVICEID_EN1217:
1922 * Macronix MX98715AEC-C/D/E parts have only a
1923 * 128-bit hash table. We need to deal with these
1924 * in the same manner as the PNIC II so that we
1925 * get the right number of bits out of the
1928 if (revision >= DC_REVISION_98715AEC_C &&
1929 revision < DC_REVISION_98725)
1930 sc->dc_flags |= DC_128BIT_HASH;
1931 sc->dc_type = DC_TYPE_987x5;
1932 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1933 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1935 case DC_DEVICEID_98727:
1936 sc->dc_type = DC_TYPE_987x5;
1937 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1938 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1940 case DC_DEVICEID_82C115:
1941 sc->dc_type = DC_TYPE_PNICII;
1942 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH;
1943 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1945 case DC_DEVICEID_82C168:
1946 sc->dc_type = DC_TYPE_PNIC;
1947 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS;
1948 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1949 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
1950 if (revision < DC_REVISION_82C169)
1951 sc->dc_pmode = DC_PMODE_SYM;
1953 case DC_DEVICEID_AX88140A:
1954 sc->dc_type = DC_TYPE_ASIX;
1955 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG;
1956 sc->dc_flags |= DC_REDUCED_MII_POLL;
1957 sc->dc_pmode = DC_PMODE_MII;
1959 case DC_DEVICEID_RS7112:
1960 sc->dc_type = DC_TYPE_CONEXANT;
1961 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1962 sc->dc_flags |= DC_REDUCED_MII_POLL;
1963 sc->dc_pmode = DC_PMODE_MII;
1964 dc_read_srom(sc, sc->dc_romwidth);
1967 printf("dc%d: unknown device: %x\n", sc->dc_unit,
1968 sc->dc_info->dc_did);
1972 /* Save the cache line size. */
1973 if (DC_IS_DAVICOM(sc))
1974 sc->dc_cachesize = 0;
1976 sc->dc_cachesize = pci_read_config(dev,
1977 DC_PCI_CFLT, 4) & 0xFF;
1979 /* Reset the adapter. */
1982 /* Take 21143 out of snooze mode */
1983 if (DC_IS_INTEL(sc)) {
1984 command = pci_read_config(dev, DC_PCI_CFDD, 4);
1985 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
1986 pci_write_config(dev, DC_PCI_CFDD, command, 4);
1990 * Try to learn something about the supported media.
1991 * We know that ASIX and ADMtek and Davicom devices
1992 * will *always* be using MII media, so that's a no-brainer.
1993 * The tricky ones are the Macronix/PNIC II and the
1996 if (DC_IS_INTEL(sc))
1997 dc_parse_21143_srom(sc);
1998 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
1999 if (sc->dc_type == DC_TYPE_98713)
2000 sc->dc_pmode = DC_PMODE_MII;
2002 sc->dc_pmode = DC_PMODE_SYM;
2003 } else if (!sc->dc_pmode)
2004 sc->dc_pmode = DC_PMODE_MII;
2007 * Get station address from the EEPROM.
2009 switch(sc->dc_type) {
2011 case DC_TYPE_98713A:
2013 case DC_TYPE_PNICII:
2014 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2015 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2016 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2019 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2021 case DC_TYPE_DM9102:
2024 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2028 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr,
2030 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0);
2032 case DC_TYPE_CONEXANT:
2033 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2036 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2041 * A 21143 or clone chip was detected. Inform the world.
2043 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":");
2046 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
2048 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF,
2049 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
2051 if (sc->dc_ldata == NULL) {
2052 printf("dc%d: no memory for list buffers!\n", unit);
2053 if (sc->dc_pnic_rx_buf != NULL)
2054 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2055 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2056 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2057 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2062 bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2064 ifp = &sc->arpcom.ac_if;
2066 ifp->if_unit = unit;
2067 ifp->if_name = "dc";
2068 ifp->if_mtu = ETHERMTU;
2069 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2070 ifp->if_ioctl = dc_ioctl;
2071 ifp->if_output = ether_output;
2072 ifp->if_start = dc_start;
2073 ifp->if_watchdog = dc_watchdog;
2074 ifp->if_init = dc_init;
2075 ifp->if_baudrate = 10000000;
2076 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1;
2079 * Do MII setup. If this is a 21143, check for a PHY on the
2080 * MII bus after applying any necessary fixups to twiddle the
2081 * GPIO bits. If we don't end up finding a PHY, restore the
2082 * old selection (SIA only or SIA/SYM) and attach the dcphy
2085 if (DC_IS_INTEL(sc)) {
2086 dc_apply_fixup(sc, IFM_AUTO);
2088 sc->dc_pmode = DC_PMODE_MII;
2091 error = mii_phy_probe(dev, &sc->dc_miibus,
2092 dc_ifmedia_upd, dc_ifmedia_sts);
2094 if (error && DC_IS_INTEL(sc)) {
2096 if (sc->dc_pmode != DC_PMODE_SIA)
2097 sc->dc_pmode = DC_PMODE_SYM;
2098 sc->dc_flags |= DC_21143_NWAY;
2099 mii_phy_probe(dev, &sc->dc_miibus,
2100 dc_ifmedia_upd, dc_ifmedia_sts);
2102 * For non-MII cards, we need to have the 21143
2103 * drive the LEDs. Except there are some systems
2104 * like the NEC VersaPro NoteBook PC which have no
2105 * LEDs, and twiddling these bits has adverse effects
2106 * on them. (I.e. you suddenly can't get a link.)
2108 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2109 sc->dc_flags |= DC_TULIP_LEDS;
2114 printf("dc%d: MII without any PHY!\n", sc->dc_unit);
2115 contigfree(sc->dc_ldata, sizeof(struct dc_list_data),
2117 if (sc->dc_pnic_rx_buf != NULL)
2118 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2119 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2120 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2121 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2127 * Call MI attach routine.
2129 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
2130 callout_handle_init(&sc->dc_stat_ch);
2132 if (DC_IS_ADMTEK(sc)) {
2134 * Set automatic TX underrun recovery for the ADMtek chips
2136 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2140 * Tell the upper layer(s) we support long frames.
2142 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2145 sc->dc_srm_media = 0;
2147 /* Remember the SRM console media setting */
2148 if (DC_IS_INTEL(sc)) {
2149 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2150 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
2151 switch ((command >> 8) & 0xff) {
2153 sc->dc_srm_media = IFM_10_T;
2156 sc->dc_srm_media = IFM_10_T | IFM_FDX;
2159 sc->dc_srm_media = IFM_100_TX;
2162 sc->dc_srm_media = IFM_100_TX | IFM_FDX;
2165 if (sc->dc_srm_media)
2166 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER;
2177 static int dc_detach(dev)
2180 struct dc_softc *sc;
2183 struct dc_mediainfo *m;
2187 sc = device_get_softc(dev);
2188 ifp = &sc->arpcom.ac_if;
2191 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
2193 bus_generic_detach(dev);
2194 device_delete_child(dev, sc->dc_miibus);
2196 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2197 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2198 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2200 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2201 if (sc->dc_pnic_rx_buf != NULL)
2202 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2204 while(sc->dc_mi != NULL) {
2205 m = sc->dc_mi->dc_next;
2206 free(sc->dc_mi, M_DEVBUF);
2209 free(sc->dc_srom, M_DEVBUF);
2217 * Initialize the transmit descriptors.
2219 static int dc_list_tx_init(sc)
2220 struct dc_softc *sc;
2222 struct dc_chain_data *cd;
2223 struct dc_list_data *ld;
2228 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2229 if (i == (DC_TX_LIST_CNT - 1)) {
2230 ld->dc_tx_list[i].dc_next =
2231 vtophys(&ld->dc_tx_list[0]);
2233 ld->dc_tx_list[i].dc_next =
2234 vtophys(&ld->dc_tx_list[i + 1]);
2236 cd->dc_tx_chain[i] = NULL;
2237 ld->dc_tx_list[i].dc_data = 0;
2238 ld->dc_tx_list[i].dc_ctl = 0;
2241 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2248 * Initialize the RX descriptors and allocate mbufs for them. Note that
2249 * we arrange the descriptors in a closed ring, so that the last descriptor
2250 * points back to the first.
2252 static int dc_list_rx_init(sc)
2253 struct dc_softc *sc;
2255 struct dc_chain_data *cd;
2256 struct dc_list_data *ld;
2262 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2263 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2265 if (i == (DC_RX_LIST_CNT - 1)) {
2266 ld->dc_rx_list[i].dc_next =
2267 vtophys(&ld->dc_rx_list[0]);
2269 ld->dc_rx_list[i].dc_next =
2270 vtophys(&ld->dc_rx_list[i + 1]);
2280 * Initialize an RX descriptor and attach an MBUF cluster.
2282 static int dc_newbuf(sc, i, m)
2283 struct dc_softc *sc;
2287 struct mbuf *m_new = NULL;
2290 c = &sc->dc_ldata->dc_rx_list[i];
2293 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2297 MCLGET(m_new, M_DONTWAIT);
2298 if (!(m_new->m_flags & M_EXT)) {
2302 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2305 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2306 m_new->m_data = m_new->m_ext.ext_buf;
2309 m_adj(m_new, sizeof(u_int64_t));
2312 * If this is a PNIC chip, zero the buffer. This is part
2313 * of the workaround for the receive bug in the 82c168 and
2316 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2317 bzero((char *)mtod(m_new, char *), m_new->m_len);
2319 sc->dc_cdata.dc_rx_chain[i] = m_new;
2320 c->dc_data = vtophys(mtod(m_new, caddr_t));
2321 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN;
2322 c->dc_status = DC_RXSTAT_OWN;
2329 * The PNIC chip has a terrible bug in it that manifests itself during
2330 * periods of heavy activity. The exact mode of failure if difficult to
2331 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2332 * will happen on slow machines. The bug is that sometimes instead of
2333 * uploading one complete frame during reception, it uploads what looks
2334 * like the entire contents of its FIFO memory. The frame we want is at
2335 * the end of the whole mess, but we never know exactly how much data has
2336 * been uploaded, so salvaging the frame is hard.
2338 * There is only one way to do it reliably, and it's disgusting.
2339 * Here's what we know:
2341 * - We know there will always be somewhere between one and three extra
2342 * descriptors uploaded.
2344 * - We know the desired received frame will always be at the end of the
2345 * total data upload.
2347 * - We know the size of the desired received frame because it will be
2348 * provided in the length field of the status word in the last descriptor.
2350 * Here's what we do:
2352 * - When we allocate buffers for the receive ring, we bzero() them.
2353 * This means that we know that the buffer contents should be all
2354 * zeros, except for data uploaded by the chip.
2356 * - We also force the PNIC chip to upload frames that include the
2357 * ethernet CRC at the end.
2359 * - We gather all of the bogus frame data into a single buffer.
2361 * - We then position a pointer at the end of this buffer and scan
2362 * backwards until we encounter the first non-zero byte of data.
2363 * This is the end of the received frame. We know we will encounter
2364 * some data at the end of the frame because the CRC will always be
2365 * there, so even if the sender transmits a packet of all zeros,
2366 * we won't be fooled.
2368 * - We know the size of the actual received frame, so we subtract
2369 * that value from the current pointer location. This brings us
2370 * to the start of the actual received packet.
2372 * - We copy this into an mbuf and pass it on, along with the actual
2375 * The performance hit is tremendous, but it beats dropping frames all
2379 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG)
2380 static void dc_pnic_rx_bug_war(sc, idx)
2381 struct dc_softc *sc;
2384 struct dc_desc *cur_rx;
2385 struct dc_desc *c = NULL;
2386 struct mbuf *m = NULL;
2389 u_int32_t rxstat = 0;
2391 i = sc->dc_pnic_rx_bug_save;
2392 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2393 ptr = sc->dc_pnic_rx_buf;
2394 bzero(ptr, DC_RXLEN * 5);
2396 /* Copy all the bytes from the bogus buffers. */
2398 c = &sc->dc_ldata->dc_rx_list[i];
2399 rxstat = c->dc_status;
2400 m = sc->dc_cdata.dc_rx_chain[i];
2401 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2403 /* If this is the last buffer, break out. */
2404 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2406 dc_newbuf(sc, i, m);
2407 DC_INC(i, DC_RX_LIST_CNT);
2410 /* Find the length of the actual receive frame. */
2411 total_len = DC_RXBYTES(rxstat);
2413 /* Scan backwards until we hit a non-zero byte. */
2418 if ((uintptr_t)(ptr) & 0x3)
2421 /* Now find the start of the frame. */
2423 if (ptr < sc->dc_pnic_rx_buf)
2424 ptr = sc->dc_pnic_rx_buf;
2427 * Now copy the salvaged frame to the last mbuf and fake up
2428 * the status word to make it look like a successful
2431 dc_newbuf(sc, i, m);
2432 bcopy(ptr, mtod(m, char *), total_len);
2433 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG;
2439 * This routine searches the RX ring for dirty descriptors in the
2440 * event that the rxeof routine falls out of sync with the chip's
2441 * current descriptor pointer. This may happen sometimes as a result
2442 * of a "no RX buffer available" condition that happens when the chip
2443 * consumes all of the RX buffers before the driver has a chance to
2444 * process the RX ring. This routine may need to be called more than
2445 * once to bring the driver back in sync with the chip, however we
2446 * should still be getting RX DONE interrupts to drive the search
2447 * for new packets in the RX ring, so we should catch up eventually.
2449 static int dc_rx_resync(sc)
2450 struct dc_softc *sc;
2453 struct dc_desc *cur_rx;
2455 pos = sc->dc_cdata.dc_rx_prod;
2457 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2458 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2459 if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2461 DC_INC(pos, DC_RX_LIST_CNT);
2464 /* If the ring really is empty, then just return. */
2465 if (i == DC_RX_LIST_CNT)
2468 /* We've fallen behing the chip: catch it. */
2469 sc->dc_cdata.dc_rx_prod = pos;
2475 * A frame has been uploaded: pass the resulting mbuf chain up to
2476 * the higher level protocols.
2478 static void dc_rxeof(sc)
2479 struct dc_softc *sc;
2481 struct ether_header *eh;
2484 struct dc_desc *cur_rx;
2485 int i, total_len = 0;
2488 ifp = &sc->arpcom.ac_if;
2489 i = sc->dc_cdata.dc_rx_prod;
2491 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2493 #ifdef DEVICE_POLLING
2494 if (ifp->if_ipending & IFF_POLLING) {
2495 if (sc->rxcycles <= 0)
2499 #endif /* DEVICE_POLLING */
2500 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2501 rxstat = cur_rx->dc_status;
2502 m = sc->dc_cdata.dc_rx_chain[i];
2503 total_len = DC_RXBYTES(rxstat);
2505 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2506 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2507 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2508 sc->dc_pnic_rx_bug_save = i;
2509 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2510 DC_INC(i, DC_RX_LIST_CNT);
2513 dc_pnic_rx_bug_war(sc, i);
2514 rxstat = cur_rx->dc_status;
2515 total_len = DC_RXBYTES(rxstat);
2519 sc->dc_cdata.dc_rx_chain[i] = NULL;
2522 * If an error occurs, update stats, clear the
2523 * status word and leave the mbuf cluster in place:
2524 * it should simply get re-used next time this descriptor
2525 * comes up in the ring. However, don't report long
2526 * frames as errors since they could be vlans
2528 if ((rxstat & DC_RXSTAT_RXERR)){
2529 if (!(rxstat & DC_RXSTAT_GIANT) ||
2530 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2531 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2532 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2534 if (rxstat & DC_RXSTAT_COLLSEEN)
2535 ifp->if_collisions++;
2536 dc_newbuf(sc, i, m);
2537 if (rxstat & DC_RXSTAT_CRCERR) {
2538 DC_INC(i, DC_RX_LIST_CNT);
2547 /* No errors; receive the packet. */
2548 total_len -= ETHER_CRC_LEN;
2552 * On the x86 we do not have alignment problems, so try to
2553 * allocate a new buffer for the receive ring, and pass up
2554 * the one where the packet is already, saving the expensive
2555 * copy done in m_devget().
2556 * If we are on an architecture with alignment problems, or
2557 * if the allocation fails, then use m_devget and leave the
2558 * existing buffer in the receive ring.
2560 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2561 m->m_pkthdr.rcvif = ifp;
2562 m->m_pkthdr.len = m->m_len = total_len;
2563 DC_INC(i, DC_RX_LIST_CNT);
2569 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2570 total_len + ETHER_ALIGN, 0, ifp, NULL);
2571 dc_newbuf(sc, i, m);
2572 DC_INC(i, DC_RX_LIST_CNT);
2577 m_adj(m0, ETHER_ALIGN);
2582 eh = mtod(m, struct ether_header *);
2584 /* Remove header from mbuf and pass it on. */
2585 m_adj(m, sizeof(struct ether_header));
2586 ether_input(ifp, eh, m);
2589 sc->dc_cdata.dc_rx_prod = i;
2593 * A frame was downloaded to the chip. It's safe for us to clean up
2599 struct dc_softc *sc;
2601 struct dc_desc *cur_tx = NULL;
2605 ifp = &sc->arpcom.ac_if;
2608 * Go through our tx list and free mbufs for those
2609 * frames that have been transmitted.
2611 idx = sc->dc_cdata.dc_tx_cons;
2612 while(idx != sc->dc_cdata.dc_tx_prod) {
2615 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2616 txstat = cur_tx->dc_status;
2618 if (txstat & DC_TXSTAT_OWN)
2621 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) ||
2622 cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2623 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2625 * Yes, the PNIC is so brain damaged
2626 * that it will sometimes generate a TX
2627 * underrun error while DMAing the RX
2628 * filter setup frame. If we detect this,
2629 * we have to send the setup frame again,
2630 * or else the filter won't be programmed
2633 if (DC_IS_PNIC(sc)) {
2634 if (txstat & DC_TXSTAT_ERRSUM)
2637 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2639 sc->dc_cdata.dc_tx_cnt--;
2640 DC_INC(idx, DC_TX_LIST_CNT);
2644 if (DC_IS_CONEXANT(sc)) {
2646 * For some reason Conexant chips like
2647 * setting the CARRLOST flag even when
2648 * the carrier is there. In CURRENT we
2649 * have the same problem for Xircom
2652 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2653 sc->dc_pmode == DC_PMODE_MII &&
2654 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2655 DC_TXSTAT_NOCARRIER)))
2656 txstat &= ~DC_TXSTAT_ERRSUM;
2658 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2659 sc->dc_pmode == DC_PMODE_MII &&
2660 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2661 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST)))
2662 txstat &= ~DC_TXSTAT_ERRSUM;
2665 if (txstat & DC_TXSTAT_ERRSUM) {
2667 if (txstat & DC_TXSTAT_EXCESSCOLL)
2668 ifp->if_collisions++;
2669 if (txstat & DC_TXSTAT_LATECOLL)
2670 ifp->if_collisions++;
2671 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2677 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2680 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2681 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2682 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2685 sc->dc_cdata.dc_tx_cnt--;
2686 DC_INC(idx, DC_TX_LIST_CNT);
2689 if (idx != sc->dc_cdata.dc_tx_cons) {
2690 /* some buffers have been freed */
2691 sc->dc_cdata.dc_tx_cons = idx;
2692 ifp->if_flags &= ~IFF_OACTIVE;
2694 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2699 static void dc_tick(xsc)
2702 struct dc_softc *sc;
2703 struct mii_data *mii;
2711 ifp = &sc->arpcom.ac_if;
2712 mii = device_get_softc(sc->dc_miibus);
2714 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2715 if (sc->dc_flags & DC_21143_NWAY) {
2716 r = CSR_READ_4(sc, DC_10BTSTAT);
2717 if (IFM_SUBTYPE(mii->mii_media_active) ==
2718 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2722 if (IFM_SUBTYPE(mii->mii_media_active) ==
2723 IFM_10_T && (r & DC_TSTAT_LS10)) {
2727 if (sc->dc_link == 0)
2730 r = CSR_READ_4(sc, DC_ISR);
2731 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2732 sc->dc_cdata.dc_tx_cnt == 0)
2734 if (!(mii->mii_media_status & IFM_ACTIVE))
2741 * When the init routine completes, we expect to be able to send
2742 * packets right away, and in fact the network code will send a
2743 * gratuitous ARP the moment the init routine marks the interface
2744 * as running. However, even though the MAC may have been initialized,
2745 * there may be a delay of a few seconds before the PHY completes
2746 * autonegotiation and the link is brought up. Any transmissions
2747 * made during that delay will be lost. Dealing with this is tricky:
2748 * we can't just pause in the init routine while waiting for the
2749 * PHY to come ready since that would bring the whole system to
2750 * a screeching halt for several seconds.
2752 * What we do here is prevent the TX start routine from sending
2753 * any packets until a link has been established. After the
2754 * interface has been initialized, the tick routine will poll
2755 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2756 * that time, packets will stay in the send queue, and once the
2757 * link comes up, they will be flushed out to the wire.
2761 if (mii->mii_media_status & IFM_ACTIVE &&
2762 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2764 if (ifp->if_snd.ifq_head != NULL)
2769 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2770 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
2772 sc->dc_stat_ch = timeout(dc_tick, sc, hz);
2780 * A transmit underrun has occurred. Back off the transmit threshold,
2781 * or switch to store and forward mode if we have to.
2783 static void dc_tx_underrun(sc)
2784 struct dc_softc *sc;
2789 if (DC_IS_DAVICOM(sc))
2792 if (DC_IS_INTEL(sc)) {
2794 * The real 21143 requires that the transmitter be idle
2795 * in order to change the transmit threshold or store
2796 * and forward state.
2798 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2800 for (i = 0; i < DC_TIMEOUT; i++) {
2801 isr = CSR_READ_4(sc, DC_ISR);
2802 if (isr & DC_ISR_TX_IDLE)
2806 if (i == DC_TIMEOUT) {
2807 printf("dc%d: failed to force tx to idle state\n",
2813 printf("dc%d: TX underrun -- ", sc->dc_unit);
2814 sc->dc_txthresh += DC_TXTHRESH_INC;
2815 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2816 printf("using store and forward mode\n");
2817 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2819 printf("increasing TX threshold\n");
2820 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2821 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2824 if (DC_IS_INTEL(sc))
2825 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2830 #ifdef DEVICE_POLLING
2831 static poll_handler_t dc_poll;
2834 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2836 struct dc_softc *sc = ifp->if_softc;
2838 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
2839 /* Re-enable interrupts. */
2840 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2843 sc->rxcycles = count;
2846 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE))
2849 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2852 status = CSR_READ_4(sc, DC_ISR);
2853 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF|
2854 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN|
2858 /* ack what we have */
2859 CSR_WRITE_4(sc, DC_ISR, status);
2861 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) {
2862 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
2863 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
2865 if (dc_rx_resync(sc))
2868 /* restart transmit unit if necessary */
2869 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
2870 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2872 if (status & DC_ISR_TX_UNDERRUN)
2875 if (status & DC_ISR_BUS_ERR) {
2876 printf("dc_poll: dc%d bus error\n", sc->dc_unit);
2882 #endif /* DEVICE_POLLING */
2884 static void dc_intr(arg)
2887 struct dc_softc *sc;
2893 if (sc->suspended) {
2897 ifp = &sc->arpcom.ac_if;
2899 #ifdef DEVICE_POLLING
2900 if (ifp->if_ipending & IFF_POLLING)
2902 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */
2903 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2906 #endif /* DEVICE_POLLING */
2908 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
2911 /* Suppress unwanted interrupts */
2912 if (!(ifp->if_flags & IFF_UP)) {
2913 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
2918 /* Disable interrupts. */
2919 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2921 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) {
2923 CSR_WRITE_4(sc, DC_ISR, status);
2925 if (status & DC_ISR_RX_OK) {
2927 curpkts = ifp->if_ipackets;
2929 if (curpkts == ifp->if_ipackets) {
2930 while(dc_rx_resync(sc))
2935 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF))
2938 if (status & DC_ISR_TX_IDLE) {
2940 if (sc->dc_cdata.dc_tx_cnt) {
2941 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2942 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2946 if (status & DC_ISR_TX_UNDERRUN)
2949 if ((status & DC_ISR_RX_WATDOGTIMEO)
2950 || (status & DC_ISR_RX_NOBUF)) {
2952 curpkts = ifp->if_ipackets;
2954 if (curpkts == ifp->if_ipackets) {
2955 while(dc_rx_resync(sc))
2960 if (status & DC_ISR_BUS_ERR) {
2966 /* Re-enable interrupts. */
2967 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2969 if (ifp->if_snd.ifq_head != NULL)
2976 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2977 * pointers to the fragment pointers.
2979 static int dc_encap(sc, m_head, txidx)
2980 struct dc_softc *sc;
2981 struct mbuf *m_head;
2984 struct dc_desc *f = NULL;
2986 int frag, cur, cnt = 0;
2989 * Start packing the mbufs in this chain into
2990 * the fragment pointers. Stop when we run out
2991 * of fragments or hit the end of the mbuf chain.
2994 cur = frag = *txidx;
2996 for (m = m_head; m != NULL; m = m->m_next) {
2997 if (m->m_len != 0) {
2998 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
2999 if (*txidx != sc->dc_cdata.dc_tx_prod &&
3000 frag == (DC_TX_LIST_CNT - 1))
3003 if ((DC_TX_LIST_CNT -
3004 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
3007 f = &sc->dc_ldata->dc_tx_list[frag];
3008 f->dc_ctl = DC_TXCTL_TLINK | m->m_len;
3011 f->dc_ctl |= DC_TXCTL_FIRSTFRAG;
3013 f->dc_status = DC_TXSTAT_OWN;
3014 f->dc_data = vtophys(mtod(m, vm_offset_t));
3016 DC_INC(frag, DC_TX_LIST_CNT);
3024 sc->dc_cdata.dc_tx_cnt += cnt;
3025 sc->dc_cdata.dc_tx_chain[cur] = m_head;
3026 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG;
3027 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3028 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT;
3029 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3030 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3031 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3032 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3033 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3040 * Coalesce an mbuf chain into a single mbuf cluster buffer.
3041 * Needed for some really badly behaved chips that just can't
3042 * do scatter/gather correctly.
3044 static int dc_coal(sc, m_head)
3045 struct dc_softc *sc;
3046 struct mbuf **m_head;
3048 struct mbuf *m_new, *m;
3051 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
3054 if (m->m_pkthdr.len > MHLEN) {
3055 MCLGET(m_new, M_DONTWAIT);
3056 if (!(m_new->m_flags & M_EXT)) {
3061 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t));
3062 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len;
3070 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3071 * to the mbuf data regions directly in the transmit lists. We also save a
3072 * copy of the pointers since the transmit list fragment pointers are
3073 * physical addresses.
3076 static void dc_start(ifp)
3079 struct dc_softc *sc;
3080 struct mbuf *m_head = NULL;
3085 if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
3088 if (ifp->if_flags & IFF_OACTIVE)
3091 idx = sc->dc_cdata.dc_tx_prod;
3093 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3094 IF_DEQUEUE(&ifp->if_snd, m_head);
3098 if (sc->dc_flags & DC_TX_COALESCE &&
3099 m_head->m_next != NULL) {
3100 /* only coalesce if have >1 mbufs */
3101 if (dc_coal(sc, &m_head)) {
3102 IF_PREPEND(&ifp->if_snd, m_head);
3103 ifp->if_flags |= IFF_OACTIVE;
3108 if (dc_encap(sc, m_head, &idx)) {
3109 IF_PREPEND(&ifp->if_snd, m_head);
3110 ifp->if_flags |= IFF_OACTIVE;
3115 * If there's a BPF listener, bounce a copy of this frame
3119 bpf_mtap(ifp, m_head);
3121 if (sc->dc_flags & DC_TX_ONE) {
3122 ifp->if_flags |= IFF_OACTIVE;
3128 sc->dc_cdata.dc_tx_prod = idx;
3129 if (!(sc->dc_flags & DC_TX_POLL))
3130 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3133 * Set a timeout in case the chip goes out to lunch.
3140 static void dc_init(xsc)
3143 struct dc_softc *sc = xsc;
3144 struct ifnet *ifp = &sc->arpcom.ac_if;
3145 struct mii_data *mii;
3150 mii = device_get_softc(sc->dc_miibus);
3153 * Cancel pending I/O and free all RX/TX buffers.
3159 * Set cache alignment and burst length.
3161 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3162 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3164 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
3166 * Evenly share the bus between receive and transmit process.
3168 if (DC_IS_INTEL(sc))
3169 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3170 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3171 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3173 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3175 if (sc->dc_flags & DC_TX_POLL)
3176 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3177 switch(sc->dc_cachesize) {
3179 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3182 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3185 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3189 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3193 if (sc->dc_flags & DC_TX_STORENFWD)
3194 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3196 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3197 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3199 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3200 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3204 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3205 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3207 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3209 * The app notes for the 98713 and 98715A say that
3210 * in order to have the chips operate properly, a magic
3211 * number must be written to CSR16. Macronix does not
3212 * document the meaning of these bits so there's no way
3213 * to know exactly what they do. The 98713 has a magic
3214 * number all its own; the rest all use a different one.
3216 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3217 if (sc->dc_type == DC_TYPE_98713)
3218 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3220 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3223 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3224 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3226 /* Init circular RX list. */
3227 if (dc_list_rx_init(sc) == ENOBUFS) {
3228 printf("dc%d: initialization failed: no "
3229 "memory for rx buffers\n", sc->dc_unit);
3236 * Init tx descriptors.
3238 dc_list_tx_init(sc);
3241 * Load the address of the RX list.
3243 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3244 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3247 * Enable interrupts.
3249 #ifdef DEVICE_POLLING
3251 * ... but only if we are not polling, and make sure they are off in
3252 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3255 if (ifp->if_ipending & IFF_POLLING)
3256 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3259 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3260 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3262 /* Enable transmitter. */
3263 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3266 * If this is an Intel 21143 and we're not using the
3267 * MII port, program the LED control pins so we get
3268 * link and activity indications.
3270 if (sc->dc_flags & DC_TULIP_LEDS) {
3271 CSR_WRITE_4(sc, DC_WATCHDOG,
3272 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY);
3273 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3277 * Load the RX/multicast filter. We do this sort of late
3278 * because the filter programming scheme on the 21143 and
3279 * some clones requires DMAing a setup frame via the TX
3280 * engine, and we need the transmitter enabled for that.
3284 /* Enable receiver. */
3285 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3286 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3289 dc_setcfg(sc, sc->dc_if_media);
3291 ifp->if_flags |= IFF_RUNNING;
3292 ifp->if_flags &= ~IFF_OACTIVE;
3296 /* Don't start the ticker if this is a homePNA link. */
3297 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA)
3300 if (sc->dc_flags & DC_21143_NWAY)
3301 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
3303 sc->dc_stat_ch = timeout(dc_tick, sc, hz);
3307 if(sc->dc_srm_media) {
3310 ifr.ifr_media = sc->dc_srm_media;
3311 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3312 sc->dc_srm_media = 0;
3319 * Set media options.
3321 static int dc_ifmedia_upd(ifp)
3324 struct dc_softc *sc;
3325 struct mii_data *mii;
3326 struct ifmedia *ifm;
3329 mii = device_get_softc(sc->dc_miibus);
3331 ifm = &mii->mii_media;
3333 if (DC_IS_DAVICOM(sc) &&
3334 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA)
3335 dc_setcfg(sc, ifm->ifm_media);
3343 * Report current media status.
3345 static void dc_ifmedia_sts(ifp, ifmr)
3347 struct ifmediareq *ifmr;
3349 struct dc_softc *sc;
3350 struct mii_data *mii;
3351 struct ifmedia *ifm;
3354 mii = device_get_softc(sc->dc_miibus);
3356 ifm = &mii->mii_media;
3357 if (DC_IS_DAVICOM(sc)) {
3358 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
3359 ifmr->ifm_active = ifm->ifm_media;
3360 ifmr->ifm_status = 0;
3364 ifmr->ifm_active = mii->mii_media_active;
3365 ifmr->ifm_status = mii->mii_media_status;
3370 static int dc_ioctl(ifp, command, data)
3375 struct dc_softc *sc = ifp->if_softc;
3376 struct ifreq *ifr = (struct ifreq *) data;
3377 struct mii_data *mii;
3386 error = ether_ioctl(ifp, command, data);
3389 if (ifp->if_flags & IFF_UP) {
3390 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3391 (IFF_PROMISC | IFF_ALLMULTI);
3392 if (ifp->if_flags & IFF_RUNNING) {
3396 sc->dc_txthresh = 0;
3400 if (ifp->if_flags & IFF_RUNNING)
3403 sc->dc_if_flags = ifp->if_flags;
3413 mii = device_get_softc(sc->dc_miibus);
3414 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3416 if (sc->dc_srm_media)
3417 sc->dc_srm_media = 0;
3430 static void dc_watchdog(ifp)
3433 struct dc_softc *sc;
3438 printf("dc%d: watchdog timeout\n", sc->dc_unit);
3444 if (ifp->if_snd.ifq_head != NULL)
3451 * Stop the adapter and free any mbufs allocated to the
3454 static void dc_stop(sc)
3455 struct dc_softc *sc;
3460 ifp = &sc->arpcom.ac_if;
3463 untimeout(dc_tick, sc, sc->dc_stat_ch);
3465 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3466 #ifdef DEVICE_POLLING
3467 ether_poll_deregister(ifp);
3470 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
3471 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3472 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3473 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3477 * Free data in the RX lists.
3479 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3480 if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3481 m_freem(sc->dc_cdata.dc_rx_chain[i]);
3482 sc->dc_cdata.dc_rx_chain[i] = NULL;
3485 bzero((char *)&sc->dc_ldata->dc_rx_list,
3486 sizeof(sc->dc_ldata->dc_rx_list));
3489 * Free the TX list buffers.
3491 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3492 if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3493 if (sc->dc_ldata->dc_tx_list[i].dc_ctl &
3495 sc->dc_cdata.dc_tx_chain[i] = NULL;
3498 m_freem(sc->dc_cdata.dc_tx_chain[i]);
3499 sc->dc_cdata.dc_tx_chain[i] = NULL;
3503 bzero((char *)&sc->dc_ldata->dc_tx_list,
3504 sizeof(sc->dc_ldata->dc_tx_list));
3510 * Stop all chip I/O so that the kernel's probe routines don't
3511 * get confused by errant DMAs when rebooting.
3513 static void dc_shutdown(dev)
3516 struct dc_softc *sc;
3518 sc = device_get_softc(dev);
3526 * Device suspend routine. Stop the interface and save some PCI
3527 * settings in case the BIOS doesn't restore them properly on
3530 static int dc_suspend(dev)
3535 struct dc_softc *sc;
3539 sc = device_get_softc(dev);
3543 for (i = 0; i < 5; i++)
3544 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3545 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3546 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3547 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3548 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3557 * Device resume routine. Restore some PCI settings in case the BIOS
3558 * doesn't, re-enable busmastering, and restart the interface if
3561 static int dc_resume(dev)
3566 struct dc_softc *sc;
3571 sc = device_get_softc(dev);
3572 ifp = &sc->arpcom.ac_if;
3576 /* better way to do this? */
3577 for (i = 0; i < 5; i++)
3578 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3579 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3580 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3581 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3582 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3584 /* reenable busmastering */
3585 pci_enable_busmaster(dev);
3586 pci_enable_io(dev, DC_RES);
3588 /* reinitialize interface if necessary */
3589 if (ifp->if_flags & IFF_UP)
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