4 * Modified by Luigi Rizzo (luigi@iet.unipi.it)
6 * The low level driver for the AD1848/CS4248 codec chip which is used for
7 * example in the MS Sound System.
9 * The CS4231 which is used in the GUS MAX and some other cards is upwards
10 * compatible with AD1848 and this driver is able to drive it.
12 * CS4231A and AD1845 are upward compatible with CS4231. However the new
13 * features of these chips are different.
15 * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU). CS4232A is
16 * an improved version of CS4232.
18 * CS4236 is also a PnP audio chip similar to the 4232
20 * OPTi931 is another high-end 1848-type chip. It differs in the use
21 * of the high 16 registers and configuration stuff. Luckily, being a
22 * PnP device, we can avoid black magic to identify the chip and be
23 * sure of its identity.
25 * Copyright by Hannu Savolainen 1994, 1995
27 * Redistribution and use in source and binary forms, with or without
28 * modification, are permitted provided that the following conditions are
29 * met: 1. Redistributions of source code must retain the above copyright
30 * notice, this list of conditions and the following disclaimer. 2.
31 * Redistributions in binary form must reproduce the above copyright notice,
32 * this list of conditions and the following disclaimer in the documentation
33 * and/or other materials provided with the distribution.
35 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
36 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
37 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
38 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
39 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
41 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
42 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * Modified: Riccardo Facchetti 24 Mar 1995 - Added the Audio Excel DSP 16
48 * initialization routine.
50 * $FreeBSD: src/sys/i386/isa/sound/ad1848.c,v 1.30 1999/12/01 14:15:30 nyan Exp $
55 #include <i386/isa/sound/sound_config.h>
57 #if defined(CONFIG_AD1848)
59 #include <i386/isa/sound/ad1848_mixer.h>
60 #include <i386/isa/sound/iwdefs.h>
62 #if defined(CONFIG_CS4232)
63 extern struct isa_driver cssdriver;
65 extern struct isa_driver mssdriver;
68 extern void IwaveStopDma(BYTE path);
73 int dual_dma; /* 1, when two DMA channels allocated */
75 u_char saved_regs[16];
96 /* Mixer parameters */
98 int supported_devices;
99 int supported_rec_devices;
102 volatile u_long timer_ticks;
108 static int nr_ad1848_devs = 0;
109 static volatile char irq2dev[17] =
110 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1};
112 static int timer_installed = -1;
113 static int mute_flag = 0;
114 static char mixer2codec[MAX_MIXER_DEV] = {0};
116 static int ad_format_mask[MD_MAXMODE /* devc->mode */ ] =
119 /* 1 - AD1848 */ AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
122 * AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE |
126 /* 2 - CS4231 */ AFMT_U8 | AFMT_S16_LE | AFMT_U16_LE,
129 * AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE |
133 /* 3 - CS4231A */ AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
134 /* 4 - AD1845 */ AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
135 /* 5 - CS4236 */ AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
138 static ad1848_info dev_info[MAX_AUDIO_DEV];
140 #define io_Index_Addr(d) ((d)->base)
141 #define io_Indexed_Data(d) ((d)->base+1)
142 #define io_Status(d) ((d)->base+2)
143 #define io_Polled_IO(d) ((d)->base+3)
145 static int ad1848_open(int dev, int mode);
146 static void ad1848_close(int dev);
147 static int ad1848_ioctl(int dev, u_int cmd, ioctl_arg arg, int local);
148 static void ad1848_output_block(int dev, u_long buf, int count, int intrflag, int dma_restart);
149 static void ad1848_start_input(int dev, u_long buf, int count, int intrflag, int dma_restart);
150 static int ad1848_prepare_for_IO(int dev, int bsize, int bcount);
151 static void ad1848_reset(int dev);
152 static void ad1848_halt(int dev);
153 static void ad1848_halt_input(int dev);
154 static void ad1848_halt_output(int dev);
155 static void ad1848_trigger(int dev, int bits);
156 static int ad1848_tmr_install(int dev);
157 static void ad1848_tmr_reprogram(int dev);
160 * AD_WAIT_INIT waits if we are initializing the board and we cannot modify
163 #define AD_WAIT_INIT(x) {int t=x; while(t>0 && inb(devc->base) == 0x80) t-- ; }
165 short ipri_to_irq(u_short ipri);
171 /* this isn't ideal but should work */
172 ad1848_interrupt(-1);
174 static short unit_to_irq[4] = {9, -1, -1, -1};
175 struct isa_device *dev;
177 if (unit_to_irq[unit] > 0)
178 ad1848_interrupt(unit_to_irq[unit]);
180 #if defined(CONFIG_CS4232)
181 dev = find_isadev(isa_devtab_null, &cssdriver, unit);
183 dev = find_isadev(isa_devtab_null, &mssdriver, unit);
186 printf("ad1848: Couldn't determine unit\n");
188 unit_to_irq[unit] = ipri_to_irq(dev->id_irq);
189 ad1848_interrupt(unit_to_irq[unit]);
196 ad_read(ad1848_info * devc, int reg)
201 AD_WAIT_INIT(900000);
203 outb(io_Index_Addr(devc), (u_char) (reg & 0xff) | devc->MCE_bit);
204 x = inb(io_Indexed_Data(devc));
211 ad_write(ad1848_info * devc, int reg, u_char data)
218 outb(io_Index_Addr(devc), (u_char) (reg & 0xff) | devc->MCE_bit);
219 outb(io_Indexed_Data(devc), (u_char) (data & 0xff));
224 wait_for_calibration(ad1848_info * devc)
229 * Wait until the auto calibration process has finished.
231 * 1) Wait until the chip becomes ready (reads don't return 0x80).
232 * 2) Wait until the ACI bit of I11 gets on and then off.
235 AD_WAIT_INIT(100000);
236 if (inb(devc->base) & 0x80)
237 printf("ad1848: Auto calibration timed out(1).\n");
240 while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
242 if (!(ad_read(devc, 11) & 0x20))
246 while (timeout > 0 && ad_read(devc, 11) & 0x20)
248 if (ad_read(devc, 11) & 0x20)
249 printf("ad1848: Auto calibration timed out(3).\n");
253 ad_mute(ad1848_info * devc)
261 * Save old register settings and mute output channels
263 for (i = 6; i < 8; i++) {
264 prev = devc->saved_regs[i] = ad_read(devc, i);
265 ad_write(devc, i, prev | 0x80);
270 ad_unmute(ad1848_info * devc)
276 * Restore back old volume registers (unmute)
278 for (i = 6; i < 8; i++)
279 ad_write(devc, i, devc->saved_regs[i] & ~0x80);
283 ad_enter_MCE(ad1848_info * devc)
288 devc->MCE_bit = 0x40;
290 if ( ( inb(io_Index_Addr(devc)) & 0x40) == 0 )
291 outb(io_Index_Addr(devc), devc->MCE_bit);
296 ad_leave_MCE(ad1848_info * devc)
305 devc->MCE_bit = 0x00;
306 prev = inb(io_Index_Addr(devc));
307 /* XXX the next call is redundant ? */
308 outb(io_Index_Addr(devc), 0x00); /* Clear the MCE bit */
310 if ((prev & 0x40) == 0) { /* Not in MCE mode */
314 outb(io_Index_Addr(devc), 0x00); /* Clear the MCE bit */
315 wait_for_calibration(devc);
321 ad1848_set_recmask(ad1848_info * devc, int mask)
326 mask &= devc->supported_rec_devices;
329 for (i = 0; i < 32; i++)/* Count selected device bits */
334 mask = SOUND_MASK_MIC;
335 else if (n != 1) { /* Too many devices selected */
336 mask &= ~devc->recmask; /* Filter out active settings */
339 for (i = 0; i < 32; i++) /* Count selected device bits */
344 mask = SOUND_MASK_MIC;
351 case SOUND_MASK_LINE:
352 case SOUND_MASK_LINE3:
357 case SOUND_MASK_LINE1:
361 case SOUND_MASK_IMIX:
366 mask = SOUND_MASK_MIC;
371 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
372 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
374 devc->recmask = mask;
379 change_bits(u_char *regval, int dev, int chn, int newval)
384 if (mix_devices[dev][chn].polarity == 1) /* Reverse */
385 newval = 100 - newval;
387 mask = (1 << mix_devices[dev][chn].nbits) - 1;
388 shift = mix_devices[dev][chn].bitpos;
389 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
391 *regval &= ~(mask << shift); /* Clear bits */
392 *regval |= (newval & mask) << shift; /* Set new value */
396 ad1848_mixer_get(ad1848_info * devc, int dev)
398 if (!((1 << dev) & devc->supported_devices))
401 return devc->levels[dev];
404 #define CLMICI 0x00781601
405 #define CRMICI 0x00791701
408 ad1848_mixer_set(ad1848_info * devc, int dev, int value)
410 int left = value & 0x000000ff;
411 int right = (value & 0x0000ff00) >> 8;
416 /* u_char clci, crmici, clmici, clici, crici; */
423 if (mix_devices[dev][RIGHT_CHN].nbits == 0) /* Mono control */
426 retvol = left | (right << 8);
429 left = mix_cvt[left];
430 right = mix_cvt[right];
433 left = mix_cvt[left];
434 right = mix_cvt[right];
439 if (!(devc->supported_devices & (1 << dev)))
442 if (mix_devices[dev][LEFT_CHN].nbits == 0)
445 devc->levels[dev] = retvol;
448 * Set the left channel
450 /* IwaveCodecMode(CODEC_MODE3); Default codec mode */
452 regoffs = mix_devices[dev][LEFT_CHN].regno;
453 val = ad_read(devc, regoffs);
455 change_bits(&val, dev, LEFT_CHN, left);
456 ad_write(devc, regoffs, val);
457 devc->saved_regs[regoffs] = val;
460 * Set the right channel
463 if (mix_devices[dev][RIGHT_CHN].nbits == 0)
464 return retvol; /* Was just a mono channel */
466 regoffs = mix_devices[dev][RIGHT_CHN].regno;
467 val = ad_read(devc, regoffs);
468 change_bits(&val, dev, RIGHT_CHN, right);
469 ad_write(devc, regoffs, val);
470 devc->saved_regs[regoffs] = val;
476 ad1848_mixer_reset(ad1848_info * devc)
481 if (devc->mode != MD_1848)
482 devc->supported_devices = MODE2_MIXER_DEVICES;
484 devc->supported_devices = MODE1_MIXER_DEVICES;
486 devc->supported_rec_devices = MODE1_REC_DEVICES;
488 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
489 if (devc->supported_devices & (1 << i))
490 ad1848_mixer_set(devc, i, default_mixer_levels[i]);
491 ad1848_set_recmask(devc, SOUND_MASK_MIC);
495 ad1848_mixer_ioctl(int dev, u_int cmd, ioctl_arg arg)
498 int codec_dev = mixer2codec[dev];
505 devc = (ad1848_info *) audio_devs[codec_dev]->devc;
507 if (((cmd >> 8) & 0xff) == 'M') {
509 switch (cmd & 0xff) {
510 case SOUND_MIXER_RECSRC:
511 return *(int *) arg = ad1848_set_recmask(devc, (*(int *) arg));
515 return *(int *) arg = ad1848_mixer_set(devc, cmd & 0xff, (*(int *) arg));
518 switch (cmd & 0xff) { /* Return parameters */
520 case SOUND_MIXER_RECSRC:
521 return *(int *) arg = devc->recmask;
524 case SOUND_MIXER_DEVMASK:
525 return *(int *) arg = devc->supported_devices;
528 case SOUND_MIXER_STEREODEVS:
529 return *(int *) arg = devc->supported_devices & ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
532 case SOUND_MIXER_RECMASK:
533 return *(int *) arg = devc->supported_rec_devices;
536 case SOUND_MIXER_CAPS:
537 return *(int *) arg = SOUND_CAP_EXCL_INPUT;
541 return *(int *) arg = ad1848_mixer_get(devc, cmd & 0xff);
547 static struct audio_operations ad1848_pcm_operations[MAX_AUDIO_DEV] =
550 "Generic AD1848 codec",
551 /* DMA_AUTOMODE | DMA_DUPLEX, */
553 AFMT_U8, /* Will be set later */
560 ad1848_prepare_for_IO,
561 ad1848_prepare_for_IO,
572 static struct mixer_operations ad1848_mixer_operations =
574 "AD1848/CS4248/CS4231/CS4236",
579 ad1848_open(int dev, int mode)
581 ad1848_info *devc = NULL;
583 int otherside = audio_devs[dev]->otherside;
585 if (dev < 0 || dev >= num_audiodevs)
588 if (otherside != -1) {
589 if (audio_devs[otherside]->busy)
592 if (audio_devs[dev]->busy)
595 devc = (ad1848_info *) audio_devs[dev]->devc;
598 if (audio_devs[dev]->busy) {
604 if (audio_devs[dev]->flags & DMA_DUPLEX) {
607 devc->intr_active = 0;
608 audio_devs[dev]->busy = 1;
610 ad1848_trigger(dev, 0);
613 * Mute output until the playback really starts. This decreases
622 ad1848_close(int dev)
625 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
626 int otherside = audio_devs[dev]->otherside;
628 if (otherside != -1) {
629 if (audio_devs[otherside]->busy)
632 DEB(printf("ad1848_close(void)\n"));
638 ad_write(devc, 9, ad_read(devc, 9) & ~0x1);
639 outb(io_Status(devc), 0); /* Clear interrupt status */
641 * ad_write (devc, 15,0); ad_write (devc, 14,0);
643 devc->irq_mode &= ~PCM_ENABLE_OUTPUT;
645 devc->intr_active = 0;
650 audio_devs[dev]->busy = 0;
656 set_speed(ad1848_info * devc, int arg)
659 * The sampling speed is encoded in the least significant nible of
660 * I8. The LSB selects the clock source (0=24.576 MHz, 1=16.9344 Mhz)
661 * and other three bits select the divisor (indirectly):
663 * The available speeds are in the following table. Keep the speeds in
664 * the increasing order.
671 static speed_struct speed_table[] = {
672 {5510, (0 << 1) | 1},
673 {5510, (0 << 1) | 1},
674 {6620, (7 << 1) | 1},
675 {8000, (0 << 1) | 0},
676 {9600, (7 << 1) | 0},
677 {11025, (1 << 1) | 1},
678 {16000, (1 << 1) | 0},
679 {18900, (2 << 1) | 1},
680 {22050, (3 << 1) | 1},
681 {27420, (2 << 1) | 0},
682 {32000, (3 << 1) | 0},
683 {33075, (6 << 1) | 1},
684 {37800, (4 << 1) | 1},
685 {44100, (5 << 1) | 1},
686 {48000, (6 << 1) | 0}
689 int i, n, selected = -1;
691 n = sizeof(speed_table) / sizeof(speed_struct);
693 if (devc->mode == MD_1845) { /* AD1845 has different timer than others */
694 RANGE (arg, 4000, 50000) ;
697 devc->speed_bits = speed_table[selected].bits;
700 if (arg < speed_table[0].speed)
702 if (arg > speed_table[n - 1].speed)
705 for (i = 1 /* really */ ; selected == -1 && i < n; i++)
706 if (speed_table[i].speed == arg)
708 else if (speed_table[i].speed > arg) {
711 diff1 = arg - speed_table[i - 1].speed;
712 diff2 = speed_table[i].speed - arg;
719 if (selected == -1) {
720 printf("ad1848: Can't find speed???\n");
723 devc->speed = speed_table[selected].speed;
724 devc->speed_bits = speed_table[selected].bits;
729 set_channels(ad1848_info * devc, int arg)
731 if (arg != 1 && arg != 2)
732 return devc->channels;
734 devc->channels = arg;
739 set_format(ad1848_info * devc, int arg)
741 static struct format_tbl {
748 { AFMT_IMA_ADPCM, 5 } ,
756 int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
759 if (!(arg & ad_format_mask[devc->mode]))
762 devc->audio_format = arg;
764 for (i = 0; i < n; i++)
765 if (format2bits[i].format == arg) {
766 if ((devc->format_bits = format2bits[i].bits) == 0)
767 return devc->audio_format = AFMT_U8; /* Was not supported */
770 /* Still hanging here. Something must be terribly wrong */
771 devc->format_bits = 0;
772 return devc->audio_format = AFMT_U8;
775 /* XXX check what is arg, (int) or *(int *) lr970705 */
777 ad1848_ioctl(int dev, u_int cmd, ioctl_arg arg, int local)
779 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
782 case SOUND_PCM_WRITE_RATE:
784 return set_speed(devc, (int) arg);
785 return *(int *) arg = set_speed(devc, (*(int *) arg));
787 case SOUND_PCM_READ_RATE:
790 return *(int *) arg = devc->speed;
792 case SNDCTL_DSP_STEREO:
794 return set_channels(devc, (int) arg + 1) - 1;
795 return *(int *) arg = set_channels(devc, (*(int *) arg) + 1) - 1;
797 case SOUND_PCM_WRITE_CHANNELS:
799 return set_channels(devc, (int) arg);
800 return *(int *) arg = set_channels(devc, (*(int *) arg));
802 case SOUND_PCM_READ_CHANNELS:
804 return devc->channels;
805 return *(int *) arg = devc->channels;
807 case SNDCTL_DSP_SAMPLESIZE:
809 return set_format(devc, (int) arg);
810 return *(int *) arg = set_format(devc, (*(int *) arg));
812 case SOUND_PCM_READ_BITS:
814 return devc->audio_format;
815 return *(int *) arg = devc->audio_format;
821 return *(int *) arg = 1;
826 return *(int *) arg = 1;
835 ad1848_output_block(int dev, u_long buf, int count, int intrflag, int dma_restart)
838 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
841 if (devc->audio_format == AFMT_IMA_ADPCM) {
844 if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
847 if (devc->channels > 1)
853 if ( devc->irq_mode & PCM_ENABLE_OUTPUT &&
854 audio_devs[dev]->flags & DMA_AUTOMODE && intrflag &&
855 cnt == devc->xfer_count) {
856 devc->irq_mode |= PCM_ENABLE_OUTPUT;
857 devc->intr_active = 1;
864 DMAbuf_start_dma(dev, buf, count, 1);
866 ad_write(devc, 15, (u_char) (cnt & 0xff));
867 ad_write(devc, 14, (u_char) ((cnt >> 8) & 0xff));
869 devc->xfer_count = cnt;
870 devc->irq_mode |= PCM_ENABLE_OUTPUT;
871 devc->intr_active = 1;
876 ad1848_start_input(int dev, u_long buf, int count,
877 int intrflag, int dma_restart)
880 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
883 if (devc->audio_format == AFMT_IMA_ADPCM)
885 else if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
887 if (devc->channels > 1)
891 if ( devc->irq_mode & PCM_ENABLE_INPUT &&
892 audio_devs[dev]->flags & DMA_AUTOMODE && intrflag &&
893 cnt == devc->xfer_count) {
894 devc->irq_mode |= PCM_ENABLE_INPUT;
895 devc->intr_active = 1;
896 return; /* Auto DMA mode on. No need to react */
901 /* ad1848_halt (dev); */
902 DMAbuf_start_dma(dev, buf, count, 0);
904 if (devc->mode == MD_1848 || !devc->dual_dma) {/* Single DMA chan. mode */
905 ad_write(devc, 15, (u_char) (cnt & 0xff));
906 ad_write(devc, 14, (u_char) ((cnt >> 8) & 0xff));
907 } else { /* Dual DMA channel mode */
908 ad_write(devc, 31, (u_char) (cnt & 0xff));
909 ad_write(devc, 30, (u_char) ((cnt >> 8) & 0xff));
912 /* ad_write (devc, 9, ad_read (devc, 9) | 0x02); *//* Capture enable */
915 devc->xfer_count = cnt;
916 devc->irq_mode |= PCM_ENABLE_INPUT;
917 devc->intr_active = 1;
922 ad1848_prepare_for_IO(int dev, int bsize, int bcount)
926 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
931 fs = devc->speed_bits | (devc->format_bits << 5);
933 if (devc->channels > 1)
939 if (devc->mode == MD_1845) { /* Use alternate speed select regs */
940 fs &= 0xf0; /* Mask off the rate select bits */
942 ad_write(devc, 22, (devc->speed >> 8) & 0xff); /* Speed MSB */
943 ad_write(devc, 23, devc->speed & 0xff); /* Speed LSB */
946 ad_enter_MCE(devc); /* Enables changes to the format select reg */
948 ad_write(devc, 8, fs);
951 * Write to I8 starts resyncronization. Wait until it completes.
956 * If mode == 2 (CS4231), set I28 also. It's the capture format
959 if (devc->mode != MD_1848) {
960 ad_write(devc, 28, fs);
963 * Write to I28 starts resyncronization. Wait until it completes.
968 ad_write(devc, 9, ad_read(devc, 9) & ~0x08);
974 devc->xfer_count = 0;
975 #ifdef CONFIG_SEQUENCER
976 if (dev == timer_installed && devc->timer_running)
977 if ((fs & 0x01) != (old_fs & 0x01)) {
978 ad1848_tmr_reprogram(dev);
985 ad1848_reset(int dev)
993 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1001 ad_write(devc, 9, ad_read(devc, 9) & ~0x03); /* Stop DMA */
1003 ad_write(devc, 14, 0); /* Clear DMA counter */
1004 ad_write(devc, 15, 0); /* Clear DMA counter */
1006 if (devc->mode != MD_1848) {
1007 ad_write(devc, 30, 0); /* Clear DMA counter */
1008 ad_write(devc, 31, 0); /* Clear DMA counter */
1011 for (timeout = 0; timeout < 1000 && !(inb(io_Status(devc)) & 0x01);
1012 timeout++); /* Wait for interrupt */
1014 outb(io_Status(devc), 0); /* Clear interrupt status */
1018 /* DMAbuf_reset_dma (dev); */
1023 ad1848_halt_input(int dev)
1025 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1028 if (devc->mode == MD_1848) {
1032 playing = ad_read(devc, 9);
1033 if (!(playing & 0x2))
1039 ad_write(devc, 9, playing & ~0x02); /* Stop capture */
1041 outb(io_Status(devc), 0); /* Clear interrupt status */
1042 outb(io_Status(devc), 0); /* Clear interrupt status */
1044 devc->irq_mode &= ~PCM_ENABLE_INPUT;
1050 ad1848_halt_output(int dev)
1052 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1056 playing = ad_read(devc, 9);
1057 if (!(playing & 0x1)) {
1058 devc->irq_mode &= ~PCM_ENABLE_OUTPUT;
1061 /* IwaveStopDma(PLAYBACK); */
1062 if (devc->mode == MD_1848) {
1067 /* ad_mute (devc); */
1069 ad_write(devc, 9, playing & ~0x1);
1070 outb(io_Status(devc), 0); /* Clear interrupt status */
1072 * ad_write (devc, 15,0); ad_write (devc, 14,0);
1074 devc->irq_mode &= ~PCM_ENABLE_OUTPUT;
1080 ad1848_trigger(int dev, int state)
1082 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1087 state &= devc->irq_mode;
1089 tmp = ad_read(devc, 9) & ~0x03;
1090 if (state & PCM_ENABLE_INPUT)
1092 if (state & PCM_ENABLE_OUTPUT) {
1095 ad_write(devc, 9, tmp);
1102 ad1848_detect(int io_base, int *ad_flags, sound_os_info * osp)
1104 static int last_probe_addr=0, last_result=0; /* to avoid multiple probes*/
1106 ad1848_info *devc = &dev_info[nr_ad1848_devs];
1107 u_char tmp, tmp1, tmp2 ;
1109 DDB(printf("ad1848_detect(%x)\n", io_base));
1110 if (io_base == last_probe_addr)
1113 last_result = 0; /* default value for detect */
1114 last_probe_addr = io_base ;
1120 if (nr_ad1848_devs >= MAX_AUDIO_DEV) {
1121 DDB(printf("ad1848 detect error - step 0\n"));
1124 devc->base = io_base;
1126 devc->timer_running = 0;
1127 devc->MCE_bit = 0x40;
1130 devc->chip_name = "AD1848";
1131 devc->mode = MD_1848; /* AD1848 or CS4248 */
1135 * Check that the I/O address is in use.
1137 * The bit 0x80 of the base I/O port is known to be 0 after the chip has
1138 * performed its power on initialization. Just assume this has
1139 * happened before the OS is starting.
1141 * If the I/O address is unused, it typically returns 0xff.
1144 DDB(printf("ad1848_detect() - step A\n"));
1146 if ((inb(devc->base) & 0x80) != 0x00) { /* Not a AD1848 */
1147 DDB(printf("ad1848 detect error - step A,"
1148 " inb(base) = 0x%02x, want 0XXX.XXXX\n",
1153 * Test if it's possible to change contents of the indirect
1154 * registers. Registers 0 and 1 are ADC volume registers. The bit
1155 * 0x10 is read only so try to avoid using it.
1158 DDB(printf("ad1848_detect() - step B, test indirect register\n"));
1160 ad_write(devc, 0, 0xaa);
1161 ad_write(devc, 1, 0x45);/* 0x55 with bit 0x10 clear */
1162 tmp1 = ad_read(devc, 0) ;
1163 tmp2 = ad_read(devc, 1) ;
1164 if ( tmp1 != 0xaa || tmp2 != 0x45) {
1165 DDB(printf("ad1848 detect error - step B (0x%02x/0x%02x) want 0xaa/0x45\n", tmp1, tmp2));
1168 DDB(printf("ad1848_detect() - step C\n"));
1169 ad_write(devc, 0, 0x45);
1170 ad_write(devc, 1, 0xaa);
1171 tmp1 = ad_read(devc, 0) ;
1172 tmp2 = ad_read(devc, 1) ;
1174 if (tmp1 != 0x45 || tmp2 != 0xaa) {
1175 DDB(printf("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1180 * The indirect register I12 has some read only bits. Lets try to
1184 DDB(printf("ad1848_detect() - step D, last 4 bits of I12 readonly\n"));
1185 tmp = ad_read(devc, 12);
1186 ad_write(devc, 12, (~tmp) & 0x0f);
1187 tmp1 = ad_read(devc, 12);
1189 if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
1190 DDB(printf("ad1848 detect error - step D, I12 (0x%02x was 0x%02x)\n",
1196 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1198 * 0x0A=RevC. also CS4231/CS4231A and OPTi931
1203 * The original AD1848/CS4248 has just 15 indirect registers. This
1204 * means that I0 and I16 should return the same value (etc.). Ensure
1205 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1209 DDB(printf("ad1848_detect() - step F\n"));
1210 ad_write(devc, 12, 0); /* Mode2=disabled */
1212 for (i = 0; i < 16; i++)
1213 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
1214 DDB(printf("ad1848 detect warning - step F(I%d/0x%02x/0x%02x)\n",
1217 * note - this seems to fail on the 4232 on I11. So we just break
1220 break ; /* return 0; */
1223 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
1224 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
1226 * On the OPTi931, however, I12 is readonly and only contains the
1227 * chip revision ID (as in the CS4231A). The upper bits return 0.
1230 DDB(printf("ad1848_detect() - step G\n"));
1231 ad_write(devc, 12, 0x40); /* Set mode2, clear 0x80 */
1233 tmp1 = ad_read(devc, 12);
1236 *ad_flags |= AD_F_CS4248;
1238 devc->chip_name = "CS4248"; /* Our best knowledge just now */
1240 if ((tmp1 & 0xf0) == 0x00) {
1241 printf("this should be an OPTi931\n");
1242 } else if ((tmp1 & 0xc0) == 0xC0) {
1244 * The 4231 has bit7=1 always, and bit6 we just set to 1.
1245 * We want to check that this is really a CS4231
1246 * Verify that setting I0 doesn't change I16.
1248 DDB(printf("ad1848_detect() - step H\n"));
1249 ad_write(devc, 16, 0); /* Set I16 to known value */
1251 ad_write(devc, 0, 0x45);
1252 if ((tmp1 = ad_read(devc, 16)) != 0x45) { /* No change -> CS4231? */
1254 ad_write(devc, 0, 0xaa);
1255 if ((tmp1 = ad_read(devc, 16)) == 0xaa) { /* Rotten bits? */
1256 DDB(printf("ad1848 detect error - step H(%x)\n", tmp1));
1260 * Verify that some bits of I25 are read only.
1263 DDB(printf("ad1848_detect() - step I\n"));
1264 tmp1 = ad_read(devc, 25); /* Original bits */
1265 ad_write(devc, 25, ~tmp1); /* Invert all bits */
1266 if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7)) {
1270 * It's at least CS4231
1272 devc->chip_name = "CS4231";
1273 devc->mode = MD_4231;
1276 * It could be an AD1845 or CS4231A as well.
1277 * CS4231 and AD1845 report the same revision info in I25
1278 * while the CS4231A reports different.
1281 DDB(printf("ad1848_detect() - step I\n"));
1282 id = ad_read(devc, 25) & 0xe7;
1284 * b7-b5 = version number;
1293 devc->chip_name = "CS4231A";
1294 devc->mode = MD_4231A;
1298 devc->chip_name = "CS4232";
1299 devc->mode = MD_4231A;
1303 /* strange: the 4231 data sheet says b4-b3 are XX
1304 * so this should be the same as 0xa2
1306 devc->chip_name = "CS4232A";
1307 devc->mode = MD_4231A;
1312 * It must be a CS4231 or AD1845. The register I23
1313 * of CS4231 is undefined and it appears to be read
1314 * only. AD1845 uses I23 for setting sample rate.
1315 * Assume the chip is AD1845 if I23 is changeable.
1318 tmp = ad_read(devc, 23);
1320 ad_write(devc, 23, ~tmp);
1321 if (ad_read(devc, 23) != tmp) { /* AD1845 ? */
1322 devc->chip_name = "AD1845";
1323 devc->mode = MD_1845;
1325 ad_write(devc, 23, tmp); /* Restore */
1328 case 0x83: /* CS4236 */
1329 case 0x03: /* Mutant CS4236 on Intel PR440fx board */
1330 devc->chip_name = "CS4236";
1331 devc->mode = MD_4236;
1334 default: /* Assume CS4231 */
1335 printf("unknown id 0x%02x, assuming CS4231\n", id);
1336 devc->mode = MD_4231;
1340 ad_write(devc, 25, tmp1); /* Restore bits */
1342 DDB(printf("ad1848_detect() - step K\n"));
1345 DDB(printf("ad1848_detect() - step L\n"));
1348 if (devc->mode != MD_1848)
1349 *ad_flags |= AD_F_CS4231;
1351 DDB(printf("ad1848_detect() - Detected OK\n"));
1352 return (last_result = 1);
1356 ad1848_init(char *name, int io_base, int irq,
1357 int dma_playback, int dma_capture, int share_dma, sound_os_info * osp)
1361 * NOTE! If irq < 0, there is another driver which has allocated the
1362 * IRQ so that this driver doesn't need to allocate/deallocate it.
1363 * The actually used IRQ is ABS(irq).
1367 * Initial values for the indirect registers of CS4248/AD1848.
1369 static int init_values[] = {
1370 0xa8, /* MIXOUTL: src:mic, +20dB, gain +12dB */
1371 0xa8, /* MIXOUTR: src:mic, +20dB, gain +12dB */
1372 0x08, /* CDL Input: mute, +6dB */
1373 0x08, /* CDR Input: mute, +6dB */
1374 0x08, /* FML Input: mute, +6dB */
1375 0x08, /* FMR Input: mute, +6dB */
1376 0x80, /* DAC-L Input: enable, 0dB */
1377 0x80, /* DAC-R Input: enable, 0dB */
1378 /* 0xa8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, */
1379 0x00, /* 8bit, lin, uns, mono, 8KHz */
1380 0x0c, /* dma-cap, dma-pb, autocal, single dma, disable cap/pb */
1381 0x02, /* int enable */
1382 0x00, /* clear error status */
1383 0x8a, /* rev. id (low bytes readonly) */
1385 0x00, /* playback upper base count */
1386 0x00, /* playback lower base count */
1388 /* Positions 16 to 31 just for CS4231 and newer devices */
1389 /* I16-I17: alt. feature enable on the 4231, but AUXL Input
1390 * on the OPTi931 (where the features are set elsewhere
1392 0x81, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
1393 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1397 ad1848_info *devc = &dev_info[nr_ad1848_devs];
1399 if (!ad1848_detect(io_base, NULL, osp))
1402 devc->irq = (irq > 0) ? irq : 0;
1404 devc->timer_ticks = 0;
1407 if (nr_ad1848_devs != 0) {
1408 bcopy((char *) &ad1848_pcm_operations[0],
1409 (char *) &ad1848_pcm_operations[nr_ad1848_devs],
1410 sizeof(struct audio_operations));
1412 for (i = 0; i < 16; i++)
1413 ad_write(devc, i, init_values[i]);
1415 ad_mute(devc); /* Initialize some variables */
1416 ad_unmute(devc); /* Leave it unmuted now */
1418 if (devc->mode > MD_1848) {
1419 if (dma_capture == dma_playback ||
1420 dma_capture == -1 || dma_playback == -1) {
1421 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1422 ad1848_pcm_operations[nr_ad1848_devs].flags &= ~DMA_DUPLEX;
1424 ad_write(devc, 9, ad_read(devc, 9) & ~0x04); /* Dual DMA mode */
1425 ad1848_pcm_operations[nr_ad1848_devs].flags |= DMA_DUPLEX;
1428 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1429 for (i = 16; i < 32; i++)
1430 ad_write(devc, i, init_values[i]);
1432 if (devc->mode == MD_4231A) {
1433 /* Enable full * calibration */
1434 ad_write(devc, 9, init_values[9] | 0x18);
1437 if (devc->mode == MD_1845) {
1438 /* Alternate freq select enabled */
1439 ad_write(devc, 27, init_values[27] | 0x08);
1442 ad1848_pcm_operations[nr_ad1848_devs].flags &= ~DMA_DUPLEX;
1443 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1446 outb(io_Status(devc), 0); /* Clear pending interrupts */
1448 if (name != NULL && name[0] != 0)
1449 snprintf(ad1848_pcm_operations[nr_ad1848_devs].name,
1450 sizeof(ad1848_pcm_operations[nr_ad1848_devs].name),
1451 "%s (%s)", name, devc->chip_name);
1453 snprintf(ad1848_pcm_operations[nr_ad1848_devs].name,
1454 sizeof(ad1848_pcm_operations[nr_ad1848_devs].name),
1455 "Generic audio codec (%s)", devc->chip_name);
1457 conf_printf2(ad1848_pcm_operations[nr_ad1848_devs].name,
1458 devc->base, devc->irq, dma_playback, dma_capture);
1461 /* ad1848_pcm_operations[nr_ad1848_devs].flags |= DMA_AUTOMODE ; */
1463 if (num_audiodevs < MAX_AUDIO_DEV) {
1464 audio_devs[my_dev = num_audiodevs++] =
1465 &ad1848_pcm_operations[nr_ad1848_devs];
1467 audio_devs[my_dev]->devc = devc;
1468 irq2dev[irq] = my_dev;
1469 if (snd_set_irq_handler(devc->irq, ad1848_interrupt, devc->osp)<0) {
1470 printf("ad1848: IRQ in use\n");
1473 if (devc->mode != MD_1848) {
1475 u_char tmp = ad_read(devc, 16);
1477 devc->timer_ticks = 0;
1479 ad_write(devc, 21, 0x00); /* Timer msb */
1480 ad_write(devc, 20, 0x10); /* Timer lsb */
1482 ad_write(devc, 16, tmp | 0x40); /* Enable timer */
1483 for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
1484 ad_write(devc, 16, tmp & ~0x40); /* Disable timer */
1486 if (devc->timer_ticks == 0)
1487 printf("[IRQ conflict???]");
1492 devc->irq_ok = 1; /* Couldn't test. assume it's OK */
1497 irq2dev[-irq] = devc->dev_no = my_dev;
1499 audio_devs[my_dev]->otherside = -1 ;
1500 audio_devs[my_dev]->flags |= DMA_AUTOMODE;
1501 audio_devs[my_dev]->dmachan1 = dma_playback;
1502 audio_devs[my_dev]->dmachan2 = dma_capture;
1503 audio_devs[my_dev]->buffsize = DSP_BUFFSIZE;
1504 audio_devs[my_dev]->devc = devc;
1505 audio_devs[my_dev]->format_mask = ad_format_mask[devc->mode];
1508 #ifdef CONFIG_SEQUENCER
1509 if (devc->mode != MD_1848 && devc->irq_ok)
1510 ad1848_tmr_install(my_dev);
1514 * Toggle the MCE bit. It completes the initialization phase.
1517 ad_enter_MCE(devc); /* In case the bit was off */
1520 if (num_mixers < MAX_MIXER_DEV) {
1521 mixer2codec[num_mixers] = my_dev + 1;
1522 audio_devs[my_dev]->mixer_dev = num_mixers;
1523 mixer_devs[num_mixers++] = &ad1848_mixer_operations;
1524 ad1848_mixer_reset(devc);
1527 printf("AD1848: Too many PCM devices available\n");
1531 ad1848_interrupt(int irq)
1537 if (irq < 0 || irq > 15)
1542 if (dev < 0 || dev >= num_audiodevs) {
1543 for (irq = 0; irq < 17; irq++)
1544 if (irq2dev[irq] != -1)
1548 printf("ad1848.c: Bogus interrupt %d\n", irq);
1553 devc = (ad1848_info *) audio_devs[dev]->devc;
1555 status = inb(io_Status(devc));
1557 if (status & 0x01) { /* we have an interrupt */
1558 int alt_stat = 0xff ;
1560 if (devc->mode != MD_1848) {
1562 * high-end devices have full-duplex dma and timer.
1563 * the exact reason for the interrupt is in reg. I24.
1564 * For old devices, we fake the interrupt bits, and
1565 * determine the real reason basing on the device mode.
1567 alt_stat = ad_read(devc, 24);
1568 if (alt_stat & 0x40) { /* Timer interrupt */
1569 devc->timer_ticks++;
1570 #ifdef CONFIG_SEQUENCER
1571 if (timer_installed == dev && devc->timer_running)
1572 sound_timer_interrupt();
1577 outb(io_Status(devc), 0); /* Clear interrupt status */
1579 if (audio_devs[dev]->busy) {
1581 if (devc->irq_mode & PCM_ENABLE_OUTPUT && alt_stat & 0x10)
1582 DMAbuf_outputintr(dev, 1);
1584 if (devc->irq_mode & PCM_ENABLE_INPUT && alt_stat & 0x20)
1585 DMAbuf_inputintr(dev);
1591 * Some extra code for the MS Sound System
1596 check_opl3(int base, struct address_info * hw_config)
1599 if (!opl3_detect(base, hw_config->osp))
1602 opl3_init(0, base, hw_config->osp);
1607 * this is the probe routine. Note, it is not necessary to
1608 * go through this for PnP devices, since they are already
1609 * indentified precisely using their PnP id.
1614 probe_mss(struct address_info * hw_config)
1618 DDB(printf("Entered probe_mss(io 0x%x, type %d)\n",
1619 hw_config->io_base, hw_config->card_subtype));
1621 if (hw_config->card_subtype == 1) { /* Has no IRQ/DMA registers */
1622 /* check_opl3(0x388, hw_config); */
1626 #if defined(CONFIG_AEDSP16) && defined(AEDSP16_MSS)
1628 * Initialize Audio Excel DSP 16 to MSS: before any operation we must
1629 * enable MSS I/O ports.
1631 InitAEDSP16_MSS(hw_config);
1635 * Check if the IO port returns valid signature. The original MS
1636 * Sound system returns 0x04 while some cards (AudioTriX Pro for
1637 * example) return 0x00 or 0x0f.
1640 if ((tmp = inb(hw_config->io_base + 3)) == 0xff) { /* Bus float */
1641 DDB(printf("I/O address inactive (%x), force type 1\n", tmp));
1642 hw_config->card_subtype = 1 ;
1646 if ((tmp & 0x3f) != 0x04 &&
1647 (tmp & 0x3f) != 0x0f &&
1648 (tmp & 0x3f) != 0x00) {
1649 DDB(printf("No MSS signature detected on port 0x%x (0x%x)\n",
1650 hw_config->io_base, inb(hw_config->io_base + 3)));
1653 if (hw_config->irq > 11) {
1654 printf("MSS: Bad IRQ %d\n", hw_config->irq);
1657 if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3) {
1658 printf("MSS: Bad DMA %d\n", hw_config->dma);
1662 * Check that DMA0 is not in use with a 8 bit board.
1665 if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80) {
1666 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1669 if (hw_config->irq > 7 && hw_config->irq != 9 &&
1670 inb(hw_config->io_base + 3) & 0x80) {
1671 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
1675 return ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp);
1679 attach_mss(struct address_info * hw_config)
1684 * XXX do we really need to detect it again ? - lr970712
1686 if (!ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp))
1690 if (hw_config->card_subtype == 1) { /* Has no IRQ/DMA registers */
1691 ad1848_init("MS Sound System1", hw_config->io_base + 4,
1694 hw_config->dma2, 0, hw_config->osp);
1697 * Set the IRQ and DMA addresses.
1700 static char interrupt_bits[13] = {
1701 -1, -1, -1, 0x08, -1, 0x10, -1, -1, -1, -1, 0x18, -1, 0x20
1704 static char interrupt_bits[12] = {
1705 -1, -1, -1, -1, -1, -1, -1, 0x08, -1, 0x10, 0x18, 0x20
1708 static char dma_bits[4] = {
1712 int config_port = hw_config->io_base + 0;
1713 int version_port = hw_config->io_base + 3;
1714 char bits = interrupt_bits[hw_config->irq];
1720 outb(config_port, bits | 0x40);
1721 if ((inb(version_port) & 0x40) == 0)
1722 printf("[IRQ Conflict?]");
1725 /* Write IRQ+DMA setup */
1726 outb(config_port, bits | dma_bits[hw_config->dma]);
1728 ad1848_init("MS Sound System0", hw_config->io_base + 4,
1731 hw_config->dma, 0, hw_config->osp);
1737 * WSS compatible PnP codec support.
1738 * XXX I doubt it works now - lr970712
1742 probe_pnp_ad1848(struct address_info * hw_config)
1744 return ad1848_detect(hw_config->io_base, NULL, hw_config->osp);
1748 attach_pnp_ad1848(struct address_info * hw_config)
1751 ad1848_init(hw_config->name, hw_config->io_base,
1754 hw_config->dma2, 0, hw_config->osp);
1757 #ifdef CONFIG_SEQUENCER
1759 * Timer stuff (for /dev/music).
1762 static u_int current_interval = 0;
1765 ad1848_tmr_start(int dev, u_int usecs)
1768 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1769 u_long xtal_nsecs; /* nanoseconds per xtal oscillaror tick */
1775 * Length of the timer interval (in nanoseconds) depends on the
1776 * selected crystal oscillator. Check this from bit 0x01 of I8.
1778 * AD1845 has just one oscillator which has cycle time of 10.050 us
1779 * (when a 24.576 MHz xtal oscillator is used).
1781 * Convert requested interval to nanoseconds before computing the timer
1785 if (devc->mode == MD_1845)
1787 else if (ad_read(devc, 8) & 0x01)
1792 divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
1794 if (divider < 100) /* Don't allow shorter intervals than about 1ms */
1797 if (divider > 65535) /* Overflow check */
1800 ad_write(devc, 21, (divider >> 8) & 0xff); /* Set upper bits */
1801 ad_write(devc, 20, divider & 0xff); /* Set lower bits */
1802 ad_write(devc, 16, ad_read(devc, 16) | 0x40); /* Start the timer */
1803 devc->timer_running = 1;
1806 return current_interval = (divider * xtal_nsecs + 500) / 1000;
1810 ad1848_tmr_reprogram(int dev)
1813 * Audio driver has changed sampling rate so that a different xtal
1814 * oscillator was selected. We have to reprogram the timer rate.
1817 ad1848_tmr_start(dev, current_interval);
1818 sound_timer_syncinterval(current_interval);
1822 ad1848_tmr_disable(int dev)
1825 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1828 ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
1829 devc->timer_running = 0;
1834 ad1848_tmr_restart(int dev)
1837 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1839 if (current_interval == 0)
1843 ad_write(devc, 16, ad_read(devc, 16) | 0x40);
1844 devc->timer_running = 1;
1848 static struct sound_lowlev_timer ad1848_tmr = {
1856 ad1848_tmr_install(int dev)
1858 if (timer_installed != -1)
1859 return 0; /* Don't install another timer */
1861 timer_installed = ad1848_tmr.dev = dev;
1862 sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);