2 * This code is derived from code available from the STB bulletin board
4 * $FreeBSD: src/usr.sbin/pcvt/set2061/ICD2061Aalt.c,v 1.5 1999/12/29 05:07:54 peter Exp $
7 /* $XFree86: mit/server/ddx/x386/common_hw/ICD2061Aalt.c,v 2.6 1994/04/15 05:10:30 dawes Exp $ */
13 #define PCVT_STANDALONE 1
17 #define MISCREG 0x03C2
18 #define MISCREAD 0x03CC
20 double fref = 14.31818 * 2.0;
21 char ascclk[] = "VIDEO CLOCK ?";
23 unsigned short clknum;
24 unsigned short vlbus_flag;
26 unsigned short crtcaddr;
27 unsigned short clockreg;
29 static double range[15] = {50.0, 51.0, 53.2, 58.5, 60.7, 64.4, 66.8, 73.5,
30 75.6, 80.9, 83.2, 91.5, 100.0, 120.0, 120.0};
33 static double genratio(unsigned int *p, unsigned int *q, double tgt);
34 static double f(unsigned int p, unsigned int q, double basefreq);
36 static void prtbinary(unsigned int size, unsigned int val);
38 static void wait_vb();
39 static void wrt_clk_bit(unsigned int value);
40 static void init_clock(unsigned long setup, unsigned short crtcport);
42 static double genratio();
45 static void prtbinary();
47 static void wait_vb();
48 static void wrt_clk_bit();
49 static void init_clock();
52 void AltICD2061SetClock(frequency, select)
53 register long frequency; /* in Hz */
56 unsigned int m, mval, ival;
64 unsigned int bestp, bestq;
67 crtcaddr=(inb(0x3CC) & 0x01) ? 0x3D4 : 0x3B4;
70 outb(crtcaddr, 0x11); /* Unlock CRTC registers */
71 tmp = inb(crtcaddr + 1);
72 outb(crtcaddr + 1, tmp & ~0x80);
74 outw(crtcaddr, 0x4838); /* Unlock S3 register set */
75 outw(crtcaddr, 0xA039);
79 freq = ((double)frequency)/1000000.0;
82 else if (freq <= 6.99)
86 * Calculate values to load into ICD 2061A clock chip to set frequency
94 for (m = 0; m < 8; m++) {
96 for (i = 14; i >= 0; i--)
103 devx = (fvco - (range[i] + range[i+1])/2)/fvco;
106 deltax = genratio(&p, &q, fvco);
109 if (deltax < delta || devx < dev) {
119 for (m=0; m<mval; m++)
121 realval = f(bestp, bestq, fvco);
122 dwv = ((((((long)ival << 7) | bestp) << 3) | mval) << 7) | bestq;
125 * Write ICD 2061A clock chip
127 init_clock(((unsigned long)dwv) | (((long)clknum) << 21), crtcaddr);
135 wait_vb(); /* 0.10 second delay... */
138 static double f(p, q, base)
143 return(base * (p + 3)/(q + 2));
146 static double genratio(p, q, tgt)
152 double test, mindiff;
155 mindiff = 999999999.0;
156 for (k = 13; k < 69; k++) { /* q={15..71}:Constraint 2 on page 14 */
160 mmax = 120*k/fref - 3; /* m..mmax is constraint 3 on page 14 */
164 test = f(m, k, fref) - tgt;
165 if (test < 0) test = -test;
166 if (mindiff > test) {
178 static void prtbinary(size, val)
187 for (k=size; --k > 0 || mask <= val/2;)
191 fputc((mask&val)? '1': '0' , stderr);
197 static void wait_vb()
199 while ((inb(crtcaddr+6) & 0x08) == 0)
201 while (inb(crtcaddr+6) & 0x08)
207 static void init_clock(unsigned long setup, unsigned short crtcport)
209 static void init_clock(setup, crtcport)
211 unsigned short crtcport;
214 unsigned char nclk[2], clk[2];
215 unsigned short restore42;
216 unsigned short oldclk;
217 unsigned short bitval;
221 #ifndef PCVT_STANDALONE
222 (void)xf86DisableInterrupts();
227 outb(crtcport, 0x42);
228 restore42 = inb(crtcport+1);
234 outb(0x3C5, 0x20 | c);
236 outb(crtcport, 0x42);
237 outb(crtcport+1, 0x03);
241 nclk[0] = oldclk & 0xF3;
242 nclk[1] = nclk[0] | 0x08;
243 clk[0] = nclk[0] | 0x04;
244 clk[1] = nclk[0] | 0x0C;
246 outb(crtcport, 0x42);
251 wrt_clk_bit(oldclk | 0x08);
252 wrt_clk_bit(oldclk | 0x0C);
253 for (i=0; i<5; i++) {
254 wrt_clk_bit(nclk[1]);
257 wrt_clk_bit(nclk[1]);
258 wrt_clk_bit(nclk[0]);
260 wrt_clk_bit(nclk[0]);
262 for (i=0; i<24; i++) {
263 bitval = setup & 0x01;
265 wrt_clk_bit(clk[1-bitval]);
266 wrt_clk_bit(nclk[1-bitval]);
267 wrt_clk_bit(nclk[bitval]);
268 wrt_clk_bit(clk[bitval]);
271 wrt_clk_bit(nclk[1]);
276 outb(0x3C5, 0xDF & c);
278 outb(crtcport, 0x42);
279 outb(crtcport+1, restore42);
285 #ifndef PCVT_STANDALONE
286 xf86EnableInterrupts();
291 static void wrt_clk_bit(value)