2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/mpapic.h>
60 #include <machine/psl.h>
61 #include <machine/segments.h>
62 #include <machine/tss.h>
63 #include <machine/specialreg.h>
64 #include <machine/globaldata.h>
65 #include <machine/pmap_inval.h>
67 #include <machine/md_var.h> /* setidt() */
68 #include <machine_base/icu/icu.h> /* IPIs */
69 #include <machine/intr_machdep.h> /* IPIs */
71 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define BIOS_BASE (0xf0000)
78 #define BIOS_BASE2 (0xe0000)
79 #define BIOS_SIZE (0x10000)
80 #define BIOS_COUNT (BIOS_SIZE/4)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 #define PROCENTRY_FLAG_EN 0x01
88 #define PROCENTRY_FLAG_BP 0x02
89 #define IOAPICENTRY_FLAG_EN 0x01
92 /* MP Floating Pointer Structure */
93 typedef struct MPFPS {
106 /* MP Configuration Table Header */
107 typedef struct MPCTH {
109 u_short base_table_length;
113 u_char product_id[12];
114 void *oem_table_pointer;
115 u_short oem_table_size;
118 u_short extended_table_length;
119 u_char extended_table_checksum;
124 typedef struct PROCENTRY {
129 u_long cpu_signature;
130 u_long feature_flags;
135 typedef struct BUSENTRY {
141 typedef struct IOAPICENTRY {
147 } *io_apic_entry_ptr;
149 typedef struct INTENTRY {
159 /* descriptions of MP basetable entries */
160 typedef struct BASETABLE_ENTRY {
169 vm_size_t mp_cth_mapsz;
172 #define MPTABLE_POS_USE_DEFAULT(mpt) \
173 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
177 int mb_type; /* MPTABLE_BUS_ */
178 TAILQ_ENTRY(mptable_bus) mb_link;
181 #define MPTABLE_BUS_ISA 0
182 #define MPTABLE_BUS_PCI 1
184 struct mptable_bus_info {
185 TAILQ_HEAD(, mptable_bus) mbi_list;
188 struct mptable_pci_int {
195 TAILQ_ENTRY(mptable_pci_int) mpci_link;
198 struct mptable_ioapic {
204 TAILQ_ENTRY(mptable_ioapic) mio_link;
207 typedef int (*mptable_iter_func)(void *, const void *, int);
210 * this code MUST be enabled here and in mpboot.s.
211 * it follows the very early stages of AP boot by placing values in CMOS ram.
212 * it NORMALLY will never be needed and thus the primitive method for enabling.
215 #if defined(CHECK_POINTS)
216 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
217 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
219 #define CHECK_INIT(D); \
220 CHECK_WRITE(0x34, (D)); \
221 CHECK_WRITE(0x35, (D)); \
222 CHECK_WRITE(0x36, (D)); \
223 CHECK_WRITE(0x37, (D)); \
224 CHECK_WRITE(0x38, (D)); \
225 CHECK_WRITE(0x39, (D));
227 #define CHECK_PRINT(S); \
228 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
237 #else /* CHECK_POINTS */
239 #define CHECK_INIT(D)
240 #define CHECK_PRINT(S)
242 #endif /* CHECK_POINTS */
245 * Values to send to the POST hardware.
247 #define MP_BOOTADDRESS_POST 0x10
248 #define MP_PROBE_POST 0x11
249 #define MPTABLE_PASS1_POST 0x12
251 #define MP_START_POST 0x13
252 #define MP_ENABLE_POST 0x14
253 #define MPTABLE_PASS2_POST 0x15
255 #define START_ALL_APS_POST 0x16
256 #define INSTALL_AP_TRAMP_POST 0x17
257 #define START_AP_POST 0x18
259 #define MP_ANNOUNCE_POST 0x19
261 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
262 int current_postcode;
264 /** XXX FIXME: what system files declare these??? */
265 extern struct region_descriptor r_gdt, r_idt;
267 int mp_naps; /* # of Applications processors */
268 #ifdef SMP /* APIC-IO */
269 static int mp_nbusses; /* # of busses */
270 int mp_napics; /* # of IO APICs */
271 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
272 u_int32_t *io_apic_versions;
276 u_int32_t cpu_apic_versions[MAXCPU];
278 extern int64_t tsc_offsets[];
280 extern u_long ebda_addr;
282 #ifdef SMP /* APIC-IO */
283 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
287 * APIC ID logical/physical mapping structures.
288 * We oversize these to simplify boot-time config.
290 int cpu_num_to_apic_id[NAPICID];
291 #ifdef SMP /* APIC-IO */
292 int io_num_to_apic_id[NAPICID];
294 int apic_id_to_logical[NAPICID];
296 /* AP uses this during bootstrap. Do not staticize. */
300 /* Hotwire a 0->4MB V==P mapping */
301 extern pt_entry_t *KPTphys;
304 * SMP page table page. Setup by locore to point to a page table
305 * page from which we allocate per-cpu privatespace areas io_apics,
309 #define IO_MAPPING_START_INDEX \
310 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
312 extern pt_entry_t *SMPpt;
313 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
315 struct pcb stoppcbs[MAXCPU];
317 static basetable_entry basetable_entry_types[] =
319 {0, 20, "Processor"},
327 * Local data and functions.
330 static u_int boot_address;
331 static u_int base_memory;
332 static int mp_finish;
334 static void mp_enable(u_int boot_addr);
336 static int mptable_iterate_entries(const mpcth_t,
337 mptable_iter_func, void *);
338 static int mptable_search(void);
339 static int mptable_search_sig(u_int32_t target, int count);
340 static int mptable_hyperthread_fixup(cpumask_t, int);
341 #ifdef SMP /* APIC-IO */
342 static void mptable_pass1(struct mptable_pos *);
343 static void mptable_pass2(struct mptable_pos *);
344 static void mptable_default(int type);
345 static void mptable_fix(void);
347 static int mptable_map(struct mptable_pos *);
348 static void mptable_unmap(struct mptable_pos *);
349 static void mptable_bus_info_alloc(const mpcth_t,
350 struct mptable_bus_info *);
351 static void mptable_bus_info_free(struct mptable_bus_info *);
353 static int mptable_lapic_probe(struct lapic_enumerator *);
354 static void mptable_lapic_enumerate(struct lapic_enumerator *);
355 static void mptable_lapic_default(void);
357 static int mptable_ioapic_probe(struct ioapic_enumerator *);
358 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
360 #ifdef SMP /* APIC-IO */
361 static void setup_apic_irq_mapping(void);
362 static int apic_int_is_bus_type(int intr, int bus_type);
364 static int start_all_aps(u_int boot_addr);
365 static void install_ap_tramp(u_int boot_addr);
366 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
367 static int smitest(void);
369 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
370 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
371 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
375 static vm_paddr_t mptable_fps_phyaddr;
376 static int mptable_use_default;
377 static TAILQ_HEAD(mptable_pci_int_list, mptable_pci_int) mptable_pci_int_list =
378 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
379 static TAILQ_HEAD(mptable_ioapic_list, mptable_ioapic) mptable_ioapic_list =
380 TAILQ_HEAD_INITIALIZER(mptable_ioapic_list);
383 * Calculate usable address in base memory for AP trampoline code.
386 mp_bootaddress(u_int basemem)
388 POSTCODE(MP_BOOTADDRESS_POST);
390 base_memory = basemem;
392 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
393 if ((base_memory - boot_address) < bootMP_size)
394 boot_address -= 4096; /* not enough, lower by 4k */
403 struct mptable_pos mpt;
406 KKASSERT(mptable_fps_phyaddr == 0);
408 mptable_fps_phyaddr = mptable_search();
409 if (mptable_fps_phyaddr == 0)
412 error = mptable_map(&mpt);
414 mptable_fps_phyaddr = 0;
418 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
419 kprintf("MPTABLE: use default configuration\n");
420 mptable_use_default = 1;
422 if (mpt.mp_fps->mpfb2 & 0x80)
427 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
430 * Look for an Intel MP spec table (ie, SMP capable hardware).
439 * Make sure our SMPpt[] page table is big enough to hold all the
442 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
444 POSTCODE(MP_PROBE_POST);
446 /* see if EBDA exists */
447 if (ebda_addr != 0) {
448 /* search first 1K of EBDA */
449 target = (u_int32_t)ebda_addr;
450 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
453 /* last 1K of base memory, effective 'top of base' passed in */
454 target = (u_int32_t)(base_memory - 0x400);
455 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
459 /* search the BIOS */
460 target = (u_int32_t)BIOS_BASE;
461 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
464 /* search the extended BIOS */
465 target = (u_int32_t)BIOS_BASE2;
466 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
474 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
476 int count, total_size;
477 const void *position;
479 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
480 total_size = cth->base_table_length - sizeof(struct MPCTH);
481 position = (const uint8_t *)cth + sizeof(struct MPCTH);
482 count = cth->entry_count;
487 KKASSERT(total_size >= 0);
488 if (total_size == 0) {
489 kprintf("invalid base MP table, "
490 "entry count and length mismatch\n");
494 type = *(const uint8_t *)position;
496 case 0: /* processor_entry */
497 case 1: /* bus_entry */
498 case 2: /* io_apic_entry */
499 case 3: /* int_entry */
500 case 4: /* int_entry */
503 kprintf("unknown base MP table entry type %d\n", type);
507 if (total_size < basetable_entry_types[type].length) {
508 kprintf("invalid base MP table length, "
509 "does not contain all entries\n");
512 total_size -= basetable_entry_types[type].length;
514 error = func(arg, position, type);
518 position = (const uint8_t *)position +
519 basetable_entry_types[type].length;
526 * Startup the SMP processors.
531 POSTCODE(MP_START_POST);
532 mp_enable(boot_address);
537 * Print various information about the SMP system hardware and setup.
544 POSTCODE(MP_ANNOUNCE_POST);
546 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
547 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
548 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
549 for (x = 1; x <= mp_naps; ++x) {
550 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
551 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
554 if (apic_io_enable) {
555 if (ioapic_use_old) {
556 for (x = 0; x < mp_napics; ++x) {
557 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
558 kprintf(", version: 0x%08x", io_apic_versions[x]);
559 kprintf(", at 0x%08lx\n", io_apic_address[x]);
563 kprintf(" Warning: APIC I/O disabled\n");
568 * AP cpu's call this to sync up protected mode.
570 * WARNING! We must ensure that the cpu is sufficiently initialized to
571 * be able to use to the FP for our optimized bzero/bcopy code before
572 * we enter more mainstream C code.
574 * WARNING! %fs is not set up on entry. This routine sets up %fs.
580 int x, myid = bootAP;
582 struct mdglobaldata *md;
583 struct privatespace *ps;
585 ps = &CPU_prvspace[myid];
587 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
588 gdt_segs[GPROC0_SEL].ssd_base =
589 (int) &ps->mdglobaldata.gd_common_tss;
590 ps->mdglobaldata.mi.gd_prvspace = ps;
592 for (x = 0; x < NGDT; x++) {
593 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
596 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
597 r_gdt.rd_base = (int) &gdt[myid * NGDT];
598 lgdt(&r_gdt); /* does magic intra-segment return */
603 mdcpu->gd_currentldt = _default_ldt;
605 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
606 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
608 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
610 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
611 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
612 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
613 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
614 md->gd_common_tssd = *md->gd_tss_gdt;
618 * Set to a known state:
619 * Set by mpboot.s: CR0_PG, CR0_PE
620 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
623 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
625 pmap_set_opt(); /* PSE/4MB pages, etc */
627 /* set up CPU registers and state */
630 /* set up FPU state on the AP */
631 npxinit(__INITIAL_NPXCW__);
633 /* set up SSE registers */
637 /*******************************************************************
638 * local functions and data
642 * start the SMP system
645 mp_enable(u_int boot_addr)
649 struct mptable_pos mpt;
651 POSTCODE(MP_ENABLE_POST);
655 /* Initialize BSP's local APIC */
661 if (apic_io_enable && ioapic_use_old) {
663 if (!mptable_fps_phyaddr)
664 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
669 * Examine the MP table for needed info
676 /* Post scan cleanup */
679 setup_apic_irq_mapping();
681 /* fill the LOGICAL io_apic_versions table */
682 for (apic = 0; apic < mp_napics; ++apic) {
683 ux = ioapic_read(ioapic[apic], IOAPIC_VER);
684 io_apic_versions[apic] = ux;
685 io_apic_set_id(apic, IO_TO_ID(apic));
688 /* program each IO APIC in the system */
689 for (apic = 0; apic < mp_napics; ++apic)
690 if (io_apic_setup(apic) < 0)
691 panic("IO APIC setup failure");
696 MachIntrABI.finalize();
698 /* start each Application Processor */
699 start_all_aps(boot_addr);
704 * look for the MP spec signature
707 /* string defined by the Intel MP Spec as identifying the MP table */
708 #define MP_SIG 0x5f504d5f /* _MP_ */
709 #define NEXT(X) ((X) += 4)
711 mptable_search_sig(u_int32_t target, int count)
717 KKASSERT(target != 0);
719 map_size = count * sizeof(u_int32_t);
720 addr = pmap_mapdev((vm_paddr_t)target, map_size);
723 for (x = 0; x < count; NEXT(x)) {
724 if (addr[x] == MP_SIG) {
725 /* make array index a byte index */
726 ret = target + (x * sizeof(u_int32_t));
731 pmap_unmapdev((vm_offset_t)addr, map_size);
736 typedef struct BUSDATA {
738 enum busTypes bus_type;
741 typedef struct INTDATA {
751 typedef struct BUSTYPENAME {
756 static bus_type_name bus_type_table[] =
762 {UNKNOWN_BUSTYPE, "---"},
765 {UNKNOWN_BUSTYPE, "---"},
766 {UNKNOWN_BUSTYPE, "---"},
767 {UNKNOWN_BUSTYPE, "---"},
768 {UNKNOWN_BUSTYPE, "---"},
769 {UNKNOWN_BUSTYPE, "---"},
771 {UNKNOWN_BUSTYPE, "---"},
772 {UNKNOWN_BUSTYPE, "---"},
773 {UNKNOWN_BUSTYPE, "---"},
774 {UNKNOWN_BUSTYPE, "---"},
776 {UNKNOWN_BUSTYPE, "---"}
778 /* from MP spec v1.4, table 5-1 */
779 static int default_data[7][5] =
781 /* nbus, id0, type0, id1, type1 */
782 {1, 0, ISA, 255, 255},
783 {1, 0, EISA, 255, 255},
784 {1, 0, EISA, 255, 255},
785 {1, 0, MCA, 255, 255},
787 {2, 0, EISA, 1, PCI},
793 static bus_datum *bus_data;
795 /* the IO INT data, one entry per possible APIC INTerrupt */
796 static io_int *io_apic_ints;
799 static int processor_entry (const struct PROCENTRY *entry, int cpu);
800 static int bus_entry (const struct BUSENTRY *entry, int bus);
801 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
802 static int int_entry (const struct INTENTRY *entry, int intr);
803 static int lookup_bus_type (char *name);
806 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
808 const struct IOAPICENTRY *ioapic_ent;
811 case 1: /* bus_entry */
815 case 2: /* io_apic_entry */
817 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
818 io_apic_address[mp_napics++] =
819 (vm_offset_t)ioapic_ent->apic_address;
823 case 3: /* int_entry */
831 * 1st pass on motherboard's Intel MP specification table.
840 mptable_pass1(struct mptable_pos *mpt)
845 POSTCODE(MPTABLE_PASS1_POST);
848 KKASSERT(fps != NULL);
850 /* clear various tables */
851 for (x = 0; x < NAPICID; ++x)
852 io_apic_address[x] = ~0; /* IO APIC address table */
858 /* check for use of 'default' configuration */
859 if (fps->mpfb1 != 0) {
860 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
861 mp_nbusses = default_data[fps->mpfb1 - 1][0];
867 error = mptable_iterate_entries(mpt->mp_cth,
868 mptable_ioapic_pass1_callback, NULL);
870 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
874 struct mptable_ioapic2_cbarg {
881 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
883 struct mptable_ioapic2_cbarg *arg = xarg;
887 if (bus_entry(pos, arg->bus))
892 if (io_apic_entry(pos, arg->apic))
897 if (int_entry(pos, arg->intr))
905 * 2nd pass on motherboard's Intel MP specification table.
908 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
909 * IO_TO_ID(N), logical IO to APIC ID table
914 mptable_pass2(struct mptable_pos *mpt)
916 struct mptable_ioapic2_cbarg arg;
920 POSTCODE(MPTABLE_PASS2_POST);
923 KKASSERT(fps != NULL);
925 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
927 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
928 M_DEVBUF, M_WAITOK | M_ZERO);
929 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
931 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
934 for (x = 0; x < mp_napics; x++)
935 ioapic[x] = ioapic_map(io_apic_address[x]);
937 /* clear various tables */
938 for (x = 0; x < NAPICID; ++x) {
939 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
940 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
943 /* clear bus data table */
944 for (x = 0; x < mp_nbusses; ++x)
945 bus_data[x].bus_id = 0xff;
947 /* clear IO APIC INT table */
948 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
949 io_apic_ints[x].int_type = 0xff;
950 io_apic_ints[x].int_vector = 0xff;
953 /* check for use of 'default' configuration */
954 if (fps->mpfb1 != 0) {
955 mptable_default(fps->mpfb1);
959 bzero(&arg, sizeof(arg));
960 error = mptable_iterate_entries(mpt->mp_cth,
961 mptable_ioapic_pass2_callback, &arg);
963 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
967 * Check if we should perform a hyperthreading "fix-up" to
968 * enumerate any logical CPU's that aren't already listed
971 * XXX: We assume that all of the physical CPUs in the
972 * system have the same number of logical CPUs.
974 * XXX: We assume that APIC ID's are allocated such that
975 * the APIC ID's for a physical processor are aligned
976 * with the number of logical CPU's in the processor.
979 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
981 int i, id, lcpus_max, logical_cpus;
983 if ((cpu_feature & CPUID_HTT) == 0)
986 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
990 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
992 * INSTRUCTION SET REFERENCE, A-M (#253666)
993 * Page 3-181, Table 3-20
994 * "The nearest power-of-2 integer that is not smaller
995 * than EBX[23:16] is the number of unique initial APIC
996 * IDs reserved for addressing different logical
997 * processors in a physical package."
1000 if ((1 << i) >= lcpus_max) {
1007 KKASSERT(cpu_count != 0);
1008 if (cpu_count == lcpus_max) {
1009 /* We have nothing to fix */
1011 } else if (cpu_count == 1) {
1012 /* XXX this may be incorrect */
1013 logical_cpus = lcpus_max;
1015 int cur, prev, dist;
1018 * Calculate the distances between two nearest
1019 * APIC IDs. If all such distances are same,
1020 * then it is the number of missing cpus that
1021 * we are going to fill later.
1023 dist = cur = prev = -1;
1024 for (id = 0; id < MAXCPU; ++id) {
1025 if ((id_mask & CPUMASK(id)) == 0)
1030 int new_dist = cur - prev;
1036 * Make sure that all distances
1037 * between two nearest APIC IDs
1040 if (dist != new_dist)
1048 /* Must be power of 2 */
1049 if (dist & (dist - 1))
1052 /* Can't exceed CPU package capacity */
1053 if (dist > lcpus_max)
1054 logical_cpus = lcpus_max;
1056 logical_cpus = dist;
1060 * For each APIC ID of a CPU that is set in the mask,
1061 * scan the other candidate APIC ID's for this
1062 * physical processor. If any of those ID's are
1063 * already in the table, then kill the fixup.
1065 for (id = 0; id < MAXCPU; id++) {
1066 if ((id_mask & CPUMASK(id)) == 0)
1068 /* First, make sure we are on a logical_cpus boundary. */
1069 if (id % logical_cpus != 0)
1071 for (i = id + 1; i < id + logical_cpus; i++)
1072 if ((id_mask & CPUMASK(i)) != 0)
1075 return logical_cpus;
1079 mptable_map(struct mptable_pos *mpt)
1083 vm_size_t cth_mapsz = 0;
1085 KKASSERT(mptable_fps_phyaddr != 0);
1087 bzero(mpt, sizeof(*mpt));
1089 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
1090 if (fps->pap != 0) {
1092 * Map configuration table header to get
1093 * the base table size
1095 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1096 cth_mapsz = cth->base_table_length;
1097 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1099 if (cth_mapsz < sizeof(*cth)) {
1100 kprintf("invalid base MP table length %d\n",
1102 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1107 * Map the base table
1109 cth = pmap_mapdev(fps->pap, cth_mapsz);
1114 mpt->mp_cth_mapsz = cth_mapsz;
1120 mptable_unmap(struct mptable_pos *mpt)
1122 if (mpt->mp_cth != NULL) {
1123 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1125 mpt->mp_cth_mapsz = 0;
1127 if (mpt->mp_fps != NULL) {
1128 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1134 assign_apic_irq(int apic, int intpin, int irq)
1138 if (int_to_apicintpin[irq].ioapic != -1)
1139 panic("assign_apic_irq: inconsistent table");
1141 int_to_apicintpin[irq].ioapic = apic;
1142 int_to_apicintpin[irq].int_pin = intpin;
1143 int_to_apicintpin[irq].apic_address = ioapic[apic];
1144 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1146 for (x = 0; x < nintrs; x++) {
1147 if ((io_apic_ints[x].int_type == 0 ||
1148 io_apic_ints[x].int_type == 3) &&
1149 io_apic_ints[x].int_vector == 0xff &&
1150 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1151 io_apic_ints[x].dst_apic_int == intpin)
1152 io_apic_ints[x].int_vector = irq;
1157 revoke_apic_irq(int irq)
1163 if (int_to_apicintpin[irq].ioapic == -1)
1164 panic("revoke_apic_irq: inconsistent table");
1166 oldapic = int_to_apicintpin[irq].ioapic;
1167 oldintpin = int_to_apicintpin[irq].int_pin;
1169 int_to_apicintpin[irq].ioapic = -1;
1170 int_to_apicintpin[irq].int_pin = 0;
1171 int_to_apicintpin[irq].apic_address = NULL;
1172 int_to_apicintpin[irq].redirindex = 0;
1174 for (x = 0; x < nintrs; x++) {
1175 if ((io_apic_ints[x].int_type == 0 ||
1176 io_apic_ints[x].int_type == 3) &&
1177 io_apic_ints[x].int_vector != 0xff &&
1178 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1179 io_apic_ints[x].dst_apic_int == oldintpin)
1180 io_apic_ints[x].int_vector = 0xff;
1188 allocate_apic_irq(int intr)
1194 if (io_apic_ints[intr].int_vector != 0xff)
1195 return; /* Interrupt handler already assigned */
1197 if (io_apic_ints[intr].int_type != 0 &&
1198 (io_apic_ints[intr].int_type != 3 ||
1199 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1200 io_apic_ints[intr].dst_apic_int == 0)))
1201 return; /* Not INT or ExtInt on != (0, 0) */
1204 while (irq < APIC_INTMAPSIZE &&
1205 int_to_apicintpin[irq].ioapic != -1)
1208 if (irq >= APIC_INTMAPSIZE)
1209 return; /* No free interrupt handlers */
1211 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1212 intpin = io_apic_ints[intr].dst_apic_int;
1214 assign_apic_irq(apic, intpin, irq);
1219 swap_apic_id(int apic, int oldid, int newid)
1226 return; /* Nothing to do */
1228 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1229 apic, oldid, newid);
1231 /* Swap physical APIC IDs in interrupt entries */
1232 for (x = 0; x < nintrs; x++) {
1233 if (io_apic_ints[x].dst_apic_id == oldid)
1234 io_apic_ints[x].dst_apic_id = newid;
1235 else if (io_apic_ints[x].dst_apic_id == newid)
1236 io_apic_ints[x].dst_apic_id = oldid;
1239 /* Swap physical APIC IDs in IO_TO_ID mappings */
1240 for (oapic = 0; oapic < mp_napics; oapic++)
1241 if (IO_TO_ID(oapic) == newid)
1244 if (oapic < mp_napics) {
1245 kprintf("Changing APIC ID for IO APIC #%d from "
1246 "%d to %d in MP table\n",
1247 oapic, newid, oldid);
1248 IO_TO_ID(oapic) = oldid;
1250 IO_TO_ID(apic) = newid;
1255 fix_id_to_io_mapping(void)
1259 for (x = 0; x < NAPICID; x++)
1262 for (x = 0; x <= mp_naps; x++)
1263 if (CPU_TO_ID(x) < NAPICID)
1264 ID_TO_IO(CPU_TO_ID(x)) = x;
1266 for (x = 0; x < mp_napics; x++)
1267 if (IO_TO_ID(x) < NAPICID)
1268 ID_TO_IO(IO_TO_ID(x)) = x;
1273 first_free_apic_id(void)
1277 for (freeid = 0; freeid < NAPICID; freeid++) {
1278 for (x = 0; x <= mp_naps; x++)
1279 if (CPU_TO_ID(x) == freeid)
1283 for (x = 0; x < mp_napics; x++)
1284 if (IO_TO_ID(x) == freeid)
1295 io_apic_id_acceptable(int apic, int id)
1297 int cpu; /* Logical CPU number */
1298 int oapic; /* Logical IO APIC number for other IO APIC */
1301 return 0; /* Out of range */
1303 for (cpu = 0; cpu <= mp_naps; cpu++)
1304 if (CPU_TO_ID(cpu) == id)
1305 return 0; /* Conflict with CPU */
1307 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1308 if (IO_TO_ID(oapic) == id)
1309 return 0; /* Conflict with other APIC */
1311 return 1; /* ID is acceptable for IO APIC */
1316 io_apic_find_int_entry(int apic, int pin)
1320 /* search each of the possible INTerrupt sources */
1321 for (x = 0; x < nintrs; ++x) {
1322 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1323 (pin == io_apic_ints[x].dst_apic_int))
1324 return (&io_apic_ints[x]);
1330 * parse an Intel MP specification table
1337 int apic; /* IO APIC unit number */
1338 int freeid; /* Free physical APIC ID */
1339 int physid; /* Current physical IO APIC ID */
1341 int bus_0 = 0; /* Stop GCC warning */
1342 int bus_pci = 0; /* Stop GCC warning */
1346 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1347 * did it wrong. The MP spec says that when more than 1 PCI bus
1348 * exists the BIOS must begin with bus entries for the PCI bus and use
1349 * actual PCI bus numbering. This implies that when only 1 PCI bus
1350 * exists the BIOS can choose to ignore this ordering, and indeed many
1351 * MP motherboards do ignore it. This causes a problem when the PCI
1352 * sub-system makes requests of the MP sub-system based on PCI bus
1353 * numbers. So here we look for the situation and renumber the
1354 * busses and associated INTs in an effort to "make it right".
1357 /* find bus 0, PCI bus, count the number of PCI busses */
1358 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1359 if (bus_data[x].bus_id == 0) {
1362 if (bus_data[x].bus_type == PCI) {
1368 * bus_0 == slot of bus with ID of 0
1369 * bus_pci == slot of last PCI bus encountered
1372 /* check the 1 PCI bus case for sanity */
1373 /* if it is number 0 all is well */
1374 if (num_pci_bus == 1 &&
1375 bus_data[bus_pci].bus_id != 0) {
1377 /* mis-numbered, swap with whichever bus uses slot 0 */
1379 /* swap the bus entry types */
1380 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1381 bus_data[bus_0].bus_type = PCI;
1383 /* swap each relavant INTerrupt entry */
1384 id = bus_data[bus_pci].bus_id;
1385 for (x = 0; x < nintrs; ++x) {
1386 if (io_apic_ints[x].src_bus_id == id) {
1387 io_apic_ints[x].src_bus_id = 0;
1389 else if (io_apic_ints[x].src_bus_id == 0) {
1390 io_apic_ints[x].src_bus_id = id;
1395 /* Assign IO APIC IDs.
1397 * First try the existing ID. If a conflict is detected, try
1398 * the ID in the MP table. If a conflict is still detected, find
1401 * We cannot use the ID_TO_IO table before all conflicts has been
1402 * resolved and the table has been corrected.
1404 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1406 /* First try to use the value set by the BIOS */
1407 physid = io_apic_get_id(apic);
1408 if (io_apic_id_acceptable(apic, physid)) {
1409 if (IO_TO_ID(apic) != physid)
1410 swap_apic_id(apic, IO_TO_ID(apic), physid);
1414 /* Then check if the value in the MP table is acceptable */
1415 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1418 /* Last resort, find a free APIC ID and use it */
1419 freeid = first_free_apic_id();
1420 if (freeid >= NAPICID)
1421 panic("No free physical APIC IDs found");
1423 if (io_apic_id_acceptable(apic, freeid)) {
1424 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1427 panic("Free physical APIC ID not usable");
1429 fix_id_to_io_mapping();
1431 /* detect and fix broken Compaq MP table */
1432 if (apic_int_type(0, 0) == -1) {
1433 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1434 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1435 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1436 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1437 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1438 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1440 } else if (apic_int_type(0, 0) == 0) {
1441 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1442 for (x = 0; x < nintrs; ++x)
1443 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1444 (0 == io_apic_ints[x].dst_apic_int)) {
1445 io_apic_ints[x].int_type = 3;
1446 io_apic_ints[x].int_vector = 0xff;
1452 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1453 * controllers universally come in pairs. If IRQ 14 is specified
1454 * as an ISA interrupt, then IRQ 15 had better be too.
1456 * [ Shuttle XPC / AMD Athlon X2 ]
1457 * The MPTable is missing an entry for IRQ 15. Note that the
1458 * ACPI table has an entry for both 14 and 15.
1460 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1461 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1462 io14 = io_apic_find_int_entry(0, 14);
1463 io_apic_ints[nintrs] = *io14;
1464 io_apic_ints[nintrs].src_bus_irq = 15;
1465 io_apic_ints[nintrs].dst_apic_int = 15;
1470 /* Assign low level interrupt handlers */
1472 setup_apic_irq_mapping(void)
1478 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1479 int_to_apicintpin[x].ioapic = -1;
1480 int_to_apicintpin[x].int_pin = 0;
1481 int_to_apicintpin[x].apic_address = NULL;
1482 int_to_apicintpin[x].redirindex = 0;
1484 /* Default to masked */
1485 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1488 /* First assign ISA/EISA interrupts */
1489 for (x = 0; x < nintrs; x++) {
1490 int_vector = io_apic_ints[x].src_bus_irq;
1491 if (int_vector < APIC_INTMAPSIZE &&
1492 io_apic_ints[x].int_vector == 0xff &&
1493 int_to_apicintpin[int_vector].ioapic == -1 &&
1494 (apic_int_is_bus_type(x, ISA) ||
1495 apic_int_is_bus_type(x, EISA)) &&
1496 io_apic_ints[x].int_type == 0) {
1497 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1498 io_apic_ints[x].dst_apic_int,
1503 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1504 for (x = 0; x < nintrs; x++) {
1505 if (io_apic_ints[x].dst_apic_int == 0 &&
1506 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1507 io_apic_ints[x].int_vector == 0xff &&
1508 int_to_apicintpin[0].ioapic == -1 &&
1509 io_apic_ints[x].int_type == 3) {
1510 assign_apic_irq(0, 0, 0);
1515 /* Assign PCI interrupts */
1516 for (x = 0; x < nintrs; ++x) {
1517 if (io_apic_ints[x].int_type == 0 &&
1518 io_apic_ints[x].int_vector == 0xff &&
1519 apic_int_is_bus_type(x, PCI))
1520 allocate_apic_irq(x);
1525 mp_set_cpuids(int cpu_id, int apic_id)
1527 CPU_TO_ID(cpu_id) = apic_id;
1528 ID_TO_CPU(apic_id) = cpu_id;
1530 if (apic_id > lapic_id_max)
1531 lapic_id_max = apic_id;
1535 processor_entry(const struct PROCENTRY *entry, int cpu)
1539 /* check for usability */
1540 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1543 /* check for BSP flag */
1544 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1545 mp_set_cpuids(0, entry->apic_id);
1546 return 0; /* its already been counted */
1549 /* add another AP to list, if less than max number of CPUs */
1550 else if (cpu < MAXCPU) {
1551 mp_set_cpuids(cpu, entry->apic_id);
1559 bus_entry(const struct BUSENTRY *entry, int bus)
1564 /* encode the name into an index */
1565 for (x = 0; x < 6; ++x) {
1566 if ((c = entry->bus_type[x]) == ' ')
1572 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1573 panic("unknown bus type: '%s'", name);
1575 bus_data[bus].bus_id = entry->bus_id;
1576 bus_data[bus].bus_type = x;
1582 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1584 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1587 IO_TO_ID(apic) = entry->apic_id;
1588 ID_TO_IO(entry->apic_id) = apic;
1594 lookup_bus_type(char *name)
1598 for (x = 0; x < MAX_BUSTYPE; ++x)
1599 if (strcmp(bus_type_table[x].name, name) == 0)
1600 return bus_type_table[x].type;
1602 return UNKNOWN_BUSTYPE;
1606 int_entry(const struct INTENTRY *entry, int intr)
1610 io_apic_ints[intr].int_type = entry->int_type;
1611 io_apic_ints[intr].int_flags = entry->int_flags;
1612 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1613 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1614 if (entry->dst_apic_id == 255) {
1615 /* This signal goes to all IO APICS. Select an IO APIC
1616 with sufficient number of interrupt pins */
1617 for (apic = 0; apic < mp_napics; apic++)
1618 if (((ioapic_read(ioapic[apic], IOAPIC_VER) &
1619 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1620 entry->dst_apic_int)
1622 if (apic < mp_napics)
1623 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1625 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1627 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1628 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1634 apic_int_is_bus_type(int intr, int bus_type)
1638 for (bus = 0; bus < mp_nbusses; ++bus)
1639 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1640 && ((int) bus_data[bus].bus_type == bus_type))
1647 * Given a traditional ISA INT mask, return an APIC mask.
1650 isa_apic_mask(u_int isa_mask)
1655 #if defined(SKIP_IRQ15_REDIRECT)
1656 if (isa_mask == (1 << 15)) {
1657 kprintf("skipping ISA IRQ15 redirect\n");
1660 #endif /* SKIP_IRQ15_REDIRECT */
1662 isa_irq = ffs(isa_mask); /* find its bit position */
1663 if (isa_irq == 0) /* doesn't exist */
1665 --isa_irq; /* make it zero based */
1667 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1671 return (1 << apic_pin); /* convert pin# to a mask */
1675 * Determine which APIC pin an ISA/EISA INT is attached to.
1677 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1678 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1679 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1680 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1682 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1684 isa_apic_irq(int isa_irq)
1688 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1689 if (INTTYPE(intr) == 0) { /* standard INT */
1690 if (SRCBUSIRQ(intr) == isa_irq) {
1691 if (apic_int_is_bus_type(intr, ISA) ||
1692 apic_int_is_bus_type(intr, EISA)) {
1693 if (INTIRQ(intr) == 0xff)
1694 return -1; /* unassigned */
1695 return INTIRQ(intr); /* found */
1700 return -1; /* NOT found */
1705 * Determine which APIC pin a PCI INT is attached to.
1707 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1708 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1709 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1711 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1715 --pciInt; /* zero based */
1717 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1718 if ((INTTYPE(intr) == 0) /* standard INT */
1719 && (SRCBUSID(intr) == pciBus)
1720 && (SRCBUSDEVICE(intr) == pciDevice)
1721 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1722 if (apic_int_is_bus_type(intr, PCI)) {
1723 if (INTIRQ(intr) == 0xff) {
1724 kprintf("IOAPIC: pci_apic_irq() "
1726 return -1; /* unassigned */
1728 return INTIRQ(intr); /* exact match */
1733 return -1; /* NOT found */
1737 next_apic_irq(int irq)
1744 for (intr = 0; intr < nintrs; intr++) {
1745 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1747 bus = SRCBUSID(intr);
1748 bustype = apic_bus_type(bus);
1749 if (bustype != ISA &&
1755 if (intr >= nintrs) {
1758 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1759 if (INTTYPE(ointr) != 0)
1761 if (bus != SRCBUSID(ointr))
1763 if (bustype == PCI) {
1764 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1766 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1769 if (bustype == ISA || bustype == EISA) {
1770 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1773 if (INTPIN(intr) == INTPIN(ointr))
1777 if (ointr >= nintrs) {
1780 return INTIRQ(ointr);
1793 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1796 * Exactly what this means is unclear at this point. It is a solution
1797 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1798 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1799 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1803 undirect_isa_irq(int rirq)
1807 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1808 /** FIXME: tickle the MB redirector chip */
1812 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1819 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1822 undirect_pci_irq(int rirq)
1826 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1828 /** FIXME: tickle the MB redirector chip */
1832 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1840 * given a bus ID, return:
1841 * the bus type if found
1845 apic_bus_type(int id)
1849 for (x = 0; x < mp_nbusses; ++x)
1850 if (bus_data[x].bus_id == id)
1851 return bus_data[x].bus_type;
1857 * given a LOGICAL APIC# and pin#, return:
1858 * the associated src bus ID if found
1862 apic_src_bus_id(int apic, int pin)
1866 /* search each of the possible INTerrupt sources */
1867 for (x = 0; x < nintrs; ++x)
1868 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1869 (pin == io_apic_ints[x].dst_apic_int))
1870 return (io_apic_ints[x].src_bus_id);
1872 return -1; /* NOT found */
1876 * given a LOGICAL APIC# and pin#, return:
1877 * the associated src bus IRQ if found
1881 apic_src_bus_irq(int apic, int pin)
1885 for (x = 0; x < nintrs; x++)
1886 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1887 (pin == io_apic_ints[x].dst_apic_int))
1888 return (io_apic_ints[x].src_bus_irq);
1890 return -1; /* NOT found */
1895 * given a LOGICAL APIC# and pin#, return:
1896 * the associated INTerrupt type if found
1900 apic_int_type(int apic, int pin)
1904 /* search each of the possible INTerrupt sources */
1905 for (x = 0; x < nintrs; ++x) {
1906 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1907 (pin == io_apic_ints[x].dst_apic_int))
1908 return (io_apic_ints[x].int_type);
1910 return -1; /* NOT found */
1914 * Return the IRQ associated with an APIC pin
1917 apic_irq(int apic, int pin)
1922 for (x = 0; x < nintrs; ++x) {
1923 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1924 (pin == io_apic_ints[x].dst_apic_int)) {
1925 res = io_apic_ints[x].int_vector;
1928 if (apic != int_to_apicintpin[res].ioapic)
1929 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1930 if (pin != int_to_apicintpin[res].int_pin)
1931 panic("apic_irq inconsistent table (2)");
1940 * given a LOGICAL APIC# and pin#, return:
1941 * the associated trigger mode if found
1945 apic_trigger(int apic, int pin)
1949 /* search each of the possible INTerrupt sources */
1950 for (x = 0; x < nintrs; ++x)
1951 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1952 (pin == io_apic_ints[x].dst_apic_int))
1953 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1955 return -1; /* NOT found */
1960 * given a LOGICAL APIC# and pin#, return:
1961 * the associated 'active' level if found
1965 apic_polarity(int apic, int pin)
1969 /* search each of the possible INTerrupt sources */
1970 for (x = 0; x < nintrs; ++x)
1971 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1972 (pin == io_apic_ints[x].dst_apic_int))
1973 return (io_apic_ints[x].int_flags & 0x03);
1975 return -1; /* NOT found */
1979 * set data according to MP defaults
1980 * FIXME: probably not complete yet...
1983 mptable_default(int type)
1989 kprintf(" MP default config type: %d\n", type);
1992 kprintf(" bus: ISA, APIC: 82489DX\n");
1995 kprintf(" bus: EISA, APIC: 82489DX\n");
1998 kprintf(" bus: EISA, APIC: 82489DX\n");
2001 kprintf(" bus: MCA, APIC: 82489DX\n");
2004 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2007 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2010 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2013 kprintf(" future type\n");
2019 /* one and only IO APIC */
2020 io_apic_id = (ioapic_read(ioapic[0], IOAPIC_ID) & APIC_ID_MASK) >> 24;
2023 * sanity check, refer to MP spec section 3.6.6, last paragraph
2024 * necessary as some hardware isn't properly setting up the IO APIC
2026 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2027 if (io_apic_id != 2) {
2029 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2030 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2031 io_apic_set_id(0, 2);
2034 IO_TO_ID(0) = io_apic_id;
2035 ID_TO_IO(io_apic_id) = 0;
2037 /* fill out bus entries */
2046 bus_data[0].bus_id = default_data[type - 1][1];
2047 bus_data[0].bus_type = default_data[type - 1][2];
2048 bus_data[1].bus_id = default_data[type - 1][3];
2049 bus_data[1].bus_type = default_data[type - 1][4];
2052 /* case 4: case 7: MCA NOT supported */
2053 default: /* illegal/reserved */
2054 panic("BAD default MP config: %d", type);
2058 /* general cases from MP v1.4, table 5-2 */
2059 for (pin = 0; pin < 16; ++pin) {
2060 io_apic_ints[pin].int_type = 0;
2061 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2062 io_apic_ints[pin].src_bus_id = 0;
2063 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2064 io_apic_ints[pin].dst_apic_id = io_apic_id;
2065 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2068 /* special cases from MP v1.4, table 5-2 */
2070 io_apic_ints[2].int_type = 0xff; /* N/C */
2071 io_apic_ints[13].int_type = 0xff; /* N/C */
2072 #if !defined(APIC_MIXED_MODE)
2074 panic("sorry, can't support type 2 default yet");
2075 #endif /* APIC_MIXED_MODE */
2078 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2081 io_apic_ints[0].int_type = 0xff; /* N/C */
2083 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2087 * Map a physical memory address representing I/O into KVA. The I/O
2088 * block is assumed not to cross a page boundary.
2091 ioapic_map(vm_paddr_t pa)
2097 KKASSERT(pa < 0x100000000LL);
2099 pgeflag = 0; /* not used for SMP yet */
2102 * If the requested physical address has already been incidently
2103 * mapped, just use the existing mapping. Otherwise create a new
2106 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2107 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2108 ((vm_offset_t)pa & PG_FRAME)) {
2112 if (i == SMPpt_alloc_index) {
2113 if (i == NPTEPG - 2) {
2114 panic("permanent_io_mapping: We ran out of space"
2117 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
2118 ((vm_offset_t)pa & PG_FRAME));
2119 ++SMPpt_alloc_index;
2121 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2122 ((vm_offset_t)pa & PAGE_MASK);
2123 return ((void *)vaddr);
2127 * start each AP in our list
2130 start_all_aps(u_int boot_addr)
2137 u_char mpbiosreason;
2138 u_long mpbioswarmvec;
2139 struct mdglobaldata *gd;
2140 struct privatespace *ps;
2144 POSTCODE(START_ALL_APS_POST);
2146 /* install the AP 1st level boot code */
2147 install_ap_tramp(boot_addr);
2150 /* save the current value of the warm-start vector */
2151 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2152 outb(CMOS_REG, BIOS_RESET);
2153 mpbiosreason = inb(CMOS_DATA);
2155 /* setup a vector to our boot code */
2156 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2157 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2158 outb(CMOS_REG, BIOS_RESET);
2159 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2162 * If we have a TSC we can figure out the SMI interrupt rate.
2163 * The SMI does not necessarily use a constant rate. Spend
2164 * up to 250ms trying to figure it out.
2167 if (cpu_feature & CPUID_TSC) {
2168 set_apic_timer(275000);
2169 smilast = read_apic_timer();
2170 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2171 smicount = smitest();
2172 if (smibest == 0 || smilast - smicount < smibest)
2173 smibest = smilast - smicount;
2176 if (smibest > 250000)
2179 smibest = smibest * (int64_t)1000000 /
2180 get_apic_timer_frequency();
2184 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2185 1000000 / smibest, smibest);
2188 /* set up temporary P==V mapping for AP boot */
2189 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2190 kptbase = (uintptr_t)(void *)KPTphys;
2191 for (x = 0; x < NKPT; x++) {
2192 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2193 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2198 for (x = 1; x <= mp_naps; ++x) {
2200 /* This is a bit verbose, it will go away soon. */
2202 /* first page of AP's private space */
2203 pg = x * i386_btop(sizeof(struct privatespace));
2205 /* allocate new private data page(s) */
2206 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2207 MDGLOBALDATA_BASEALLOC_SIZE);
2208 /* wire it into the private page table page */
2209 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2210 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2211 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2213 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2215 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2216 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2217 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2218 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2220 /* allocate and set up an idle stack data page */
2221 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2222 for (i = 0; i < UPAGES; i++) {
2223 SMPpt[pg + 4 + i] = (pt_entry_t)
2224 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2227 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2228 bzero(gd, sizeof(*gd));
2229 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2231 /* prime data page for it to use */
2232 mi_gdinit(&gd->mi, x);
2234 gd->gd_CMAP1 = &SMPpt[pg + 0];
2235 gd->gd_CMAP2 = &SMPpt[pg + 1];
2236 gd->gd_CMAP3 = &SMPpt[pg + 2];
2237 gd->gd_PMAP1 = &SMPpt[pg + 3];
2238 gd->gd_CADDR1 = ps->CPAGE1;
2239 gd->gd_CADDR2 = ps->CPAGE2;
2240 gd->gd_CADDR3 = ps->CPAGE3;
2241 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2244 * Per-cpu pmap for get_ptbase().
2246 gd->gd_GDADDR1= (unsigned *)
2247 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
2248 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
2250 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2251 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2254 * Setup the AP boot stack
2256 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2259 /* attempt to start the Application Processor */
2260 CHECK_INIT(99); /* setup checkpoints */
2261 if (!start_ap(gd, boot_addr, smibest)) {
2262 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2263 CHECK_PRINT("trace"); /* show checkpoints */
2264 /* better panic as the AP may be running loose */
2265 kprintf("panic y/n? [y] ");
2266 if (cngetc() != 'n')
2269 CHECK_PRINT("trace"); /* show checkpoints */
2271 /* record its version info */
2272 cpu_apic_versions[x] = cpu_apic_versions[0];
2275 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2278 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2279 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2282 ncpus2_shift = shift;
2283 ncpus2 = 1 << shift;
2284 ncpus2_mask = ncpus2 - 1;
2286 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2287 if ((1 << shift) < ncpus)
2289 ncpus_fit = 1 << shift;
2290 ncpus_fit_mask = ncpus_fit - 1;
2292 /* build our map of 'other' CPUs */
2293 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2294 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2295 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2297 /* fill in our (BSP) APIC version */
2298 cpu_apic_versions[0] = lapic.version;
2300 /* restore the warmstart vector */
2301 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2302 outb(CMOS_REG, BIOS_RESET);
2303 outb(CMOS_DATA, mpbiosreason);
2306 * NOTE! The idlestack for the BSP was setup by locore. Finish
2307 * up, clean out the P==V mapping we did earlier.
2309 for (x = 0; x < NKPT; x++)
2313 /* number of APs actually started */
2318 * load the 1st level AP boot code into base memory.
2321 /* targets for relocation */
2322 extern void bigJump(void);
2323 extern void bootCodeSeg(void);
2324 extern void bootDataSeg(void);
2325 extern void MPentry(void);
2326 extern u_int MP_GDT;
2327 extern u_int mp_gdtbase;
2330 install_ap_tramp(u_int boot_addr)
2333 int size = *(int *) ((u_long) & bootMP_size);
2334 u_char *src = (u_char *) ((u_long) bootMP);
2335 u_char *dst = (u_char *) boot_addr + KERNBASE;
2336 u_int boot_base = (u_int) bootMP;
2341 POSTCODE(INSTALL_AP_TRAMP_POST);
2343 for (x = 0; x < size; ++x)
2347 * modify addresses in code we just moved to basemem. unfortunately we
2348 * need fairly detailed info about mpboot.s for this to work. changes
2349 * to mpboot.s might require changes here.
2352 /* boot code is located in KERNEL space */
2353 dst = (u_char *) boot_addr + KERNBASE;
2355 /* modify the lgdt arg */
2356 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2357 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2359 /* modify the ljmp target for MPentry() */
2360 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2361 *dst32 = ((u_int) MPentry - KERNBASE);
2363 /* modify the target for boot code segment */
2364 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2365 dst8 = (u_int8_t *) (dst16 + 1);
2366 *dst16 = (u_int) boot_addr & 0xffff;
2367 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2369 /* modify the target for boot data segment */
2370 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2371 dst8 = (u_int8_t *) (dst16 + 1);
2372 *dst16 = (u_int) boot_addr & 0xffff;
2373 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2378 * This function starts the AP (application processor) identified
2379 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2380 * to accomplish this. This is necessary because of the nuances
2381 * of the different hardware we might encounter. It ain't pretty,
2382 * but it seems to work.
2384 * NOTE: eventually an AP gets to ap_init(), which is called just
2385 * before the AP goes into the LWKT scheduler's idle loop.
2388 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2392 u_long icr_lo, icr_hi;
2394 POSTCODE(START_AP_POST);
2396 /* get the PHYSICAL APIC ID# */
2397 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2399 /* calculate the vector */
2400 vector = (boot_addr >> 12) & 0xff;
2402 /* We don't want anything interfering */
2405 /* Make sure the target cpu sees everything */
2409 * Try to detect when a SMI has occurred, wait up to 200ms.
2411 * If a SMI occurs during an AP reset but before we issue
2412 * the STARTUP command, the AP may brick. To work around
2413 * this problem we hold off doing the AP startup until
2414 * after we have detected the SMI. Hopefully another SMI
2415 * will not occur before we finish the AP startup.
2417 * Retries don't seem to help. SMIs have a window of opportunity
2418 * and if USB->legacy keyboard emulation is enabled in the BIOS
2419 * the interrupt rate can be quite high.
2421 * NOTE: Don't worry about the L1 cache load, it might bloat
2422 * ldelta a little but ndelta will be so huge when the SMI
2423 * occurs the detection logic will still work fine.
2426 set_apic_timer(200000);
2431 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2432 * and running the target CPU. OR this INIT IPI might be latched (P5
2433 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2436 * see apic/apicreg.h for icr bit definitions.
2438 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2442 * Setup the address for the target AP. We can setup
2443 * icr_hi once and then just trigger operations with
2446 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2447 icr_hi |= (physical_cpu << 24);
2448 icr_lo = lapic.icr_lo & 0xfff00000;
2449 lapic.icr_hi = icr_hi;
2452 * Do an INIT IPI: assert RESET
2454 * Use edge triggered mode to assert INIT
2456 lapic.icr_lo = icr_lo | 0x0000c500;
2457 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2461 * The spec calls for a 10ms delay but we may have to use a
2462 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2463 * interrupt. We have other loops here too and dividing by 2
2464 * doesn't seem to be enough even after subtracting 350us,
2465 * so we divide by 4.
2467 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2468 * interrupt was detected we use the full 10ms.
2472 else if (smibest < 150 * 4 + 350)
2474 else if ((smibest - 350) / 4 < 10000)
2475 u_sleep((smibest - 350) / 4);
2480 * Do an INIT IPI: deassert RESET
2482 * Use level triggered mode to deassert. It is unclear
2483 * why we need to do this.
2485 lapic.icr_lo = icr_lo | 0x00008500;
2486 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2488 u_sleep(150); /* wait 150us */
2491 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2492 * latched, (P5 bug) this 1st STARTUP would then terminate
2493 * immediately, and the previously started INIT IPI would continue. OR
2494 * the previous INIT IPI has already run. and this STARTUP IPI will
2495 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2498 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2499 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2501 u_sleep(200); /* wait ~200uS */
2504 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2505 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2506 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2507 * recognized after hardware RESET or INIT IPI.
2509 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2510 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2513 /* Resume normal operation */
2516 /* wait for it to start, see ap_init() */
2517 set_apic_timer(5000000);/* == 5 seconds */
2518 while (read_apic_timer()) {
2519 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2520 return 1; /* return SUCCESS */
2523 return 0; /* return FAILURE */
2538 while (read_apic_timer()) {
2540 for (count = 0; count < 100; ++count)
2541 ntsc = rdtsc(); /* force loop to occur */
2543 ndelta = ntsc - ltsc;
2544 if (ldelta > ndelta)
2546 if (ndelta > ldelta * 2)
2549 ldelta = ntsc - ltsc;
2552 return(read_apic_timer());
2556 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2558 * If for some reason we were unable to start all cpus we cannot safely
2559 * use broadcast IPIs.
2562 static cpumask_t smp_invltlb_req;
2563 #define SMP_INVLTLB_DEBUG
2569 struct mdglobaldata *md = mdcpu;
2570 #ifdef SMP_INVLTLB_DEBUG
2575 crit_enter_gd(&md->mi);
2576 md->gd_invltlb_ret = 0;
2577 ++md->mi.gd_cnt.v_smpinvltlb;
2578 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2579 #ifdef SMP_INVLTLB_DEBUG
2582 if (smp_startup_mask == smp_active_mask) {
2583 all_but_self_ipi(XINVLTLB_OFFSET);
2585 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2586 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2589 #ifdef SMP_INVLTLB_DEBUG
2591 kprintf("smp_invltlb: ipi sent\n");
2593 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2594 (smp_active_mask & ~md->mi.gd_cpumask)) {
2597 #ifdef SMP_INVLTLB_DEBUG
2599 if (++count == 400000000) {
2600 print_backtrace(-1);
2601 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2602 "rflags %016lx retry",
2603 (long)md->gd_invltlb_ret,
2604 (long)smp_invltlb_req,
2605 (long)read_eflags());
2606 __asm __volatile ("sti");
2609 lwkt_process_ipiq();
2611 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2612 ~md->mi.gd_cpumask &
2615 kprintf("bcpu %d\n", bcpu);
2616 xgd = globaldata_find(bcpu);
2617 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2626 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2627 crit_exit_gd(&md->mi);
2634 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2635 * bother to bump the critical section count or nested interrupt count
2636 * so only do very low level operations here.
2639 smp_invltlb_intr(void)
2641 struct mdglobaldata *md = mdcpu;
2642 struct mdglobaldata *omd;
2646 mask = smp_invltlb_req;
2650 cpu = BSFCPUMASK(mask);
2651 mask &= ~CPUMASK(cpu);
2652 omd = (struct mdglobaldata *)globaldata_find(cpu);
2653 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2660 * When called the executing CPU will send an IPI to all other CPUs
2661 * requesting that they halt execution.
2663 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2665 * - Signals all CPUs in map to stop.
2666 * - Waits for each to stop.
2673 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2674 * from executing at same time.
2677 stop_cpus(cpumask_t map)
2679 map &= smp_active_mask;
2681 /* send the Xcpustop IPI to all CPUs in map */
2682 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2684 while ((stopped_cpus & map) != map)
2692 * Called by a CPU to restart stopped CPUs.
2694 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2696 * - Signals all CPUs in map to restart.
2697 * - Waits for each to restart.
2705 restart_cpus(cpumask_t map)
2707 /* signal other cpus to restart */
2708 started_cpus = map & smp_active_mask;
2710 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2717 * This is called once the mpboot code has gotten us properly relocated
2718 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2719 * and when it returns the scheduler will call the real cpu_idle() main
2720 * loop for the idlethread. Interrupts are disabled on entry and should
2721 * remain disabled at return.
2729 * Adjust smp_startup_mask to signal the BSP that we have started
2730 * up successfully. Note that we do not yet hold the BGL. The BSP
2731 * is waiting for our signal.
2733 * We can't set our bit in smp_active_mask yet because we are holding
2734 * interrupts physically disabled and remote cpus could deadlock
2735 * trying to send us an IPI.
2737 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2741 * Interlock for finalization. Wait until mp_finish is non-zero,
2742 * then get the MP lock.
2744 * Note: We are in a critical section.
2746 * Note: we are the idle thread, we can only spin.
2748 * Note: The load fence is memory volatile and prevents the compiler
2749 * from improperly caching mp_finish, and the cpu from improperly
2752 while (mp_finish == 0)
2754 while (try_mplock() == 0)
2757 if (cpu_feature & CPUID_TSC) {
2759 * The BSP is constantly updating tsc0_offset, figure out
2760 * the relative difference to synchronize ktrdump.
2762 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2765 /* BSP may have changed PTD while we're waiting for the lock */
2768 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2772 /* Build our map of 'other' CPUs. */
2773 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2775 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2777 /* A quick check from sanity claus */
2778 apic_id = (apic_id_to_logical[(lapic.id & 0xff000000) >> 24]);
2779 if (mycpu->gd_cpuid != apic_id) {
2780 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2781 kprintf("SMP: apic_id = %d\n", apic_id);
2782 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2783 panic("cpuid mismatch! boom!!");
2786 /* Initialize AP's local APIC for irq's */
2789 /* Set memory range attributes for this CPU to match the BSP */
2790 mem_range_AP_init();
2793 * Once we go active we must process any IPIQ messages that may
2794 * have been queued, because no actual IPI will occur until we
2795 * set our bit in the smp_active_mask. If we don't the IPI
2796 * message interlock could be left set which would also prevent
2799 * The idle loop doesn't expect the BGL to be held and while
2800 * lwkt_switch() normally cleans things up this is a special case
2801 * because we returning almost directly into the idle loop.
2803 * The idle thread is never placed on the runq, make sure
2804 * nothing we've done put it there.
2806 KKASSERT(get_mplock_count(curthread) == 1);
2807 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2810 * Enable interrupts here. idle_restore will also do it, but
2811 * doing it here lets us clean up any strays that got posted to
2812 * the CPU during the AP boot while we are still in a critical
2815 __asm __volatile("sti; pause; pause"::);
2816 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2818 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2819 lwkt_process_ipiq();
2822 * Releasing the mp lock lets the BSP finish up the SMP init
2825 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2829 * Get SMP fully working before we start initializing devices.
2837 kprintf("Finish MP startup\n");
2838 if (cpu_feature & CPUID_TSC)
2839 tsc0_offset = rdtsc();
2842 while (smp_active_mask != smp_startup_mask) {
2844 if (cpu_feature & CPUID_TSC)
2845 tsc0_offset = rdtsc();
2847 while (try_mplock() == 0)
2850 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2853 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2856 cpu_send_ipiq(int dcpu)
2858 if (CPUMASK(dcpu) & smp_active_mask)
2859 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2862 #if 0 /* single_apic_ipi_passive() not working yet */
2864 * Returns 0 on failure, 1 on success
2867 cpu_send_ipiq_passive(int dcpu)
2870 if (CPUMASK(dcpu) & smp_active_mask) {
2871 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2872 APIC_DELMODE_FIXED);
2879 mptable_bus_info_callback(void *xarg, const void *pos, int type)
2881 struct mptable_bus_info *bus_info = xarg;
2882 const struct BUSENTRY *ent;
2883 struct mptable_bus *bus;
2889 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2890 if (bus->mb_id == ent->bus_id) {
2891 kprintf("mptable_bus_info_alloc: duplicated bus id "
2892 "(%d)\n", bus->mb_id);
2898 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
2899 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2900 bus->mb_type = MPTABLE_BUS_PCI;
2901 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
2902 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2903 bus->mb_type = MPTABLE_BUS_ISA;
2907 bus->mb_id = ent->bus_id;
2908 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
2914 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
2918 bzero(bus_info, sizeof(*bus_info));
2919 TAILQ_INIT(&bus_info->mbi_list);
2921 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
2923 mptable_bus_info_free(bus_info);
2927 mptable_bus_info_free(struct mptable_bus_info *bus_info)
2929 struct mptable_bus *bus;
2931 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
2932 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
2937 struct mptable_lapic_cbarg1 {
2940 u_int ht_apicid_mask;
2944 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2946 const struct PROCENTRY *ent;
2947 struct mptable_lapic_cbarg1 *arg = xarg;
2953 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2957 if (ent->apic_id < 32) {
2958 arg->ht_apicid_mask |= 1 << ent->apic_id;
2959 } else if (arg->ht_fixup) {
2960 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2966 struct mptable_lapic_cbarg2 {
2973 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2975 const struct PROCENTRY *ent;
2976 struct mptable_lapic_cbarg2 *arg = xarg;
2982 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2983 KKASSERT(!arg->found_bsp);
2987 if (processor_entry(ent, arg->cpu))
2990 if (arg->logical_cpus) {
2991 struct PROCENTRY proc;
2995 * Create fake mptable processor entries
2996 * and feed them to processor_entry() to
2997 * enumerate the logical CPUs.
2999 bzero(&proc, sizeof(proc));
3001 proc.cpu_flags = PROCENTRY_FLAG_EN;
3002 proc.apic_id = ent->apic_id;
3004 for (i = 1; i < arg->logical_cpus; i++) {
3006 processor_entry(&proc, arg->cpu);
3014 mptable_lapic_default(void)
3016 int ap_apicid, bsp_apicid;
3018 mp_naps = 1; /* exclude BSP */
3020 /* Map local apic before the id field is accessed */
3021 lapic_map(DEFAULT_APIC_BASE);
3023 bsp_apicid = APIC_ID(lapic.id);
3024 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3027 mp_set_cpuids(0, bsp_apicid);
3028 /* one and only AP */
3029 mp_set_cpuids(1, ap_apicid);
3035 * ID_TO_CPU(N), APIC ID to logical CPU table
3036 * CPU_TO_ID(N), logical CPU to APIC ID table
3039 mptable_lapic_enumerate(struct lapic_enumerator *e)
3041 struct mptable_pos mpt;
3042 struct mptable_lapic_cbarg1 arg1;
3043 struct mptable_lapic_cbarg2 arg2;
3045 int error, logical_cpus = 0;
3046 vm_offset_t lapic_addr;
3048 if (mptable_use_default) {
3049 mptable_lapic_default();
3053 error = mptable_map(&mpt);
3055 panic("mptable_lapic_enumerate mptable_map failed\n");
3056 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3060 /* Save local apic address */
3061 lapic_addr = (vm_offset_t)cth->apic_address;
3062 KKASSERT(lapic_addr != 0);
3065 * Find out how many CPUs do we have
3067 bzero(&arg1, sizeof(arg1));
3068 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3070 error = mptable_iterate_entries(cth,
3071 mptable_lapic_pass1_callback, &arg1);
3073 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3074 KKASSERT(arg1.cpu_count != 0);
3076 /* See if we need to fixup HT logical CPUs. */
3077 if (arg1.ht_fixup) {
3078 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3080 if (logical_cpus != 0)
3081 arg1.cpu_count *= logical_cpus;
3083 mp_naps = arg1.cpu_count;
3085 /* Qualify the numbers again, after possible HT fixup */
3086 if (mp_naps > MAXCPU) {
3087 kprintf("Warning: only using %d of %d available CPUs!\n",
3092 --mp_naps; /* subtract the BSP */
3095 * Link logical CPU id to local apic id
3097 bzero(&arg2, sizeof(arg2));
3099 arg2.logical_cpus = logical_cpus;
3101 error = mptable_iterate_entries(cth,
3102 mptable_lapic_pass2_callback, &arg2);
3104 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3105 KKASSERT(arg2.found_bsp);
3107 /* Map local apic */
3108 lapic_map(lapic_addr);
3110 mptable_unmap(&mpt);
3113 struct mptable_lapic_probe_cbarg {
3119 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
3121 const struct PROCENTRY *ent;
3122 struct mptable_lapic_probe_cbarg *arg = xarg;
3128 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
3132 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3133 if (arg->found_bsp) {
3134 kprintf("more than one BSP in base MP table\n");
3143 mptable_lapic_probe(struct lapic_enumerator *e)
3145 struct mptable_pos mpt;
3146 struct mptable_lapic_probe_cbarg arg;
3150 if (mptable_fps_phyaddr == 0)
3153 if (mptable_use_default)
3156 error = mptable_map(&mpt);
3159 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3164 if (cth->apic_address == 0)
3167 bzero(&arg, sizeof(arg));
3168 error = mptable_iterate_entries(cth,
3169 mptable_lapic_probe_callback, &arg);
3171 if (arg.cpu_count == 0) {
3172 kprintf("MP table contains no processor entries\n");
3174 } else if (!arg.found_bsp) {
3175 kprintf("MP table does not contains BSP entry\n");
3180 mptable_unmap(&mpt);
3184 static struct lapic_enumerator mptable_lapic_enumerator = {
3185 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3186 .lapic_probe = mptable_lapic_probe,
3187 .lapic_enumerate = mptable_lapic_enumerate
3191 mptable_lapic_enum_register(void)
3193 lapic_enumerator_register(&mptable_lapic_enumerator);
3195 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3196 mptable_lapic_enum_register, 0);
3199 mptable_ioapic_list_callback(void *xarg, const void *pos, int type)
3201 const struct IOAPICENTRY *ent;
3202 struct mptable_ioapic *nioapic, *ioapic;
3208 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
3211 if (ent->apic_address == 0) {
3212 kprintf("mptable_ioapic_create_list: zero IOAPIC addr\n");
3216 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3217 if (ioapic->mio_apic_id == ent->apic_id) {
3218 kprintf("mptable_ioapic_create_list: duplicated "
3219 "apic id %d\n", ioapic->mio_apic_id);
3222 if (ioapic->mio_addr == (uint32_t)ent->apic_address) {
3223 kprintf("mptable_ioapic_create_list: overlapped "
3224 "IOAPIC addr 0x%08x", ioapic->mio_addr);
3229 nioapic = kmalloc(sizeof(*nioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3230 nioapic->mio_apic_id = ent->apic_id;
3231 nioapic->mio_addr = (uint32_t)ent->apic_address;
3234 * Create IOAPIC list in ascending order of APIC ID
3236 TAILQ_FOREACH_REVERSE(ioapic, &mptable_ioapic_list,
3237 mptable_ioapic_list, mio_link) {
3238 if (nioapic->mio_apic_id > ioapic->mio_apic_id) {
3239 TAILQ_INSERT_AFTER(&mptable_ioapic_list,
3240 ioapic, nioapic, mio_link);
3245 TAILQ_INSERT_HEAD(&mptable_ioapic_list, nioapic, mio_link);
3251 mptable_ioapic_create_list(void)
3253 struct mptable_ioapic *ioapic;
3254 struct mptable_pos mpt;
3257 if (mptable_fps_phyaddr == 0)
3260 if (mptable_use_default) {
3261 ioapic = kmalloc(sizeof(*ioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3262 ioapic->mio_idx = 0;
3263 ioapic->mio_apic_id = 0; /* NOTE: any value is ok here */
3264 ioapic->mio_addr = 0xfec00000; /* XXX magic number */
3266 TAILQ_INSERT_HEAD(&mptable_ioapic_list, ioapic, mio_link);
3270 error = mptable_map(&mpt);
3272 panic("mptable_ioapic_create_list: mptable_map failed\n");
3273 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3275 error = mptable_iterate_entries(mpt.mp_cth,
3276 mptable_ioapic_list_callback, NULL);
3278 while ((ioapic = TAILQ_FIRST(&mptable_ioapic_list)) != NULL) {
3279 TAILQ_REMOVE(&mptable_ioapic_list, ioapic, mio_link);
3280 kfree(ioapic, M_DEVBUF);
3286 * Assign index number for each IOAPIC
3289 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3290 ioapic->mio_idx = idx;
3294 mptable_unmap(&mpt);
3296 SYSINIT(mptable_ioapic_list, SI_BOOT2_PRESMP, SI_ORDER_SECOND,
3297 mptable_ioapic_create_list, 0);
3300 mptable_pci_int_callback(void *xarg, const void *pos, int type)
3302 const struct mptable_bus_info *bus_info = xarg;
3303 const struct mptable_ioapic *ioapic;
3304 const struct mptable_bus *bus;
3305 struct mptable_pci_int *pci_int;
3306 const struct INTENTRY *ent;
3307 int pci_pin, pci_dev;
3313 if (ent->int_type != 0)
3316 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
3317 if (bus->mb_type == MPTABLE_BUS_PCI &&
3318 bus->mb_id == ent->src_bus_id)
3324 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3325 if (ioapic->mio_apic_id == ent->dst_apic_id)
3328 if (ioapic == NULL) {
3329 kprintf("MPTABLE: warning PCI int dst apic id %d "
3330 "does not exist\n", ent->dst_apic_id);
3334 pci_pin = ent->src_bus_irq & 0x3;
3335 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
3337 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
3338 if (pci_int->mpci_bus == ent->src_bus_id &&
3339 pci_int->mpci_dev == pci_dev &&
3340 pci_int->mpci_pin == pci_pin) {
3341 if (pci_int->mpci_ioapic_idx == ioapic->mio_idx &&
3342 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
3343 kprintf("MPTABLE: warning duplicated "
3344 "PCI int entry for "
3345 "bus %d, dev %d, pin %d\n",
3351 kprintf("mptable_pci_int_register: "
3352 "conflict PCI int entry for "
3353 "bus %d, dev %d, pin %d, "
3354 "IOAPIC %d.%d -> %d.%d\n",
3358 pci_int->mpci_ioapic_idx,
3359 pci_int->mpci_ioapic_pin,
3367 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
3369 pci_int->mpci_bus = ent->src_bus_id;
3370 pci_int->mpci_dev = pci_dev;
3371 pci_int->mpci_pin = pci_pin;
3372 pci_int->mpci_ioapic_idx = ioapic->mio_idx;
3373 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
3375 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
3381 mptable_pci_int_register(void)
3383 struct mptable_bus_info bus_info;
3384 const struct mptable_bus *bus;
3385 struct mptable_pci_int *pci_int;
3386 struct mptable_pos mpt;
3387 int error, force_pci0, npcibus;
3390 if (mptable_fps_phyaddr == 0)
3393 if (mptable_use_default)
3396 if (TAILQ_EMPTY(&mptable_ioapic_list))
3399 error = mptable_map(&mpt);
3401 panic("mptable_pci_int_register: mptable_map failed\n");
3402 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3406 mptable_bus_info_alloc(cth, &bus_info);
3407 if (TAILQ_EMPTY(&bus_info.mbi_list))
3411 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
3412 if (bus->mb_type == MPTABLE_BUS_PCI)
3416 mptable_bus_info_free(&bus_info);
3418 } else if (npcibus == 1) {
3422 error = mptable_iterate_entries(cth,
3423 mptable_pci_int_callback, &bus_info);
3425 mptable_bus_info_free(&bus_info);
3428 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
3429 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
3430 kfree(pci_int, M_DEVBUF);
3436 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
3437 pci_int->mpci_bus = 0;
3440 mptable_unmap(&mpt);
3442 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3443 mptable_pci_int_register, 0);
3445 struct mptable_ioapic_probe_cbarg {
3446 const struct mptable_bus_info *bus_info;
3450 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
3452 struct mptable_ioapic_probe_cbarg *arg = xarg;
3453 const struct mptable_ioapic *ioapic;
3454 const struct mptable_bus *bus;
3455 const struct INTENTRY *ent;
3461 if (ent->int_type != 0)
3464 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3465 if (bus->mb_type == MPTABLE_BUS_ISA &&
3466 bus->mb_id == ent->src_bus_id)
3472 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3473 if (ioapic->mio_apic_id == ent->dst_apic_id)
3476 if (ioapic == NULL) {
3477 kprintf("MPTABLE: warning ISA int dst apic id %d "
3478 "does not exist\n", ent->dst_apic_id);
3482 /* XXX magic number */
3483 if (ent->src_bus_irq >= 16) {
3484 kprintf("mptable_ioapic_probe: invalid ISA irq (%d)\n",
3492 mptable_ioapic_probe(struct ioapic_enumerator *e)
3494 struct mptable_ioapic_probe_cbarg arg;
3495 struct mptable_bus_info bus_info;
3496 struct mptable_pos mpt;
3500 if (mptable_fps_phyaddr == 0)
3503 if (mptable_use_default)
3506 if (TAILQ_EMPTY(&mptable_ioapic_list))
3509 error = mptable_map(&mpt);
3511 panic("mptable_ioapic_probe: mptable_map failed\n");
3512 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3516 mptable_bus_info_alloc(cth, &bus_info);
3518 bzero(&arg, sizeof(arg));
3519 arg.bus_info = &bus_info;
3521 error = mptable_iterate_entries(cth,
3522 mptable_ioapic_probe_callback, &arg);
3524 mptable_bus_info_free(&bus_info);
3525 mptable_unmap(&mpt);
3530 struct mptable_ioapic_int_cbarg {
3531 const struct mptable_bus_info *bus_info;
3536 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
3538 struct mptable_ioapic_int_cbarg *arg = xarg;
3539 const struct mptable_ioapic *ioapic;
3540 const struct mptable_bus *bus;
3541 const struct INTENTRY *ent;
3549 if (ent->int_type != 0)
3552 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3553 if (bus->mb_type == MPTABLE_BUS_ISA &&
3554 bus->mb_id == ent->src_bus_id)
3560 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3561 if (ioapic->mio_apic_id == ent->dst_apic_id)
3564 if (ioapic == NULL) {
3565 kprintf("MPTABLE: warning ISA int dst apic id %d "
3566 "does not exist\n", ent->dst_apic_id);
3570 if (!ioapic_use_old) {
3573 if (ent->dst_apic_int >= ioapic->mio_npin) {
3574 panic("mptable_ioapic_enumerate: invalid I/O APIC "
3575 "pin %d, should be < %d",
3576 ent->dst_apic_int, ioapic->mio_npin);
3578 gsi = ioapic->mio_gsi_base + ent->dst_apic_int;
3580 if (ent->src_bus_irq != gsi) {
3582 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3583 ent->src_bus_irq, gsi);
3585 ioapic_intsrc(ent->src_bus_irq, gsi);
3588 /* XXX rough estimation */
3589 if (ent->src_bus_irq != ent->dst_apic_int) {
3591 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3592 ent->src_bus_irq, ent->dst_apic_int);
3600 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
3602 struct mptable_bus_info bus_info;
3603 struct mptable_ioapic *ioapic;
3604 struct mptable_pos mpt;
3608 KKASSERT(mptable_fps_phyaddr != 0);
3609 KKASSERT(!TAILQ_EMPTY(&mptable_ioapic_list));
3611 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3612 if (!ioapic_use_old) {
3613 const struct mptable_ioapic *prev_ioapic;
3617 addr = ioapic_map(ioapic->mio_addr);
3619 ver = ioapic_read(addr, IOAPIC_VER);
3620 ioapic->mio_npin = ((ver & IOART_VER_MAXREDIR)
3621 >> MAXREDIRSHIFT) + 1;
3623 prev_ioapic = TAILQ_PREV(ioapic,
3624 mptable_ioapic_list, mio_link);
3625 if (prev_ioapic == NULL) {
3626 ioapic->mio_gsi_base = 0;
3628 ioapic->mio_gsi_base =
3629 prev_ioapic->mio_gsi_base +
3630 prev_ioapic->mio_npin;
3632 ioapic_add(addr, ioapic->mio_gsi_base,
3636 kprintf("MPTABLE: IOAPIC addr 0x%08x, "
3637 "apic id %d, idx %d, gsi base %d, npin %d\n",
3639 ioapic->mio_apic_id,
3641 ioapic->mio_gsi_base,
3646 if (mptable_use_default) {
3648 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
3649 ioapic_intsrc(0, 2);
3653 error = mptable_map(&mpt);
3655 panic("mptable_ioapic_probe: mptable_map failed\n");
3656 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3660 mptable_bus_info_alloc(cth, &bus_info);
3662 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
3664 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
3665 ioapic_intsrc(0, 2);
3667 struct mptable_ioapic_int_cbarg arg;
3669 bzero(&arg, sizeof(arg));
3670 arg.bus_info = &bus_info;
3672 error = mptable_iterate_entries(cth,
3673 mptable_ioapic_int_callback, &arg);
3675 panic("mptable_ioapic_int failed\n");
3677 if (arg.ioapic_nint == 0) {
3679 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
3682 ioapic_intsrc(0, 2);
3686 mptable_bus_info_free(&bus_info);
3688 mptable_unmap(&mpt);
3691 static struct ioapic_enumerator mptable_ioapic_enumerator = {
3692 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
3693 .ioapic_probe = mptable_ioapic_probe,
3694 .ioapic_enumerate = mptable_ioapic_enumerate
3698 mptable_ioapic_enum_register(void)
3700 ioapic_enumerator_register(&mptable_ioapic_enumerator);
3702 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3703 mptable_ioapic_enum_register, 0);