2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_SIZE (0x10000)
75 #define BIOS_COUNT (BIOS_SIZE/4)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
82 #define PROCENTRY_FLAG_EN 0x01
83 #define PROCENTRY_FLAG_BP 0x02
84 #define IOAPICENTRY_FLAG_EN 0x01
87 /* MP Floating Pointer Structure */
88 typedef struct MPFPS {
101 /* MP Configuration Table Header */
102 typedef struct MPCTH {
104 u_short base_table_length;
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
119 typedef struct PROCENTRY {
124 u_long cpu_signature;
125 u_long feature_flags;
130 typedef struct BUSENTRY {
136 typedef struct IOAPICENTRY {
142 } *io_apic_entry_ptr;
144 typedef struct INTENTRY {
154 /* descriptions of MP basetable entries */
155 typedef struct BASETABLE_ENTRY {
164 vm_size_t mp_cth_mapsz;
167 typedef int (*mptable_iter_func)(void *, const void *, int);
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
175 #if defined(CHECK_POINTS)
176 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
179 #define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
187 #define CHECK_PRINT(S); \
188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
197 #else /* CHECK_POINTS */
199 #define CHECK_INIT(D)
200 #define CHECK_PRINT(S)
202 #endif /* CHECK_POINTS */
205 * Values to send to the POST hardware.
207 #define MP_BOOTADDRESS_POST 0x10
208 #define MP_PROBE_POST 0x11
209 #define MPTABLE_PASS1_POST 0x12
211 #define MP_START_POST 0x13
212 #define MP_ENABLE_POST 0x14
213 #define MPTABLE_PASS2_POST 0x15
215 #define START_ALL_APS_POST 0x16
216 #define INSTALL_AP_TRAMP_POST 0x17
217 #define START_AP_POST 0x18
219 #define MP_ANNOUNCE_POST 0x19
221 static int madt_probe_test;
222 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
224 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
225 int current_postcode;
227 /** XXX FIXME: what system files declare these??? */
228 extern struct region_descriptor r_gdt, r_idt;
230 int mp_naps; /* # of Applications processors */
232 static int mp_nbusses; /* # of busses */
233 int mp_napics; /* # of IO APICs */
235 static vm_offset_t cpu_apic_address;
237 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
238 u_int32_t *io_apic_versions;
242 u_int32_t cpu_apic_versions[MAXCPU];
244 extern int64_t tsc_offsets[];
246 extern u_long ebda_addr;
249 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
253 * APIC ID logical/physical mapping structures.
254 * We oversize these to simplify boot-time config.
256 int cpu_num_to_apic_id[NAPICID];
258 int io_num_to_apic_id[NAPICID];
260 int apic_id_to_logical[NAPICID];
262 /* AP uses this during bootstrap. Do not staticize. */
266 /* Hotwire a 0->4MB V==P mapping */
267 extern pt_entry_t *KPTphys;
270 * SMP page table page. Setup by locore to point to a page table
271 * page from which we allocate per-cpu privatespace areas io_apics,
275 #define IO_MAPPING_START_INDEX \
276 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
278 extern pt_entry_t *SMPpt;
279 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
281 struct pcb stoppcbs[MAXCPU];
283 static basetable_entry basetable_entry_types[] =
285 {0, 20, "Processor"},
293 * Local data and functions.
296 static u_int boot_address;
297 static u_int base_memory;
298 static int mp_finish;
300 static void mp_enable(u_int boot_addr);
302 static int mptable_iterate_entries(const mpcth_t,
303 mptable_iter_func, void *);
304 static int mptable_probe(void);
305 static int mptable_check(vm_paddr_t);
306 static int mptable_search_sig(u_int32_t target, int count);
307 static int mptable_hyperthread_fixup(u_int, int);
308 static void mptable_pass1(struct mptable_pos *);
309 static void mptable_pass2(struct mptable_pos *);
310 static void mptable_default(int type);
311 static void mptable_fix(void);
312 static int mptable_map(struct mptable_pos *, vm_paddr_t);
313 static void mptable_unmap(struct mptable_pos *);
314 static void mptable_lapic_enumerate(struct mptable_pos *);
315 static void mptable_lapic_default(void);
316 static void mptable_imcr(struct mptable_pos *);
319 static void setup_apic_irq_mapping(void);
320 static int apic_int_is_bus_type(int intr, int bus_type);
322 static int start_all_aps(u_int boot_addr);
323 static void install_ap_tramp(u_int boot_addr);
324 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
325 static void lapic_init(vm_offset_t);
327 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
328 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
329 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
332 * Calculate usable address in base memory for AP trampoline code.
335 mp_bootaddress(u_int basemem)
337 POSTCODE(MP_BOOTADDRESS_POST);
339 base_memory = basemem;
341 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
342 if ((base_memory - boot_address) < bootMP_size)
343 boot_address -= 4096; /* not enough, lower by 4k */
350 * Look for an Intel MP spec table (ie, SMP capable hardware).
359 * Make sure our SMPpt[] page table is big enough to hold all the
362 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
364 POSTCODE(MP_PROBE_POST);
366 /* see if EBDA exists */
367 if (ebda_addr != 0) {
368 /* search first 1K of EBDA */
369 target = (u_int32_t)ebda_addr;
370 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
373 /* last 1K of base memory, effective 'top of base' passed in */
374 target = (u_int32_t)(base_memory - 0x400);
375 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
379 /* search the BIOS */
380 target = (u_int32_t)BIOS_BASE;
381 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
388 struct mptable_check_cbarg {
394 mptable_check_callback(void *xarg, const void *pos, int type)
396 const struct PROCENTRY *ent;
397 struct mptable_check_cbarg *arg = xarg;
403 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
407 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
408 if (arg->found_bsp) {
409 kprintf("more than one BSP in base MP table\n");
418 mptable_check(vm_paddr_t mpfps_paddr)
420 struct mptable_pos mpt;
421 struct mptable_check_cbarg arg;
425 if (mpfps_paddr == 0)
428 error = mptable_map(&mpt, mpfps_paddr);
432 if (mpt.mp_fps->mpfb1 != 0)
440 if (cth->apic_address == 0)
443 bzero(&arg, sizeof(arg));
444 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
446 if (arg.cpu_count == 0) {
447 kprintf("MP table contains no processor entries\n");
449 } else if (!arg.found_bsp) {
450 kprintf("MP table does not contains BSP entry\n");
460 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
462 int count, total_size;
463 const void *position;
465 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
466 total_size = cth->base_table_length - sizeof(struct MPCTH);
467 position = (const uint8_t *)cth + sizeof(struct MPCTH);
468 count = cth->entry_count;
473 KKASSERT(total_size >= 0);
474 if (total_size == 0) {
475 kprintf("invalid base MP table, "
476 "entry count and length mismatch\n");
480 type = *(const uint8_t *)position;
482 case 0: /* processor_entry */
483 case 1: /* bus_entry */
484 case 2: /* io_apic_entry */
485 case 3: /* int_entry */
486 case 4: /* int_entry */
489 kprintf("unknown base MP table entry type %d\n", type);
493 if (total_size < basetable_entry_types[type].length) {
494 kprintf("invalid base MP table length, "
495 "does not contain all entries\n");
498 total_size -= basetable_entry_types[type].length;
500 error = func(arg, position, type);
504 position = (const uint8_t *)position +
505 basetable_entry_types[type].length;
512 * Startup the SMP processors.
517 POSTCODE(MP_START_POST);
518 mp_enable(boot_address);
523 * Print various information about the SMP system hardware and setup.
530 POSTCODE(MP_ANNOUNCE_POST);
532 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
533 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
534 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
535 kprintf(", at 0x%08x\n", cpu_apic_address);
536 for (x = 1; x <= mp_naps; ++x) {
537 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
538 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
539 kprintf(", at 0x%08x\n", cpu_apic_address);
543 for (x = 0; x < mp_napics; ++x) {
544 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
545 kprintf(", version: 0x%08x", io_apic_versions[x]);
546 kprintf(", at 0x%08x\n", io_apic_address[x]);
549 kprintf(" Warning: APIC I/O disabled\n");
554 * AP cpu's call this to sync up protected mode.
556 * WARNING! We must ensure that the cpu is sufficiently initialized to
557 * be able to use to the FP for our optimized bzero/bcopy code before
558 * we enter more mainstream C code.
560 * WARNING! %fs is not set up on entry. This routine sets up %fs.
566 int x, myid = bootAP;
568 struct mdglobaldata *md;
569 struct privatespace *ps;
571 ps = &CPU_prvspace[myid];
573 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
574 gdt_segs[GPROC0_SEL].ssd_base =
575 (int) &ps->mdglobaldata.gd_common_tss;
576 ps->mdglobaldata.mi.gd_prvspace = ps;
578 for (x = 0; x < NGDT; x++) {
579 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
582 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
583 r_gdt.rd_base = (int) &gdt[myid * NGDT];
584 lgdt(&r_gdt); /* does magic intra-segment return */
589 mdcpu->gd_currentldt = _default_ldt;
591 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
592 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
594 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
596 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
597 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
598 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
599 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
600 md->gd_common_tssd = *md->gd_tss_gdt;
604 * Set to a known state:
605 * Set by mpboot.s: CR0_PG, CR0_PE
606 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
609 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
611 pmap_set_opt(); /* PSE/4MB pages, etc */
613 /* set up CPU registers and state */
616 /* set up FPU state on the AP */
617 npxinit(__INITIAL_NPXCW__);
619 /* set up SSE registers */
623 /*******************************************************************
624 * local functions and data
628 * start the SMP system
631 mp_enable(u_int boot_addr)
637 vm_paddr_t mpfps_paddr;
639 POSTCODE(MP_ENABLE_POST);
641 if (madt_probe_test) {
644 mpfps_paddr = mptable_probe();
645 if (mptable_check(mpfps_paddr))
650 struct mptable_pos mpt;
652 mptable_map(&mpt, mpfps_paddr);
654 mptable_lapic_enumerate(&mpt);
659 * Examine the MP table for needed info
666 /* Post scan cleanup */
669 vm_paddr_t madt_paddr;
670 vm_offset_t lapic_addr;
673 madt_paddr = madt_probe();
675 panic("mp_enable: madt_probe failed\n");
677 lapic_addr = madt_pass1(madt_paddr);
679 panic("mp_enable: no local apic (madt)!\n");
681 lapic_init(lapic_addr);
683 bsp_apic_id = APIC_ID(lapic.id);
684 if (madt_pass2(madt_paddr, bsp_apic_id))
685 panic("mp_enable: madt_pass2 failed\n");
690 setup_apic_irq_mapping();
692 /* fill the LOGICAL io_apic_versions table */
693 for (apic = 0; apic < mp_napics; ++apic) {
694 ux = io_apic_read(apic, IOAPIC_VER);
695 io_apic_versions[apic] = ux;
696 io_apic_set_id(apic, IO_TO_ID(apic));
699 /* program each IO APIC in the system */
700 for (apic = 0; apic < mp_napics; ++apic)
701 if (io_apic_setup(apic) < 0)
702 panic("IO APIC setup failure");
707 * These are required for SMP operation
710 /* install a 'Spurious INTerrupt' vector */
711 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
712 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
714 /* install an inter-CPU IPI for TLB invalidation */
715 setidt(XINVLTLB_OFFSET, Xinvltlb,
716 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
718 /* install an inter-CPU IPI for IPIQ messaging */
719 setidt(XIPIQ_OFFSET, Xipiq,
720 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
722 /* install a timer vector */
723 setidt(XTIMER_OFFSET, Xtimer,
724 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
726 /* install an inter-CPU IPI for CPU stop/restart */
727 setidt(XCPUSTOP_OFFSET, Xcpustop,
728 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
730 /* start each Application Processor */
731 start_all_aps(boot_addr);
736 * look for the MP spec signature
739 /* string defined by the Intel MP Spec as identifying the MP table */
740 #define MP_SIG 0x5f504d5f /* _MP_ */
741 #define NEXT(X) ((X) += 4)
743 mptable_search_sig(u_int32_t target, int count)
749 KKASSERT(target != 0);
751 map_size = count * sizeof(u_int32_t);
752 addr = pmap_mapdev((vm_paddr_t)target, map_size);
755 for (x = 0; x < count; NEXT(x)) {
756 if (addr[x] == MP_SIG) {
757 /* make array index a byte index */
758 ret = target + (x * sizeof(u_int32_t));
763 pmap_unmapdev((vm_offset_t)addr, map_size);
768 typedef struct BUSDATA {
770 enum busTypes bus_type;
773 typedef struct INTDATA {
783 typedef struct BUSTYPENAME {
788 static bus_type_name bus_type_table[] =
794 {UNKNOWN_BUSTYPE, "---"},
797 {UNKNOWN_BUSTYPE, "---"},
798 {UNKNOWN_BUSTYPE, "---"},
799 {UNKNOWN_BUSTYPE, "---"},
800 {UNKNOWN_BUSTYPE, "---"},
801 {UNKNOWN_BUSTYPE, "---"},
803 {UNKNOWN_BUSTYPE, "---"},
804 {UNKNOWN_BUSTYPE, "---"},
805 {UNKNOWN_BUSTYPE, "---"},
806 {UNKNOWN_BUSTYPE, "---"},
808 {UNKNOWN_BUSTYPE, "---"}
810 /* from MP spec v1.4, table 5-1 */
811 static int default_data[7][5] =
813 /* nbus, id0, type0, id1, type1 */
814 {1, 0, ISA, 255, 255},
815 {1, 0, EISA, 255, 255},
816 {1, 0, EISA, 255, 255},
817 {1, 0, MCA, 255, 255},
819 {2, 0, EISA, 1, PCI},
827 static bus_datum *bus_data;
829 /* the IO INT data, one entry per possible APIC INTerrupt */
830 static io_int *io_apic_ints;
835 static int processor_entry (const struct PROCENTRY *entry, int cpu);
837 static int bus_entry (const struct BUSENTRY *entry, int bus);
838 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
839 static int int_entry (const struct INTENTRY *entry, int intr);
841 static int lookup_bus_type (char *name);
846 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
848 const struct IOAPICENTRY *ioapic_ent;
851 case 1: /* bus_entry */
855 case 2: /* io_apic_entry */
857 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
858 io_apic_address[mp_napics++] =
859 (vm_offset_t)ioapic_ent->apic_address;
863 case 3: /* int_entry */
873 * 1st pass on motherboard's Intel MP specification table.
882 mptable_pass1(struct mptable_pos *mpt)
888 POSTCODE(MPTABLE_PASS1_POST);
891 KKASSERT(fps != NULL);
893 /* clear various tables */
894 for (x = 0; x < NAPICID; ++x)
895 io_apic_address[x] = ~0; /* IO APIC address table */
901 /* check for use of 'default' configuration */
902 if (fps->mpfb1 != 0) {
903 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
904 mp_nbusses = default_data[fps->mpfb1 - 1][0];
910 error = mptable_iterate_entries(mpt->mp_cth,
911 mptable_ioapic_pass1_callback, NULL);
913 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
920 struct mptable_ioapic2_cbarg {
927 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
929 struct mptable_ioapic2_cbarg *arg = xarg;
933 if (bus_entry(pos, arg->bus))
938 if (io_apic_entry(pos, arg->apic))
943 if (int_entry(pos, arg->intr))
953 * 2nd pass on motherboard's Intel MP specification table.
956 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
957 * IO_TO_ID(N), logical IO to APIC ID table
962 mptable_pass2(struct mptable_pos *mpt)
965 struct mptable_ioapic2_cbarg arg;
969 POSTCODE(MPTABLE_PASS2_POST);
972 KKASSERT(fps != NULL);
974 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
976 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
977 M_DEVBUF, M_WAITOK | M_ZERO);
978 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
980 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
983 for (x = 0; x < mp_napics; x++)
984 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
986 /* clear various tables */
987 for (x = 0; x < NAPICID; ++x) {
988 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
989 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
992 /* clear bus data table */
993 for (x = 0; x < mp_nbusses; ++x)
994 bus_data[x].bus_id = 0xff;
996 /* clear IO APIC INT table */
997 for (x = 0; x < (nintrs + 1); ++x) {
998 io_apic_ints[x].int_type = 0xff;
999 io_apic_ints[x].int_vector = 0xff;
1002 /* check for use of 'default' configuration */
1003 if (fps->mpfb1 != 0) {
1004 mptable_default(fps->mpfb1);
1008 bzero(&arg, sizeof(arg));
1009 error = mptable_iterate_entries(mpt->mp_cth,
1010 mptable_ioapic_pass2_callback, &arg);
1012 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1017 * Check if we should perform a hyperthreading "fix-up" to
1018 * enumerate any logical CPU's that aren't already listed
1021 * XXX: We assume that all of the physical CPUs in the
1022 * system have the same number of logical CPUs.
1024 * XXX: We assume that APIC ID's are allocated such that
1025 * the APIC ID's for a physical processor are aligned
1026 * with the number of logical CPU's in the processor.
1029 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1031 int i, id, lcpus_max, logical_cpus;
1033 if ((cpu_feature & CPUID_HTT) == 0)
1036 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1040 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1042 * INSTRUCTION SET REFERENCE, A-M (#253666)
1043 * Page 3-181, Table 3-20
1044 * "The nearest power-of-2 integer that is not smaller
1045 * than EBX[23:16] is the number of unique initial APIC
1046 * IDs reserved for addressing different logical
1047 * processors in a physical package."
1049 for (i = 0; ; ++i) {
1050 if ((1 << i) >= lcpus_max) {
1057 KKASSERT(cpu_count != 0);
1058 if (cpu_count == lcpus_max) {
1059 /* We have nothing to fix */
1061 } else if (cpu_count == 1) {
1062 /* XXX this may be incorrect */
1063 logical_cpus = lcpus_max;
1065 int cur, prev, dist;
1068 * Calculate the distances between two nearest
1069 * APIC IDs. If all such distances are same,
1070 * then it is the number of missing cpus that
1071 * we are going to fill later.
1073 dist = cur = prev = -1;
1074 for (id = 0; id < MAXCPU; ++id) {
1075 if ((id_mask & 1 << id) == 0)
1080 int new_dist = cur - prev;
1086 * Make sure that all distances
1087 * between two nearest APIC IDs
1090 if (dist != new_dist)
1098 /* Must be power of 2 */
1099 if (dist & (dist - 1))
1102 /* Can't exceed CPU package capacity */
1103 if (dist > lcpus_max)
1104 logical_cpus = lcpus_max;
1106 logical_cpus = dist;
1110 * For each APIC ID of a CPU that is set in the mask,
1111 * scan the other candidate APIC ID's for this
1112 * physical processor. If any of those ID's are
1113 * already in the table, then kill the fixup.
1115 for (id = 0; id < MAXCPU; id++) {
1116 if ((id_mask & 1 << id) == 0)
1118 /* First, make sure we are on a logical_cpus boundary. */
1119 if (id % logical_cpus != 0)
1121 for (i = id + 1; i < id + logical_cpus; i++)
1122 if ((id_mask & 1 << i) != 0)
1125 return logical_cpus;
1129 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1133 vm_size_t cth_mapsz = 0;
1135 bzero(mpt, sizeof(*mpt));
1137 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1138 if (fps->pap != 0) {
1140 * Map configuration table header to get
1141 * the base table size
1143 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1144 cth_mapsz = cth->base_table_length;
1145 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1147 if (cth_mapsz < sizeof(*cth)) {
1148 kprintf("invalid base MP table length %d\n",
1150 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1155 * Map the base table
1157 cth = pmap_mapdev(fps->pap, cth_mapsz);
1162 mpt->mp_cth_mapsz = cth_mapsz;
1168 mptable_unmap(struct mptable_pos *mpt)
1170 if (mpt->mp_cth != NULL) {
1171 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1173 mpt->mp_cth_mapsz = 0;
1175 if (mpt->mp_fps != NULL) {
1176 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1184 assign_apic_irq(int apic, int intpin, int irq)
1188 if (int_to_apicintpin[irq].ioapic != -1)
1189 panic("assign_apic_irq: inconsistent table");
1191 int_to_apicintpin[irq].ioapic = apic;
1192 int_to_apicintpin[irq].int_pin = intpin;
1193 int_to_apicintpin[irq].apic_address = ioapic[apic];
1194 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1196 for (x = 0; x < nintrs; x++) {
1197 if ((io_apic_ints[x].int_type == 0 ||
1198 io_apic_ints[x].int_type == 3) &&
1199 io_apic_ints[x].int_vector == 0xff &&
1200 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1201 io_apic_ints[x].dst_apic_int == intpin)
1202 io_apic_ints[x].int_vector = irq;
1207 revoke_apic_irq(int irq)
1213 if (int_to_apicintpin[irq].ioapic == -1)
1214 panic("revoke_apic_irq: inconsistent table");
1216 oldapic = int_to_apicintpin[irq].ioapic;
1217 oldintpin = int_to_apicintpin[irq].int_pin;
1219 int_to_apicintpin[irq].ioapic = -1;
1220 int_to_apicintpin[irq].int_pin = 0;
1221 int_to_apicintpin[irq].apic_address = NULL;
1222 int_to_apicintpin[irq].redirindex = 0;
1224 for (x = 0; x < nintrs; x++) {
1225 if ((io_apic_ints[x].int_type == 0 ||
1226 io_apic_ints[x].int_type == 3) &&
1227 io_apic_ints[x].int_vector != 0xff &&
1228 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1229 io_apic_ints[x].dst_apic_int == oldintpin)
1230 io_apic_ints[x].int_vector = 0xff;
1238 allocate_apic_irq(int intr)
1244 if (io_apic_ints[intr].int_vector != 0xff)
1245 return; /* Interrupt handler already assigned */
1247 if (io_apic_ints[intr].int_type != 0 &&
1248 (io_apic_ints[intr].int_type != 3 ||
1249 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1250 io_apic_ints[intr].dst_apic_int == 0)))
1251 return; /* Not INT or ExtInt on != (0, 0) */
1254 while (irq < APIC_INTMAPSIZE &&
1255 int_to_apicintpin[irq].ioapic != -1)
1258 if (irq >= APIC_INTMAPSIZE)
1259 return; /* No free interrupt handlers */
1261 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1262 intpin = io_apic_ints[intr].dst_apic_int;
1264 assign_apic_irq(apic, intpin, irq);
1265 io_apic_setup_intpin(apic, intpin);
1270 swap_apic_id(int apic, int oldid, int newid)
1277 return; /* Nothing to do */
1279 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1280 apic, oldid, newid);
1282 /* Swap physical APIC IDs in interrupt entries */
1283 for (x = 0; x < nintrs; x++) {
1284 if (io_apic_ints[x].dst_apic_id == oldid)
1285 io_apic_ints[x].dst_apic_id = newid;
1286 else if (io_apic_ints[x].dst_apic_id == newid)
1287 io_apic_ints[x].dst_apic_id = oldid;
1290 /* Swap physical APIC IDs in IO_TO_ID mappings */
1291 for (oapic = 0; oapic < mp_napics; oapic++)
1292 if (IO_TO_ID(oapic) == newid)
1295 if (oapic < mp_napics) {
1296 kprintf("Changing APIC ID for IO APIC #%d from "
1297 "%d to %d in MP table\n",
1298 oapic, newid, oldid);
1299 IO_TO_ID(oapic) = oldid;
1301 IO_TO_ID(apic) = newid;
1306 fix_id_to_io_mapping(void)
1310 for (x = 0; x < NAPICID; x++)
1313 for (x = 0; x <= mp_naps; x++)
1314 if (CPU_TO_ID(x) < NAPICID)
1315 ID_TO_IO(CPU_TO_ID(x)) = x;
1317 for (x = 0; x < mp_napics; x++)
1318 if (IO_TO_ID(x) < NAPICID)
1319 ID_TO_IO(IO_TO_ID(x)) = x;
1324 first_free_apic_id(void)
1328 for (freeid = 0; freeid < NAPICID; freeid++) {
1329 for (x = 0; x <= mp_naps; x++)
1330 if (CPU_TO_ID(x) == freeid)
1334 for (x = 0; x < mp_napics; x++)
1335 if (IO_TO_ID(x) == freeid)
1346 io_apic_id_acceptable(int apic, int id)
1348 int cpu; /* Logical CPU number */
1349 int oapic; /* Logical IO APIC number for other IO APIC */
1352 return 0; /* Out of range */
1354 for (cpu = 0; cpu <= mp_naps; cpu++)
1355 if (CPU_TO_ID(cpu) == id)
1356 return 0; /* Conflict with CPU */
1358 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1359 if (IO_TO_ID(oapic) == id)
1360 return 0; /* Conflict with other APIC */
1362 return 1; /* ID is acceptable for IO APIC */
1367 io_apic_find_int_entry(int apic, int pin)
1371 /* search each of the possible INTerrupt sources */
1372 for (x = 0; x < nintrs; ++x) {
1373 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1374 (pin == io_apic_ints[x].dst_apic_int))
1375 return (&io_apic_ints[x]);
1383 * parse an Intel MP specification table
1391 int apic; /* IO APIC unit number */
1392 int freeid; /* Free physical APIC ID */
1393 int physid; /* Current physical IO APIC ID */
1395 int bus_0 = 0; /* Stop GCC warning */
1396 int bus_pci = 0; /* Stop GCC warning */
1400 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1401 * did it wrong. The MP spec says that when more than 1 PCI bus
1402 * exists the BIOS must begin with bus entries for the PCI bus and use
1403 * actual PCI bus numbering. This implies that when only 1 PCI bus
1404 * exists the BIOS can choose to ignore this ordering, and indeed many
1405 * MP motherboards do ignore it. This causes a problem when the PCI
1406 * sub-system makes requests of the MP sub-system based on PCI bus
1407 * numbers. So here we look for the situation and renumber the
1408 * busses and associated INTs in an effort to "make it right".
1411 /* find bus 0, PCI bus, count the number of PCI busses */
1412 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1413 if (bus_data[x].bus_id == 0) {
1416 if (bus_data[x].bus_type == PCI) {
1422 * bus_0 == slot of bus with ID of 0
1423 * bus_pci == slot of last PCI bus encountered
1426 /* check the 1 PCI bus case for sanity */
1427 /* if it is number 0 all is well */
1428 if (num_pci_bus == 1 &&
1429 bus_data[bus_pci].bus_id != 0) {
1431 /* mis-numbered, swap with whichever bus uses slot 0 */
1433 /* swap the bus entry types */
1434 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1435 bus_data[bus_0].bus_type = PCI;
1437 /* swap each relavant INTerrupt entry */
1438 id = bus_data[bus_pci].bus_id;
1439 for (x = 0; x < nintrs; ++x) {
1440 if (io_apic_ints[x].src_bus_id == id) {
1441 io_apic_ints[x].src_bus_id = 0;
1443 else if (io_apic_ints[x].src_bus_id == 0) {
1444 io_apic_ints[x].src_bus_id = id;
1449 /* Assign IO APIC IDs.
1451 * First try the existing ID. If a conflict is detected, try
1452 * the ID in the MP table. If a conflict is still detected, find
1455 * We cannot use the ID_TO_IO table before all conflicts has been
1456 * resolved and the table has been corrected.
1458 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1460 /* First try to use the value set by the BIOS */
1461 physid = io_apic_get_id(apic);
1462 if (io_apic_id_acceptable(apic, physid)) {
1463 if (IO_TO_ID(apic) != physid)
1464 swap_apic_id(apic, IO_TO_ID(apic), physid);
1468 /* Then check if the value in the MP table is acceptable */
1469 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1472 /* Last resort, find a free APIC ID and use it */
1473 freeid = first_free_apic_id();
1474 if (freeid >= NAPICID)
1475 panic("No free physical APIC IDs found");
1477 if (io_apic_id_acceptable(apic, freeid)) {
1478 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1481 panic("Free physical APIC ID not usable");
1483 fix_id_to_io_mapping();
1485 /* detect and fix broken Compaq MP table */
1486 if (apic_int_type(0, 0) == -1) {
1487 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1488 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1489 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1490 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1491 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1492 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1494 } else if (apic_int_type(0, 0) == 0) {
1495 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1496 for (x = 0; x < nintrs; ++x)
1497 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1498 (0 == io_apic_ints[x].dst_apic_int)) {
1499 io_apic_ints[x].int_type = 3;
1500 io_apic_ints[x].int_vector = 0xff;
1506 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1507 * controllers universally come in pairs. If IRQ 14 is specified
1508 * as an ISA interrupt, then IRQ 15 had better be too.
1510 * [ Shuttle XPC / AMD Athlon X2 ]
1511 * The MPTable is missing an entry for IRQ 15. Note that the
1512 * ACPI table has an entry for both 14 and 15.
1514 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1515 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1516 io14 = io_apic_find_int_entry(0, 14);
1517 io_apic_ints[nintrs] = *io14;
1518 io_apic_ints[nintrs].src_bus_irq = 15;
1519 io_apic_ints[nintrs].dst_apic_int = 15;
1527 /* Assign low level interrupt handlers */
1529 setup_apic_irq_mapping(void)
1535 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1536 int_to_apicintpin[x].ioapic = -1;
1537 int_to_apicintpin[x].int_pin = 0;
1538 int_to_apicintpin[x].apic_address = NULL;
1539 int_to_apicintpin[x].redirindex = 0;
1542 /* First assign ISA/EISA interrupts */
1543 for (x = 0; x < nintrs; x++) {
1544 int_vector = io_apic_ints[x].src_bus_irq;
1545 if (int_vector < APIC_INTMAPSIZE &&
1546 io_apic_ints[x].int_vector == 0xff &&
1547 int_to_apicintpin[int_vector].ioapic == -1 &&
1548 (apic_int_is_bus_type(x, ISA) ||
1549 apic_int_is_bus_type(x, EISA)) &&
1550 io_apic_ints[x].int_type == 0) {
1551 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1552 io_apic_ints[x].dst_apic_int,
1557 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1558 for (x = 0; x < nintrs; x++) {
1559 if (io_apic_ints[x].dst_apic_int == 0 &&
1560 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1561 io_apic_ints[x].int_vector == 0xff &&
1562 int_to_apicintpin[0].ioapic == -1 &&
1563 io_apic_ints[x].int_type == 3) {
1564 assign_apic_irq(0, 0, 0);
1568 /* PCI interrupt assignment is deferred */
1574 mp_set_cpuids(int cpu_id, int apic_id)
1576 CPU_TO_ID(cpu_id) = apic_id;
1577 ID_TO_CPU(apic_id) = cpu_id;
1581 processor_entry(const struct PROCENTRY *entry, int cpu)
1585 /* check for usability */
1586 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1589 /* check for BSP flag */
1590 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1591 mp_set_cpuids(0, entry->apic_id);
1592 return 0; /* its already been counted */
1595 /* add another AP to list, if less than max number of CPUs */
1596 else if (cpu < MAXCPU) {
1597 mp_set_cpuids(cpu, entry->apic_id);
1607 bus_entry(const struct BUSENTRY *entry, int bus)
1612 /* encode the name into an index */
1613 for (x = 0; x < 6; ++x) {
1614 if ((c = entry->bus_type[x]) == ' ')
1620 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1621 panic("unknown bus type: '%s'", name);
1623 bus_data[bus].bus_id = entry->bus_id;
1624 bus_data[bus].bus_type = x;
1630 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1632 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1635 IO_TO_ID(apic) = entry->apic_id;
1636 ID_TO_IO(entry->apic_id) = apic;
1644 lookup_bus_type(char *name)
1648 for (x = 0; x < MAX_BUSTYPE; ++x)
1649 if (strcmp(bus_type_table[x].name, name) == 0)
1650 return bus_type_table[x].type;
1652 return UNKNOWN_BUSTYPE;
1658 int_entry(const struct INTENTRY *entry, int intr)
1662 io_apic_ints[intr].int_type = entry->int_type;
1663 io_apic_ints[intr].int_flags = entry->int_flags;
1664 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1665 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1666 if (entry->dst_apic_id == 255) {
1667 /* This signal goes to all IO APICS. Select an IO APIC
1668 with sufficient number of interrupt pins */
1669 for (apic = 0; apic < mp_napics; apic++)
1670 if (((io_apic_read(apic, IOAPIC_VER) &
1671 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1672 entry->dst_apic_int)
1674 if (apic < mp_napics)
1675 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1677 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1679 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1680 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1686 apic_int_is_bus_type(int intr, int bus_type)
1690 for (bus = 0; bus < mp_nbusses; ++bus)
1691 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1692 && ((int) bus_data[bus].bus_type == bus_type))
1699 * Given a traditional ISA INT mask, return an APIC mask.
1702 isa_apic_mask(u_int isa_mask)
1707 #if defined(SKIP_IRQ15_REDIRECT)
1708 if (isa_mask == (1 << 15)) {
1709 kprintf("skipping ISA IRQ15 redirect\n");
1712 #endif /* SKIP_IRQ15_REDIRECT */
1714 isa_irq = ffs(isa_mask); /* find its bit position */
1715 if (isa_irq == 0) /* doesn't exist */
1717 --isa_irq; /* make it zero based */
1719 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1723 return (1 << apic_pin); /* convert pin# to a mask */
1727 * Determine which APIC pin an ISA/EISA INT is attached to.
1729 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1730 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1731 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1732 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1734 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1736 isa_apic_irq(int isa_irq)
1740 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1741 if (INTTYPE(intr) == 0) { /* standard INT */
1742 if (SRCBUSIRQ(intr) == isa_irq) {
1743 if (apic_int_is_bus_type(intr, ISA) ||
1744 apic_int_is_bus_type(intr, EISA)) {
1745 if (INTIRQ(intr) == 0xff)
1746 return -1; /* unassigned */
1747 return INTIRQ(intr); /* found */
1752 return -1; /* NOT found */
1757 * Determine which APIC pin a PCI INT is attached to.
1759 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1760 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1761 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1763 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1767 --pciInt; /* zero based */
1769 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1770 if ((INTTYPE(intr) == 0) /* standard INT */
1771 && (SRCBUSID(intr) == pciBus)
1772 && (SRCBUSDEVICE(intr) == pciDevice)
1773 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1774 if (apic_int_is_bus_type(intr, PCI)) {
1775 if (INTIRQ(intr) == 0xff)
1776 allocate_apic_irq(intr);
1777 if (INTIRQ(intr) == 0xff)
1778 return -1; /* unassigned */
1779 return INTIRQ(intr); /* exact match */
1784 return -1; /* NOT found */
1788 next_apic_irq(int irq)
1795 for (intr = 0; intr < nintrs; intr++) {
1796 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1798 bus = SRCBUSID(intr);
1799 bustype = apic_bus_type(bus);
1800 if (bustype != ISA &&
1806 if (intr >= nintrs) {
1809 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1810 if (INTTYPE(ointr) != 0)
1812 if (bus != SRCBUSID(ointr))
1814 if (bustype == PCI) {
1815 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1817 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1820 if (bustype == ISA || bustype == EISA) {
1821 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1824 if (INTPIN(intr) == INTPIN(ointr))
1828 if (ointr >= nintrs) {
1831 return INTIRQ(ointr);
1846 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1849 * Exactly what this means is unclear at this point. It is a solution
1850 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1851 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1852 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1856 undirect_isa_irq(int rirq)
1860 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1861 /** FIXME: tickle the MB redirector chip */
1865 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1872 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1875 undirect_pci_irq(int rirq)
1879 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1881 /** FIXME: tickle the MB redirector chip */
1885 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1895 * given a bus ID, return:
1896 * the bus type if found
1900 apic_bus_type(int id)
1904 for (x = 0; x < mp_nbusses; ++x)
1905 if (bus_data[x].bus_id == id)
1906 return bus_data[x].bus_type;
1912 * given a LOGICAL APIC# and pin#, return:
1913 * the associated src bus ID if found
1917 apic_src_bus_id(int apic, int pin)
1921 /* search each of the possible INTerrupt sources */
1922 for (x = 0; x < nintrs; ++x)
1923 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1924 (pin == io_apic_ints[x].dst_apic_int))
1925 return (io_apic_ints[x].src_bus_id);
1927 return -1; /* NOT found */
1931 * given a LOGICAL APIC# and pin#, return:
1932 * the associated src bus IRQ if found
1936 apic_src_bus_irq(int apic, int pin)
1940 for (x = 0; x < nintrs; x++)
1941 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1942 (pin == io_apic_ints[x].dst_apic_int))
1943 return (io_apic_ints[x].src_bus_irq);
1945 return -1; /* NOT found */
1950 * given a LOGICAL APIC# and pin#, return:
1951 * the associated INTerrupt type if found
1955 apic_int_type(int apic, int pin)
1959 /* search each of the possible INTerrupt sources */
1960 for (x = 0; x < nintrs; ++x) {
1961 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1962 (pin == io_apic_ints[x].dst_apic_int))
1963 return (io_apic_ints[x].int_type);
1965 return -1; /* NOT found */
1969 * Return the IRQ associated with an APIC pin
1972 apic_irq(int apic, int pin)
1977 for (x = 0; x < nintrs; ++x) {
1978 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1979 (pin == io_apic_ints[x].dst_apic_int)) {
1980 res = io_apic_ints[x].int_vector;
1983 if (apic != int_to_apicintpin[res].ioapic)
1984 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1985 if (pin != int_to_apicintpin[res].int_pin)
1986 panic("apic_irq inconsistent table (2)");
1995 * given a LOGICAL APIC# and pin#, return:
1996 * the associated trigger mode if found
2000 apic_trigger(int apic, int pin)
2004 /* search each of the possible INTerrupt sources */
2005 for (x = 0; x < nintrs; ++x)
2006 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2007 (pin == io_apic_ints[x].dst_apic_int))
2008 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2010 return -1; /* NOT found */
2015 * given a LOGICAL APIC# and pin#, return:
2016 * the associated 'active' level if found
2020 apic_polarity(int apic, int pin)
2024 /* search each of the possible INTerrupt sources */
2025 for (x = 0; x < nintrs; ++x)
2026 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2027 (pin == io_apic_ints[x].dst_apic_int))
2028 return (io_apic_ints[x].int_flags & 0x03);
2030 return -1; /* NOT found */
2036 * set data according to MP defaults
2037 * FIXME: probably not complete yet...
2040 mptable_default(int type)
2042 #if defined(APIC_IO)
2047 kprintf(" MP default config type: %d\n", type);
2050 kprintf(" bus: ISA, APIC: 82489DX\n");
2053 kprintf(" bus: EISA, APIC: 82489DX\n");
2056 kprintf(" bus: EISA, APIC: 82489DX\n");
2059 kprintf(" bus: MCA, APIC: 82489DX\n");
2062 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2065 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2068 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2071 kprintf(" future type\n");
2077 /* one and only IO APIC */
2078 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2081 * sanity check, refer to MP spec section 3.6.6, last paragraph
2082 * necessary as some hardware isn't properly setting up the IO APIC
2084 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2085 if (io_apic_id != 2) {
2087 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2088 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2089 io_apic_set_id(0, 2);
2092 IO_TO_ID(0) = io_apic_id;
2093 ID_TO_IO(io_apic_id) = 0;
2095 /* fill out bus entries */
2104 bus_data[0].bus_id = default_data[type - 1][1];
2105 bus_data[0].bus_type = default_data[type - 1][2];
2106 bus_data[1].bus_id = default_data[type - 1][3];
2107 bus_data[1].bus_type = default_data[type - 1][4];
2110 /* case 4: case 7: MCA NOT supported */
2111 default: /* illegal/reserved */
2112 panic("BAD default MP config: %d", type);
2116 /* general cases from MP v1.4, table 5-2 */
2117 for (pin = 0; pin < 16; ++pin) {
2118 io_apic_ints[pin].int_type = 0;
2119 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2120 io_apic_ints[pin].src_bus_id = 0;
2121 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2122 io_apic_ints[pin].dst_apic_id = io_apic_id;
2123 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2126 /* special cases from MP v1.4, table 5-2 */
2128 io_apic_ints[2].int_type = 0xff; /* N/C */
2129 io_apic_ints[13].int_type = 0xff; /* N/C */
2130 #if !defined(APIC_MIXED_MODE)
2132 panic("sorry, can't support type 2 default yet");
2133 #endif /* APIC_MIXED_MODE */
2136 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2139 io_apic_ints[0].int_type = 0xff; /* N/C */
2141 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2142 #endif /* APIC_IO */
2146 * Map a physical memory address representing I/O into KVA. The I/O
2147 * block is assumed not to cross a page boundary.
2150 permanent_io_mapping(vm_paddr_t pa)
2156 KKASSERT(pa < 0x100000000LL);
2158 pgeflag = 0; /* not used for SMP yet */
2161 * If the requested physical address has already been incidently
2162 * mapped, just use the existing mapping. Otherwise create a new
2165 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2166 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2167 ((vm_offset_t)pa & PG_FRAME)) {
2171 if (i == SMPpt_alloc_index) {
2172 if (i == NPTEPG - 2) {
2173 panic("permanent_io_mapping: We ran out of space"
2176 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2177 ((vm_offset_t)pa & PG_FRAME));
2178 ++SMPpt_alloc_index;
2180 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2181 ((vm_offset_t)pa & PAGE_MASK);
2182 return ((void *)vaddr);
2186 * start each AP in our list
2189 start_all_aps(u_int boot_addr)
2193 u_char mpbiosreason;
2194 u_long mpbioswarmvec;
2195 struct mdglobaldata *gd;
2196 struct privatespace *ps;
2200 POSTCODE(START_ALL_APS_POST);
2202 /* Initialize BSP's local APIC */
2203 apic_initialize(TRUE);
2205 /* install the AP 1st level boot code */
2206 install_ap_tramp(boot_addr);
2209 /* save the current value of the warm-start vector */
2210 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2211 outb(CMOS_REG, BIOS_RESET);
2212 mpbiosreason = inb(CMOS_DATA);
2214 /* set up temporary P==V mapping for AP boot */
2215 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2216 kptbase = (uintptr_t)(void *)KPTphys;
2217 for (x = 0; x < NKPT; x++) {
2218 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2219 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2224 for (x = 1; x <= mp_naps; ++x) {
2226 /* This is a bit verbose, it will go away soon. */
2228 /* first page of AP's private space */
2229 pg = x * i386_btop(sizeof(struct privatespace));
2231 /* allocate new private data page(s) */
2232 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2233 MDGLOBALDATA_BASEALLOC_SIZE);
2234 /* wire it into the private page table page */
2235 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2236 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2237 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2239 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2241 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2242 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2243 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2244 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2246 /* allocate and set up an idle stack data page */
2247 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2248 for (i = 0; i < UPAGES; i++) {
2249 SMPpt[pg + 4 + i] = (pt_entry_t)
2250 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2253 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2254 bzero(gd, sizeof(*gd));
2255 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2257 /* prime data page for it to use */
2258 mi_gdinit(&gd->mi, x);
2260 gd->gd_CMAP1 = &SMPpt[pg + 0];
2261 gd->gd_CMAP2 = &SMPpt[pg + 1];
2262 gd->gd_CMAP3 = &SMPpt[pg + 2];
2263 gd->gd_PMAP1 = &SMPpt[pg + 3];
2264 gd->gd_CADDR1 = ps->CPAGE1;
2265 gd->gd_CADDR2 = ps->CPAGE2;
2266 gd->gd_CADDR3 = ps->CPAGE3;
2267 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2268 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2269 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2271 /* setup a vector to our boot code */
2272 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2273 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2274 outb(CMOS_REG, BIOS_RESET);
2275 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2278 * Setup the AP boot stack
2280 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2283 /* attempt to start the Application Processor */
2284 CHECK_INIT(99); /* setup checkpoints */
2285 if (!start_ap(gd, boot_addr)) {
2286 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2287 CHECK_PRINT("trace"); /* show checkpoints */
2288 /* better panic as the AP may be running loose */
2289 kprintf("panic y/n? [y] ");
2290 if (cngetc() != 'n')
2293 CHECK_PRINT("trace"); /* show checkpoints */
2295 /* record its version info */
2296 cpu_apic_versions[x] = cpu_apic_versions[0];
2299 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2302 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2303 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2306 ncpus2_shift = shift;
2307 ncpus2 = 1 << shift;
2308 ncpus2_mask = ncpus2 - 1;
2310 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2311 if ((1 << shift) < ncpus)
2313 ncpus_fit = 1 << shift;
2314 ncpus_fit_mask = ncpus_fit - 1;
2316 /* build our map of 'other' CPUs */
2317 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2318 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2319 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2321 /* fill in our (BSP) APIC version */
2322 cpu_apic_versions[0] = lapic.version;
2324 /* restore the warmstart vector */
2325 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2326 outb(CMOS_REG, BIOS_RESET);
2327 outb(CMOS_DATA, mpbiosreason);
2330 * NOTE! The idlestack for the BSP was setup by locore. Finish
2331 * up, clean out the P==V mapping we did earlier.
2333 for (x = 0; x < NKPT; x++)
2337 /* number of APs actually started */
2343 * load the 1st level AP boot code into base memory.
2346 /* targets for relocation */
2347 extern void bigJump(void);
2348 extern void bootCodeSeg(void);
2349 extern void bootDataSeg(void);
2350 extern void MPentry(void);
2351 extern u_int MP_GDT;
2352 extern u_int mp_gdtbase;
2355 install_ap_tramp(u_int boot_addr)
2358 int size = *(int *) ((u_long) & bootMP_size);
2359 u_char *src = (u_char *) ((u_long) bootMP);
2360 u_char *dst = (u_char *) boot_addr + KERNBASE;
2361 u_int boot_base = (u_int) bootMP;
2366 POSTCODE(INSTALL_AP_TRAMP_POST);
2368 for (x = 0; x < size; ++x)
2372 * modify addresses in code we just moved to basemem. unfortunately we
2373 * need fairly detailed info about mpboot.s for this to work. changes
2374 * to mpboot.s might require changes here.
2377 /* boot code is located in KERNEL space */
2378 dst = (u_char *) boot_addr + KERNBASE;
2380 /* modify the lgdt arg */
2381 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2382 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2384 /* modify the ljmp target for MPentry() */
2385 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2386 *dst32 = ((u_int) MPentry - KERNBASE);
2388 /* modify the target for boot code segment */
2389 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2390 dst8 = (u_int8_t *) (dst16 + 1);
2391 *dst16 = (u_int) boot_addr & 0xffff;
2392 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2394 /* modify the target for boot data segment */
2395 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2396 dst8 = (u_int8_t *) (dst16 + 1);
2397 *dst16 = (u_int) boot_addr & 0xffff;
2398 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2403 * this function starts the AP (application processor) identified
2404 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2405 * to accomplish this. This is necessary because of the nuances
2406 * of the different hardware we might encounter. It ain't pretty,
2407 * but it seems to work.
2409 * NOTE: eventually an AP gets to ap_init(), which is called just
2410 * before the AP goes into the LWKT scheduler's idle loop.
2413 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2417 u_long icr_lo, icr_hi;
2419 POSTCODE(START_AP_POST);
2421 /* get the PHYSICAL APIC ID# */
2422 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2424 /* calculate the vector */
2425 vector = (boot_addr >> 12) & 0xff;
2427 /* Make sure the target cpu sees everything */
2431 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2432 * and running the target CPU. OR this INIT IPI might be latched (P5
2433 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2437 /* setup the address for the target AP */
2438 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2439 icr_hi |= (physical_cpu << 24);
2440 lapic.icr_hi = icr_hi;
2442 /* do an INIT IPI: assert RESET */
2443 icr_lo = lapic.icr_lo & 0xfff00000;
2444 lapic.icr_lo = icr_lo | 0x0000c500;
2446 /* wait for pending status end */
2447 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2450 /* do an INIT IPI: deassert RESET */
2451 lapic.icr_lo = icr_lo | 0x00008500;
2453 /* wait for pending status end */
2454 u_sleep(10000); /* wait ~10mS */
2455 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2459 * next we do a STARTUP IPI: the previous INIT IPI might still be
2460 * latched, (P5 bug) this 1st STARTUP would then terminate
2461 * immediately, and the previously started INIT IPI would continue. OR
2462 * the previous INIT IPI has already run. and this STARTUP IPI will
2463 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2467 /* do a STARTUP IPI */
2468 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2469 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2471 u_sleep(200); /* wait ~200uS */
2474 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2475 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2476 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2477 * recognized after hardware RESET or INIT IPI.
2480 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2481 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2483 u_sleep(200); /* wait ~200uS */
2485 /* wait for it to start, see ap_init() */
2486 set_apic_timer(5000000);/* == 5 seconds */
2487 while (read_apic_timer()) {
2488 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2489 return 1; /* return SUCCESS */
2491 return 0; /* return FAILURE */
2496 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2498 * If for some reason we were unable to start all cpus we cannot safely
2499 * use broadcast IPIs.
2505 if (smp_startup_mask == smp_active_mask) {
2506 all_but_self_ipi(XINVLTLB_OFFSET);
2508 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2509 APIC_DELMODE_FIXED);
2515 * When called the executing CPU will send an IPI to all other CPUs
2516 * requesting that they halt execution.
2518 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2520 * - Signals all CPUs in map to stop.
2521 * - Waits for each to stop.
2528 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2529 * from executing at same time.
2532 stop_cpus(u_int map)
2534 map &= smp_active_mask;
2536 /* send the Xcpustop IPI to all CPUs in map */
2537 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2539 while ((stopped_cpus & map) != map)
2547 * Called by a CPU to restart stopped CPUs.
2549 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2551 * - Signals all CPUs in map to restart.
2552 * - Waits for each to restart.
2560 restart_cpus(u_int map)
2562 /* signal other cpus to restart */
2563 started_cpus = map & smp_active_mask;
2565 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2572 * This is called once the mpboot code has gotten us properly relocated
2573 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2574 * and when it returns the scheduler will call the real cpu_idle() main
2575 * loop for the idlethread. Interrupts are disabled on entry and should
2576 * remain disabled at return.
2584 * Adjust smp_startup_mask to signal the BSP that we have started
2585 * up successfully. Note that we do not yet hold the BGL. The BSP
2586 * is waiting for our signal.
2588 * We can't set our bit in smp_active_mask yet because we are holding
2589 * interrupts physically disabled and remote cpus could deadlock
2590 * trying to send us an IPI.
2592 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2596 * Interlock for finalization. Wait until mp_finish is non-zero,
2597 * then get the MP lock.
2599 * Note: We are in a critical section.
2601 * Note: We have to synchronize td_mpcount to our desired MP state
2602 * before calling cpu_try_mplock().
2604 * Note: we are the idle thread, we can only spin.
2606 * Note: The load fence is memory volatile and prevents the compiler
2607 * from improperly caching mp_finish, and the cpu from improperly
2610 while (mp_finish == 0)
2612 ++curthread->td_mpcount;
2613 while (cpu_try_mplock() == 0)
2616 if (cpu_feature & CPUID_TSC) {
2618 * The BSP is constantly updating tsc0_offset, figure out the
2619 * relative difference to synchronize ktrdump.
2621 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2624 /* BSP may have changed PTD while we're waiting for the lock */
2627 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2631 /* Build our map of 'other' CPUs. */
2632 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2634 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2636 /* A quick check from sanity claus */
2637 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2638 if (mycpu->gd_cpuid != apic_id) {
2639 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2640 kprintf("SMP: apic_id = %d\n", apic_id);
2641 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2642 panic("cpuid mismatch! boom!!");
2645 /* Initialize AP's local APIC for irq's */
2646 apic_initialize(FALSE);
2648 /* Set memory range attributes for this CPU to match the BSP */
2649 mem_range_AP_init();
2652 * Once we go active we must process any IPIQ messages that may
2653 * have been queued, because no actual IPI will occur until we
2654 * set our bit in the smp_active_mask. If we don't the IPI
2655 * message interlock could be left set which would also prevent
2658 * The idle loop doesn't expect the BGL to be held and while
2659 * lwkt_switch() normally cleans things up this is a special case
2660 * because we returning almost directly into the idle loop.
2662 * The idle thread is never placed on the runq, make sure
2663 * nothing we've done put it there.
2665 KKASSERT(curthread->td_mpcount == 1);
2666 smp_active_mask |= 1 << mycpu->gd_cpuid;
2669 * Enable interrupts here. idle_restore will also do it, but
2670 * doing it here lets us clean up any strays that got posted to
2671 * the CPU during the AP boot while we are still in a critical
2674 __asm __volatile("sti; pause; pause"::);
2675 mdcpu->gd_fpending = 0;
2676 mdcpu->gd_ipending = 0;
2678 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2679 lwkt_process_ipiq();
2682 * Releasing the mp lock lets the BSP finish up the SMP init
2685 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2689 * Get SMP fully working before we start initializing devices.
2697 kprintf("Finish MP startup\n");
2698 if (cpu_feature & CPUID_TSC)
2699 tsc0_offset = rdtsc();
2702 while (smp_active_mask != smp_startup_mask) {
2704 if (cpu_feature & CPUID_TSC)
2705 tsc0_offset = rdtsc();
2707 while (try_mplock() == 0)
2710 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2713 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2716 cpu_send_ipiq(int dcpu)
2718 if ((1 << dcpu) & smp_active_mask)
2719 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2722 #if 0 /* single_apic_ipi_passive() not working yet */
2724 * Returns 0 on failure, 1 on success
2727 cpu_send_ipiq_passive(int dcpu)
2730 if ((1 << dcpu) & smp_active_mask) {
2731 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2732 APIC_DELMODE_FIXED);
2738 struct mptable_lapic_cbarg1 {
2741 u_int ht_apicid_mask;
2745 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2747 const struct PROCENTRY *ent;
2748 struct mptable_lapic_cbarg1 *arg = xarg;
2754 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2758 if (ent->apic_id < 32) {
2759 arg->ht_apicid_mask |= 1 << ent->apic_id;
2760 } else if (arg->ht_fixup) {
2761 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2767 struct mptable_lapic_cbarg2 {
2774 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2776 const struct PROCENTRY *ent;
2777 struct mptable_lapic_cbarg2 *arg = xarg;
2783 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2784 KKASSERT(!arg->found_bsp);
2788 if (processor_entry(ent, arg->cpu))
2791 if (arg->logical_cpus) {
2792 struct PROCENTRY proc;
2796 * Create fake mptable processor entries
2797 * and feed them to processor_entry() to
2798 * enumerate the logical CPUs.
2800 bzero(&proc, sizeof(proc));
2802 proc.cpu_flags = PROCENTRY_FLAG_EN;
2803 proc.apic_id = ent->apic_id;
2805 for (i = 1; i < arg->logical_cpus; i++) {
2807 processor_entry(&proc, arg->cpu);
2815 mptable_lapic_default(void)
2817 int ap_apicid, bsp_apicid;
2819 mp_naps = 1; /* exclude BSP */
2821 /* Map local apic before the id field is accessed */
2822 lapic_init(DEFAULT_APIC_BASE);
2824 bsp_apicid = APIC_ID(lapic.id);
2825 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2828 mp_set_cpuids(0, bsp_apicid);
2829 /* one and only AP */
2830 mp_set_cpuids(1, ap_apicid);
2835 * cpu_apic_address (common to all CPUs)
2837 * ID_TO_CPU(N), APIC ID to logical CPU table
2838 * CPU_TO_ID(N), logical CPU to APIC ID table
2841 mptable_lapic_enumerate(struct mptable_pos *mpt)
2843 struct mptable_lapic_cbarg1 arg1;
2844 struct mptable_lapic_cbarg2 arg2;
2846 int error, logical_cpus = 0;
2847 vm_offset_t lapic_addr;
2849 KKASSERT(mpt->mp_fps != NULL);
2852 * Check for use of 'default' configuration
2854 if (mpt->mp_fps->mpfb1 != 0) {
2855 mptable_lapic_default();
2860 KKASSERT(cth != NULL);
2862 /* Save local apic address */
2863 lapic_addr = (vm_offset_t)cth->apic_address;
2864 KKASSERT(lapic_addr != 0);
2867 * Find out how many CPUs do we have
2869 bzero(&arg1, sizeof(arg1));
2870 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2872 error = mptable_iterate_entries(cth,
2873 mptable_lapic_pass1_callback, &arg1);
2875 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2876 KKASSERT(arg1.cpu_count != 0);
2878 /* See if we need to fixup HT logical CPUs. */
2879 if (arg1.ht_fixup) {
2880 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2882 if (logical_cpus != 0)
2883 arg1.cpu_count *= logical_cpus;
2885 mp_naps = arg1.cpu_count;
2887 /* Qualify the numbers again, after possible HT fixup */
2888 if (mp_naps > MAXCPU) {
2889 kprintf("Warning: only using %d of %d available CPUs!\n",
2894 --mp_naps; /* subtract the BSP */
2897 * Link logical CPU id to local apic id
2899 bzero(&arg2, sizeof(arg2));
2901 arg2.logical_cpus = logical_cpus;
2903 error = mptable_iterate_entries(cth,
2904 mptable_lapic_pass2_callback, &arg2);
2906 panic("mptable_iterate_entries(lapic_pass2) failed\n");
2907 KKASSERT(arg2.found_bsp);
2909 /* Map local apic */
2910 lapic_init(lapic_addr);
2914 mptable_imcr(struct mptable_pos *mpt)
2916 /* record whether PIC or virtual-wire mode */
2917 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2918 mpt->mp_fps->mpfb2 & 0x80);
2922 lapic_init(vm_offset_t lapic_addr)
2924 /* Local apic is mapped on last page */
2925 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
2926 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
2928 /* Just for printing */
2929 cpu_apic_address = lapic_addr;