2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/mpapic.h>
60 #include <machine/psl.h>
61 #include <machine/segments.h>
62 #include <machine/tss.h>
63 #include <machine/specialreg.h>
64 #include <machine/globaldata.h>
65 #include <machine/pmap_inval.h>
67 #include <machine/md_var.h> /* setidt() */
68 #include <machine_base/icu/icu.h> /* IPIs */
69 #include <machine/intr_machdep.h> /* IPIs */
71 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define BIOS_BASE (0xf0000)
78 #define BIOS_BASE2 (0xe0000)
79 #define BIOS_SIZE (0x10000)
80 #define BIOS_COUNT (BIOS_SIZE/4)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 #define PROCENTRY_FLAG_EN 0x01
88 #define PROCENTRY_FLAG_BP 0x02
89 #define IOAPICENTRY_FLAG_EN 0x01
92 /* MP Floating Pointer Structure */
93 typedef struct MPFPS {
106 /* MP Configuration Table Header */
107 typedef struct MPCTH {
109 u_short base_table_length;
113 u_char product_id[12];
114 void *oem_table_pointer;
115 u_short oem_table_size;
118 u_short extended_table_length;
119 u_char extended_table_checksum;
124 typedef struct PROCENTRY {
129 u_long cpu_signature;
130 u_long feature_flags;
135 typedef struct BUSENTRY {
141 typedef struct IOAPICENTRY {
147 } *io_apic_entry_ptr;
149 typedef struct INTENTRY {
159 /* descriptions of MP basetable entries */
160 typedef struct BASETABLE_ENTRY {
169 vm_size_t mp_cth_mapsz;
172 typedef int (*mptable_iter_func)(void *, const void *, int);
175 * this code MUST be enabled here and in mpboot.s.
176 * it follows the very early stages of AP boot by placing values in CMOS ram.
177 * it NORMALLY will never be needed and thus the primitive method for enabling.
180 #if defined(CHECK_POINTS)
181 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
182 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
184 #define CHECK_INIT(D); \
185 CHECK_WRITE(0x34, (D)); \
186 CHECK_WRITE(0x35, (D)); \
187 CHECK_WRITE(0x36, (D)); \
188 CHECK_WRITE(0x37, (D)); \
189 CHECK_WRITE(0x38, (D)); \
190 CHECK_WRITE(0x39, (D));
192 #define CHECK_PRINT(S); \
193 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
202 #else /* CHECK_POINTS */
204 #define CHECK_INIT(D)
205 #define CHECK_PRINT(S)
207 #endif /* CHECK_POINTS */
210 * Values to send to the POST hardware.
212 #define MP_BOOTADDRESS_POST 0x10
213 #define MP_PROBE_POST 0x11
214 #define MPTABLE_PASS1_POST 0x12
216 #define MP_START_POST 0x13
217 #define MP_ENABLE_POST 0x14
218 #define MPTABLE_PASS2_POST 0x15
220 #define START_ALL_APS_POST 0x16
221 #define INSTALL_AP_TRAMP_POST 0x17
222 #define START_AP_POST 0x18
224 #define MP_ANNOUNCE_POST 0x19
226 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
227 int current_postcode;
229 /** XXX FIXME: what system files declare these??? */
230 extern struct region_descriptor r_gdt, r_idt;
232 int mp_naps; /* # of Applications processors */
233 #ifdef SMP /* APIC-IO */
234 static int mp_nbusses; /* # of busses */
235 int mp_napics; /* # of IO APICs */
236 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
237 u_int32_t *io_apic_versions;
241 u_int32_t cpu_apic_versions[MAXCPU];
243 extern int64_t tsc_offsets[];
245 extern u_long ebda_addr;
247 #ifdef SMP /* APIC-IO */
248 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
252 * APIC ID logical/physical mapping structures.
253 * We oversize these to simplify boot-time config.
255 int cpu_num_to_apic_id[NAPICID];
256 #ifdef SMP /* APIC-IO */
257 int io_num_to_apic_id[NAPICID];
259 int apic_id_to_logical[NAPICID];
261 /* AP uses this during bootstrap. Do not staticize. */
265 /* Hotwire a 0->4MB V==P mapping */
266 extern pt_entry_t *KPTphys;
269 * SMP page table page. Setup by locore to point to a page table
270 * page from which we allocate per-cpu privatespace areas io_apics,
274 #define IO_MAPPING_START_INDEX \
275 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
277 extern pt_entry_t *SMPpt;
278 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
280 struct pcb stoppcbs[MAXCPU];
282 static basetable_entry basetable_entry_types[] =
284 {0, 20, "Processor"},
292 * Local data and functions.
295 static u_int boot_address;
296 static u_int base_memory;
297 static int mp_finish;
299 static void mp_enable(u_int boot_addr);
301 static int mptable_iterate_entries(const mpcth_t,
302 mptable_iter_func, void *);
303 static int mptable_search(void);
304 static int mptable_search_sig(u_int32_t target, int count);
305 static int mptable_hyperthread_fixup(cpumask_t, int);
306 #ifdef SMP /* APIC-IO */
307 static void mptable_pass1(struct mptable_pos *);
308 static void mptable_pass2(struct mptable_pos *);
309 static void mptable_default(int type);
310 static void mptable_fix(void);
312 static int mptable_map(struct mptable_pos *);
313 static void mptable_unmap(struct mptable_pos *);
314 static void mptable_imcr(struct mptable_pos *);
316 static int mptable_lapic_probe(struct lapic_enumerator *);
317 static void mptable_lapic_enumerate(struct lapic_enumerator *);
318 static void mptable_lapic_default(void);
320 #ifdef SMP /* APIC-IO */
321 static void setup_apic_irq_mapping(void);
322 static int apic_int_is_bus_type(int intr, int bus_type);
324 static int start_all_aps(u_int boot_addr);
325 static void install_ap_tramp(u_int boot_addr);
326 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
327 static int smitest(void);
329 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
330 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
331 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
333 static vm_paddr_t mptable_fps_phyaddr;
336 * Calculate usable address in base memory for AP trampoline code.
339 mp_bootaddress(u_int basemem)
341 POSTCODE(MP_BOOTADDRESS_POST);
343 base_memory = basemem;
345 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
346 if ((base_memory - boot_address) < bootMP_size)
347 boot_address -= 4096; /* not enough, lower by 4k */
356 KKASSERT(mptable_fps_phyaddr == 0);
357 mptable_fps_phyaddr = mptable_search();
359 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
362 * Look for an Intel MP spec table (ie, SMP capable hardware).
371 * Make sure our SMPpt[] page table is big enough to hold all the
374 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
376 POSTCODE(MP_PROBE_POST);
378 /* see if EBDA exists */
379 if (ebda_addr != 0) {
380 /* search first 1K of EBDA */
381 target = (u_int32_t)ebda_addr;
382 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
385 /* last 1K of base memory, effective 'top of base' passed in */
386 target = (u_int32_t)(base_memory - 0x400);
387 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
391 /* search the BIOS */
392 target = (u_int32_t)BIOS_BASE;
393 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
396 /* search the extended BIOS */
397 target = (u_int32_t)BIOS_BASE2;
398 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
406 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
408 int count, total_size;
409 const void *position;
411 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
412 total_size = cth->base_table_length - sizeof(struct MPCTH);
413 position = (const uint8_t *)cth + sizeof(struct MPCTH);
414 count = cth->entry_count;
419 KKASSERT(total_size >= 0);
420 if (total_size == 0) {
421 kprintf("invalid base MP table, "
422 "entry count and length mismatch\n");
426 type = *(const uint8_t *)position;
428 case 0: /* processor_entry */
429 case 1: /* bus_entry */
430 case 2: /* io_apic_entry */
431 case 3: /* int_entry */
432 case 4: /* int_entry */
435 kprintf("unknown base MP table entry type %d\n", type);
439 if (total_size < basetable_entry_types[type].length) {
440 kprintf("invalid base MP table length, "
441 "does not contain all entries\n");
444 total_size -= basetable_entry_types[type].length;
446 error = func(arg, position, type);
450 position = (const uint8_t *)position +
451 basetable_entry_types[type].length;
458 * Startup the SMP processors.
463 POSTCODE(MP_START_POST);
464 mp_enable(boot_address);
469 * Print various information about the SMP system hardware and setup.
476 POSTCODE(MP_ANNOUNCE_POST);
478 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
479 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
480 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
481 for (x = 1; x <= mp_naps; ++x) {
482 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
483 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
486 if (apic_io_enable) {
487 for (x = 0; x < mp_napics; ++x) {
488 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
489 kprintf(", version: 0x%08x", io_apic_versions[x]);
490 kprintf(", at 0x%08lx\n", io_apic_address[x]);
493 kprintf(" Warning: APIC I/O disabled\n");
498 * AP cpu's call this to sync up protected mode.
500 * WARNING! We must ensure that the cpu is sufficiently initialized to
501 * be able to use to the FP for our optimized bzero/bcopy code before
502 * we enter more mainstream C code.
504 * WARNING! %fs is not set up on entry. This routine sets up %fs.
510 int x, myid = bootAP;
512 struct mdglobaldata *md;
513 struct privatespace *ps;
515 ps = &CPU_prvspace[myid];
517 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
518 gdt_segs[GPROC0_SEL].ssd_base =
519 (int) &ps->mdglobaldata.gd_common_tss;
520 ps->mdglobaldata.mi.gd_prvspace = ps;
522 for (x = 0; x < NGDT; x++) {
523 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
526 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
527 r_gdt.rd_base = (int) &gdt[myid * NGDT];
528 lgdt(&r_gdt); /* does magic intra-segment return */
533 mdcpu->gd_currentldt = _default_ldt;
535 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
536 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
538 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
540 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
541 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
542 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
543 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
544 md->gd_common_tssd = *md->gd_tss_gdt;
548 * Set to a known state:
549 * Set by mpboot.s: CR0_PG, CR0_PE
550 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
553 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
555 pmap_set_opt(); /* PSE/4MB pages, etc */
557 /* set up CPU registers and state */
560 /* set up FPU state on the AP */
561 npxinit(__INITIAL_NPXCW__);
563 /* set up SSE registers */
567 /*******************************************************************
568 * local functions and data
572 * start the SMP system
575 mp_enable(u_int boot_addr)
579 struct mptable_pos mpt;
581 POSTCODE(MP_ENABLE_POST);
588 if (mptable_fps_phyaddr) {
593 if (apic_io_enable) {
595 if (!mptable_fps_phyaddr)
596 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
601 * Examine the MP table for needed info
608 /* Post scan cleanup */
611 setup_apic_irq_mapping();
613 /* fill the LOGICAL io_apic_versions table */
614 for (apic = 0; apic < mp_napics; ++apic) {
615 ux = ioapic_read(ioapic[apic], IOAPIC_VER);
616 io_apic_versions[apic] = ux;
617 io_apic_set_id(apic, IO_TO_ID(apic));
620 /* program each IO APIC in the system */
621 for (apic = 0; apic < mp_napics; ++apic)
622 if (io_apic_setup(apic) < 0)
623 panic("IO APIC setup failure");
628 * These are required for SMP operation
631 /* install a 'Spurious INTerrupt' vector */
632 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
633 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
635 /* install an inter-CPU IPI for TLB invalidation */
636 setidt(XINVLTLB_OFFSET, Xinvltlb,
637 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
639 /* install an inter-CPU IPI for IPIQ messaging */
640 setidt(XIPIQ_OFFSET, Xipiq,
641 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
643 /* install a timer vector */
644 setidt(XTIMER_OFFSET, Xtimer,
645 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
647 /* install an inter-CPU IPI for CPU stop/restart */
648 setidt(XCPUSTOP_OFFSET, Xcpustop,
649 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
651 /* start each Application Processor */
652 start_all_aps(boot_addr);
657 * look for the MP spec signature
660 /* string defined by the Intel MP Spec as identifying the MP table */
661 #define MP_SIG 0x5f504d5f /* _MP_ */
662 #define NEXT(X) ((X) += 4)
664 mptable_search_sig(u_int32_t target, int count)
670 KKASSERT(target != 0);
672 map_size = count * sizeof(u_int32_t);
673 addr = pmap_mapdev((vm_paddr_t)target, map_size);
676 for (x = 0; x < count; NEXT(x)) {
677 if (addr[x] == MP_SIG) {
678 /* make array index a byte index */
679 ret = target + (x * sizeof(u_int32_t));
684 pmap_unmapdev((vm_offset_t)addr, map_size);
689 typedef struct BUSDATA {
691 enum busTypes bus_type;
694 typedef struct INTDATA {
704 typedef struct BUSTYPENAME {
709 static bus_type_name bus_type_table[] =
715 {UNKNOWN_BUSTYPE, "---"},
718 {UNKNOWN_BUSTYPE, "---"},
719 {UNKNOWN_BUSTYPE, "---"},
720 {UNKNOWN_BUSTYPE, "---"},
721 {UNKNOWN_BUSTYPE, "---"},
722 {UNKNOWN_BUSTYPE, "---"},
724 {UNKNOWN_BUSTYPE, "---"},
725 {UNKNOWN_BUSTYPE, "---"},
726 {UNKNOWN_BUSTYPE, "---"},
727 {UNKNOWN_BUSTYPE, "---"},
729 {UNKNOWN_BUSTYPE, "---"}
731 /* from MP spec v1.4, table 5-1 */
732 static int default_data[7][5] =
734 /* nbus, id0, type0, id1, type1 */
735 {1, 0, ISA, 255, 255},
736 {1, 0, EISA, 255, 255},
737 {1, 0, EISA, 255, 255},
738 {1, 0, MCA, 255, 255},
740 {2, 0, EISA, 1, PCI},
746 static bus_datum *bus_data;
748 /* the IO INT data, one entry per possible APIC INTerrupt */
749 static io_int *io_apic_ints;
752 static int processor_entry (const struct PROCENTRY *entry, int cpu);
753 static int bus_entry (const struct BUSENTRY *entry, int bus);
754 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
755 static int int_entry (const struct INTENTRY *entry, int intr);
756 static int lookup_bus_type (char *name);
759 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
761 const struct IOAPICENTRY *ioapic_ent;
764 case 1: /* bus_entry */
768 case 2: /* io_apic_entry */
770 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
771 io_apic_address[mp_napics++] =
772 (vm_offset_t)ioapic_ent->apic_address;
776 case 3: /* int_entry */
784 * 1st pass on motherboard's Intel MP specification table.
793 mptable_pass1(struct mptable_pos *mpt)
798 POSTCODE(MPTABLE_PASS1_POST);
801 KKASSERT(fps != NULL);
803 /* clear various tables */
804 for (x = 0; x < NAPICID; ++x)
805 io_apic_address[x] = ~0; /* IO APIC address table */
811 /* check for use of 'default' configuration */
812 if (fps->mpfb1 != 0) {
813 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
814 mp_nbusses = default_data[fps->mpfb1 - 1][0];
820 error = mptable_iterate_entries(mpt->mp_cth,
821 mptable_ioapic_pass1_callback, NULL);
823 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
827 struct mptable_ioapic2_cbarg {
834 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
836 struct mptable_ioapic2_cbarg *arg = xarg;
840 if (bus_entry(pos, arg->bus))
845 if (io_apic_entry(pos, arg->apic))
850 if (int_entry(pos, arg->intr))
858 * 2nd pass on motherboard's Intel MP specification table.
861 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
862 * IO_TO_ID(N), logical IO to APIC ID table
867 mptable_pass2(struct mptable_pos *mpt)
869 struct mptable_ioapic2_cbarg arg;
873 POSTCODE(MPTABLE_PASS2_POST);
876 KKASSERT(fps != NULL);
878 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
880 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
881 M_DEVBUF, M_WAITOK | M_ZERO);
882 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
884 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
887 for (x = 0; x < mp_napics; x++)
888 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
890 /* clear various tables */
891 for (x = 0; x < NAPICID; ++x) {
892 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
893 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
896 /* clear bus data table */
897 for (x = 0; x < mp_nbusses; ++x)
898 bus_data[x].bus_id = 0xff;
900 /* clear IO APIC INT table */
901 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
902 io_apic_ints[x].int_type = 0xff;
903 io_apic_ints[x].int_vector = 0xff;
906 /* check for use of 'default' configuration */
907 if (fps->mpfb1 != 0) {
908 mptable_default(fps->mpfb1);
912 bzero(&arg, sizeof(arg));
913 error = mptable_iterate_entries(mpt->mp_cth,
914 mptable_ioapic_pass2_callback, &arg);
916 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
920 * Check if we should perform a hyperthreading "fix-up" to
921 * enumerate any logical CPU's that aren't already listed
924 * XXX: We assume that all of the physical CPUs in the
925 * system have the same number of logical CPUs.
927 * XXX: We assume that APIC ID's are allocated such that
928 * the APIC ID's for a physical processor are aligned
929 * with the number of logical CPU's in the processor.
932 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
934 int i, id, lcpus_max, logical_cpus;
936 if ((cpu_feature & CPUID_HTT) == 0)
939 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
943 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
945 * INSTRUCTION SET REFERENCE, A-M (#253666)
946 * Page 3-181, Table 3-20
947 * "The nearest power-of-2 integer that is not smaller
948 * than EBX[23:16] is the number of unique initial APIC
949 * IDs reserved for addressing different logical
950 * processors in a physical package."
953 if ((1 << i) >= lcpus_max) {
960 KKASSERT(cpu_count != 0);
961 if (cpu_count == lcpus_max) {
962 /* We have nothing to fix */
964 } else if (cpu_count == 1) {
965 /* XXX this may be incorrect */
966 logical_cpus = lcpus_max;
971 * Calculate the distances between two nearest
972 * APIC IDs. If all such distances are same,
973 * then it is the number of missing cpus that
974 * we are going to fill later.
976 dist = cur = prev = -1;
977 for (id = 0; id < MAXCPU; ++id) {
978 if ((id_mask & CPUMASK(id)) == 0)
983 int new_dist = cur - prev;
989 * Make sure that all distances
990 * between two nearest APIC IDs
993 if (dist != new_dist)
1001 /* Must be power of 2 */
1002 if (dist & (dist - 1))
1005 /* Can't exceed CPU package capacity */
1006 if (dist > lcpus_max)
1007 logical_cpus = lcpus_max;
1009 logical_cpus = dist;
1013 * For each APIC ID of a CPU that is set in the mask,
1014 * scan the other candidate APIC ID's for this
1015 * physical processor. If any of those ID's are
1016 * already in the table, then kill the fixup.
1018 for (id = 0; id < MAXCPU; id++) {
1019 if ((id_mask & CPUMASK(id)) == 0)
1021 /* First, make sure we are on a logical_cpus boundary. */
1022 if (id % logical_cpus != 0)
1024 for (i = id + 1; i < id + logical_cpus; i++)
1025 if ((id_mask & CPUMASK(i)) != 0)
1028 return logical_cpus;
1032 mptable_map(struct mptable_pos *mpt)
1036 vm_size_t cth_mapsz = 0;
1038 KKASSERT(mptable_fps_phyaddr != 0);
1040 bzero(mpt, sizeof(*mpt));
1042 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
1043 if (fps->pap != 0) {
1045 * Map configuration table header to get
1046 * the base table size
1048 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1049 cth_mapsz = cth->base_table_length;
1050 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1052 if (cth_mapsz < sizeof(*cth)) {
1053 kprintf("invalid base MP table length %d\n",
1055 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1060 * Map the base table
1062 cth = pmap_mapdev(fps->pap, cth_mapsz);
1067 mpt->mp_cth_mapsz = cth_mapsz;
1073 mptable_unmap(struct mptable_pos *mpt)
1075 if (mpt->mp_cth != NULL) {
1076 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1078 mpt->mp_cth_mapsz = 0;
1080 if (mpt->mp_fps != NULL) {
1081 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1087 assign_apic_irq(int apic, int intpin, int irq)
1091 if (int_to_apicintpin[irq].ioapic != -1)
1092 panic("assign_apic_irq: inconsistent table");
1094 int_to_apicintpin[irq].ioapic = apic;
1095 int_to_apicintpin[irq].int_pin = intpin;
1096 int_to_apicintpin[irq].apic_address = ioapic[apic];
1097 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1099 for (x = 0; x < nintrs; x++) {
1100 if ((io_apic_ints[x].int_type == 0 ||
1101 io_apic_ints[x].int_type == 3) &&
1102 io_apic_ints[x].int_vector == 0xff &&
1103 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1104 io_apic_ints[x].dst_apic_int == intpin)
1105 io_apic_ints[x].int_vector = irq;
1110 revoke_apic_irq(int irq)
1116 if (int_to_apicintpin[irq].ioapic == -1)
1117 panic("revoke_apic_irq: inconsistent table");
1119 oldapic = int_to_apicintpin[irq].ioapic;
1120 oldintpin = int_to_apicintpin[irq].int_pin;
1122 int_to_apicintpin[irq].ioapic = -1;
1123 int_to_apicintpin[irq].int_pin = 0;
1124 int_to_apicintpin[irq].apic_address = NULL;
1125 int_to_apicintpin[irq].redirindex = 0;
1127 for (x = 0; x < nintrs; x++) {
1128 if ((io_apic_ints[x].int_type == 0 ||
1129 io_apic_ints[x].int_type == 3) &&
1130 io_apic_ints[x].int_vector != 0xff &&
1131 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1132 io_apic_ints[x].dst_apic_int == oldintpin)
1133 io_apic_ints[x].int_vector = 0xff;
1141 allocate_apic_irq(int intr)
1147 if (io_apic_ints[intr].int_vector != 0xff)
1148 return; /* Interrupt handler already assigned */
1150 if (io_apic_ints[intr].int_type != 0 &&
1151 (io_apic_ints[intr].int_type != 3 ||
1152 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1153 io_apic_ints[intr].dst_apic_int == 0)))
1154 return; /* Not INT or ExtInt on != (0, 0) */
1157 while (irq < APIC_INTMAPSIZE &&
1158 int_to_apicintpin[irq].ioapic != -1)
1161 if (irq >= APIC_INTMAPSIZE)
1162 return; /* No free interrupt handlers */
1164 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1165 intpin = io_apic_ints[intr].dst_apic_int;
1167 assign_apic_irq(apic, intpin, irq);
1172 swap_apic_id(int apic, int oldid, int newid)
1179 return; /* Nothing to do */
1181 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1182 apic, oldid, newid);
1184 /* Swap physical APIC IDs in interrupt entries */
1185 for (x = 0; x < nintrs; x++) {
1186 if (io_apic_ints[x].dst_apic_id == oldid)
1187 io_apic_ints[x].dst_apic_id = newid;
1188 else if (io_apic_ints[x].dst_apic_id == newid)
1189 io_apic_ints[x].dst_apic_id = oldid;
1192 /* Swap physical APIC IDs in IO_TO_ID mappings */
1193 for (oapic = 0; oapic < mp_napics; oapic++)
1194 if (IO_TO_ID(oapic) == newid)
1197 if (oapic < mp_napics) {
1198 kprintf("Changing APIC ID for IO APIC #%d from "
1199 "%d to %d in MP table\n",
1200 oapic, newid, oldid);
1201 IO_TO_ID(oapic) = oldid;
1203 IO_TO_ID(apic) = newid;
1208 fix_id_to_io_mapping(void)
1212 for (x = 0; x < NAPICID; x++)
1215 for (x = 0; x <= mp_naps; x++)
1216 if (CPU_TO_ID(x) < NAPICID)
1217 ID_TO_IO(CPU_TO_ID(x)) = x;
1219 for (x = 0; x < mp_napics; x++)
1220 if (IO_TO_ID(x) < NAPICID)
1221 ID_TO_IO(IO_TO_ID(x)) = x;
1226 first_free_apic_id(void)
1230 for (freeid = 0; freeid < NAPICID; freeid++) {
1231 for (x = 0; x <= mp_naps; x++)
1232 if (CPU_TO_ID(x) == freeid)
1236 for (x = 0; x < mp_napics; x++)
1237 if (IO_TO_ID(x) == freeid)
1248 io_apic_id_acceptable(int apic, int id)
1250 int cpu; /* Logical CPU number */
1251 int oapic; /* Logical IO APIC number for other IO APIC */
1254 return 0; /* Out of range */
1256 for (cpu = 0; cpu <= mp_naps; cpu++)
1257 if (CPU_TO_ID(cpu) == id)
1258 return 0; /* Conflict with CPU */
1260 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1261 if (IO_TO_ID(oapic) == id)
1262 return 0; /* Conflict with other APIC */
1264 return 1; /* ID is acceptable for IO APIC */
1269 io_apic_find_int_entry(int apic, int pin)
1273 /* search each of the possible INTerrupt sources */
1274 for (x = 0; x < nintrs; ++x) {
1275 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1276 (pin == io_apic_ints[x].dst_apic_int))
1277 return (&io_apic_ints[x]);
1283 * parse an Intel MP specification table
1290 int apic; /* IO APIC unit number */
1291 int freeid; /* Free physical APIC ID */
1292 int physid; /* Current physical IO APIC ID */
1294 int bus_0 = 0; /* Stop GCC warning */
1295 int bus_pci = 0; /* Stop GCC warning */
1299 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1300 * did it wrong. The MP spec says that when more than 1 PCI bus
1301 * exists the BIOS must begin with bus entries for the PCI bus and use
1302 * actual PCI bus numbering. This implies that when only 1 PCI bus
1303 * exists the BIOS can choose to ignore this ordering, and indeed many
1304 * MP motherboards do ignore it. This causes a problem when the PCI
1305 * sub-system makes requests of the MP sub-system based on PCI bus
1306 * numbers. So here we look for the situation and renumber the
1307 * busses and associated INTs in an effort to "make it right".
1310 /* find bus 0, PCI bus, count the number of PCI busses */
1311 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1312 if (bus_data[x].bus_id == 0) {
1315 if (bus_data[x].bus_type == PCI) {
1321 * bus_0 == slot of bus with ID of 0
1322 * bus_pci == slot of last PCI bus encountered
1325 /* check the 1 PCI bus case for sanity */
1326 /* if it is number 0 all is well */
1327 if (num_pci_bus == 1 &&
1328 bus_data[bus_pci].bus_id != 0) {
1330 /* mis-numbered, swap with whichever bus uses slot 0 */
1332 /* swap the bus entry types */
1333 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1334 bus_data[bus_0].bus_type = PCI;
1336 /* swap each relavant INTerrupt entry */
1337 id = bus_data[bus_pci].bus_id;
1338 for (x = 0; x < nintrs; ++x) {
1339 if (io_apic_ints[x].src_bus_id == id) {
1340 io_apic_ints[x].src_bus_id = 0;
1342 else if (io_apic_ints[x].src_bus_id == 0) {
1343 io_apic_ints[x].src_bus_id = id;
1348 /* Assign IO APIC IDs.
1350 * First try the existing ID. If a conflict is detected, try
1351 * the ID in the MP table. If a conflict is still detected, find
1354 * We cannot use the ID_TO_IO table before all conflicts has been
1355 * resolved and the table has been corrected.
1357 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1359 /* First try to use the value set by the BIOS */
1360 physid = io_apic_get_id(apic);
1361 if (io_apic_id_acceptable(apic, physid)) {
1362 if (IO_TO_ID(apic) != physid)
1363 swap_apic_id(apic, IO_TO_ID(apic), physid);
1367 /* Then check if the value in the MP table is acceptable */
1368 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1371 /* Last resort, find a free APIC ID and use it */
1372 freeid = first_free_apic_id();
1373 if (freeid >= NAPICID)
1374 panic("No free physical APIC IDs found");
1376 if (io_apic_id_acceptable(apic, freeid)) {
1377 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1380 panic("Free physical APIC ID not usable");
1382 fix_id_to_io_mapping();
1384 /* detect and fix broken Compaq MP table */
1385 if (apic_int_type(0, 0) == -1) {
1386 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1387 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1388 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1389 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1390 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1391 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1393 } else if (apic_int_type(0, 0) == 0) {
1394 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1395 for (x = 0; x < nintrs; ++x)
1396 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1397 (0 == io_apic_ints[x].dst_apic_int)) {
1398 io_apic_ints[x].int_type = 3;
1399 io_apic_ints[x].int_vector = 0xff;
1405 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1406 * controllers universally come in pairs. If IRQ 14 is specified
1407 * as an ISA interrupt, then IRQ 15 had better be too.
1409 * [ Shuttle XPC / AMD Athlon X2 ]
1410 * The MPTable is missing an entry for IRQ 15. Note that the
1411 * ACPI table has an entry for both 14 and 15.
1413 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1414 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1415 io14 = io_apic_find_int_entry(0, 14);
1416 io_apic_ints[nintrs] = *io14;
1417 io_apic_ints[nintrs].src_bus_irq = 15;
1418 io_apic_ints[nintrs].dst_apic_int = 15;
1423 /* Assign low level interrupt handlers */
1425 setup_apic_irq_mapping(void)
1431 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1432 int_to_apicintpin[x].ioapic = -1;
1433 int_to_apicintpin[x].int_pin = 0;
1434 int_to_apicintpin[x].apic_address = NULL;
1435 int_to_apicintpin[x].redirindex = 0;
1437 /* Default to masked */
1438 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1441 /* First assign ISA/EISA interrupts */
1442 for (x = 0; x < nintrs; x++) {
1443 int_vector = io_apic_ints[x].src_bus_irq;
1444 if (int_vector < APIC_INTMAPSIZE &&
1445 io_apic_ints[x].int_vector == 0xff &&
1446 int_to_apicintpin[int_vector].ioapic == -1 &&
1447 (apic_int_is_bus_type(x, ISA) ||
1448 apic_int_is_bus_type(x, EISA)) &&
1449 io_apic_ints[x].int_type == 0) {
1450 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1451 io_apic_ints[x].dst_apic_int,
1456 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1457 for (x = 0; x < nintrs; x++) {
1458 if (io_apic_ints[x].dst_apic_int == 0 &&
1459 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1460 io_apic_ints[x].int_vector == 0xff &&
1461 int_to_apicintpin[0].ioapic == -1 &&
1462 io_apic_ints[x].int_type == 3) {
1463 assign_apic_irq(0, 0, 0);
1468 /* Assign PCI interrupts */
1469 for (x = 0; x < nintrs; ++x) {
1470 if (io_apic_ints[x].int_type == 0 &&
1471 io_apic_ints[x].int_vector == 0xff &&
1472 apic_int_is_bus_type(x, PCI))
1473 allocate_apic_irq(x);
1478 mp_set_cpuids(int cpu_id, int apic_id)
1480 CPU_TO_ID(cpu_id) = apic_id;
1481 ID_TO_CPU(apic_id) = cpu_id;
1485 processor_entry(const struct PROCENTRY *entry, int cpu)
1489 /* check for usability */
1490 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1493 /* check for BSP flag */
1494 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1495 mp_set_cpuids(0, entry->apic_id);
1496 return 0; /* its already been counted */
1499 /* add another AP to list, if less than max number of CPUs */
1500 else if (cpu < MAXCPU) {
1501 mp_set_cpuids(cpu, entry->apic_id);
1509 bus_entry(const struct BUSENTRY *entry, int bus)
1514 /* encode the name into an index */
1515 for (x = 0; x < 6; ++x) {
1516 if ((c = entry->bus_type[x]) == ' ')
1522 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1523 panic("unknown bus type: '%s'", name);
1525 bus_data[bus].bus_id = entry->bus_id;
1526 bus_data[bus].bus_type = x;
1532 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1534 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1537 IO_TO_ID(apic) = entry->apic_id;
1538 ID_TO_IO(entry->apic_id) = apic;
1544 lookup_bus_type(char *name)
1548 for (x = 0; x < MAX_BUSTYPE; ++x)
1549 if (strcmp(bus_type_table[x].name, name) == 0)
1550 return bus_type_table[x].type;
1552 return UNKNOWN_BUSTYPE;
1556 int_entry(const struct INTENTRY *entry, int intr)
1560 io_apic_ints[intr].int_type = entry->int_type;
1561 io_apic_ints[intr].int_flags = entry->int_flags;
1562 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1563 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1564 if (entry->dst_apic_id == 255) {
1565 /* This signal goes to all IO APICS. Select an IO APIC
1566 with sufficient number of interrupt pins */
1567 for (apic = 0; apic < mp_napics; apic++)
1568 if (((ioapic_read(ioapic[apic], IOAPIC_VER) &
1569 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1570 entry->dst_apic_int)
1572 if (apic < mp_napics)
1573 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1575 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1577 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1578 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1584 apic_int_is_bus_type(int intr, int bus_type)
1588 for (bus = 0; bus < mp_nbusses; ++bus)
1589 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1590 && ((int) bus_data[bus].bus_type == bus_type))
1597 * Given a traditional ISA INT mask, return an APIC mask.
1600 isa_apic_mask(u_int isa_mask)
1605 #if defined(SKIP_IRQ15_REDIRECT)
1606 if (isa_mask == (1 << 15)) {
1607 kprintf("skipping ISA IRQ15 redirect\n");
1610 #endif /* SKIP_IRQ15_REDIRECT */
1612 isa_irq = ffs(isa_mask); /* find its bit position */
1613 if (isa_irq == 0) /* doesn't exist */
1615 --isa_irq; /* make it zero based */
1617 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1621 return (1 << apic_pin); /* convert pin# to a mask */
1625 * Determine which APIC pin an ISA/EISA INT is attached to.
1627 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1628 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1629 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1630 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1632 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1634 isa_apic_irq(int isa_irq)
1638 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1639 if (INTTYPE(intr) == 0) { /* standard INT */
1640 if (SRCBUSIRQ(intr) == isa_irq) {
1641 if (apic_int_is_bus_type(intr, ISA) ||
1642 apic_int_is_bus_type(intr, EISA)) {
1643 if (INTIRQ(intr) == 0xff)
1644 return -1; /* unassigned */
1645 return INTIRQ(intr); /* found */
1650 return -1; /* NOT found */
1655 * Determine which APIC pin a PCI INT is attached to.
1657 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1658 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1659 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1661 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1665 --pciInt; /* zero based */
1667 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1668 if ((INTTYPE(intr) == 0) /* standard INT */
1669 && (SRCBUSID(intr) == pciBus)
1670 && (SRCBUSDEVICE(intr) == pciDevice)
1671 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1672 if (apic_int_is_bus_type(intr, PCI)) {
1673 if (INTIRQ(intr) == 0xff) {
1674 kprintf("IOAPIC: pci_apic_irq() "
1676 return -1; /* unassigned */
1678 return INTIRQ(intr); /* exact match */
1683 return -1; /* NOT found */
1687 next_apic_irq(int irq)
1694 for (intr = 0; intr < nintrs; intr++) {
1695 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1697 bus = SRCBUSID(intr);
1698 bustype = apic_bus_type(bus);
1699 if (bustype != ISA &&
1705 if (intr >= nintrs) {
1708 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1709 if (INTTYPE(ointr) != 0)
1711 if (bus != SRCBUSID(ointr))
1713 if (bustype == PCI) {
1714 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1716 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1719 if (bustype == ISA || bustype == EISA) {
1720 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1723 if (INTPIN(intr) == INTPIN(ointr))
1727 if (ointr >= nintrs) {
1730 return INTIRQ(ointr);
1743 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1746 * Exactly what this means is unclear at this point. It is a solution
1747 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1748 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1749 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1753 undirect_isa_irq(int rirq)
1757 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1758 /** FIXME: tickle the MB redirector chip */
1762 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1769 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1772 undirect_pci_irq(int rirq)
1776 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1778 /** FIXME: tickle the MB redirector chip */
1782 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1790 * given a bus ID, return:
1791 * the bus type if found
1795 apic_bus_type(int id)
1799 for (x = 0; x < mp_nbusses; ++x)
1800 if (bus_data[x].bus_id == id)
1801 return bus_data[x].bus_type;
1807 * given a LOGICAL APIC# and pin#, return:
1808 * the associated src bus ID if found
1812 apic_src_bus_id(int apic, int pin)
1816 /* search each of the possible INTerrupt sources */
1817 for (x = 0; x < nintrs; ++x)
1818 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1819 (pin == io_apic_ints[x].dst_apic_int))
1820 return (io_apic_ints[x].src_bus_id);
1822 return -1; /* NOT found */
1826 * given a LOGICAL APIC# and pin#, return:
1827 * the associated src bus IRQ if found
1831 apic_src_bus_irq(int apic, int pin)
1835 for (x = 0; x < nintrs; x++)
1836 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1837 (pin == io_apic_ints[x].dst_apic_int))
1838 return (io_apic_ints[x].src_bus_irq);
1840 return -1; /* NOT found */
1845 * given a LOGICAL APIC# and pin#, return:
1846 * the associated INTerrupt type if found
1850 apic_int_type(int apic, int pin)
1854 /* search each of the possible INTerrupt sources */
1855 for (x = 0; x < nintrs; ++x) {
1856 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1857 (pin == io_apic_ints[x].dst_apic_int))
1858 return (io_apic_ints[x].int_type);
1860 return -1; /* NOT found */
1864 * Return the IRQ associated with an APIC pin
1867 apic_irq(int apic, int pin)
1872 for (x = 0; x < nintrs; ++x) {
1873 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1874 (pin == io_apic_ints[x].dst_apic_int)) {
1875 res = io_apic_ints[x].int_vector;
1878 if (apic != int_to_apicintpin[res].ioapic)
1879 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1880 if (pin != int_to_apicintpin[res].int_pin)
1881 panic("apic_irq inconsistent table (2)");
1890 * given a LOGICAL APIC# and pin#, return:
1891 * the associated trigger mode if found
1895 apic_trigger(int apic, int pin)
1899 /* search each of the possible INTerrupt sources */
1900 for (x = 0; x < nintrs; ++x)
1901 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1902 (pin == io_apic_ints[x].dst_apic_int))
1903 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1905 return -1; /* NOT found */
1910 * given a LOGICAL APIC# and pin#, return:
1911 * the associated 'active' level if found
1915 apic_polarity(int apic, int pin)
1919 /* search each of the possible INTerrupt sources */
1920 for (x = 0; x < nintrs; ++x)
1921 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1922 (pin == io_apic_ints[x].dst_apic_int))
1923 return (io_apic_ints[x].int_flags & 0x03);
1925 return -1; /* NOT found */
1929 * set data according to MP defaults
1930 * FIXME: probably not complete yet...
1933 mptable_default(int type)
1939 kprintf(" MP default config type: %d\n", type);
1942 kprintf(" bus: ISA, APIC: 82489DX\n");
1945 kprintf(" bus: EISA, APIC: 82489DX\n");
1948 kprintf(" bus: EISA, APIC: 82489DX\n");
1951 kprintf(" bus: MCA, APIC: 82489DX\n");
1954 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
1957 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
1960 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
1963 kprintf(" future type\n");
1969 /* one and only IO APIC */
1970 io_apic_id = (ioapic_read(ioapic[0], IOAPIC_ID) & APIC_ID_MASK) >> 24;
1973 * sanity check, refer to MP spec section 3.6.6, last paragraph
1974 * necessary as some hardware isn't properly setting up the IO APIC
1976 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1977 if (io_apic_id != 2) {
1979 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1980 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1981 io_apic_set_id(0, 2);
1984 IO_TO_ID(0) = io_apic_id;
1985 ID_TO_IO(io_apic_id) = 0;
1987 /* fill out bus entries */
1996 bus_data[0].bus_id = default_data[type - 1][1];
1997 bus_data[0].bus_type = default_data[type - 1][2];
1998 bus_data[1].bus_id = default_data[type - 1][3];
1999 bus_data[1].bus_type = default_data[type - 1][4];
2002 /* case 4: case 7: MCA NOT supported */
2003 default: /* illegal/reserved */
2004 panic("BAD default MP config: %d", type);
2008 /* general cases from MP v1.4, table 5-2 */
2009 for (pin = 0; pin < 16; ++pin) {
2010 io_apic_ints[pin].int_type = 0;
2011 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2012 io_apic_ints[pin].src_bus_id = 0;
2013 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2014 io_apic_ints[pin].dst_apic_id = io_apic_id;
2015 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2018 /* special cases from MP v1.4, table 5-2 */
2020 io_apic_ints[2].int_type = 0xff; /* N/C */
2021 io_apic_ints[13].int_type = 0xff; /* N/C */
2022 #if !defined(APIC_MIXED_MODE)
2024 panic("sorry, can't support type 2 default yet");
2025 #endif /* APIC_MIXED_MODE */
2028 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2031 io_apic_ints[0].int_type = 0xff; /* N/C */
2033 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2037 * Map a physical memory address representing I/O into KVA. The I/O
2038 * block is assumed not to cross a page boundary.
2041 permanent_io_mapping(vm_paddr_t pa)
2047 KKASSERT(pa < 0x100000000LL);
2049 pgeflag = 0; /* not used for SMP yet */
2052 * If the requested physical address has already been incidently
2053 * mapped, just use the existing mapping. Otherwise create a new
2056 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2057 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2058 ((vm_offset_t)pa & PG_FRAME)) {
2062 if (i == SMPpt_alloc_index) {
2063 if (i == NPTEPG - 2) {
2064 panic("permanent_io_mapping: We ran out of space"
2067 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
2068 ((vm_offset_t)pa & PG_FRAME));
2069 ++SMPpt_alloc_index;
2071 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2072 ((vm_offset_t)pa & PAGE_MASK);
2073 return ((void *)vaddr);
2077 * start each AP in our list
2080 start_all_aps(u_int boot_addr)
2087 u_char mpbiosreason;
2088 u_long mpbioswarmvec;
2089 struct mdglobaldata *gd;
2090 struct privatespace *ps;
2094 POSTCODE(START_ALL_APS_POST);
2096 /* Initialize BSP's local APIC */
2097 apic_initialize(TRUE);
2100 MachIntrABI.finalize();
2102 /* install the AP 1st level boot code */
2103 install_ap_tramp(boot_addr);
2106 /* save the current value of the warm-start vector */
2107 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2108 outb(CMOS_REG, BIOS_RESET);
2109 mpbiosreason = inb(CMOS_DATA);
2111 /* setup a vector to our boot code */
2112 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2113 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2114 outb(CMOS_REG, BIOS_RESET);
2115 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2118 * If we have a TSC we can figure out the SMI interrupt rate.
2119 * The SMI does not necessarily use a constant rate. Spend
2120 * up to 250ms trying to figure it out.
2123 if (cpu_feature & CPUID_TSC) {
2124 set_apic_timer(275000);
2125 smilast = read_apic_timer();
2126 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2127 smicount = smitest();
2128 if (smibest == 0 || smilast - smicount < smibest)
2129 smibest = smilast - smicount;
2132 if (smibest > 250000)
2135 smibest = smibest * (int64_t)1000000 /
2136 get_apic_timer_frequency();
2140 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2141 1000000 / smibest, smibest);
2144 /* set up temporary P==V mapping for AP boot */
2145 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2146 kptbase = (uintptr_t)(void *)KPTphys;
2147 for (x = 0; x < NKPT; x++) {
2148 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2149 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2154 for (x = 1; x <= mp_naps; ++x) {
2156 /* This is a bit verbose, it will go away soon. */
2158 /* first page of AP's private space */
2159 pg = x * i386_btop(sizeof(struct privatespace));
2161 /* allocate new private data page(s) */
2162 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2163 MDGLOBALDATA_BASEALLOC_SIZE);
2164 /* wire it into the private page table page */
2165 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2166 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2167 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2169 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2171 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2172 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2173 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2174 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2176 /* allocate and set up an idle stack data page */
2177 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2178 for (i = 0; i < UPAGES; i++) {
2179 SMPpt[pg + 4 + i] = (pt_entry_t)
2180 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2183 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2184 bzero(gd, sizeof(*gd));
2185 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2187 /* prime data page for it to use */
2188 mi_gdinit(&gd->mi, x);
2190 gd->gd_CMAP1 = &SMPpt[pg + 0];
2191 gd->gd_CMAP2 = &SMPpt[pg + 1];
2192 gd->gd_CMAP3 = &SMPpt[pg + 2];
2193 gd->gd_PMAP1 = &SMPpt[pg + 3];
2194 gd->gd_CADDR1 = ps->CPAGE1;
2195 gd->gd_CADDR2 = ps->CPAGE2;
2196 gd->gd_CADDR3 = ps->CPAGE3;
2197 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2200 * Per-cpu pmap for get_ptbase().
2202 gd->gd_GDADDR1= (unsigned *)
2203 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
2204 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
2206 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2207 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2210 * Setup the AP boot stack
2212 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2215 /* attempt to start the Application Processor */
2216 CHECK_INIT(99); /* setup checkpoints */
2217 if (!start_ap(gd, boot_addr, smibest)) {
2218 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2219 CHECK_PRINT("trace"); /* show checkpoints */
2220 /* better panic as the AP may be running loose */
2221 kprintf("panic y/n? [y] ");
2222 if (cngetc() != 'n')
2225 CHECK_PRINT("trace"); /* show checkpoints */
2227 /* record its version info */
2228 cpu_apic_versions[x] = cpu_apic_versions[0];
2231 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2234 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2235 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2238 ncpus2_shift = shift;
2239 ncpus2 = 1 << shift;
2240 ncpus2_mask = ncpus2 - 1;
2242 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2243 if ((1 << shift) < ncpus)
2245 ncpus_fit = 1 << shift;
2246 ncpus_fit_mask = ncpus_fit - 1;
2248 /* build our map of 'other' CPUs */
2249 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2250 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2251 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2253 /* fill in our (BSP) APIC version */
2254 cpu_apic_versions[0] = lapic.version;
2256 /* restore the warmstart vector */
2257 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2258 outb(CMOS_REG, BIOS_RESET);
2259 outb(CMOS_DATA, mpbiosreason);
2262 * NOTE! The idlestack for the BSP was setup by locore. Finish
2263 * up, clean out the P==V mapping we did earlier.
2265 for (x = 0; x < NKPT; x++)
2269 /* number of APs actually started */
2274 * load the 1st level AP boot code into base memory.
2277 /* targets for relocation */
2278 extern void bigJump(void);
2279 extern void bootCodeSeg(void);
2280 extern void bootDataSeg(void);
2281 extern void MPentry(void);
2282 extern u_int MP_GDT;
2283 extern u_int mp_gdtbase;
2286 install_ap_tramp(u_int boot_addr)
2289 int size = *(int *) ((u_long) & bootMP_size);
2290 u_char *src = (u_char *) ((u_long) bootMP);
2291 u_char *dst = (u_char *) boot_addr + KERNBASE;
2292 u_int boot_base = (u_int) bootMP;
2297 POSTCODE(INSTALL_AP_TRAMP_POST);
2299 for (x = 0; x < size; ++x)
2303 * modify addresses in code we just moved to basemem. unfortunately we
2304 * need fairly detailed info about mpboot.s for this to work. changes
2305 * to mpboot.s might require changes here.
2308 /* boot code is located in KERNEL space */
2309 dst = (u_char *) boot_addr + KERNBASE;
2311 /* modify the lgdt arg */
2312 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2313 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2315 /* modify the ljmp target for MPentry() */
2316 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2317 *dst32 = ((u_int) MPentry - KERNBASE);
2319 /* modify the target for boot code segment */
2320 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2321 dst8 = (u_int8_t *) (dst16 + 1);
2322 *dst16 = (u_int) boot_addr & 0xffff;
2323 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2325 /* modify the target for boot data segment */
2326 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2327 dst8 = (u_int8_t *) (dst16 + 1);
2328 *dst16 = (u_int) boot_addr & 0xffff;
2329 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2334 * This function starts the AP (application processor) identified
2335 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2336 * to accomplish this. This is necessary because of the nuances
2337 * of the different hardware we might encounter. It ain't pretty,
2338 * but it seems to work.
2340 * NOTE: eventually an AP gets to ap_init(), which is called just
2341 * before the AP goes into the LWKT scheduler's idle loop.
2344 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2348 u_long icr_lo, icr_hi;
2350 POSTCODE(START_AP_POST);
2352 /* get the PHYSICAL APIC ID# */
2353 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2355 /* calculate the vector */
2356 vector = (boot_addr >> 12) & 0xff;
2358 /* We don't want anything interfering */
2361 /* Make sure the target cpu sees everything */
2365 * Try to detect when a SMI has occurred, wait up to 200ms.
2367 * If a SMI occurs during an AP reset but before we issue
2368 * the STARTUP command, the AP may brick. To work around
2369 * this problem we hold off doing the AP startup until
2370 * after we have detected the SMI. Hopefully another SMI
2371 * will not occur before we finish the AP startup.
2373 * Retries don't seem to help. SMIs have a window of opportunity
2374 * and if USB->legacy keyboard emulation is enabled in the BIOS
2375 * the interrupt rate can be quite high.
2377 * NOTE: Don't worry about the L1 cache load, it might bloat
2378 * ldelta a little but ndelta will be so huge when the SMI
2379 * occurs the detection logic will still work fine.
2382 set_apic_timer(200000);
2387 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2388 * and running the target CPU. OR this INIT IPI might be latched (P5
2389 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2392 * see apic/apicreg.h for icr bit definitions.
2394 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2398 * Setup the address for the target AP. We can setup
2399 * icr_hi once and then just trigger operations with
2402 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2403 icr_hi |= (physical_cpu << 24);
2404 icr_lo = lapic.icr_lo & 0xfff00000;
2405 lapic.icr_hi = icr_hi;
2408 * Do an INIT IPI: assert RESET
2410 * Use edge triggered mode to assert INIT
2412 lapic.icr_lo = icr_lo | 0x0000c500;
2413 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2417 * The spec calls for a 10ms delay but we may have to use a
2418 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2419 * interrupt. We have other loops here too and dividing by 2
2420 * doesn't seem to be enough even after subtracting 350us,
2421 * so we divide by 4.
2423 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2424 * interrupt was detected we use the full 10ms.
2428 else if (smibest < 150 * 4 + 350)
2430 else if ((smibest - 350) / 4 < 10000)
2431 u_sleep((smibest - 350) / 4);
2436 * Do an INIT IPI: deassert RESET
2438 * Use level triggered mode to deassert. It is unclear
2439 * why we need to do this.
2441 lapic.icr_lo = icr_lo | 0x00008500;
2442 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2444 u_sleep(150); /* wait 150us */
2447 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2448 * latched, (P5 bug) this 1st STARTUP would then terminate
2449 * immediately, and the previously started INIT IPI would continue. OR
2450 * the previous INIT IPI has already run. and this STARTUP IPI will
2451 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2454 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2455 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2457 u_sleep(200); /* wait ~200uS */
2460 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2461 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2462 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2463 * recognized after hardware RESET or INIT IPI.
2465 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2466 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2469 /* Resume normal operation */
2472 /* wait for it to start, see ap_init() */
2473 set_apic_timer(5000000);/* == 5 seconds */
2474 while (read_apic_timer()) {
2475 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2476 return 1; /* return SUCCESS */
2479 return 0; /* return FAILURE */
2494 while (read_apic_timer()) {
2496 for (count = 0; count < 100; ++count)
2497 ntsc = rdtsc(); /* force loop to occur */
2499 ndelta = ntsc - ltsc;
2500 if (ldelta > ndelta)
2502 if (ndelta > ldelta * 2)
2505 ldelta = ntsc - ltsc;
2508 return(read_apic_timer());
2512 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2514 * If for some reason we were unable to start all cpus we cannot safely
2515 * use broadcast IPIs.
2518 static cpumask_t smp_invltlb_req;
2519 #define SMP_INVLTLB_DEBUG
2525 struct mdglobaldata *md = mdcpu;
2526 #ifdef SMP_INVLTLB_DEBUG
2531 crit_enter_gd(&md->mi);
2532 md->gd_invltlb_ret = 0;
2533 ++md->mi.gd_cnt.v_smpinvltlb;
2534 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2535 #ifdef SMP_INVLTLB_DEBUG
2538 if (smp_startup_mask == smp_active_mask) {
2539 all_but_self_ipi(XINVLTLB_OFFSET);
2541 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2542 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2545 #ifdef SMP_INVLTLB_DEBUG
2547 kprintf("smp_invltlb: ipi sent\n");
2549 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2550 (smp_active_mask & ~md->mi.gd_cpumask)) {
2553 #ifdef SMP_INVLTLB_DEBUG
2555 if (++count == 400000000) {
2556 print_backtrace(-1);
2557 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2558 "rflags %016lx retry",
2559 (long)md->gd_invltlb_ret,
2560 (long)smp_invltlb_req,
2561 (long)read_eflags());
2562 __asm __volatile ("sti");
2565 lwkt_process_ipiq();
2567 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2568 ~md->mi.gd_cpumask &
2571 kprintf("bcpu %d\n", bcpu);
2572 xgd = globaldata_find(bcpu);
2573 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2582 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2583 crit_exit_gd(&md->mi);
2590 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2591 * bother to bump the critical section count or nested interrupt count
2592 * so only do very low level operations here.
2595 smp_invltlb_intr(void)
2597 struct mdglobaldata *md = mdcpu;
2598 struct mdglobaldata *omd;
2602 mask = smp_invltlb_req;
2606 cpu = BSFCPUMASK(mask);
2607 mask &= ~CPUMASK(cpu);
2608 omd = (struct mdglobaldata *)globaldata_find(cpu);
2609 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2616 * When called the executing CPU will send an IPI to all other CPUs
2617 * requesting that they halt execution.
2619 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2621 * - Signals all CPUs in map to stop.
2622 * - Waits for each to stop.
2629 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2630 * from executing at same time.
2633 stop_cpus(cpumask_t map)
2635 map &= smp_active_mask;
2637 /* send the Xcpustop IPI to all CPUs in map */
2638 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2640 while ((stopped_cpus & map) != map)
2648 * Called by a CPU to restart stopped CPUs.
2650 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2652 * - Signals all CPUs in map to restart.
2653 * - Waits for each to restart.
2661 restart_cpus(cpumask_t map)
2663 /* signal other cpus to restart */
2664 started_cpus = map & smp_active_mask;
2666 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2673 * This is called once the mpboot code has gotten us properly relocated
2674 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2675 * and when it returns the scheduler will call the real cpu_idle() main
2676 * loop for the idlethread. Interrupts are disabled on entry and should
2677 * remain disabled at return.
2685 * Adjust smp_startup_mask to signal the BSP that we have started
2686 * up successfully. Note that we do not yet hold the BGL. The BSP
2687 * is waiting for our signal.
2689 * We can't set our bit in smp_active_mask yet because we are holding
2690 * interrupts physically disabled and remote cpus could deadlock
2691 * trying to send us an IPI.
2693 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2697 * Interlock for finalization. Wait until mp_finish is non-zero,
2698 * then get the MP lock.
2700 * Note: We are in a critical section.
2702 * Note: we are the idle thread, we can only spin.
2704 * Note: The load fence is memory volatile and prevents the compiler
2705 * from improperly caching mp_finish, and the cpu from improperly
2708 while (mp_finish == 0)
2710 while (try_mplock() == 0)
2713 if (cpu_feature & CPUID_TSC) {
2715 * The BSP is constantly updating tsc0_offset, figure out
2716 * the relative difference to synchronize ktrdump.
2718 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2721 /* BSP may have changed PTD while we're waiting for the lock */
2724 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2728 /* Build our map of 'other' CPUs. */
2729 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2731 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2733 /* A quick check from sanity claus */
2734 apic_id = (apic_id_to_logical[(lapic.id & 0xff000000) >> 24]);
2735 if (mycpu->gd_cpuid != apic_id) {
2736 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2737 kprintf("SMP: apic_id = %d\n", apic_id);
2738 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2739 panic("cpuid mismatch! boom!!");
2742 /* Initialize AP's local APIC for irq's */
2743 apic_initialize(FALSE);
2745 /* Set memory range attributes for this CPU to match the BSP */
2746 mem_range_AP_init();
2749 * Once we go active we must process any IPIQ messages that may
2750 * have been queued, because no actual IPI will occur until we
2751 * set our bit in the smp_active_mask. If we don't the IPI
2752 * message interlock could be left set which would also prevent
2755 * The idle loop doesn't expect the BGL to be held and while
2756 * lwkt_switch() normally cleans things up this is a special case
2757 * because we returning almost directly into the idle loop.
2759 * The idle thread is never placed on the runq, make sure
2760 * nothing we've done put it there.
2762 KKASSERT(get_mplock_count(curthread) == 1);
2763 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2766 * Enable interrupts here. idle_restore will also do it, but
2767 * doing it here lets us clean up any strays that got posted to
2768 * the CPU during the AP boot while we are still in a critical
2771 __asm __volatile("sti; pause; pause"::);
2772 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2774 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2775 lwkt_process_ipiq();
2778 * Releasing the mp lock lets the BSP finish up the SMP init
2781 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2785 * Get SMP fully working before we start initializing devices.
2793 kprintf("Finish MP startup\n");
2794 if (cpu_feature & CPUID_TSC)
2795 tsc0_offset = rdtsc();
2798 while (smp_active_mask != smp_startup_mask) {
2800 if (cpu_feature & CPUID_TSC)
2801 tsc0_offset = rdtsc();
2803 while (try_mplock() == 0)
2806 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2809 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2812 cpu_send_ipiq(int dcpu)
2814 if (CPUMASK(dcpu) & smp_active_mask)
2815 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2818 #if 0 /* single_apic_ipi_passive() not working yet */
2820 * Returns 0 on failure, 1 on success
2823 cpu_send_ipiq_passive(int dcpu)
2826 if (CPUMASK(dcpu) & smp_active_mask) {
2827 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2828 APIC_DELMODE_FIXED);
2834 struct mptable_lapic_cbarg1 {
2837 u_int ht_apicid_mask;
2841 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2843 const struct PROCENTRY *ent;
2844 struct mptable_lapic_cbarg1 *arg = xarg;
2850 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2854 if (ent->apic_id < 32) {
2855 arg->ht_apicid_mask |= 1 << ent->apic_id;
2856 } else if (arg->ht_fixup) {
2857 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2863 struct mptable_lapic_cbarg2 {
2870 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2872 const struct PROCENTRY *ent;
2873 struct mptable_lapic_cbarg2 *arg = xarg;
2879 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2880 KKASSERT(!arg->found_bsp);
2884 if (processor_entry(ent, arg->cpu))
2887 if (arg->logical_cpus) {
2888 struct PROCENTRY proc;
2892 * Create fake mptable processor entries
2893 * and feed them to processor_entry() to
2894 * enumerate the logical CPUs.
2896 bzero(&proc, sizeof(proc));
2898 proc.cpu_flags = PROCENTRY_FLAG_EN;
2899 proc.apic_id = ent->apic_id;
2901 for (i = 1; i < arg->logical_cpus; i++) {
2903 processor_entry(&proc, arg->cpu);
2911 mptable_imcr(struct mptable_pos *mpt)
2913 /* record whether PIC or virtual-wire mode */
2914 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2915 mpt->mp_fps->mpfb2 & 0x80);
2919 mptable_lapic_default(void)
2921 int ap_apicid, bsp_apicid;
2923 mp_naps = 1; /* exclude BSP */
2925 /* Map local apic before the id field is accessed */
2926 lapic_map(DEFAULT_APIC_BASE);
2928 bsp_apicid = APIC_ID(lapic.id);
2929 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2932 mp_set_cpuids(0, bsp_apicid);
2933 /* one and only AP */
2934 mp_set_cpuids(1, ap_apicid);
2940 * ID_TO_CPU(N), APIC ID to logical CPU table
2941 * CPU_TO_ID(N), logical CPU to APIC ID table
2944 mptable_lapic_enumerate(struct lapic_enumerator *e)
2946 struct mptable_pos mpt;
2947 struct mptable_lapic_cbarg1 arg1;
2948 struct mptable_lapic_cbarg2 arg2;
2950 int error, logical_cpus = 0;
2951 vm_offset_t lapic_addr;
2953 error = mptable_map(&mpt);
2955 panic("mptable_lapic_enumerate mptable_map failed\n");
2957 KKASSERT(mpt.mp_fps != NULL);
2960 * Check for use of 'default' configuration
2962 if (mpt.mp_fps->mpfb1 != 0) {
2963 mptable_lapic_default();
2964 mptable_unmap(&mpt);
2969 KKASSERT(cth != NULL);
2971 /* Save local apic address */
2972 lapic_addr = (vm_offset_t)cth->apic_address;
2973 KKASSERT(lapic_addr != 0);
2976 * Find out how many CPUs do we have
2978 bzero(&arg1, sizeof(arg1));
2979 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2981 error = mptable_iterate_entries(cth,
2982 mptable_lapic_pass1_callback, &arg1);
2984 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2985 KKASSERT(arg1.cpu_count != 0);
2987 /* See if we need to fixup HT logical CPUs. */
2988 if (arg1.ht_fixup) {
2989 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2991 if (logical_cpus != 0)
2992 arg1.cpu_count *= logical_cpus;
2994 mp_naps = arg1.cpu_count;
2996 /* Qualify the numbers again, after possible HT fixup */
2997 if (mp_naps > MAXCPU) {
2998 kprintf("Warning: only using %d of %d available CPUs!\n",
3003 --mp_naps; /* subtract the BSP */
3006 * Link logical CPU id to local apic id
3008 bzero(&arg2, sizeof(arg2));
3010 arg2.logical_cpus = logical_cpus;
3012 error = mptable_iterate_entries(cth,
3013 mptable_lapic_pass2_callback, &arg2);
3015 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3016 KKASSERT(arg2.found_bsp);
3018 /* Map local apic */
3019 lapic_map(lapic_addr);
3021 mptable_unmap(&mpt);
3024 struct mptable_lapic_probe_cbarg {
3030 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
3032 const struct PROCENTRY *ent;
3033 struct mptable_lapic_probe_cbarg *arg = xarg;
3039 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
3043 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3044 if (arg->found_bsp) {
3045 kprintf("more than one BSP in base MP table\n");
3054 mptable_lapic_probe(struct lapic_enumerator *e)
3056 struct mptable_pos mpt;
3057 struct mptable_lapic_probe_cbarg arg;
3061 if (mptable_fps_phyaddr == 0)
3064 error = mptable_map(&mpt);
3068 if (mpt.mp_fps->mpfb1 != 0)
3076 if (cth->apic_address == 0)
3079 bzero(&arg, sizeof(arg));
3080 error = mptable_iterate_entries(cth,
3081 mptable_lapic_probe_callback, &arg);
3083 if (arg.cpu_count == 0) {
3084 kprintf("MP table contains no processor entries\n");
3086 } else if (!arg.found_bsp) {
3087 kprintf("MP table does not contains BSP entry\n");
3092 mptable_unmap(&mpt);
3096 static struct lapic_enumerator mptable_lapic_enumerator = {
3097 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3098 .lapic_probe = mptable_lapic_probe,
3099 .lapic_enumerate = mptable_lapic_enumerate
3103 mptable_apic_register(void)
3105 lapic_enumerator_register(&mptable_lapic_enumerator);
3107 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);