2 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 1991 The Regents of the University of California.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
10 * This code is derived from software contributed to Berkeley by
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * $DragonFly: src/sys/platform/pc32/apic/apic_abi.c,v 1.8 2005/11/04 01:21:39 dillon Exp $
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/machintr.h>
47 #include <sys/interrupt.h>
49 #include <machine/smp.h>
50 #include <machine/segments.h>
51 #include <machine/md_var.h>
52 #include <machine/clock.h> /* apic_8254_intr */
53 #include <i386/isa/intr_machdep.h>
54 #include <i386/icu/icu.h>
59 extern void APIC_INTREN(int);
60 extern void APIC_INTRDIS(int);
63 IDTVEC(apic_fastintr0), IDTVEC(apic_fastintr1),
64 IDTVEC(apic_fastintr2), IDTVEC(apic_fastintr3),
65 IDTVEC(apic_fastintr4), IDTVEC(apic_fastintr5),
66 IDTVEC(apic_fastintr6), IDTVEC(apic_fastintr7),
67 IDTVEC(apic_fastintr8), IDTVEC(apic_fastintr9),
68 IDTVEC(apic_fastintr10), IDTVEC(apic_fastintr11),
69 IDTVEC(apic_fastintr12), IDTVEC(apic_fastintr13),
70 IDTVEC(apic_fastintr14), IDTVEC(apic_fastintr15),
71 IDTVEC(apic_fastintr16), IDTVEC(apic_fastintr17),
72 IDTVEC(apic_fastintr18), IDTVEC(apic_fastintr19),
73 IDTVEC(apic_fastintr20), IDTVEC(apic_fastintr21),
74 IDTVEC(apic_fastintr22), IDTVEC(apic_fastintr23);
77 IDTVEC(apic_slowintr0), IDTVEC(apic_slowintr1),
78 IDTVEC(apic_slowintr2), IDTVEC(apic_slowintr3),
79 IDTVEC(apic_slowintr4), IDTVEC(apic_slowintr5),
80 IDTVEC(apic_slowintr6), IDTVEC(apic_slowintr7),
81 IDTVEC(apic_slowintr8), IDTVEC(apic_slowintr9),
82 IDTVEC(apic_slowintr10), IDTVEC(apic_slowintr11),
83 IDTVEC(apic_slowintr12), IDTVEC(apic_slowintr13),
84 IDTVEC(apic_slowintr14), IDTVEC(apic_slowintr15),
85 IDTVEC(apic_slowintr16), IDTVEC(apic_slowintr17),
86 IDTVEC(apic_slowintr18), IDTVEC(apic_slowintr19),
87 IDTVEC(apic_slowintr20), IDTVEC(apic_slowintr21),
88 IDTVEC(apic_slowintr22), IDTVEC(apic_slowintr23);
91 IDTVEC(apic_wrongintr0), IDTVEC(apic_wrongintr1),
92 IDTVEC(apic_wrongintr2), IDTVEC(apic_wrongintr3),
93 IDTVEC(apic_wrongintr4), IDTVEC(apic_wrongintr5),
94 IDTVEC(apic_wrongintr6), IDTVEC(apic_wrongintr7),
95 IDTVEC(apic_wrongintr8), IDTVEC(apic_wrongintr9),
96 IDTVEC(apic_wrongintr10), IDTVEC(apic_wrongintr11),
97 IDTVEC(apic_wrongintr12), IDTVEC(apic_wrongintr13),
98 IDTVEC(apic_wrongintr14), IDTVEC(apic_wrongintr15),
99 IDTVEC(apic_wrongintr16), IDTVEC(apic_wrongintr17),
100 IDTVEC(apic_wrongintr18), IDTVEC(apic_wrongintr19),
101 IDTVEC(apic_wrongintr20), IDTVEC(apic_wrongintr21),
102 IDTVEC(apic_wrongintr22), IDTVEC(apic_wrongintr23);
104 static int apic_setvar(int, const void *);
105 static int apic_getvar(int, void *);
106 static int apic_vectorctl(int, int, int);
107 static void apic_finalize(void);
109 static inthand_t *apic_fastintr[APIC_HWI_VECTORS] = {
110 &IDTVEC(apic_fastintr0), &IDTVEC(apic_fastintr1),
111 &IDTVEC(apic_fastintr2), &IDTVEC(apic_fastintr3),
112 &IDTVEC(apic_fastintr4), &IDTVEC(apic_fastintr5),
113 &IDTVEC(apic_fastintr6), &IDTVEC(apic_fastintr7),
114 &IDTVEC(apic_fastintr8), &IDTVEC(apic_fastintr9),
115 &IDTVEC(apic_fastintr10), &IDTVEC(apic_fastintr11),
116 &IDTVEC(apic_fastintr12), &IDTVEC(apic_fastintr13),
117 &IDTVEC(apic_fastintr14), &IDTVEC(apic_fastintr15),
118 &IDTVEC(apic_fastintr16), &IDTVEC(apic_fastintr17),
119 &IDTVEC(apic_fastintr18), &IDTVEC(apic_fastintr19),
120 &IDTVEC(apic_fastintr20), &IDTVEC(apic_fastintr21),
121 &IDTVEC(apic_fastintr22), &IDTVEC(apic_fastintr23)
124 static inthand_t *apic_slowintr[APIC_HWI_VECTORS] = {
125 &IDTVEC(apic_slowintr0), &IDTVEC(apic_slowintr1),
126 &IDTVEC(apic_slowintr2), &IDTVEC(apic_slowintr3),
127 &IDTVEC(apic_slowintr4), &IDTVEC(apic_slowintr5),
128 &IDTVEC(apic_slowintr6), &IDTVEC(apic_slowintr7),
129 &IDTVEC(apic_slowintr8), &IDTVEC(apic_slowintr9),
130 &IDTVEC(apic_slowintr10), &IDTVEC(apic_slowintr11),
131 &IDTVEC(apic_slowintr12), &IDTVEC(apic_slowintr13),
132 &IDTVEC(apic_slowintr14), &IDTVEC(apic_slowintr15),
133 &IDTVEC(apic_slowintr16), &IDTVEC(apic_slowintr17),
134 &IDTVEC(apic_slowintr18), &IDTVEC(apic_slowintr19),
135 &IDTVEC(apic_slowintr20), &IDTVEC(apic_slowintr21),
136 &IDTVEC(apic_slowintr22), &IDTVEC(apic_slowintr23)
139 static inthand_t *apic_wrongintr[APIC_HWI_VECTORS] = {
140 &IDTVEC(apic_wrongintr0), &IDTVEC(apic_wrongintr1),
141 &IDTVEC(apic_wrongintr2), &IDTVEC(apic_wrongintr3),
142 &IDTVEC(apic_wrongintr4), &IDTVEC(apic_wrongintr5),
143 &IDTVEC(apic_wrongintr6), &IDTVEC(apic_wrongintr7),
144 &IDTVEC(apic_wrongintr8), &IDTVEC(apic_wrongintr9),
145 &IDTVEC(apic_wrongintr10), &IDTVEC(apic_wrongintr11),
146 &IDTVEC(apic_wrongintr12), &IDTVEC(apic_wrongintr13),
147 &IDTVEC(apic_wrongintr14), &IDTVEC(apic_wrongintr15),
148 &IDTVEC(apic_wrongintr16), &IDTVEC(apic_wrongintr17),
149 &IDTVEC(apic_wrongintr18), &IDTVEC(apic_wrongintr19),
150 &IDTVEC(apic_wrongintr20), &IDTVEC(apic_wrongintr21),
151 &IDTVEC(apic_wrongintr22), &IDTVEC(apic_wrongintr23)
156 struct machintr_abi MachIntrABI = {
167 apic_setvar(int varid, const void *buf)
172 case MACHINTR_VAR_PICMODE:
173 picmode = *(const int *)buf;
183 apic_getvar(int varid, void *buf)
188 case MACHINTR_VAR_PICMODE:
189 *(int *)buf = picmode;
199 * Final configuration of the BSP's local APIC:
200 * - disable 'pic mode'.
201 * - disable 'virtual wire mode'.
210 /* leave 'pic mode' if necessary */
212 outb(0x22, 0x70); /* select IMCR */
213 byte = inb(0x23); /* current contents */
214 byte |= 0x01; /* mask external INTR */
215 outb(0x23, byte); /* disconnect 8259s/NMI */
219 * Setup lint0 (the 8259 'virtual wire' connection). We
220 * mask the interrupt.
222 temp = lapic.lvt_lint0;
223 temp |= APIC_LVT_MASKED;
224 lapic.lvt_lint0 = temp;
227 * setup lint1 to handle an NMI
229 temp = lapic.lvt_lint1;
230 temp &= ~APIC_LVT_MASKED;
231 lapic.lvt_lint1 = temp;
234 apic_dump("bsp_apic_configure()");
239 apic_vectorctl(int op, int intr, int flags)
247 if (intr < 0 || intr >= APIC_HWI_VECTORS)
255 case MACHINTR_VECTOR_SETUP:
257 * Setup an interrupt vector. First install the vector in the
258 * cpu's Interrupt Descriptor Table (IDT).
260 if (flags & INTR_FAST) {
261 vector = TPR_SLOW_INTS + intr;
262 setidt(vector, apic_wrongintr[intr],
263 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
264 vector = TPR_FAST_INTS + intr;
265 setidt(vector, apic_fastintr[intr],
266 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
268 vector = TPR_SLOW_INTS + intr;
271 * This is probably not needed any more. XXX
273 if (intr == apic_8254_intr || intr == 8) {
274 vector = TPR_FAST_INTS + intr;
276 setidt(vector, apic_slowintr[intr],
277 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
281 * Now reprogram the vector in the IO APIC. In order to avoid
282 * losing an EOI for a level interrupt, which is vector based,
283 * make sure that the IO APIC is programmed for edge-triggering
284 * first, then reprogrammed with the new vector. This should
287 if (int_to_apicintpin[intr].ioapic >= 0) {
289 select = int_to_apicintpin[intr].redirindex;
290 value = io_apic_read(int_to_apicintpin[intr].ioapic, select);
291 io_apic_write(int_to_apicintpin[intr].ioapic,
292 select, (value & ~APIC_TRIGMOD_MASK));
293 io_apic_write(int_to_apicintpin[intr].ioapic,
294 select, (value & ~IOART_INTVEC) | vector);
297 machintr_intren(intr);
299 case MACHINTR_VECTOR_TEARDOWN:
301 * Teardown an interrupt vector. The vector should already be
302 * installed in the cpu's IDT, but make sure.
304 machintr_intrdis(intr);
305 vector = TPR_SLOW_INTS + intr;
306 setidt(vector, apic_slowintr[intr], SDT_SYS386IGT, SEL_KPL,
307 GSEL(GCODE_SEL, SEL_KPL));
310 * And then reprogram the IO APIC to point to the SLOW vector (it may
311 * have previously been pointed to the FAST version of the vector).
312 * This will allow us to keep track of spurious interrupts.
314 * In order to avoid losing an EOI for a level interrupt, which is
315 * vector based, make sure that the IO APIC is programmed for
316 * edge-triggering first, then reprogrammed with the new vector.
317 * This should clear the IRR bit.
319 if (int_to_apicintpin[intr].ioapic >= 0) {
321 select = int_to_apicintpin[intr].redirindex;
322 value = io_apic_read(int_to_apicintpin[intr].ioapic, select);
323 io_apic_write(int_to_apicintpin[intr].ioapic,
324 select, (value & ~APIC_TRIGMOD_MASK));
325 io_apic_write(int_to_apicintpin[intr].ioapic,
326 select, (value & ~IOART_INTVEC) | vector);
330 case MACHINTR_VECTOR_SETDEFAULT:
332 * This is a just-in-case an int pin is running through the 8259
333 * when we don't expect it to, or an IO APIC pin somehow wound
334 * up getting enabled without us specifically programming it in
335 * this ABI. Note that IO APIC pins are by default programmed
336 * to IDT_OFFSET + intr.
338 vector = IDT_OFFSET + intr;
339 setidt(vector, apic_slowintr[intr], SDT_SYS386IGT, SEL_KPL,
340 GSEL(GCODE_SEL, SEL_KPL));