2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $
33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.55 2008/09/17 07:51:59 sephe Exp $
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
79 * The 3c90x series chips use a bus-master DMA interface for transfering
80 * packets to and from the controller chip. Some of the "vortex" cards
81 * (3c59x) also supported a bus master mode, however for those chips
82 * you could only DMA packets to/from a contiguous memory buffer. For
83 * transmission this would mean copying the contents of the queued mbuf
84 * chain into an mbuf cluster and then DMAing the cluster. This extra
85 * copy would sort of defeat the purpose of the bus master support for
86 * any packet that doesn't fit into a single mbuf.
88 * By contrast, the 3c90x cards support a fragment-based bus master
89 * mode where mbuf chains can be encapsulated using TX descriptors.
90 * This is similar to other PCI chips such as the Texas Instruments
91 * ThunderLAN and the Intel 82557/82558.
93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
94 * bus master chips because they maintain the old PIO interface for
95 * backwards compatibility, but starting with the 3c905B and the
96 * "cyclone" chips, the compatibility interface has been dropped.
97 * Since using bus master DMA is a big win, we use this driver to
98 * support the PCI "boomerang" chips even though they work with the
99 * "vortex" driver in order to obtain better performance.
102 #include "opt_polling.h"
103 #include "opt_ethernet.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/sockio.h>
108 #include <sys/endian.h>
109 #include <sys/mbuf.h>
110 #include <sys/kernel.h>
111 #include <sys/socket.h>
112 #include <sys/serialize.h>
114 #include <sys/rman.h>
115 #include <sys/thread2.h>
116 #include <sys/interrupt.h>
119 #include <net/ifq_var.h>
120 #include <net/if_arp.h>
121 #include <net/ethernet.h>
122 #include <net/if_dl.h>
123 #include <net/if_media.h>
124 #include <net/vlan/if_vlan_var.h>
128 #include "../mii_layer/mii.h"
129 #include "../mii_layer/miivar.h"
131 #include <bus/pci/pcireg.h>
132 #include <bus/pci/pcivar.h>
134 /* "controller miibus0" required. See GENERIC if you get errors here. */
135 #include "miibus_if.h"
137 #include "if_xlreg.h"
139 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
142 * Various supported device vendors/types and their names.
144 static struct xl_type xl_devs[] = {
145 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
146 "3Com 3c900-TPO Etherlink XL" },
147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
148 "3Com 3c900-COMBO Etherlink XL" },
149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
150 "3Com 3c905-TX Fast Etherlink XL" },
151 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
152 "3Com 3c905-T4 Fast Etherlink XL" },
153 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
154 "3Com 3c900B-TPO Etherlink XL" },
155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
156 "3Com 3c900B-COMBO Etherlink XL" },
157 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
158 "3Com 3c900B-TPC Etherlink XL" },
159 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
160 "3Com 3c900B-FL Etherlink XL" },
161 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
162 "3Com 3c905B-TX Fast Etherlink XL" },
163 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
164 "3Com 3c905B-T4 Fast Etherlink XL" },
165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
166 "3Com 3c905B-FX/SC Fast Etherlink XL" },
167 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
168 "3Com 3c905B-COMBO Fast Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
170 "3Com 3c905C-TX Fast Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
172 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
174 "3Com 3c980 Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
176 "3Com 3c980C Fast Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
178 "3Com 3cSOHO100-TX OfficeConnect" },
179 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
180 "3Com 3c450-TX HomeConnect" },
181 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
182 "3Com 3c555 Fast Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
184 "3Com 3c556 Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
186 "3Com 3c556B Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
188 "3Com 3c575TX Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
190 "3Com 3c575B Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
192 "3Com 3c575C Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
194 "3Com 3c656 Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
196 "3Com 3c656B Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
198 "3Com 3c656C Fast Etherlink XL" },
202 static int xl_probe (device_t);
203 static int xl_attach (device_t);
204 static int xl_detach (device_t);
205 static void xl_shutdown (device_t);
206 static int xl_suspend (device_t);
207 static int xl_resume (device_t);
209 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *);
210 static void xl_stats_update (void *);
211 static void xl_stats_update_serialized(void *);
212 static int xl_encap (struct xl_softc *, struct xl_chain *,
214 static void xl_rxeof (struct xl_softc *, int);
215 static int xl_rx_resync (struct xl_softc *);
216 static void xl_txeof (struct xl_softc *);
217 static void xl_txeof_90xB (struct xl_softc *);
218 static void xl_txeoc (struct xl_softc *);
219 static void xl_intr (void *);
220 static void xl_start_body (struct ifnet *, int);
221 static void xl_start (struct ifnet *);
222 static void xl_start_poll (struct ifnet *);
223 static void xl_start_90xB (struct ifnet *);
224 static int xl_ioctl (struct ifnet *, u_long, caddr_t,
226 static void xl_init (void *);
227 static void xl_stop (struct xl_softc *);
228 static void xl_watchdog (struct ifnet *);
229 #ifdef DEVICE_POLLING
230 static void xl_poll (struct ifnet *, enum poll_cmd, int);
232 static void xl_enable_intrs (struct xl_softc *, uint16_t);
234 static int xl_ifmedia_upd (struct ifnet *);
235 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
237 static int xl_eeprom_wait (struct xl_softc *);
238 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
239 static void xl_mii_sync (struct xl_softc *);
240 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
241 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
242 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
244 static void xl_setcfg (struct xl_softc *);
245 static void xl_setmode (struct xl_softc *, int);
246 static void xl_setmulti (struct xl_softc *);
247 static void xl_setmulti_hash (struct xl_softc *);
248 static void xl_reset (struct xl_softc *);
249 static int xl_list_rx_init (struct xl_softc *);
250 static void xl_list_tx_init (struct xl_softc *);
251 static void xl_list_tx_init_90xB(struct xl_softc *);
252 static void xl_wait (struct xl_softc *);
253 static void xl_mediacheck (struct xl_softc *);
254 static void xl_choose_xcvr (struct xl_softc *, int);
255 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int);
256 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t,
258 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t,
261 static int xl_dma_alloc (device_t);
262 static void xl_dma_free (device_t);
265 static void xl_testpacket (struct xl_softc *);
268 static int xl_miibus_readreg (device_t, int, int);
269 static int xl_miibus_writereg (device_t, int, int, int);
270 static void xl_miibus_statchg (device_t);
271 static void xl_miibus_mediainit (device_t);
273 static device_method_t xl_methods[] = {
274 /* Device interface */
275 DEVMETHOD(device_probe, xl_probe),
276 DEVMETHOD(device_attach, xl_attach),
277 DEVMETHOD(device_detach, xl_detach),
278 DEVMETHOD(device_shutdown, xl_shutdown),
279 DEVMETHOD(device_suspend, xl_suspend),
280 DEVMETHOD(device_resume, xl_resume),
283 DEVMETHOD(bus_print_child, bus_generic_print_child),
284 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
287 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
288 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
289 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
290 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
295 static driver_t xl_driver = {
298 sizeof(struct xl_softc)
301 static devclass_t xl_devclass;
303 DECLARE_DUMMY_MODULE(if_xl);
304 MODULE_DEPEND(if_xl, miibus, 1, 1, 1);
305 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
306 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0);
307 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
310 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs)
312 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF);
313 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs);
314 if (sc->xl_flags & XL_FLAG_FUNCREG)
315 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
319 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
324 *paddr = segs->ds_addr;
328 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
329 bus_size_t mapsize, int error)
335 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
337 *paddr = segs->ds_addr;
341 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
342 bus_size_t mapsize, int error)
350 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
354 for (i = 0; i < nseg; i++) {
355 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
356 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
357 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
358 total_len += segs[i].ds_len;
360 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
362 l->xl_status = htole32(total_len);
367 * Murphy's law says that it's possible the chip can wedge and
368 * the 'command in progress' bit may never clear. Hence, we wait
369 * only a finite amount of time to avoid getting caught in an
370 * infinite loop. Normally this delay routine would be a macro,
371 * but it isn't called during normal operation so we can afford
372 * to make it a function.
375 xl_wait(struct xl_softc *sc)
379 for (i = 0; i < XL_TIMEOUT; i++) {
380 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
385 if_printf(&sc->arpcom.ac_if, "command never completed!");
391 * MII access routines are provided for adapters with external
392 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
393 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
394 * Note: if you don't perform the MDIO operations just right,
395 * it's possible to end up with code that works correctly with
396 * some chips/CPUs/processor speeds/bus speeds/etc but not
400 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
401 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
404 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
405 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
408 * Sync the PHYs by setting data bit and strobing the clock 32 times.
411 xl_mii_sync(struct xl_softc *sc)
416 MII_SET(XL_MII_DIR|XL_MII_DATA);
418 for (i = 0; i < 32; i++) {
420 MII_SET(XL_MII_DATA);
421 MII_SET(XL_MII_DATA);
423 MII_SET(XL_MII_DATA);
424 MII_SET(XL_MII_DATA);
431 * Clock a series of bits through the MII.
434 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
441 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
443 MII_SET(XL_MII_DATA);
445 MII_CLR(XL_MII_DATA);
453 * Read an PHY register through the MII.
456 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
461 * Set up frame for RX.
463 frame->mii_stdelim = XL_MII_STARTDELIM;
464 frame->mii_opcode = XL_MII_READOP;
465 frame->mii_turnaround = 0;
469 * Select register window 4.
474 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
483 * Send command/address info.
485 xl_mii_send(sc, frame->mii_stdelim, 2);
486 xl_mii_send(sc, frame->mii_opcode, 2);
487 xl_mii_send(sc, frame->mii_phyaddr, 5);
488 xl_mii_send(sc, frame->mii_regaddr, 5);
491 MII_CLR((XL_MII_CLK|XL_MII_DATA));
499 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
503 * Now try reading data bits. If the ack failed, we still
504 * need to clock through 16 cycles to keep the PHY(s) in sync.
507 for(i = 0; i < 16; i++) {
514 for (i = 0x8000; i; i >>= 1) {
517 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
518 frame->mii_data |= i;
534 * Write to a PHY register through the MII.
537 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
540 * Set up frame for TX.
543 frame->mii_stdelim = XL_MII_STARTDELIM;
544 frame->mii_opcode = XL_MII_WRITEOP;
545 frame->mii_turnaround = XL_MII_TURNAROUND;
548 * Select the window 4.
553 * Turn on data output.
559 xl_mii_send(sc, frame->mii_stdelim, 2);
560 xl_mii_send(sc, frame->mii_opcode, 2);
561 xl_mii_send(sc, frame->mii_phyaddr, 5);
562 xl_mii_send(sc, frame->mii_regaddr, 5);
563 xl_mii_send(sc, frame->mii_turnaround, 2);
564 xl_mii_send(sc, frame->mii_data, 16);
579 xl_miibus_readreg(device_t dev, int phy, int reg)
582 struct xl_mii_frame frame;
584 sc = device_get_softc(dev);
587 * Pretend that PHYs are only available at MII address 24.
588 * This is to guard against problems with certain 3Com ASIC
589 * revisions that incorrectly map the internal transceiver
590 * control registers at all MII addresses. This can cause
591 * the miibus code to attach the same PHY several times over.
593 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
596 bzero((char *)&frame, sizeof(frame));
598 frame.mii_phyaddr = phy;
599 frame.mii_regaddr = reg;
600 xl_mii_readreg(sc, &frame);
602 return(frame.mii_data);
606 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
609 struct xl_mii_frame frame;
611 sc = device_get_softc(dev);
613 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
616 bzero((char *)&frame, sizeof(frame));
618 frame.mii_phyaddr = phy;
619 frame.mii_regaddr = reg;
620 frame.mii_data = data;
622 xl_mii_writereg(sc, &frame);
628 xl_miibus_statchg(device_t dev)
631 struct mii_data *mii;
633 sc = device_get_softc(dev);
634 mii = device_get_softc(sc->xl_miibus);
636 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
640 /* Set ASIC's duplex mode to match the PHY. */
642 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
643 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
645 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
646 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
650 * Special support for the 3c905B-COMBO. This card has 10/100 support
651 * plus BNC and AUI ports. This means we will have both an miibus attached
652 * plus some non-MII media settings. In order to allow this, we have to
653 * add the extra media to the miibus's ifmedia struct, but we can't do
654 * that during xl_attach() because the miibus hasn't been attached yet.
655 * So instead, we wait until the miibus probe/attach is done, at which
656 * point we will get a callback telling is that it's safe to add our
660 xl_miibus_mediainit(device_t dev)
663 struct mii_data *mii;
666 sc = device_get_softc(dev);
667 mii = device_get_softc(sc->xl_miibus);
668 ifm = &mii->mii_media;
670 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
672 * Check for a 10baseFL board in disguise.
674 if (sc->xl_type == XL_TYPE_905B &&
675 sc->xl_media == XL_MEDIAOPT_10FL) {
677 device_printf(dev, "found 10baseFL\n");
678 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
679 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
680 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
682 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
685 device_printf(dev, "found AUI\n");
686 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
690 if (sc->xl_media & XL_MEDIAOPT_BNC) {
692 device_printf(dev, "found BNC\n");
693 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
700 * The EEPROM is slow: give it time to come ready after issuing
704 xl_eeprom_wait(struct xl_softc *sc)
708 for (i = 0; i < 100; i++) {
709 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
716 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n");
724 * Read a sequence of words from the EEPROM. Note that ethernet address
725 * data is stored in the EEPROM in network byte order.
728 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
731 u_int16_t word = 0, *ptr;
732 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
733 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
735 * It's easy to accidentally overwrite the rom content!
736 * Note: the 3c575 uses 8bit EEPROM offsets.
740 if (xl_eeprom_wait(sc))
743 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
746 for (i = 0; i < cnt; i++) {
747 if (sc->xl_flags & XL_FLAG_8BITROM)
748 CSR_WRITE_2(sc, XL_W0_EE_CMD,
749 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
751 CSR_WRITE_2(sc, XL_W0_EE_CMD,
752 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
753 err = xl_eeprom_wait(sc);
756 word = CSR_READ_2(sc, XL_W0_EE_DATA);
757 ptr = (u_int16_t *)(dest + (i * 2));
768 * NICs older than the 3c905B have only one multicast option, which
769 * is to enable reception of all multicast frames.
772 xl_setmulti(struct xl_softc *sc)
775 struct ifmultiaddr *ifma;
779 ifp = &sc->arpcom.ac_if;
782 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
784 if (ifp->if_flags & IFF_ALLMULTI) {
785 rxfilt |= XL_RXFILTER_ALLMULTI;
786 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
790 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
794 rxfilt |= XL_RXFILTER_ALLMULTI;
796 rxfilt &= ~XL_RXFILTER_ALLMULTI;
798 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
804 * 3c905B adapters have a hash filter that we can program.
807 xl_setmulti_hash(struct xl_softc *sc)
811 struct ifmultiaddr *ifma;
815 ifp = &sc->arpcom.ac_if;
818 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
820 if (ifp->if_flags & IFF_ALLMULTI) {
821 rxfilt |= XL_RXFILTER_ALLMULTI;
822 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
825 rxfilt &= ~XL_RXFILTER_ALLMULTI;
828 /* first, zot all the existing hash bits */
829 for (i = 0; i < XL_HASHFILT_SIZE; i++)
830 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
832 /* now program new ones */
833 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
834 if (ifma->ifma_addr->sa_family != AF_LINK)
838 * Note: the 3c905B currently only supports a 64-bit
839 * hash table, which means we really only need 6 bits,
840 * but the manual indicates that future chip revisions
841 * will have a 256-bit hash table, hence the routine is
842 * set up to calculate 8 bits of position info in case
843 * we need it some day.
844 * Note II, The Sequel: _CURRENT_ versions of the 3c905B
845 * have a 256 bit hash table. This means we have to use
846 * all 8 bits regardless. On older cards, the upper 2
847 * bits will be ignored. Grrrr....
850 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
851 ETHER_ADDR_LEN) & 0xff;
852 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
857 rxfilt |= XL_RXFILTER_MULTIHASH;
859 rxfilt &= ~XL_RXFILTER_MULTIHASH;
861 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
868 xl_testpacket(struct xl_softc *sc)
873 ifp = &sc->arpcom.ac_if;
875 MGETHDR(m, MB_DONTWAIT, MT_DATA);
880 bcopy(&sc->arpcom.ac_enaddr,
881 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
882 bcopy(&sc->arpcom.ac_enaddr,
883 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
884 mtod(m, struct ether_header *)->ether_type = htons(3);
885 mtod(m, unsigned char *)[14] = 0;
886 mtod(m, unsigned char *)[15] = 0;
887 mtod(m, unsigned char *)[16] = 0xE3;
888 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
889 IF_ENQUEUE(&ifp->if_snd, m);
897 xl_setcfg(struct xl_softc *sc)
902 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
903 icfg &= ~XL_ICFG_CONNECTOR_MASK;
904 if (sc->xl_media & XL_MEDIAOPT_MII ||
905 sc->xl_media & XL_MEDIAOPT_BT4)
906 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
907 if (sc->xl_media & XL_MEDIAOPT_BTX)
908 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
910 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
911 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
917 xl_setmode(struct xl_softc *sc, int media)
919 struct ifnet *ifp = &sc->arpcom.ac_if;
923 if_printf(ifp, "selecting ");
926 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
928 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
930 if (sc->xl_media & XL_MEDIAOPT_BT) {
931 if (IFM_SUBTYPE(media) == IFM_10_T) {
932 kprintf("10baseT transceiver, ");
933 sc->xl_xcvr = XL_XCVR_10BT;
934 icfg &= ~XL_ICFG_CONNECTOR_MASK;
935 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
936 mediastat |= XL_MEDIASTAT_LINKBEAT|
937 XL_MEDIASTAT_JABGUARD;
938 mediastat &= ~XL_MEDIASTAT_SQEENB;
942 if (sc->xl_media & XL_MEDIAOPT_BFX) {
943 if (IFM_SUBTYPE(media) == IFM_100_FX) {
944 kprintf("100baseFX port, ");
945 sc->xl_xcvr = XL_XCVR_100BFX;
946 icfg &= ~XL_ICFG_CONNECTOR_MASK;
947 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
948 mediastat |= XL_MEDIASTAT_LINKBEAT;
949 mediastat &= ~XL_MEDIASTAT_SQEENB;
953 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
954 if (IFM_SUBTYPE(media) == IFM_10_5) {
955 kprintf("AUI port, ");
956 sc->xl_xcvr = XL_XCVR_AUI;
957 icfg &= ~XL_ICFG_CONNECTOR_MASK;
958 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
959 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
960 XL_MEDIASTAT_JABGUARD);
961 mediastat |= ~XL_MEDIASTAT_SQEENB;
963 if (IFM_SUBTYPE(media) == IFM_10_FL) {
964 kprintf("10baseFL transceiver, ");
965 sc->xl_xcvr = XL_XCVR_AUI;
966 icfg &= ~XL_ICFG_CONNECTOR_MASK;
967 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
968 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
969 XL_MEDIASTAT_JABGUARD);
970 mediastat |= ~XL_MEDIASTAT_SQEENB;
974 if (sc->xl_media & XL_MEDIAOPT_BNC) {
975 if (IFM_SUBTYPE(media) == IFM_10_2) {
976 kprintf("BNC port, ");
977 sc->xl_xcvr = XL_XCVR_COAX;
978 icfg &= ~XL_ICFG_CONNECTOR_MASK;
979 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
980 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
981 XL_MEDIASTAT_JABGUARD|
982 XL_MEDIASTAT_SQEENB);
986 if ((media & IFM_GMASK) == IFM_FDX ||
987 IFM_SUBTYPE(media) == IFM_100_FX) {
988 kprintf("full duplex\n");
990 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
992 kprintf("half duplex\n");
994 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
995 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
998 if (IFM_SUBTYPE(media) == IFM_10_2)
999 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1001 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1002 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1004 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1010 xl_reset(struct xl_softc *sc)
1015 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1016 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1017 XL_RESETOPT_DISADVFD:0));
1020 * If we're using memory mapped register mode, pause briefly
1021 * after issuing the reset command before trying to access any
1022 * other registers. With my 3c575C cardbus card, failing to do
1023 * this results in the system locking up while trying to poll
1024 * the command busy bit in the status register.
1026 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1029 for (i = 0; i < XL_TIMEOUT; i++) {
1031 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1035 if (i == XL_TIMEOUT)
1036 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n");
1038 /* Reset TX and RX. */
1039 /* Note: the RX reset takes an absurd amount of time
1040 * on newer versions of the Tornado chips such as those
1041 * on the 3c905CX and newer 3c908C cards. We wait an
1042 * extra amount of time so that xl_wait() doesn't complain
1043 * and annoy the users.
1045 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1048 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1051 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1052 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1054 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1055 XL_W2_RESET_OPTIONS)
1056 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1057 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1061 /* Wait a little while for the chip to get its brains in order. */
1067 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1068 * IDs against our list and return a device name if we find a match.
1071 xl_probe(device_t dev)
1076 vid = pci_get_vendor(dev);
1077 did = pci_get_device(dev);
1078 for (t = xl_devs; t->xl_name != NULL; t++) {
1079 if (vid == t->xl_vid && did == t->xl_did) {
1080 device_set_desc(dev, t->xl_name);
1088 * This routine is a kludge to work around possible hardware faults
1089 * or manufacturing defects that can cause the media options register
1090 * (or reset options register, as it's called for the first generation
1091 * 3c90x adapters) to return an incorrect result. I have encountered
1092 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1093 * which doesn't have any of the 'mediaopt' bits set. This screws up
1094 * the attach routine pretty badly because it doesn't know what media
1095 * to look for. If we find ourselves in this predicament, this routine
1096 * will try to guess the media options values and warn the user of a
1097 * possible manufacturing defect with his adapter/system/whatever.
1100 xl_mediacheck(struct xl_softc *sc)
1102 struct ifnet *ifp = &sc->arpcom.ac_if;
1105 * If some of the media options bits are set, assume they are
1106 * correct. If not, try to figure it out down below.
1107 * XXX I should check for 10baseFL, but I don't have an adapter
1110 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1112 * Check the XCVR value. If it's not in the normal range
1113 * of values, we need to fake it up here.
1115 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1118 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n",
1121 "choosing new default based on card type\n");
1124 if (sc->xl_type == XL_TYPE_905B &&
1125 sc->xl_media & XL_MEDIAOPT_10FL)
1127 if_printf(ifp, "WARNING: no media options bits set in "
1128 "the media options register!!\n");
1129 if_printf(ifp, "this could be a manufacturing defect in "
1130 "your adapter or system\n");
1131 if_printf(ifp, "attempting to guess media type; you "
1132 "should probably consult your vendor\n");
1135 xl_choose_xcvr(sc, 1);
1139 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1141 struct ifnet *ifp = &sc->arpcom.ac_if;
1145 * Read the device ID from the EEPROM.
1146 * This is what's loaded into the PCI device ID register, so it has
1147 * to be correct otherwise we wouldn't have gotten this far.
1149 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1152 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1153 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1154 sc->xl_media = XL_MEDIAOPT_BT;
1155 sc->xl_xcvr = XL_XCVR_10BT;
1157 if_printf(ifp, "guessing 10BaseT transceiver\n");
1159 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1160 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1161 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1162 sc->xl_xcvr = XL_XCVR_10BT;
1164 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n");
1166 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1167 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1168 sc->xl_xcvr = XL_XCVR_10BT;
1170 if_printf(ifp, "guessing TPC (BNC/TP)\n");
1172 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1173 sc->xl_media = XL_MEDIAOPT_10FL;
1174 sc->xl_xcvr = XL_XCVR_AUI;
1176 if_printf(ifp, "guessing 10baseFL\n");
1178 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1179 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1180 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1181 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1182 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1183 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1184 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1185 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1186 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1187 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1188 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1189 sc->xl_media = XL_MEDIAOPT_MII;
1190 sc->xl_xcvr = XL_XCVR_MII;
1192 if_printf(ifp, "guessing MII\n");
1194 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1195 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1196 sc->xl_media = XL_MEDIAOPT_BT4;
1197 sc->xl_xcvr = XL_XCVR_MII;
1199 if_printf(ifp, "guessing 100BaseT4/MII\n");
1201 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1202 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1203 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1204 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1205 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1206 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1207 sc->xl_media = XL_MEDIAOPT_BTX;
1208 sc->xl_xcvr = XL_XCVR_AUTO;
1210 if_printf(ifp, "guessing 10/100 internal\n");
1212 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1213 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1214 sc->xl_xcvr = XL_XCVR_AUTO;
1216 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n");
1220 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1221 sc->xl_media = XL_MEDIAOPT_BT;
1229 * Attach the interface. Allocate softc structures, do ifmedia
1230 * setup and ethernet/BPF attach.
1233 xl_attach(device_t dev)
1235 u_char eaddr[ETHER_ADDR_LEN];
1237 struct xl_softc *sc;
1239 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1240 int error = 0, rid, res;
1243 sc = device_get_softc(dev);
1245 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1247 did = pci_get_device(dev);
1250 if (did == TC_DEVICEID_HURRICANE_555)
1251 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1252 if (did == TC_DEVICEID_HURRICANE_556 ||
1253 did == TC_DEVICEID_HURRICANE_556B)
1254 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1255 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1256 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1257 if (did == TC_DEVICEID_HURRICANE_555 ||
1258 did == TC_DEVICEID_HURRICANE_556)
1259 sc->xl_flags |= XL_FLAG_8BITROM;
1260 if (did == TC_DEVICEID_HURRICANE_556B)
1261 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1262 if (did == TC_DEVICEID_HURRICANE_575B ||
1263 did == TC_DEVICEID_HURRICANE_575C ||
1264 did == TC_DEVICEID_HURRICANE_656B ||
1265 did == TC_DEVICEID_TORNADO_656C)
1266 sc->xl_flags |= XL_FLAG_FUNCREG;
1267 if (did == TC_DEVICEID_HURRICANE_575A ||
1268 did == TC_DEVICEID_HURRICANE_575B ||
1269 did == TC_DEVICEID_HURRICANE_575C ||
1270 did == TC_DEVICEID_HURRICANE_656B ||
1271 did == TC_DEVICEID_TORNADO_656C)
1272 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1274 if (did == TC_DEVICEID_HURRICANE_656)
1275 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1276 if (did == TC_DEVICEID_HURRICANE_575B)
1277 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1278 if (did == TC_DEVICEID_HURRICANE_575C)
1279 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1280 if (did == TC_DEVICEID_TORNADO_656C)
1281 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1282 if (did == TC_DEVICEID_HURRICANE_656 ||
1283 did == TC_DEVICEID_HURRICANE_656B)
1284 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1285 XL_FLAG_INVERT_LED_PWR;
1286 if (did == TC_DEVICEID_TORNADO_10_100BT_920B)
1287 sc->xl_flags |= XL_FLAG_PHYOK;
1288 #ifndef BURN_BRIDGES
1290 * If this is a 3c905B, we have to check one extra thing.
1291 * The 905B supports power management and may be placed in
1292 * a low-power mode (D3 mode), typically by certain operating
1293 * systems which shall not be named. The PCI BIOS is supposed
1294 * to reset the NIC and bring it out of low-power mode, but
1295 * some do not. Consequently, we have to see if this chip
1296 * supports power management, and if so, make sure it's not
1297 * in low-power mode. If power management is available, the
1298 * capid byte will be 0x01.
1300 * I _think_ that what actually happens is that the chip
1301 * loses its PCI configuration during the transition from
1302 * D3 back to D0; this means that it should be possible for
1303 * us to save the PCI iobase, membase and IRQ, put the chip
1304 * back in the D0 state, then restore the PCI config ourselves.
1307 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1308 u_int32_t iobase, membase, irq;
1310 /* Save important PCI config data. */
1311 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1312 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1313 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1315 /* Reset the power state. */
1316 device_printf(dev, "chip is in D%d power mode "
1317 "-- setting to D0\n", pci_get_powerstate(dev));
1319 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1321 /* Restore PCI config data. */
1322 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1323 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1324 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1328 * Map control/status registers.
1330 pci_enable_busmaster(dev);
1333 res = SYS_RES_MEMORY;
1336 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1339 if (sc->xl_res != NULL) {
1340 sc->xl_flags |= XL_FLAG_USE_MMIO;
1342 device_printf(dev, "using memory mapped I/O\n");
1345 res = SYS_RES_IOPORT;
1346 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1347 if (sc->xl_res == NULL) {
1348 device_printf(dev, "couldn't map ports/memory\n");
1353 device_printf(dev, "using port I/O\n");
1356 sc->xl_btag = rman_get_bustag(sc->xl_res);
1357 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1359 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1360 rid = XL_PCI_FUNCMEM;
1361 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1364 if (sc->xl_fres == NULL) {
1365 device_printf(dev, "couldn't map funcreg memory\n");
1370 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1371 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1374 /* Allocate interrupt */
1376 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1377 RF_SHAREABLE | RF_ACTIVE);
1378 if (sc->xl_irq == NULL) {
1379 device_printf(dev, "couldn't map interrupt\n");
1384 ifp = &sc->arpcom.ac_if;
1385 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1387 /* Reset the adapter. */
1391 * Get station address from the EEPROM.
1393 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1394 device_printf(dev, "failed to read station address\n");
1399 callout_init(&sc->xl_stat_timer);
1401 error = xl_dma_alloc(dev);
1406 * Figure out the card type. 3c905B adapters have the
1407 * 'supportsNoTxLength' bit set in the capabilities
1408 * word in the EEPROM.
1409 * Note: my 3c575C cardbus card lies. It returns a value
1410 * of 0x1578 for its capabilities word, which is somewhat
1411 * nonsensical. Another way to distinguish a 3c90x chip
1412 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1413 * bit. This will only be set for 3c90x boomerage chips.
1415 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1416 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1417 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1418 sc->xl_type = XL_TYPE_905B;
1420 sc->xl_type = XL_TYPE_90X;
1422 device_printf(dev, "type %s\n",
1423 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X");
1427 ifp->if_mtu = ETHERMTU;
1428 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1429 ifp->if_ioctl = xl_ioctl;
1430 if (sc->xl_type == XL_TYPE_905B) {
1431 ifp->if_start = xl_start_90xB;
1432 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_MTU;
1434 ifp->if_start = xl_start;
1436 ifp->if_watchdog = xl_watchdog;
1437 ifp->if_init = xl_init;
1438 #ifdef DEVICE_POLLING
1439 ifp->if_poll = xl_poll;
1441 ifp->if_baudrate = 10000000;
1442 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1443 ifq_set_ready(&ifp->if_snd);
1445 * NOTE: Hardware checksum features disabled by default.
1446 * This seems to corrupt tx packet data one out of a
1447 * million packets or so and then generates a good checksum
1448 * so the receiver doesn't know the packet is bad
1450 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1451 if (ifp->if_capenable & IFCAP_TXCSUM)
1452 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1455 * Now we have to see what sort of media we have.
1456 * This includes probing for an MII interace and a
1460 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1462 if_printf(ifp, "media options word: %x\n", sc->xl_media);
1464 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1465 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1466 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1467 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1471 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1472 || sc->xl_media & XL_MEDIAOPT_BT4) {
1474 if_printf(ifp, "found MII/AUTO\n");
1477 error = mii_phy_probe(dev, &sc->xl_miibus,
1478 xl_ifmedia_upd, xl_ifmedia_sts);
1480 if_printf(ifp, "no PHY found!\n");
1488 * Sanity check. If the user has selected "auto" and this isn't
1489 * a 10/100 card of some kind, we need to force the transceiver
1490 * type to something sane.
1492 if (sc->xl_xcvr == XL_XCVR_AUTO)
1493 xl_choose_xcvr(sc, bootverbose);
1498 if (sc->xl_media & XL_MEDIAOPT_BT) {
1500 if_printf(ifp, "found 10baseT\n");
1501 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1502 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1503 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1504 ifmedia_add(&sc->ifmedia,
1505 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1508 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1510 * Check for a 10baseFL board in disguise.
1512 if (sc->xl_type == XL_TYPE_905B &&
1513 sc->xl_media == XL_MEDIAOPT_10FL) {
1515 if_printf(ifp, "found 10baseFL\n");
1516 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1517 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1519 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1520 ifmedia_add(&sc->ifmedia,
1521 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1524 if_printf(ifp, "found AUI\n");
1525 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1529 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1531 if_printf(ifp, "found BNC\n");
1532 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1535 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1537 if_printf(ifp, "found 100baseFX\n");
1538 ifp->if_baudrate = 100000000;
1539 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1542 /* Choose a default media. */
1543 switch(sc->xl_xcvr) {
1545 media = IFM_ETHER|IFM_10_T;
1546 xl_setmode(sc, media);
1549 if (sc->xl_type == XL_TYPE_905B &&
1550 sc->xl_media == XL_MEDIAOPT_10FL) {
1551 media = IFM_ETHER|IFM_10_FL;
1552 xl_setmode(sc, media);
1554 media = IFM_ETHER|IFM_10_5;
1555 xl_setmode(sc, media);
1559 media = IFM_ETHER|IFM_10_2;
1560 xl_setmode(sc, media);
1563 case XL_XCVR_100BTX:
1565 /* Chosen by miibus */
1567 case XL_XCVR_100BFX:
1568 media = IFM_ETHER|IFM_100_FX;
1571 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr);
1573 * This will probably be wrong, but it prevents
1574 * the ifmedia code from panicking.
1576 media = IFM_ETHER|IFM_10_T;
1580 if (sc->xl_miibus == NULL)
1581 ifmedia_set(&sc->ifmedia, media);
1585 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1587 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1591 * Call MI attach routine.
1593 ether_ifattach(ifp, eaddr, NULL);
1596 * Tell the upper layer(s) we support long frames.
1598 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1600 /* Hook interrupt last to avoid having to lock softc */
1601 error = bus_setup_intr(dev, sc->xl_irq, INTR_MPSAFE,
1602 xl_intr, sc, &sc->xl_intrhand,
1603 ifp->if_serializer);
1605 if_printf(ifp, "couldn't set up irq\n");
1606 ether_ifdetach(ifp);
1610 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->xl_irq));
1611 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1621 * Shutdown hardware and free up resources. This can be called any
1622 * time after the mutex has been initialized. It is called in both
1623 * the error case in attach and the normal detach case so it needs
1624 * to be careful about only freeing resources that have actually been
1628 xl_detach(device_t dev)
1630 struct xl_softc *sc;
1634 sc = device_get_softc(dev);
1635 ifp = &sc->arpcom.ac_if;
1637 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1639 res = SYS_RES_MEMORY;
1642 res = SYS_RES_IOPORT;
1645 if (device_is_attached(dev)) {
1646 lwkt_serialize_enter(ifp->if_serializer);
1649 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1650 lwkt_serialize_exit(ifp->if_serializer);
1652 ether_ifdetach(ifp);
1656 device_delete_child(dev, sc->xl_miibus);
1657 bus_generic_detach(dev);
1658 ifmedia_removeall(&sc->ifmedia);
1661 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1662 if (sc->xl_fres != NULL)
1663 bus_release_resource(dev, SYS_RES_MEMORY,
1664 XL_PCI_FUNCMEM, sc->xl_fres);
1666 bus_release_resource(dev, res, rid, sc->xl_res);
1674 xl_dma_alloc(device_t dev)
1676 struct xl_softc *sc;
1677 struct xl_chain_data *cd;
1678 struct xl_list_data *ld;
1681 sc = device_get_softc(dev);
1686 * Now allocate a tag for the DMA descriptor lists and a chunk
1687 * of DMA-able memory based on the tag. Also obtain the DMA
1688 * addresses of the RX and TX ring, which we'll need later.
1689 * All of our lists are allocated as a contiguous block
1692 error = bus_dma_tag_create(NULL, 8, 0,
1693 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1695 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ,
1698 device_printf(dev, "failed to allocate rx dma tag\n");
1702 error = bus_dmamem_alloc(ld->xl_rx_tag, (void **)&ld->xl_rx_list,
1703 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1706 device_printf(dev, "no memory for rx list buffers!\n");
1707 bus_dma_tag_destroy(ld->xl_rx_tag);
1708 ld->xl_rx_tag = NULL;
1712 error = bus_dmamap_load(ld->xl_rx_tag, ld->xl_rx_dmamap,
1713 ld->xl_rx_list, XL_RX_LIST_SZ,
1714 xl_dma_map_addr, &ld->xl_rx_dmaaddr,
1717 device_printf(dev, "cannot get dma address of the rx ring!\n");
1718 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list,
1720 bus_dma_tag_destroy(ld->xl_rx_tag);
1721 ld->xl_rx_tag = NULL;
1725 error = bus_dma_tag_create(NULL, 8, 0,
1726 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1728 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ,
1731 device_printf(dev, "failed to allocate tx dma tag\n");
1735 error = bus_dmamem_alloc(ld->xl_tx_tag, (void **)&ld->xl_tx_list,
1736 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1739 device_printf(dev, "no memory for list buffers!\n");
1740 bus_dma_tag_destroy(ld->xl_tx_tag);
1741 ld->xl_tx_tag = NULL;
1745 error = bus_dmamap_load(ld->xl_tx_tag, ld->xl_tx_dmamap,
1746 ld->xl_tx_list, XL_TX_LIST_SZ,
1747 xl_dma_map_addr, &ld->xl_tx_dmaaddr,
1750 device_printf(dev, "cannot get dma address of the tx ring!\n");
1751 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list,
1753 bus_dma_tag_destroy(ld->xl_tx_tag);
1754 ld->xl_tx_tag = NULL;
1759 * Allocate a DMA tag for the mapping of mbufs.
1761 error = bus_dma_tag_create(NULL, 1, 0,
1762 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1764 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS,
1765 MCLBYTES, 0, &sc->xl_mtag);
1767 device_printf(dev, "failed to allocate mbuf dma tag\n");
1772 * Allocate a spare DMA map for the RX ring.
1774 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1776 device_printf(dev, "failed to create mbuf dma map\n");
1777 bus_dma_tag_destroy(sc->xl_mtag);
1782 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1783 error = bus_dmamap_create(sc->xl_mtag, 0,
1784 &cd->xl_rx_chain[i].xl_map);
1786 device_printf(dev, "failed to create %dth "
1787 "rx descriptor dma map!\n", i);
1790 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1793 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1794 error = bus_dmamap_create(sc->xl_mtag, 0,
1795 &cd->xl_tx_chain[i].xl_map);
1797 device_printf(dev, "failed to create %dth "
1798 "tx descriptor dma map!\n", i);
1801 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1807 xl_dma_free(device_t dev)
1809 struct xl_softc *sc;
1810 struct xl_chain_data *cd;
1811 struct xl_list_data *ld;
1814 sc = device_get_softc(dev);
1818 for (i = 0; i < XL_RX_LIST_CNT; ++i) {
1819 if (cd->xl_rx_chain[i].xl_ptr != NULL) {
1820 if (cd->xl_rx_chain[i].xl_mbuf != NULL) {
1821 bus_dmamap_unload(sc->xl_mtag,
1822 cd->xl_rx_chain[i].xl_map);
1823 m_freem(cd->xl_rx_chain[i].xl_mbuf);
1825 bus_dmamap_destroy(sc->xl_mtag,
1826 cd->xl_rx_chain[i].xl_map);
1830 for (i = 0; i < XL_TX_LIST_CNT; ++i) {
1831 if (cd->xl_tx_chain[i].xl_ptr != NULL) {
1832 if (cd->xl_tx_chain[i].xl_mbuf != NULL) {
1833 bus_dmamap_unload(sc->xl_mtag,
1834 cd->xl_tx_chain[i].xl_map);
1835 m_freem(cd->xl_tx_chain[i].xl_mbuf);
1837 bus_dmamap_destroy(sc->xl_mtag,
1838 cd->xl_tx_chain[i].xl_map);
1842 if (ld->xl_rx_tag) {
1843 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap);
1844 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list,
1846 bus_dma_tag_destroy(ld->xl_rx_tag);
1849 if (ld->xl_tx_tag) {
1850 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap);
1851 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list,
1853 bus_dma_tag_destroy(ld->xl_tx_tag);
1857 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1858 bus_dma_tag_destroy(sc->xl_mtag);
1863 * Initialize the transmit descriptors.
1866 xl_list_tx_init(struct xl_softc *sc)
1868 struct xl_chain_data *cd;
1869 struct xl_list_data *ld;
1874 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1875 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1876 i * sizeof(struct xl_list);
1877 if (i == (XL_TX_LIST_CNT - 1))
1878 cd->xl_tx_chain[i].xl_next = NULL;
1880 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1883 cd->xl_tx_free = &cd->xl_tx_chain[0];
1884 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1886 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1890 * Initialize the transmit descriptors.
1893 xl_list_tx_init_90xB(struct xl_softc *sc)
1895 struct xl_chain_data *cd;
1896 struct xl_list_data *ld;
1901 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1902 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1903 i * sizeof(struct xl_list);
1904 if (i == (XL_TX_LIST_CNT - 1))
1905 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1907 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1909 cd->xl_tx_chain[i].xl_prev =
1910 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1912 cd->xl_tx_chain[i].xl_prev =
1913 &cd->xl_tx_chain[i - 1];
1917 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1923 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1927 * Initialize the RX descriptors and allocate mbufs for them. Note that
1928 * we arrange the descriptors in a closed ring, so that the last descriptor
1929 * points back to the first.
1932 xl_list_rx_init(struct xl_softc *sc)
1934 struct xl_chain_data *cd;
1935 struct xl_list_data *ld;
1942 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1943 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1946 if (i == (XL_RX_LIST_CNT - 1))
1950 nextptr = ld->xl_rx_dmaaddr +
1951 next * sizeof(struct xl_list_onefrag);
1952 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1953 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1956 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1957 cd->xl_rx_head = &cd->xl_rx_chain[0];
1963 * Initialize an RX descriptor and attach an MBUF cluster.
1964 * If we fail to do so, we need to leave the old mbuf and
1965 * the old DMA map untouched so that it can be reused.
1968 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1975 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1979 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1981 /* Force longword alignment for packet payload. */
1982 m_adj(m_new, ETHER_ALIGN);
1984 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
1985 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
1988 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n",
1993 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1995 c->xl_map = sc->xl_tmpmap;
1996 sc->xl_tmpmap = map;
1998 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1999 c->xl_ptr->xl_status = 0;
2000 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
2001 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
2006 xl_rx_resync(struct xl_softc *sc)
2008 struct xl_chain_onefrag *pos;
2011 pos = sc->xl_cdata.xl_rx_head;
2013 for (i = 0; i < XL_RX_LIST_CNT; i++) {
2014 if (pos->xl_ptr->xl_status)
2019 if (i == XL_RX_LIST_CNT)
2022 sc->xl_cdata.xl_rx_head = pos;
2028 * A frame has been uploaded: pass the resulting mbuf chain up to
2029 * the higher level protocols.
2032 xl_rxeof(struct xl_softc *sc, int count)
2036 struct xl_chain_onefrag *cur_rx;
2039 #ifdef ETHER_INPUT_CHAIN
2040 struct mbuf_chain chain[MAXCPU];
2043 ifp = &sc->arpcom.ac_if;
2045 #ifdef ETHER_INPUT_CHAIN
2046 ether_input_chain_init(chain);
2051 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
2052 BUS_DMASYNC_POSTREAD);
2053 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
2054 #ifdef DEVICE_POLLING
2055 if (count >= 0 && count-- == 0)
2058 cur_rx = sc->xl_cdata.xl_rx_head;
2059 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
2060 total_len = rxstat & XL_RXSTAT_LENMASK;
2063 * Since we have told the chip to allow large frames,
2064 * we need to trap giant frame errors in software. We allow
2065 * a little more than the normal frame size to account for
2066 * frames with VLAN tags.
2068 if (total_len > XL_MAX_FRAMELEN)
2069 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
2072 * If an error occurs, update stats, clear the
2073 * status word and leave the mbuf cluster in place:
2074 * it should simply get re-used next time this descriptor
2075 * comes up in the ring.
2077 if (rxstat & XL_RXSTAT_UP_ERROR) {
2079 cur_rx->xl_ptr->xl_status = 0;
2080 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2081 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2086 * If the error bit was not set, the upload complete
2087 * bit should be set which means we have a valid packet.
2088 * If not, something truly strange has happened.
2090 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2092 "bad receive status -- packet dropped\n");
2094 cur_rx->xl_ptr->xl_status = 0;
2095 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2096 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2100 /* No errors; receive the packet. */
2101 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2102 BUS_DMASYNC_POSTREAD);
2103 m = cur_rx->xl_mbuf;
2106 * Try to conjure up a new mbuf cluster. If that
2107 * fails, it means we have an out of memory condition and
2108 * should leave the buffer in place and continue. This will
2109 * result in a lost packet, but there's little else we
2110 * can do in this situation.
2112 if (xl_newbuf(sc, cur_rx)) {
2114 cur_rx->xl_ptr->xl_status = 0;
2115 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2116 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2119 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2120 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2123 m->m_pkthdr.rcvif = ifp;
2124 m->m_pkthdr.len = m->m_len = total_len;
2126 if (ifp->if_capenable & IFCAP_RXCSUM) {
2127 /* Do IP checksum checking. */
2128 if (rxstat & XL_RXSTAT_IPCKOK)
2129 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2130 if (!(rxstat & XL_RXSTAT_IPCKERR))
2131 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2132 if ((rxstat & XL_RXSTAT_TCPCOK &&
2133 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2134 (rxstat & XL_RXSTAT_UDPCKOK &&
2135 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2136 m->m_pkthdr.csum_flags |=
2137 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
2138 CSUM_FRAG_NOT_CHECKED;
2139 m->m_pkthdr.csum_data = 0xffff;
2143 #ifdef ETHER_INPUT_CHAIN
2144 ether_input_chain(ifp, m, chain);
2146 ifp->if_input(ifp, m);
2150 if (sc->xl_type != XL_TYPE_905B) {
2152 * Handle the 'end of channel' condition. When the upload
2153 * engine hits the end of the RX ring, it will stall. This
2154 * is our cue to flush the RX ring, reload the uplist pointer
2155 * register and unstall the engine.
2156 * XXX This is actually a little goofy. With the ThunderLAN
2157 * chip, you get an interrupt when the receiver hits the end
2158 * of the receive ring, which tells you exactly when you
2159 * you need to reload the ring pointer. Here we have to
2160 * fake it. I'm mad at myself for not being clever enough
2161 * to avoid the use of a goto here.
2163 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2164 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2167 CSR_WRITE_4(sc, XL_UPLIST_PTR,
2168 sc->xl_ldata.xl_rx_dmaaddr);
2169 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2170 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2175 #ifdef ETHER_INPUT_CHAIN
2176 ether_input_dispatch(chain);
2181 * A frame was downloaded to the chip. It's safe for us to clean up
2185 xl_txeof(struct xl_softc *sc)
2187 struct xl_chain *cur_tx;
2190 ifp = &sc->arpcom.ac_if;
2192 /* Clear the timeout timer. */
2196 * Go through our tx list and free mbufs for those
2197 * frames that have been uploaded. Note: the 3c905B
2198 * sets a special bit in the status word to let us
2199 * know that a frame has been downloaded, but the
2200 * original 3c900/3c905 adapters don't do that.
2201 * Consequently, we have to use a different test if
2202 * xl_type != XL_TYPE_905B.
2204 while(sc->xl_cdata.xl_tx_head != NULL) {
2205 cur_tx = sc->xl_cdata.xl_tx_head;
2207 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2210 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2211 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2212 BUS_DMASYNC_POSTWRITE);
2213 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2214 m_freem(cur_tx->xl_mbuf);
2215 cur_tx->xl_mbuf = NULL;
2218 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2219 sc->xl_cdata.xl_tx_free = cur_tx;
2222 if (sc->xl_cdata.xl_tx_head == NULL) {
2223 ifp->if_flags &= ~IFF_OACTIVE;
2224 sc->xl_cdata.xl_tx_tail = NULL;
2226 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2227 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2228 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2229 sc->xl_cdata.xl_tx_head->xl_phys);
2230 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2238 xl_txeof_90xB(struct xl_softc *sc)
2240 struct xl_chain *cur_tx = NULL;
2244 ifp = &sc->arpcom.ac_if;
2246 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2247 BUS_DMASYNC_POSTREAD);
2248 idx = sc->xl_cdata.xl_tx_cons;
2249 while(idx != sc->xl_cdata.xl_tx_prod) {
2251 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2253 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2254 XL_TXSTAT_DL_COMPLETE))
2257 if (cur_tx->xl_mbuf != NULL) {
2258 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2259 BUS_DMASYNC_POSTWRITE);
2260 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2261 m_freem(cur_tx->xl_mbuf);
2262 cur_tx->xl_mbuf = NULL;
2267 sc->xl_cdata.xl_tx_cnt--;
2268 XL_INC(idx, XL_TX_LIST_CNT);
2272 sc->xl_cdata.xl_tx_cons = idx;
2275 ifp->if_flags &= ~IFF_OACTIVE;
2281 * TX 'end of channel' interrupt handler. Actually, we should
2282 * only get a 'TX complete' interrupt if there's a transmit error,
2283 * so this is really TX error handler.
2286 xl_txeoc(struct xl_softc *sc)
2288 struct ifnet *ifp = &sc->arpcom.ac_if;
2291 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2292 if (txstat & XL_TXSTATUS_UNDERRUN ||
2293 txstat & XL_TXSTATUS_JABBER ||
2294 txstat & XL_TXSTATUS_RECLAIM) {
2295 if_printf(ifp, "transmission error: %x\n", txstat);
2296 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2298 if (sc->xl_type == XL_TYPE_905B) {
2299 if (sc->xl_cdata.xl_tx_cnt) {
2302 i = sc->xl_cdata.xl_tx_cons;
2303 c = &sc->xl_cdata.xl_tx_chain[i];
2304 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2306 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2309 if (sc->xl_cdata.xl_tx_head != NULL)
2310 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2311 sc->xl_cdata.xl_tx_head->xl_phys);
2314 * Remember to set this for the
2315 * first generation 3c90X chips.
2317 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2318 if (txstat & XL_TXSTATUS_UNDERRUN &&
2319 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2320 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2321 if_printf(ifp, "tx underrun, increasing tx start"
2322 " threshold to %d bytes\n",
2325 CSR_WRITE_2(sc, XL_COMMAND,
2326 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2327 if (sc->xl_type == XL_TYPE_905B) {
2328 CSR_WRITE_2(sc, XL_COMMAND,
2329 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2331 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2332 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2334 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2335 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2338 * Write an arbitrary byte to the TX_STATUS register
2339 * to clear this interrupt/error and advance to the next.
2341 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2347 #ifdef DEVICE_POLLING
2350 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2352 struct xl_softc *sc = ifp->if_softc;
2354 ASSERT_SERIALIZED(ifp->if_serializer);
2358 xl_enable_intrs(sc, 0);
2359 if (sc->xl_type != XL_TYPE_905B)
2360 ifp->if_start = xl_start_poll;
2362 case POLL_DEREGISTER:
2363 if (sc->xl_type != XL_TYPE_905B)
2364 ifp->if_start = xl_start;
2365 xl_enable_intrs(sc, XL_INTRS);
2368 case POLL_AND_CHECK_STATUS:
2369 xl_rxeof(sc, count);
2370 if (sc->xl_type == XL_TYPE_905B)
2375 if (!ifq_is_empty(&ifp->if_snd))
2378 if (cmd == POLL_AND_CHECK_STATUS) {
2381 /* XXX copy & pasted from xl_intr() */
2382 status = CSR_READ_2(sc, XL_STATUS);
2383 if ((status & XL_INTRS) && status != 0xFFFF) {
2384 CSR_WRITE_2(sc, XL_COMMAND,
2385 XL_CMD_INTR_ACK | (status & XL_INTRS));
2387 if (status & XL_STAT_TX_COMPLETE) {
2392 if (status & XL_STAT_ADFAIL) {
2397 if (status & XL_STAT_STATSOFLOW) {
2398 sc->xl_stats_no_timeout = 1;
2399 xl_stats_update_serialized(sc);
2400 sc->xl_stats_no_timeout = 0;
2408 #endif /* DEVICE_POLLING */
2413 struct xl_softc *sc;
2418 ifp = &sc->arpcom.ac_if;
2420 ASSERT_SERIALIZED(ifp->if_serializer);
2422 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) &&
2425 CSR_WRITE_2(sc, XL_COMMAND,
2426 XL_CMD_INTR_ACK|(status & XL_INTRS));
2428 if (status & XL_STAT_UP_COMPLETE) {
2431 curpkts = ifp->if_ipackets;
2433 if (curpkts == ifp->if_ipackets) {
2434 while (xl_rx_resync(sc))
2439 if (status & XL_STAT_DOWN_COMPLETE) {
2440 if (sc->xl_type == XL_TYPE_905B)
2446 if (status & XL_STAT_TX_COMPLETE) {
2451 if (status & XL_STAT_ADFAIL) {
2456 if (status & XL_STAT_STATSOFLOW) {
2457 sc->xl_stats_no_timeout = 1;
2458 xl_stats_update_serialized(sc);
2459 sc->xl_stats_no_timeout = 0;
2463 if (!ifq_is_empty(&ifp->if_snd))
2468 xl_stats_update(void *xsc)
2470 struct xl_softc *sc = xsc;
2472 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2473 xl_stats_update_serialized(xsc);
2474 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2478 xl_stats_update_serialized(void *xsc)
2480 struct xl_softc *sc;
2482 struct xl_stats xl_stats;
2485 struct mii_data *mii = NULL;
2487 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2490 ifp = &sc->arpcom.ac_if;
2491 if (sc->xl_miibus != NULL)
2492 mii = device_get_softc(sc->xl_miibus);
2494 p = (u_int8_t *)&xl_stats;
2496 /* Read all the stats registers. */
2499 for (i = 0; i < 16; i++)
2500 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2502 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2504 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2505 xl_stats.xl_tx_single_collision +
2506 xl_stats.xl_tx_late_collision;
2509 * Boomerang and cyclone chips have an extra stats counter
2510 * in window 4 (BadSSD). We have to read this too in order
2511 * to clear out all the stats registers and avoid a statsoflow
2515 CSR_READ_1(sc, XL_W4_BADSSD);
2517 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2522 if (!sc->xl_stats_no_timeout)
2523 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2529 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2530 * pointers to the fragment pointers.
2533 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head)
2539 ifp = &sc->arpcom.ac_if;
2542 * Start packing the mbufs in this chain into
2543 * the fragment pointers. Stop when we run out
2544 * of fragments or hit the end of the mbuf chain.
2546 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2547 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2549 if (error && error != EFBIG) {
2551 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2556 * Handle special case: we used up all 63 fragments,
2557 * but we have more mbufs left in the chain. Copy the
2558 * data into an mbuf cluster. Note that we don't
2559 * bother clearing the values in the other fragment
2560 * pointers/counters; it wouldn't gain us anything,
2561 * and would waste cycles.
2566 m_new = m_defrag(m_head, MB_DONTWAIT);
2567 if (m_new == NULL) {
2574 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2575 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2578 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2583 if (sc->xl_type == XL_TYPE_905B) {
2584 status = XL_TXSTAT_RND_DEFEAT;
2586 if (m_head->m_pkthdr.csum_flags) {
2587 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2588 status |= XL_TXSTAT_IPCKSUM;
2589 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2590 status |= XL_TXSTAT_TCPCKSUM;
2591 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2592 status |= XL_TXSTAT_UDPCKSUM;
2594 c->xl_ptr->xl_status = htole32(status);
2597 c->xl_mbuf = m_head;
2598 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2603 xl_start(struct ifnet *ifp)
2605 ASSERT_SERIALIZED(ifp->if_serializer);
2606 xl_start_body(ifp, 1);
2610 xl_start_poll(struct ifnet *ifp)
2612 xl_start_body(ifp, 0);
2616 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2617 * to the mbuf data regions directly in the transmit lists. We also save a
2618 * copy of the pointers since the transmit list fragment pointers are
2619 * physical addresses.
2622 xl_start_body(struct ifnet *ifp, int proc_rx)
2624 struct xl_softc *sc;
2625 struct mbuf *m_head = NULL;
2626 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2627 struct xl_chain *prev_tx;
2633 * Check for an available queue slot. If there are none,
2636 if (sc->xl_cdata.xl_tx_free == NULL) {
2639 if (sc->xl_cdata.xl_tx_free == NULL) {
2640 ifp->if_flags |= IFF_OACTIVE;
2645 start_tx = sc->xl_cdata.xl_tx_free;
2647 while(sc->xl_cdata.xl_tx_free != NULL) {
2648 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2652 /* Pick a descriptor off the free list. */
2654 cur_tx = sc->xl_cdata.xl_tx_free;
2656 /* Pack the data into the descriptor. */
2657 error = xl_encap(sc, cur_tx, m_head);
2663 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2664 cur_tx->xl_next = NULL;
2666 /* Chain it together. */
2668 prev->xl_next = cur_tx;
2669 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2673 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2677 * If there are no packets queued, bail.
2683 * Place the request for the upload interrupt
2684 * in the last descriptor in the chain. This way, if
2685 * we're chaining several packets at once, we'll only
2686 * get an interupt once for the whole chain rather than
2687 * once for each packet.
2689 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2693 * Queue the packets. If the TX channel is clear, update
2694 * the downlist pointer register.
2696 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2699 if (sc->xl_cdata.xl_tx_head != NULL) {
2700 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2701 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2702 htole32(start_tx->xl_phys);
2703 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2704 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2705 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2706 sc->xl_cdata.xl_tx_tail = cur_tx;
2708 sc->xl_cdata.xl_tx_head = start_tx;
2709 sc->xl_cdata.xl_tx_tail = cur_tx;
2711 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2712 BUS_DMASYNC_PREWRITE);
2714 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2715 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2717 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2722 * Set a timeout in case the chip goes out to lunch.
2728 * XXX Under certain conditions, usually on slower machines
2729 * where interrupts may be dropped, it's possible for the
2730 * adapter to chew up all the buffers in the receive ring
2731 * and stall, without us being able to do anything about it.
2732 * To guard against this, we need to make a pass over the
2733 * RX queue to make sure there aren't any packets pending.
2734 * Doing it here means we can flush the receive ring at the
2735 * same time the chip is DMAing the transmit descriptors we
2738 * 3Com goes to some lengths to emphasize the Parallel
2739 * Tasking (tm) nature of their chips in all their marketing
2740 * literature; we may as well take advantage of it. :)
2747 xl_start_90xB(struct ifnet *ifp)
2749 struct xl_softc *sc;
2750 struct mbuf *m_head = NULL;
2751 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2752 struct xl_chain *prev_tx;
2755 ASSERT_SERIALIZED(ifp->if_serializer);
2759 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
2762 idx = sc->xl_cdata.xl_tx_prod;
2763 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2765 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2767 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2768 ifp->if_flags |= IFF_OACTIVE;
2772 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2777 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2779 /* Pack the data into the descriptor. */
2780 error = xl_encap(sc, cur_tx, m_head);
2786 /* Chain it together. */
2788 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2791 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2793 XL_INC(idx, XL_TX_LIST_CNT);
2794 sc->xl_cdata.xl_tx_cnt++;
2798 * If there are no packets queued, bail.
2804 * Place the request for the upload interrupt
2805 * in the last descriptor in the chain. This way, if
2806 * we're chaining several packets at once, we'll only
2807 * get an interupt once for the whole chain rather than
2808 * once for each packet.
2810 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2813 /* Start transmission */
2814 sc->xl_cdata.xl_tx_prod = idx;
2815 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2817 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2818 BUS_DMASYNC_PREWRITE);
2821 * Set a timeout in case the chip goes out to lunch.
2829 struct xl_softc *sc = xsc;
2830 struct ifnet *ifp = &sc->arpcom.ac_if;
2832 u_int16_t rxfilt = 0;
2833 struct mii_data *mii = NULL;
2835 ASSERT_SERIALIZED(ifp->if_serializer);
2838 * Cancel pending I/O and free all RX/TX buffers.
2842 if (sc->xl_miibus == NULL) {
2843 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2846 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2850 if (sc->xl_miibus != NULL)
2851 mii = device_get_softc(sc->xl_miibus);
2853 /* Init our MAC address */
2855 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2856 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2857 sc->arpcom.ac_enaddr[i]);
2860 /* Clear the station mask. */
2861 for (i = 0; i < 3; i++)
2862 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2864 /* Reset TX and RX. */
2865 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2867 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2870 /* Init circular RX list. */
2871 error = xl_list_rx_init(sc);
2873 if_printf(ifp, "initialization of the rx ring failed (%d)\n",
2879 /* Init TX descriptors. */
2880 if (sc->xl_type == XL_TYPE_905B)
2881 xl_list_tx_init_90xB(sc);
2883 xl_list_tx_init(sc);
2886 * Set the TX freethresh value.
2887 * Note that this has no effect on 3c905B "cyclone"
2888 * cards but is required for 3c900/3c905 "boomerang"
2889 * cards in order to enable the download engine.
2891 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2893 /* Set the TX start threshold for best performance. */
2894 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2895 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2898 * If this is a 3c905B, also set the tx reclaim threshold.
2899 * This helps cut down on the number of tx reclaim errors
2900 * that could happen on a busy network. The chip multiplies
2901 * the register value by 16 to obtain the actual threshold
2902 * in bytes, so we divide by 16 when setting the value here.
2903 * The existing threshold value can be examined by reading
2904 * the register at offset 9 in window 5.
2906 if (sc->xl_type == XL_TYPE_905B) {
2907 CSR_WRITE_2(sc, XL_COMMAND,
2908 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2911 /* Set RX filter bits. */
2913 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2915 /* Set the individual bit to receive frames for this host only. */
2916 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2918 /* If we want promiscuous mode, set the allframes bit. */
2919 if (ifp->if_flags & IFF_PROMISC) {
2920 rxfilt |= XL_RXFILTER_ALLFRAMES;
2921 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2923 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2924 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2928 * Set capture broadcast bit to capture broadcast frames.
2930 if (ifp->if_flags & IFF_BROADCAST) {
2931 rxfilt |= XL_RXFILTER_BROADCAST;
2932 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2934 rxfilt &= ~XL_RXFILTER_BROADCAST;
2935 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2939 * Program the multicast filter, if necessary.
2941 if (sc->xl_type == XL_TYPE_905B)
2942 xl_setmulti_hash(sc);
2946 if (sc->xl_type == XL_TYPE_905B) {
2947 /* Set UP polling interval */
2948 CSR_WRITE_1(sc, XL_UP_POLL, 64);
2952 * Load the address of the RX list. We have to
2953 * stall the upload engine before we can manipulate
2954 * the uplist pointer register, then unstall it when
2955 * we're finished. We also have to wait for the
2956 * stall command to complete before proceeding.
2957 * Note that we have to do this after any RX resets
2958 * have completed since the uplist register is cleared
2961 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2963 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2964 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2967 if (sc->xl_type == XL_TYPE_905B) {
2968 /* Set DN polling interval */
2969 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2971 /* Load the address of the TX list */
2972 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2974 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2975 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2976 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2981 * If the coax transceiver is on, make sure to enable
2982 * the DC-DC converter.
2985 if (sc->xl_xcvr == XL_XCVR_COAX)
2986 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2988 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2991 * increase packet size to allow reception of 802.1q or ISL packets.
2992 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2993 * control register. For 3c90xB/C chips, use the RX packet size
2997 if (sc->xl_type == XL_TYPE_905B) {
2998 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
3001 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
3002 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
3003 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
3006 /* Clear out the stats counters. */
3007 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3008 sc->xl_stats_no_timeout = 1;
3009 xl_stats_update_serialized(sc);
3010 sc->xl_stats_no_timeout = 0;
3012 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
3013 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
3016 * Enable interrupts.
3018 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS);
3019 #ifdef DEVICE_POLLING
3020 /* Do not enable interrupt if polling(4) is enabled */
3021 if ((ifp->if_flags & IFF_POLLING) != 0)
3022 xl_enable_intrs(sc, 0);
3025 xl_enable_intrs(sc, XL_INTRS);
3027 /* Set the RX early threshold */
3028 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
3029 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
3031 /* Enable receiver and transmitter. */
3032 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
3034 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3040 /* Select window 7 for normal operations. */
3043 ifp->if_flags |= IFF_RUNNING;
3044 ifp->if_flags &= ~IFF_OACTIVE;
3046 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
3050 * Set media options.
3053 xl_ifmedia_upd(struct ifnet *ifp)
3055 struct xl_softc *sc;
3056 struct ifmedia *ifm = NULL;
3057 struct mii_data *mii = NULL;
3059 ASSERT_SERIALIZED(ifp->if_serializer);
3062 if (sc->xl_miibus != NULL)
3063 mii = device_get_softc(sc->xl_miibus);
3067 ifm = &mii->mii_media;
3069 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3074 xl_setmode(sc, ifm->ifm_media);
3081 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
3082 || sc->xl_media & XL_MEDIAOPT_BT4) {
3085 xl_setmode(sc, ifm->ifm_media);
3092 * Report current media status.
3095 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3097 struct xl_softc *sc;
3099 struct mii_data *mii = NULL;
3101 ASSERT_SERIALIZED(ifp->if_serializer);
3104 if (sc->xl_miibus != NULL)
3105 mii = device_get_softc(sc->xl_miibus);
3108 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3109 icfg >>= XL_ICFG_CONNECTOR_BITS;
3111 ifmr->ifm_active = IFM_ETHER;
3115 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3116 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3117 ifmr->ifm_active |= IFM_FDX;
3119 ifmr->ifm_active |= IFM_HDX;
3122 if (sc->xl_type == XL_TYPE_905B &&
3123 sc->xl_media == XL_MEDIAOPT_10FL) {
3124 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3125 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3126 ifmr->ifm_active |= IFM_FDX;
3128 ifmr->ifm_active |= IFM_HDX;
3130 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3133 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3136 * XXX MII and BTX/AUTO should be separate cases.
3139 case XL_XCVR_100BTX:
3144 ifmr->ifm_active = mii->mii_media_active;
3145 ifmr->ifm_status = mii->mii_media_status;
3148 case XL_XCVR_100BFX:
3149 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3152 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3160 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3162 struct xl_softc *sc = ifp->if_softc;
3163 struct ifreq *ifr = (struct ifreq *) data;
3165 struct mii_data *mii = NULL;
3168 ASSERT_SERIALIZED(ifp->if_serializer);
3173 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3174 if (ifp->if_flags & IFF_UP) {
3175 if (ifp->if_flags & IFF_RUNNING &&
3176 ifp->if_flags & IFF_PROMISC &&
3177 !(sc->xl_if_flags & IFF_PROMISC)) {
3178 rxfilt |= XL_RXFILTER_ALLFRAMES;
3179 CSR_WRITE_2(sc, XL_COMMAND,
3180 XL_CMD_RX_SET_FILT|rxfilt);
3182 } else if (ifp->if_flags & IFF_RUNNING &&
3183 !(ifp->if_flags & IFF_PROMISC) &&
3184 sc->xl_if_flags & IFF_PROMISC) {
3185 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3186 CSR_WRITE_2(sc, XL_COMMAND,
3187 XL_CMD_RX_SET_FILT|rxfilt);
3192 if (ifp->if_flags & IFF_RUNNING)
3195 sc->xl_if_flags = ifp->if_flags;
3200 if (sc->xl_type == XL_TYPE_905B)
3201 xl_setmulti_hash(sc);
3208 if (sc->xl_miibus != NULL)
3209 mii = device_get_softc(sc->xl_miibus);
3211 error = ifmedia_ioctl(ifp, ifr,
3212 &sc->ifmedia, command);
3214 error = ifmedia_ioctl(ifp, ifr,
3215 &mii->mii_media, command);
3218 ifp->if_capenable &= ~IFCAP_HWCSUM;
3219 ifp->if_capenable |= (ifr->ifr_reqcap & IFCAP_HWCSUM);
3220 if (ifp->if_capenable & IFCAP_HWCSUM)
3221 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3223 ifp->if_hwassist = 0;
3226 error = ether_ioctl(ifp, command, data);
3233 xl_watchdog(struct ifnet *ifp)
3235 struct xl_softc *sc;
3236 u_int16_t status = 0;
3238 ASSERT_SERIALIZED(ifp->if_serializer);
3244 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3245 if_printf(ifp, "watchdog timeout\n");
3247 if (status & XL_MEDIASTAT_CARRIER)
3248 if_printf(ifp, "no carrier - transceiver cable problem?\n");
3255 if (!ifq_is_empty(&ifp->if_snd))
3260 * Stop the adapter and free any mbufs allocated to the
3264 xl_stop(struct xl_softc *sc)
3269 ifp = &sc->arpcom.ac_if;
3270 ASSERT_SERIALIZED(ifp->if_serializer);
3274 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3275 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3276 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3277 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3279 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3280 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3284 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3286 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3290 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3291 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3292 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3293 if (sc->xl_flags & XL_FLAG_FUNCREG)
3294 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3296 /* Stop the stats updater. */
3297 callout_stop(&sc->xl_stat_timer);
3300 * Free data in the RX lists.
3302 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3303 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3304 bus_dmamap_unload(sc->xl_mtag,
3305 sc->xl_cdata.xl_rx_chain[i].xl_map);
3306 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3307 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3310 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3313 * Free the TX list buffers.
3315 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3316 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3317 bus_dmamap_unload(sc->xl_mtag,
3318 sc->xl_cdata.xl_tx_chain[i].xl_map);
3319 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3320 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3323 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3325 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3329 * Stop all chip I/O so that the kernel's probe routines don't
3330 * get confused by errant DMAs when rebooting.
3333 xl_shutdown(device_t dev)
3335 struct xl_softc *sc = device_get_softc(dev);
3337 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
3340 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
3344 xl_suspend(device_t dev)
3346 struct xl_softc *sc = device_get_softc(dev);
3348 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
3350 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
3356 xl_resume(device_t dev)
3358 struct xl_softc *sc;
3361 sc = device_get_softc(dev);
3362 ifp = &sc->arpcom.ac_if;
3364 lwkt_serialize_enter(ifp->if_serializer);
3366 if (ifp->if_flags & IFF_UP)
3368 lwkt_serialize_exit(ifp->if_serializer);