sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_dma.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34 #include "intel_ringbuffer.h"
  35 #include <linux/workqueue.h>
  36
  37 extern struct drm_i915_private *i915_mch_dev;
  38
  39 static int i915_driver_unload_int(struct drm_device *dev, bool locked);
  40
  41 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  42 {
  43         /*
  44          * The dri breadcrumb update races against the drm master disappearing.
  45          * Instead of trying to fix this (this is by far not the only ums issue)
  46          * just don't do the update in kms mode.
  47          */
  48         if (drm_core_check_feature(dev, DRIVER_MODESET))
  49                 return;
  50
  51         /* XXX: don't do it at all actually */
  52         return;
  53 }
  54
  55 static void i915_write_hws_pga(struct drm_device *dev)
  56 {
  57         drm_i915_private_t *dev_priv = dev->dev_private;
  58         u32 addr;
  59
  60         addr = dev_priv->status_page_dmah->busaddr;
  61         if (INTEL_INFO(dev)->gen >= 4)
  62                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  63         I915_WRITE(HWS_PGA, addr);
  64 }
  65
  66 /**
  67  * Sets up the hardware status page for devices that need a physical address
  68  * in the register.
  69  */
  70 static int i915_init_phys_hws(struct drm_device *dev)
  71 {
  72         drm_i915_private_t *dev_priv = dev->dev_private;
  73         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  74
  75         /*
  76          * Program Hardware Status Page
  77          * XXXKIB Keep 4GB limit for allocation for now.  This method
  78          * of allocation is used on <= 965 hardware, that has several
  79          * erratas regarding the use of physical memory > 4 GB.
  80          */
  81         DRM_UNLOCK(dev);
  82         dev_priv->status_page_dmah =
  83                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  84         DRM_LOCK(dev);
  85         if (!dev_priv->status_page_dmah) {
  86                 DRM_ERROR("Can not allocate hardware status page\n");
  87                 return -ENOMEM;
  88         }
  89         ring->status_page.page_addr = dev_priv->hw_status_page =
  90             dev_priv->status_page_dmah->vaddr;
  91         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  92
  93         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  94
  95         i915_write_hws_pga(dev);
  96         DRM_DEBUG("Enabled hardware status page, phys %jx\n",
  97             (uintmax_t)dev_priv->dma_status_page);
  98         return 0;
  99 }
 100
 101 /**
 102  * Frees the hardware status page, whether it's a physical address or a virtual
 103  * address set up by the X Server.
 104  */
 105 static void i915_free_hws(struct drm_device *dev)
 106 {
 107         drm_i915_private_t *dev_priv = dev->dev_private;
 108         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 109
 110         if (dev_priv->status_page_dmah) {
 111                 drm_pci_free(dev, dev_priv->status_page_dmah);
 112                 dev_priv->status_page_dmah = NULL;
 113         }
 114
 115         if (dev_priv->status_gfx_addr) {
 116                 dev_priv->status_gfx_addr = 0;
 117                 ring->status_page.gfx_addr = 0;
 118                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 119         }
 120
 121         /* Need to rewrite hardware status page */
 122         I915_WRITE(HWS_PGA, 0x1ffff000);
 123 }
 124
 125 void i915_kernel_lost_context(struct drm_device * dev)
 126 {
 127         drm_i915_private_t *dev_priv = dev->dev_private;
 128         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 129
 130         /*
 131          * We should never lose context on the ring with modesetting
 132          * as we don't expose it to userspace
 133          */
 134         if (drm_core_check_feature(dev, DRIVER_MODESET))
 135                 return;
 136
 137         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 138         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 139         ring->space = ring->head - (ring->tail + 8);
 140         if (ring->space < 0)
 141                 ring->space += ring->size;
 142
 143 #if 1
 144         KIB_NOTYET();
 145 #else
 146         if (!dev->primary->master)
 147                 return;
 148 #endif
 149
 150         if (ring->head == ring->tail && dev_priv->sarea_priv)
 151                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 152 }
 153
 154 static int i915_dma_cleanup(struct drm_device * dev)
 155 {
 156         drm_i915_private_t *dev_priv = dev->dev_private;
 157         int i;
 158
 159
 160         /* Make sure interrupts are disabled here because the uninstall ioctl
 161          * may not have been called from userspace and after dev_private
 162          * is freed, it's too late.
 163          */
 164         if (dev->irq_enabled)
 165                 drm_irq_uninstall(dev);
 166
 167         for (i = 0; i < I915_NUM_RINGS; i++)
 168                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 169
 170         /* Clear the HWS virtual address at teardown */
 171         if (I915_NEED_GFX_HWS(dev))
 172                 i915_free_hws(dev);
 173
 174         return 0;
 175 }
 176
 177 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 178 {
 179         drm_i915_private_t *dev_priv = dev->dev_private;
 180         int ret;
 181
 182         dev_priv->sarea = drm_getsarea(dev);
 183         if (!dev_priv->sarea) {
 184                 DRM_ERROR("can not find sarea!\n");
 185                 i915_dma_cleanup(dev);
 186                 return -EINVAL;
 187         }
 188
 189         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 190             ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
 191
 192         if (init->ring_size != 0) {
 193                 if (LP_RING(dev_priv)->obj != NULL) {
 194                         i915_dma_cleanup(dev);
 195                         DRM_ERROR("Client tried to initialize ringbuffer in "
 196                                   "GEM mode\n");
 197                         return -EINVAL;
 198                 }
 199
 200                 ret = intel_render_ring_init_dri(dev,
 201                                                  init->ring_start,
 202                                                  init->ring_size);
 203                 if (ret) {
 204                         i915_dma_cleanup(dev);
 205                         return ret;
 206                 }
 207         }
 208
 209         dev_priv->cpp = init->cpp;
 210         dev_priv->back_offset = init->back_offset;
 211         dev_priv->front_offset = init->front_offset;
 212         dev_priv->current_page = 0;
 213         dev_priv->sarea_priv->pf_current_page = 0;
 214
 215         /* Allow hardware batchbuffers unless told otherwise.
 216          */
 217         dev_priv->allow_batchbuffer = 1;
 218
 219         return 0;
 220 }
 221
 222 static int i915_dma_resume(struct drm_device * dev)
 223 {
 224         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 225         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 226
 227         DRM_DEBUG("\n");
 228
 229         if (ring->map.handle == NULL) {
 230                 DRM_ERROR("can not ioremap virtual address for"
 231                           " ring buffer\n");
 232                 return -ENOMEM;
 233         }
 234
 235         /* Program Hardware Status Page */
 236         if (!ring->status_page.page_addr) {
 237                 DRM_ERROR("Can not find hardware status page\n");
 238                 return -EINVAL;
 239         }
 240         DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
 241         if (ring->status_page.gfx_addr != 0)
 242                 intel_ring_setup_status_page(ring);
 243         else
 244                 i915_write_hws_pga(dev);
 245
 246         DRM_DEBUG("Enabled hardware status page\n");
 247
 248         return 0;
 249 }
 250
 251 static int i915_dma_init(struct drm_device *dev, void *data,
 252                          struct drm_file *file_priv)
 253 {
 254         drm_i915_init_t *init = data;
 255         int retcode = 0;
 256
 257         switch (init->func) {
 258         case I915_INIT_DMA:
 259                 retcode = i915_initialize(dev, init);
 260                 break;
 261         case I915_CLEANUP_DMA:
 262                 retcode = i915_dma_cleanup(dev);
 263                 break;
 264         case I915_RESUME_DMA:
 265                 retcode = i915_dma_resume(dev);
 266                 break;
 267         default:
 268                 retcode = -EINVAL;
 269                 break;
 270         }
 271
 272         return retcode;
 273 }
 274
 275 /* Implement basically the same security restrictions as hardware does
 276  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 277  *
 278  * Most of the calculations below involve calculating the size of a
 279  * particular instruction.  It's important to get the size right as
 280  * that tells us where the next instruction to check is.  Any illegal
 281  * instruction detected will be given a size of zero, which is a
 282  * signal to abort the rest of the buffer.
 283  */
 284 static int do_validate_cmd(int cmd)
 285 {
 286         switch (((cmd >> 29) & 0x7)) {
 287         case 0x0:
 288                 switch ((cmd >> 23) & 0x3f) {
 289                 case 0x0:
 290                         return 1;       /* MI_NOOP */
 291                 case 0x4:
 292                         return 1;       /* MI_FLUSH */
 293                 default:
 294                         return 0;       /* disallow everything else */
 295                 }
 296                 break;
 297         case 0x1:
 298                 return 0;       /* reserved */
 299         case 0x2:
 300                 return (cmd & 0xff) + 2;        /* 2d commands */
 301         case 0x3:
 302                 if (((cmd >> 24) & 0x1f) <= 0x18)
 303                         return 1;
 304
 305                 switch ((cmd >> 24) & 0x1f) {
 306                 case 0x1c:
 307                         return 1;
 308                 case 0x1d:
 309                         switch ((cmd >> 16) & 0xff) {
 310                         case 0x3:
 311                                 return (cmd & 0x1f) + 2;
 312                         case 0x4:
 313                                 return (cmd & 0xf) + 2;
 314                         default:
 315                                 return (cmd & 0xffff) + 2;
 316                         }
 317                 case 0x1e:
 318                         if (cmd & (1 << 23))
 319                                 return (cmd & 0xffff) + 1;
 320                         else
 321                                 return 1;
 322                 case 0x1f:
 323                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 324                                 return (cmd & 0x1ffff) + 2;
 325                         else if (cmd & (1 << 17))       /* indirect random */
 326                                 if ((cmd & 0xffff) == 0)
 327                                         return 0;       /* unknown length, too hard */
 328                                 else
 329                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 330                         else
 331                                 return 2;       /* indirect sequential */
 332                 default:
 333                         return 0;
 334                 }
 335         default:
 336                 return 0;
 337         }
 338
 339         return 0;
 340 }
 341
 342 static int validate_cmd(int cmd)
 343 {
 344         int ret = do_validate_cmd(cmd);
 345
 346 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 347
 348         return ret;
 349 }
 350
 351 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 352                           int dwords)
 353 {
 354         drm_i915_private_t *dev_priv = dev->dev_private;
 355         int i, ret;
 356
 357         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 358                 return -EINVAL;
 359
 360         ret = BEGIN_LP_RING((dwords+1)&~1);
 361         if (ret)
 362                 return ret;
 363
 364         for (i = 0; i < dwords;) {
 365                 int cmd, sz;
 366
 367                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 368                         return -EINVAL;
 369
 370                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 371                         return -EINVAL;
 372
 373                 OUT_RING(cmd);
 374
 375                 while (++i, --sz) {
 376                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 377                                                          sizeof(cmd))) {
 378                                 return -EINVAL;
 379                         }
 380                         OUT_RING(cmd);
 381                 }
 382         }
 383
 384         if (dwords & 1)
 385                 OUT_RING(0);
 386
 387         ADVANCE_LP_RING();
 388
 389         return 0;
 390 }
 391
 392 int i915_emit_box(struct drm_device * dev,
 393                   struct drm_clip_rect *boxes,
 394                   int i, int DR1, int DR4)
 395 {
 396         struct drm_clip_rect box;
 397
 398         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 399                 return -EFAULT;
 400         }
 401
 402         return (i915_emit_box_p(dev, &box, DR1, DR4));
 403 }
 404
 405 int
 406 i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box,
 407     int DR1, int DR4)
 408 {
 409         drm_i915_private_t *dev_priv = dev->dev_private;
 410         int ret;
 411
 412         if (box->y2 <= box->y1 || box->x2 <= box->x1 || box->y2 <= 0 ||
 413             box->x2 <= 0) {
 414                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 415                           box->x1, box->y1, box->x2, box->y2);
 416                 return -EINVAL;
 417         }
 418
 419         if (INTEL_INFO(dev)->gen >= 4) {
 420                 ret = BEGIN_LP_RING(4);
 421                 if (ret != 0)
 422                         return (ret);
 423
 424                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 425                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 426                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 427                 OUT_RING(DR4);
 428         } else {
 429                 ret = BEGIN_LP_RING(6);
 430                 if (ret != 0)
 431                         return (ret);
 432
 433                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 434                 OUT_RING(DR1);
 435                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 436                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 437                 OUT_RING(DR4);
 438                 OUT_RING(0);
 439         }
 440         ADVANCE_LP_RING();
 441
 442         return 0;
 443 }
 444
 445 /* XXX: Emitting the counter should really be moved to part of the IRQ
 446  * emit. For now, do it in both places:
 447  */
 448
 449 static void i915_emit_breadcrumb(struct drm_device *dev)
 450 {
 451         drm_i915_private_t *dev_priv = dev->dev_private;
 452
 453         if (++dev_priv->counter > 0x7FFFFFFFUL)
 454                 dev_priv->counter = 0;
 455         if (dev_priv->sarea_priv)
 456                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 457
 458         if (BEGIN_LP_RING(4) == 0) {
 459                 OUT_RING(MI_STORE_DWORD_INDEX);
 460                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 461                 OUT_RING(dev_priv->counter);
 462                 OUT_RING(0);
 463                 ADVANCE_LP_RING();
 464         }
 465 }
 466
 467 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 468     drm_i915_cmdbuffer_t * cmd, struct drm_clip_rect *cliprects, void *cmdbuf)
 469 {
 470         int nbox = cmd->num_cliprects;
 471         int i = 0, count, ret;
 472
 473         if (cmd->sz & 0x3) {
 474                 DRM_ERROR("alignment\n");
 475                 return -EINVAL;
 476         }
 477
 478         i915_kernel_lost_context(dev);
 479
 480         count = nbox ? nbox : 1;
 481
 482         for (i = 0; i < count; i++) {
 483                 if (i < nbox) {
 484                         ret = i915_emit_box_p(dev, &cmd->cliprects[i],
 485                             cmd->DR1, cmd->DR4);
 486                         if (ret)
 487                                 return ret;
 488                 }
 489
 490                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 491                 if (ret)
 492                         return ret;
 493         }
 494
 495         i915_emit_breadcrumb(dev);
 496         return 0;
 497 }
 498
 499 static int
 500 i915_dispatch_batchbuffer(struct drm_device * dev,
 501     drm_i915_batchbuffer_t * batch, struct drm_clip_rect *cliprects)
 502 {
 503         drm_i915_private_t *dev_priv = dev->dev_private;
 504         int nbox = batch->num_cliprects;
 505         int i, count, ret;
 506
 507         if ((batch->start | batch->used) & 0x7) {
 508                 DRM_ERROR("alignment\n");
 509                 return -EINVAL;
 510         }
 511
 512         i915_kernel_lost_context(dev);
 513
 514         count = nbox ? nbox : 1;
 515
 516         for (i = 0; i < count; i++) {
 517                 if (i < nbox) {
 518                         int ret = i915_emit_box_p(dev, &cliprects[i],
 519                             batch->DR1, batch->DR4);
 520                         if (ret)
 521                                 return ret;
 522                 }
 523
 524                 if (!IS_I830(dev) && !IS_845G(dev)) {
 525                         ret = BEGIN_LP_RING(2);
 526                         if (ret != 0)
 527                                 return (ret);
 528
 529                         if (INTEL_INFO(dev)->gen >= 4) {
 530                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) |
 531                                     MI_BATCH_NON_SECURE_I965);
 532                                 OUT_RING(batch->start);
 533                         } else {
 534                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 535                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 536                         }
 537                 } else {
 538                         ret = BEGIN_LP_RING(4);
 539                         if (ret != 0)
 540                                 return (ret);
 541
 542                         OUT_RING(MI_BATCH_BUFFER);
 543                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 544                         OUT_RING(batch->start + batch->used - 4);
 545                         OUT_RING(0);
 546                 }
 547                 ADVANCE_LP_RING();
 548         }
 549
 550         i915_emit_breadcrumb(dev);
 551
 552         return 0;
 553 }
 554
 555 static int i915_dispatch_flip(struct drm_device * dev)
 556 {
 557         drm_i915_private_t *dev_priv = dev->dev_private;
 558         int ret;
 559
 560         if (!dev_priv->sarea_priv)
 561                 return -EINVAL;
 562
 563         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 564                   __func__,
 565                   dev_priv->current_page,
 566                   dev_priv->sarea_priv->pf_current_page);
 567
 568         i915_kernel_lost_context(dev);
 569
 570         ret = BEGIN_LP_RING(10);
 571         if (ret)
 572                 return ret;
 573         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 574         OUT_RING(0);
 575
 576         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 577         OUT_RING(0);
 578         if (dev_priv->current_page == 0) {
 579                 OUT_RING(dev_priv->back_offset);
 580                 dev_priv->current_page = 1;
 581         } else {
 582                 OUT_RING(dev_priv->front_offset);
 583                 dev_priv->current_page = 0;
 584         }
 585         OUT_RING(0);
 586
 587         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 588         OUT_RING(0);
 589
 590         ADVANCE_LP_RING();
 591
 592         if (++dev_priv->counter > 0x7FFFFFFFUL)
 593                 dev_priv->counter = 0;
 594         if (dev_priv->sarea_priv)
 595                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 596
 597         if (BEGIN_LP_RING(4) == 0) {
 598                 OUT_RING(MI_STORE_DWORD_INDEX);
 599                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 600                 OUT_RING(dev_priv->counter);
 601                 OUT_RING(0);
 602                 ADVANCE_LP_RING();
 603         }
 604
 605         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 606         return 0;
 607 }
 608
 609 static int i915_quiescent(struct drm_device *dev)
 610 {
 611         i915_kernel_lost_context(dev);
 612         return intel_ring_idle(LP_RING(dev->dev_private));
 613 }
 614
 615 static int
 616 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
 617 {
 618         int ret;
 619
 620         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 621
 622         DRM_LOCK(dev);
 623         ret = i915_quiescent(dev);
 624         DRM_UNLOCK(dev);
 625
 626         return (ret);
 627 }
 628
 629 static int i915_batchbuffer(struct drm_device *dev, void *data,
 630                             struct drm_file *file_priv)
 631 {
 632         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 633         drm_i915_sarea_t *sarea_priv;
 634         drm_i915_batchbuffer_t *batch = data;
 635         struct drm_clip_rect *cliprects;
 636         size_t cliplen;
 637         int ret;
 638
 639         if (!dev_priv->allow_batchbuffer) {
 640                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 641                 return -EINVAL;
 642         }
 643         DRM_UNLOCK(dev);
 644
 645         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 646                   batch->start, batch->used, batch->num_cliprects);
 647
 648         cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
 649         if (batch->num_cliprects < 0)
 650                 return -EFAULT;
 651         if (batch->num_cliprects != 0) {
 652                 cliprects = kmalloc(batch->num_cliprects *
 653                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 654                     M_WAITOK | M_ZERO);
 655
 656                 ret = -copyin(batch->cliprects, cliprects,
 657                     batch->num_cliprects * sizeof(struct drm_clip_rect));
 658                 if (ret != 0) {
 659                         DRM_LOCK(dev);
 660                         goto fail_free;
 661                 }
 662         } else
 663                 cliprects = NULL;
 664
 665         DRM_LOCK(dev);
 666         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 667         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 668
 669         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 670         if (sarea_priv)
 671                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 672
 673 fail_free:
 674         drm_free(cliprects, DRM_MEM_DMA);
 675         return ret;
 676 }
 677
 678 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 679                           struct drm_file *file_priv)
 680 {
 681         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 682         drm_i915_sarea_t *sarea_priv;
 683         drm_i915_cmdbuffer_t *cmdbuf = data;
 684         struct drm_clip_rect *cliprects = NULL;
 685         void *batch_data;
 686         int ret;
 687
 688         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 689                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 690
 691         if (cmdbuf->num_cliprects < 0)
 692                 return -EINVAL;
 693
 694         DRM_UNLOCK(dev);
 695
 696         batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
 697
 698         ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
 699         if (ret != 0) {
 700                 DRM_LOCK(dev);
 701                 goto fail_batch_free;
 702         }
 703
 704         if (cmdbuf->num_cliprects) {
 705                 cliprects = kmalloc(cmdbuf->num_cliprects *
 706                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 707                     M_WAITOK | M_ZERO);
 708                 ret = -copyin(cmdbuf->cliprects, cliprects,
 709                     cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
 710                 if (ret != 0) {
 711                         DRM_LOCK(dev);
 712                         goto fail_clip_free;
 713                 }
 714         }
 715
 716         DRM_LOCK(dev);
 717         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 718         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 719         if (ret) {
 720                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 721                 goto fail_clip_free;
 722         }
 723
 724         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 725         if (sarea_priv)
 726                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 727
 728 fail_clip_free:
 729         drm_free(cliprects, DRM_MEM_DMA);
 730 fail_batch_free:
 731         drm_free(batch_data, DRM_MEM_DMA);
 732         return ret;
 733 }
 734
 735 static int i915_emit_irq(struct drm_device * dev)
 736 {
 737         drm_i915_private_t *dev_priv = dev->dev_private;
 738 #if 0
 739         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 740 #endif
 741
 742         i915_kernel_lost_context(dev);
 743
 744         DRM_DEBUG("i915: emit_irq\n");
 745
 746         dev_priv->counter++;
 747         if (dev_priv->counter > 0x7FFFFFFFUL)
 748                 dev_priv->counter = 1;
 749 #if 0
 750         if (master_priv->sarea_priv)
 751                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 752 #else
 753         if (dev_priv->sarea_priv)
 754                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 755 #endif
 756
 757         if (BEGIN_LP_RING(4) == 0) {
 758                 OUT_RING(MI_STORE_DWORD_INDEX);
 759                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 760                 OUT_RING(dev_priv->counter);
 761                 OUT_RING(MI_USER_INTERRUPT);
 762                 ADVANCE_LP_RING();
 763         }
 764
 765         return dev_priv->counter;
 766 }
 767
 768 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 769 {
 770         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 771 #if 0
 772         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 773 #endif
 774         int ret = 0;
 775         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 776
 777         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 778                   READ_BREADCRUMB(dev_priv));
 779
 780 #if 0
 781         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 782                 if (master_priv->sarea_priv)
 783                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 784                 return 0;
 785         }
 786
 787         if (master_priv->sarea_priv)
 788                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 789 #else
 790         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 791                 if (dev_priv->sarea_priv) {
 792                         dev_priv->sarea_priv->last_dispatch =
 793                                 READ_BREADCRUMB(dev_priv);
 794                 }
 795                 return 0;
 796         }
 797
 798         if (dev_priv->sarea_priv)
 799                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 800 #endif
 801
 802         if (ring->irq_get(ring)) {
 803                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 804                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 805                 ring->irq_put(ring);
 806         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 807                 ret = -EBUSY;
 808
 809         if (ret == -EBUSY) {
 810                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 811                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 812         }
 813
 814         return ret;
 815 }
 816
 817 /* Needs the lock as it touches the ring.
 818  */
 819 int i915_irq_emit(struct drm_device *dev, void *data,
 820                          struct drm_file *file_priv)
 821 {
 822         drm_i915_private_t *dev_priv = dev->dev_private;
 823         drm_i915_irq_emit_t *emit = data;
 824         int result;
 825
 826         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 827                 DRM_ERROR("called with no initialization\n");
 828                 return -EINVAL;
 829         }
 830
 831         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 832
 833         DRM_LOCK(dev);
 834         result = i915_emit_irq(dev);
 835         DRM_UNLOCK(dev);
 836
 837         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 838                 DRM_ERROR("copy_to_user\n");
 839                 return -EFAULT;
 840         }
 841
 842         return 0;
 843 }
 844
 845 /* Doesn't need the hardware lock.
 846  */
 847 int i915_irq_wait(struct drm_device *dev, void *data,
 848                          struct drm_file *file_priv)
 849 {
 850         drm_i915_private_t *dev_priv = dev->dev_private;
 851         drm_i915_irq_wait_t *irqwait = data;
 852
 853         if (!dev_priv) {
 854                 DRM_ERROR("called with no initialization\n");
 855                 return -EINVAL;
 856         }
 857
 858         return i915_wait_irq(dev, irqwait->irq_seq);
 859 }
 860
 861 static int i915_flip_bufs(struct drm_device *dev, void *data,
 862                           struct drm_file *file_priv)
 863 {
 864         int ret;
 865
 866         DRM_DEBUG("%s\n", __func__);
 867
 868         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 869
 870         ret = i915_dispatch_flip(dev);
 871
 872         return ret;
 873 }
 874
 875 static int i915_getparam(struct drm_device *dev, void *data,
 876                          struct drm_file *file_priv)
 877 {
 878         drm_i915_private_t *dev_priv = dev->dev_private;
 879         drm_i915_getparam_t *param = data;
 880         int value;
 881
 882         if (!dev_priv) {
 883                 DRM_ERROR("called with no initialization\n");
 884                 return -EINVAL;
 885         }
 886
 887         switch (param->param) {
 888         case I915_PARAM_IRQ_ACTIVE:
 889                 value = dev->irq_enabled ? 1 : 0;
 890                 break;
 891         case I915_PARAM_ALLOW_BATCHBUFFER:
 892                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 893                 break;
 894         case I915_PARAM_LAST_DISPATCH:
 895                 value = READ_BREADCRUMB(dev_priv);
 896                 break;
 897         case I915_PARAM_CHIPSET_ID:
 898                 value = dev->pci_device;
 899                 break;
 900         case I915_PARAM_HAS_GEM:
 901                 value = 1;
 902                 break;
 903         case I915_PARAM_NUM_FENCES_AVAIL:
 904                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 905                 break;
 906         case I915_PARAM_HAS_OVERLAY:
 907                 value = dev_priv->overlay ? 1 : 0;
 908                 break;
 909         case I915_PARAM_HAS_PAGEFLIPPING:
 910                 value = 1;
 911                 break;
 912         case I915_PARAM_HAS_EXECBUF2:
 913                 value = 1;
 914                 break;
 915         case I915_PARAM_HAS_BSD:
 916                 value = HAS_BSD(dev);
 917                 break;
 918         case I915_PARAM_HAS_BLT:
 919                 value = HAS_BLT(dev);
 920                 break;
 921         case I915_PARAM_HAS_RELAXED_FENCING:
 922                 value = 1;
 923                 break;
 924         case I915_PARAM_HAS_COHERENT_RINGS:
 925                 value = 1;
 926                 break;
 927         case I915_PARAM_HAS_EXEC_CONSTANTS:
 928                 value = INTEL_INFO(dev)->gen >= 4;
 929                 break;
 930         case I915_PARAM_HAS_RELAXED_DELTA:
 931                 value = 1;
 932                 break;
 933         case I915_PARAM_HAS_GEN7_SOL_RESET:
 934                 value = 1;
 935                 break;
 936         case I915_PARAM_HAS_LLC:
 937                 value = HAS_LLC(dev);
 938                 break;
 939         default:
 940                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 941                                  param->param);
 942                 return -EINVAL;
 943         }
 944
 945         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 946                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 947                 return -EFAULT;
 948         }
 949
 950         return 0;
 951 }
 952
 953 static int i915_setparam(struct drm_device *dev, void *data,
 954                          struct drm_file *file_priv)
 955 {
 956         drm_i915_private_t *dev_priv = dev->dev_private;
 957         drm_i915_setparam_t *param = data;
 958
 959         if (!dev_priv) {
 960                 DRM_ERROR("called with no initialization\n");
 961                 return -EINVAL;
 962         }
 963
 964         switch (param->param) {
 965         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 966                 break;
 967         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 968                 dev_priv->tex_lru_log_granularity = param->value;
 969                 break;
 970         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 971                 dev_priv->allow_batchbuffer = param->value;
 972                 break;
 973         case I915_SETPARAM_NUM_USED_FENCES:
 974                 if (param->value > dev_priv->num_fence_regs ||
 975                     param->value < 0)
 976                         return -EINVAL;
 977                 /* Userspace can use first N regs */
 978                 dev_priv->fence_reg_start = param->value;
 979                 break;
 980         default:
 981                 DRM_DEBUG("unknown parameter %d\n", param->param);
 982                 return -EINVAL;
 983         }
 984
 985         return 0;
 986 }
 987
 988 static int i915_set_status_page(struct drm_device *dev, void *data,
 989                                 struct drm_file *file_priv)
 990 {
 991         drm_i915_private_t *dev_priv = dev->dev_private;
 992         drm_i915_hws_addr_t *hws = data;
 993         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 994
 995         if (!I915_NEED_GFX_HWS(dev))
 996                 return -EINVAL;
 997
 998         if (!dev_priv) {
 999                 DRM_ERROR("called with no initialization\n");
1000                 return -EINVAL;
1001         }
1002
1003         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1004         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1005                 DRM_ERROR("tried to set status page when mode setting active\n");
1006                 return 0;
1007         }
1008
1009         ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
1010             hws->addr & (0x1ffff<<12);
1011
1012         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1013         dev_priv->hws_map.size = 4*1024;
1014         dev_priv->hws_map.type = 0;
1015         dev_priv->hws_map.flags = 0;
1016         dev_priv->hws_map.mtrr = 0;
1017
1018         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
1019         if (dev_priv->hws_map.virtual == NULL) {
1020                 i915_dma_cleanup(dev);
1021                 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
1022                 DRM_ERROR("can not ioremap virtual address for"
1023                                 " G33 hw status page\n");
1024                 return -ENOMEM;
1025         }
1026         ring->status_page.page_addr = dev_priv->hw_status_page =
1027             dev_priv->hws_map.virtual;
1028
1029         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1030         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
1031         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
1032                         dev_priv->status_gfx_addr);
1033         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1034         return 0;
1035 }
1036
1037 static bool
1038 intel_enable_ppgtt(struct drm_device *dev)
1039 {
1040         if (i915_enable_ppgtt >= 0)
1041                 return i915_enable_ppgtt;
1042
1043         /* Disable ppgtt on SNB if VT-d is on. */
1044         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
1045                 return false;
1046
1047         return true;
1048 }
1049
1050 static int
1051 i915_load_gem_init(struct drm_device *dev)
1052 {
1053         struct drm_i915_private *dev_priv = dev->dev_private;
1054         unsigned long prealloc_size, gtt_size, mappable_size;
1055         int ret;
1056
1057         prealloc_size = dev_priv->mm.gtt->stolen_size;
1058         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1059         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1060
1061         /* Basic memrange allocator for stolen space */
1062         drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1063
1064         DRM_LOCK(dev);
1065         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
1066                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
1067                  * aperture accordingly when using aliasing ppgtt. */
1068                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
1069                 /* For paranoia keep the guard page in between. */
1070                 gtt_size -= PAGE_SIZE;
1071
1072                 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
1073
1074                 ret = i915_gem_init_aliasing_ppgtt(dev);
1075                 if (ret) {
1076                         DRM_UNLOCK(dev);
1077                         return ret;
1078                 }
1079         } else {
1080                 /* Let GEM Manage all of the aperture.
1081                  *
1082                  * However, leave one page at the end still bound to the scratch
1083                  * page.  There are a number of places where the hardware
1084                  * apparently prefetches past the end of the object, and we've
1085                  * seen multiple hangs with the GPU head pointer stuck in a
1086                  * batchbuffer bound at the last page of the aperture.  One page
1087                  * should be enough to keep any prefetching inside of the
1088                  * aperture.
1089                  */
1090                 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
1091         }
1092
1093         ret = i915_gem_init_hw(dev);
1094         DRM_UNLOCK(dev);
1095         if (ret != 0) {
1096                 i915_gem_cleanup_aliasing_ppgtt(dev);
1097                 return (ret);
1098         }
1099
1100 #if 0
1101         /* Try to set up FBC with a reasonable compressed buffer size */
1102         if (I915_HAS_FBC(dev) && i915_powersave) {
1103                 int cfb_size;
1104
1105                 /* Leave 1M for line length buffer & misc. */
1106
1107                 /* Try to get a 32M buffer... */
1108                 if (prealloc_size > (36*1024*1024))
1109                         cfb_size = 32*1024*1024;
1110                 else /* fall back to 7/8 of the stolen space */
1111                         cfb_size = prealloc_size * 7 / 8;
1112                 i915_setup_compression(dev, cfb_size);
1113         }
1114 #endif
1115
1116         /* Allow hardware batchbuffers unless told otherwise. */
1117         dev_priv->allow_batchbuffer = 1;
1118         return 0;
1119 }
1120
1121 static int
1122 i915_load_modeset_init(struct drm_device *dev)
1123 {
1124         struct drm_i915_private *dev_priv = dev->dev_private;
1125         int ret;
1126
1127         ret = intel_parse_bios(dev);
1128         if (ret)
1129                 DRM_INFO("failed to find VBIOS tables\n");
1130
1131 #if 0
1132         intel_register_dsm_handler();
1133 #endif
1134
1135         /* IIR "flip pending" bit means done if this bit is set */
1136         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1137                 dev_priv->flip_pending_is_done = true;
1138
1139         intel_modeset_init(dev);
1140
1141         ret = i915_load_gem_init(dev);
1142         if (ret != 0)
1143                 goto cleanup_gem;
1144
1145         intel_modeset_gem_init(dev);
1146
1147         ret = drm_irq_install(dev);
1148         if (ret)
1149                 goto cleanup_gem;
1150
1151         dev->vblank_disable_allowed = 1;
1152
1153         ret = intel_fbdev_init(dev);
1154         if (ret)
1155                 goto cleanup_gem;
1156
1157         drm_kms_helper_poll_init(dev);
1158
1159         /* We're off and running w/KMS */
1160         dev_priv->mm.suspended = 0;
1161
1162         return (0);
1163
1164 cleanup_gem:
1165         DRM_LOCK(dev);
1166         i915_gem_cleanup_ringbuffer(dev);
1167         DRM_UNLOCK(dev);
1168         i915_gem_cleanup_aliasing_ppgtt(dev);
1169         return (ret);
1170 }
1171
1172 static int
1173 i915_get_bridge_dev(struct drm_device *dev)
1174 {
1175         struct drm_i915_private *dev_priv;
1176
1177         dev_priv = dev->dev_private;
1178
1179         dev_priv->bridge_dev = intel_gtt_get_bridge_device();
1180         if (dev_priv->bridge_dev == NULL) {
1181                 DRM_ERROR("bridge device not found\n");
1182                 return (-1);
1183         }
1184         return (0);
1185 }
1186
1187 #define MCHBAR_I915 0x44
1188 #define MCHBAR_I965 0x48
1189 #define MCHBAR_SIZE (4*4096)
1190
1191 #define DEVEN_REG 0x54
1192 #define   DEVEN_MCHBAR_EN (1 << 28)
1193
1194 /* Allocate space for the MCH regs if needed, return nonzero on error */
1195 static int
1196 intel_alloc_mchbar_resource(struct drm_device *dev)
1197 {
1198         drm_i915_private_t *dev_priv;
1199         device_t vga;
1200         int reg;
1201         u32 temp_lo, temp_hi;
1202         u64 mchbar_addr, temp;
1203
1204         dev_priv = dev->dev_private;
1205         reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1206
1207         if (INTEL_INFO(dev)->gen >= 4)
1208                 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1209         else
1210                 temp_hi = 0;
1211         temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1212         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1213
1214         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1215 #ifdef XXX_CONFIG_PNP
1216         if (mchbar_addr &&
1217             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1218                 return 0;
1219 #endif
1220
1221         /* Get some space for it */
1222         vga = device_get_parent(dev->dev);
1223         dev_priv->mch_res_rid = 0x100;
1224         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1225             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1226             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1227         if (dev_priv->mch_res == NULL) {
1228                 DRM_ERROR("failed mchbar resource alloc\n");
1229                 return (-ENOMEM);
1230         }
1231
1232         if (INTEL_INFO(dev)->gen >= 4) {
1233                 temp = rman_get_start(dev_priv->mch_res);
1234                 temp >>= 32;
1235                 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1236         }
1237         pci_write_config(dev_priv->bridge_dev, reg,
1238             rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1239         return (0);
1240 }
1241
1242 static void
1243 intel_setup_mchbar(struct drm_device *dev)
1244 {
1245         drm_i915_private_t *dev_priv;
1246         int mchbar_reg;
1247         u32 temp;
1248         bool enabled;
1249
1250         dev_priv = dev->dev_private;
1251         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1252
1253         dev_priv->mchbar_need_disable = false;
1254
1255         if (IS_I915G(dev) || IS_I915GM(dev)) {
1256                 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1257                 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1258         } else {
1259                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1260                 enabled = temp & 1;
1261         }
1262
1263         /* If it's already enabled, don't have to do anything */
1264         if (enabled) {
1265                 DRM_DEBUG("mchbar already enabled\n");
1266                 return;
1267         }
1268
1269         if (intel_alloc_mchbar_resource(dev))
1270                 return;
1271
1272         dev_priv->mchbar_need_disable = true;
1273
1274         /* Space is allocated or reserved, so enable it. */
1275         if (IS_I915G(dev) || IS_I915GM(dev)) {
1276                 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1277                     temp | DEVEN_MCHBAR_EN, 4);
1278         } else {
1279                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1280                 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1281         }
1282 }
1283
1284 static void
1285 intel_teardown_mchbar(struct drm_device *dev)
1286 {
1287         drm_i915_private_t *dev_priv;
1288         device_t vga;
1289         int mchbar_reg;
1290         u32 temp;
1291
1292         dev_priv = dev->dev_private;
1293         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1294
1295         if (dev_priv->mchbar_need_disable) {
1296                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1297                         temp = pci_read_config(dev_priv->bridge_dev,
1298                             DEVEN_REG, 4);
1299                         temp &= ~DEVEN_MCHBAR_EN;
1300                         pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1301                             temp, 4);
1302                 } else {
1303                         temp = pci_read_config(dev_priv->bridge_dev,
1304                             mchbar_reg, 4);
1305                         temp &= ~1;
1306                         pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1307                             temp, 4);
1308                 }
1309         }
1310
1311         if (dev_priv->mch_res != NULL) {
1312                 vga = device_get_parent(dev->dev);
1313                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1314                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1315                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1316                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1317                 dev_priv->mch_res = NULL;
1318         }
1319 }
1320
1321 /**
1322  * i915_driver_load - setup chip and create an initial config
1323  * @dev: DRM device
1324  * @flags: startup flags
1325  *
1326  * The driver load routine has to do several things:
1327  *   - drive output discovery via intel_modeset_init()
1328  *   - initialize the memory manager
1329  *   - allocate initial config memory
1330  *   - setup the DRM framebuffer with the allocated memory
1331  */
1332 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1333 {
1334         struct drm_i915_private *dev_priv = dev->dev_private;
1335         unsigned long base, size;
1336         int mmio_bar, ret;
1337
1338         ret = 0;
1339
1340         /* i915 has 4 more counters */
1341         dev->counters += 4;
1342         dev->types[6] = _DRM_STAT_IRQ;
1343         dev->types[7] = _DRM_STAT_PRIMARY;
1344         dev->types[8] = _DRM_STAT_SECONDARY;
1345         dev->types[9] = _DRM_STAT_DMA;
1346
1347         dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1348             M_ZERO | M_WAITOK);
1349         if (dev_priv == NULL)
1350                 return -ENOMEM;
1351
1352         dev->dev_private = (void *)dev_priv;
1353         dev_priv->dev = dev;
1354         dev_priv->info = i915_get_device_id(dev->pci_device);
1355
1356         if (i915_get_bridge_dev(dev)) {
1357                 drm_free(dev_priv, DRM_MEM_DRIVER);
1358                 return (-EIO);
1359         }
1360         dev_priv->mm.gtt = intel_gtt_get();
1361
1362         /* Add register map (needed for suspend/resume) */
1363         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1364         base = drm_get_resource_start(dev, mmio_bar);
1365         size = drm_get_resource_len(dev, mmio_bar);
1366
1367         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1368             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1369
1370         /* The i915 workqueue is primarily used for batched retirement of
1371          * requests (and thus managing bo) once the task has been completed
1372          * by the GPU. i915_gem_retire_requests() is called directly when we
1373          * need high-priority retirement, such as waiting for an explicit
1374          * bo.
1375          *
1376          * It is also used for periodic low-priority events, such as
1377          * idle-timers and recording error state.
1378          *
1379          * All tasks on the workqueue are expected to acquire the dev mutex
1380          * so there is no point in running more than one instance of the
1381          * workqueue at any time.  Use an ordered one.
1382          */
1383         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1384         if (dev_priv->wq == NULL) {
1385                 DRM_ERROR("Failed to create our workqueue.\n");
1386                 ret = -ENOMEM;
1387                 goto out_mtrrfree;
1388         }
1389
1390         /* This must be called before any calls to HAS_PCH_* */
1391         intel_detect_pch(dev);
1392
1393         intel_irq_init(dev);
1394         intel_gt_init(dev);
1395
1396         /* Try to make sure MCHBAR is enabled before poking at it */
1397         intel_setup_mchbar(dev);
1398         intel_setup_gmbus(dev);
1399         intel_opregion_setup(dev);
1400
1401         intel_setup_bios(dev);
1402
1403         i915_gem_load(dev);
1404
1405         /* On the 945G/GM, the chipset reports the MSI capability on the
1406          * integrated graphics even though the support isn't actually there
1407          * according to the published specs.  It doesn't appear to function
1408          * correctly in testing on 945G.
1409          * This may be a side effect of MSI having been made available for PEG
1410          * and the registers being closely associated.
1411          *
1412          * According to chipset errata, on the 965GM, MSI interrupts may
1413          * be lost or delayed, but we use them anyways to avoid
1414          * stuck interrupts on some machines.
1415          */
1416
1417         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1418         lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1419         spin_init(&dev_priv->rps.lock);
1420         lockinit(&dev_priv->error_completion_lock, "915cmp", 0, LK_CANRECURSE);
1421
1422         lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1423
1424         /* Init HWS */
1425         if (!I915_NEED_GFX_HWS(dev)) {
1426                 ret = i915_init_phys_hws(dev);
1427                 if (ret != 0) {
1428                         drm_rmmap(dev, dev_priv->mmio_map);
1429                         drm_free(dev_priv, DRM_MEM_DRIVER);
1430                         return ret;
1431                 }
1432         }
1433
1434         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1435                 dev_priv->num_pipe = 3;
1436         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1437                 dev_priv->num_pipe = 2;
1438         else
1439                 dev_priv->num_pipe = 1;
1440
1441         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1442         if (ret)
1443                 goto out_gem_unload;
1444
1445         /* Start out suspended */
1446         dev_priv->mm.suspended = 1;
1447
1448         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1449                 ret = i915_load_modeset_init(dev);
1450                 if (ret < 0) {
1451                         DRM_ERROR("failed to init modeset\n");
1452                         goto out_gem_unload;
1453                 }
1454         }
1455
1456         /* Must be done after probing outputs */
1457         intel_opregion_init(dev);
1458
1459         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1460                     (unsigned long) dev);
1461
1462         if (IS_GEN5(dev)) {
1463                 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1464                 i915_mch_dev = dev_priv;
1465                 dev_priv->mchdev_lock = &mchdev_lock;
1466                 lockmgr(&mchdev_lock, LK_RELEASE);
1467         }
1468
1469         return 0;
1470
1471 out_gem_unload:
1472         /* XXXKIB */
1473         (void) i915_driver_unload_int(dev, true);
1474         return (ret);
1475 out_mtrrfree:
1476         return ret;
1477 }
1478
1479 static int
1480 i915_driver_unload_int(struct drm_device *dev, bool locked)
1481 {
1482         struct drm_i915_private *dev_priv = dev->dev_private;
1483         int ret;
1484
1485         if (!locked)
1486                 DRM_LOCK(dev);
1487         ret = i915_gpu_idle(dev);
1488         if (ret)
1489                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1490         if (!locked)
1491                 DRM_UNLOCK(dev);
1492
1493         i915_free_hws(dev);
1494
1495         intel_teardown_mchbar(dev);
1496
1497         if (locked)
1498                 DRM_UNLOCK(dev);
1499         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1500                 intel_fbdev_fini(dev);
1501                 intel_modeset_cleanup(dev);
1502         }
1503
1504         /* Free error state after interrupts are fully disabled. */
1505         del_timer_sync(&dev_priv->hangcheck_timer);
1506
1507         i915_destroy_error_state(dev);
1508
1509         intel_opregion_fini(dev);
1510
1511         if (locked)
1512                 DRM_LOCK(dev);
1513
1514         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1515                 if (!locked)
1516                         DRM_LOCK(dev);
1517                 i915_gem_free_all_phys_object(dev);
1518                 i915_gem_cleanup_ringbuffer(dev);
1519                 if (!locked)
1520                         DRM_UNLOCK(dev);
1521                 i915_gem_cleanup_aliasing_ppgtt(dev);
1522 #if 1
1523                 KIB_NOTYET();
1524 #else
1525                 if (I915_HAS_FBC(dev) && i915_powersave)
1526                         i915_cleanup_compression(dev);
1527 #endif
1528                 drm_mm_takedown(&dev_priv->mm.stolen);
1529
1530                 intel_cleanup_overlay(dev);
1531
1532                 if (!I915_NEED_GFX_HWS(dev))
1533                         i915_free_hws(dev);
1534         }
1535
1536         i915_gem_unload(dev);
1537
1538         lockuninit(&dev_priv->irq_lock);
1539
1540         if (dev_priv->wq != NULL)
1541                 destroy_workqueue(dev_priv->wq);
1542
1543         bus_generic_detach(dev->dev);
1544         drm_rmmap(dev, dev_priv->mmio_map);
1545         intel_teardown_gmbus(dev);
1546
1547         lockuninit(&dev_priv->error_lock);
1548         lockuninit(&dev_priv->error_completion_lock);
1549         drm_free(dev->dev_private, DRM_MEM_DRIVER);
1550
1551         return (0);
1552 }
1553
1554 int
1555 i915_driver_unload(struct drm_device *dev)
1556 {
1557
1558         return (i915_driver_unload_int(dev, true));
1559 }
1560
1561 int
1562 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1563 {
1564         struct drm_i915_file_private *i915_file_priv;
1565
1566         i915_file_priv = kmalloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1567             M_WAITOK | M_ZERO);
1568
1569         spin_init(&i915_file_priv->mm.lock);
1570         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1571         file_priv->driver_priv = i915_file_priv;
1572
1573         return (0);
1574 }
1575
1576 void
1577 i915_driver_lastclose(struct drm_device * dev)
1578 {
1579         drm_i915_private_t *dev_priv = dev->dev_private;
1580
1581         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1582 #if 1
1583                 KIB_NOTYET();
1584 #else
1585                 drm_fb_helper_restore();
1586                 vga_switcheroo_process_delayed_switch();
1587 #endif
1588                 return;
1589         }
1590         i915_gem_lastclose(dev);
1591         i915_dma_cleanup(dev);
1592 }
1593
1594 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1595 {
1596
1597         i915_gem_release(dev, file_priv);
1598 }
1599
1600 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1601 {
1602         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1603
1604         spin_uninit(&i915_file_priv->mm.lock);
1605         drm_free(i915_file_priv, DRM_MEM_FILES);
1606 }
1607
1608 struct drm_ioctl_desc i915_ioctls[] = {
1609         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1610         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1611         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1612         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1613         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1614         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1615         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1616         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1617         DRM_IOCTL_DEF(DRM_I915_ALLOC, drm_noop, DRM_AUTH),
1618         DRM_IOCTL_DEF(DRM_I915_FREE, drm_noop, DRM_AUTH),
1619         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1620         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1621         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1622         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1623         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1624         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1625         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1626         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1627         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH | DRM_UNLOCKED),
1628         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH | DRM_UNLOCKED),
1629         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1630         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1631         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1632         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1633         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1634         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1635         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1636         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1637         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1638         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1639         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1640         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1641         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1642         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1643         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1644         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1645         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1646         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1647         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1648         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1649         DRM_IOCTL_DEF(DRM_I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1650         DRM_IOCTL_DEF(DRM_I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1651 };
1652
1653 struct drm_driver i915_driver_info = {
1654         .driver_features =   DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1655             DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1656             DRIVER_GEM /*| DRIVER_MODESET*/,
1657
1658         .buf_priv_size  = sizeof(drm_i915_private_t),
1659         .load           = i915_driver_load,
1660         .open           = i915_driver_open,
1661         .unload         = i915_driver_unload,
1662         .preclose       = i915_driver_preclose,
1663         .lastclose      = i915_driver_lastclose,
1664         .postclose      = i915_driver_postclose,
1665         .device_is_agp  = i915_driver_device_is_agp,
1666         .gem_init_object = i915_gem_init_object,
1667         .gem_free_object = i915_gem_free_object,
1668         .gem_pager_ops  = &i915_gem_pager_ops,
1669         .dumb_create    = i915_gem_dumb_create,
1670         .dumb_map_offset = i915_gem_mmap_gtt,
1671         .dumb_destroy   = i915_gem_dumb_destroy,
1672         .sysctl_init    = i915_sysctl_init,
1673         .sysctl_cleanup = i915_sysctl_cleanup,
1674
1675         .ioctls         = i915_ioctls,
1676         .max_ioctl      = DRM_ARRAY_SIZE(i915_ioctls),
1677
1678         .name           = DRIVER_NAME,
1679         .desc           = DRIVER_DESC,
1680         .date           = DRIVER_DATE,
1681         .major          = DRIVER_MAJOR,
1682         .minor          = DRIVER_MINOR,
1683         .patchlevel     = DRIVER_PATCHLEVEL,
1684 };
1685
1686 /**
1687  * Determine if the device really is AGP or not.
1688  *
1689  * All Intel graphics chipsets are treated as AGP, even if they are really
1690  * built-in.
1691  *
1692  * \param dev   The device to be tested.
1693  *
1694  * \returns
1695  * A value of 1 is always retured to indictate every i9x5 is AGP.
1696  */
1697 int i915_driver_device_is_agp(struct drm_device * dev)
1698 {
1699         return 1;
1700 }