sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_dma.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34 #include "intel_ringbuffer.h"
  35 #include <linux/workqueue.h>
  36
  37 extern struct drm_i915_private *i915_mch_dev;
  38
  39 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  40 {
  41         /*
  42          * The dri breadcrumb update races against the drm master disappearing.
  43          * Instead of trying to fix this (this is by far not the only ums issue)
  44          * just don't do the update in kms mode.
  45          */
  46         if (drm_core_check_feature(dev, DRIVER_MODESET))
  47                 return;
  48
  49         /* XXX: don't do it at all actually */
  50         return;
  51 }
  52
  53 static void i915_write_hws_pga(struct drm_device *dev)
  54 {
  55         drm_i915_private_t *dev_priv = dev->dev_private;
  56         u32 addr;
  57
  58         addr = dev_priv->status_page_dmah->busaddr;
  59         if (INTEL_INFO(dev)->gen >= 4)
  60                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  61         I915_WRITE(HWS_PGA, addr);
  62 }
  63
  64 /**
  65  * Sets up the hardware status page for devices that need a physical address
  66  * in the register.
  67  */
  68 static int i915_init_phys_hws(struct drm_device *dev)
  69 {
  70         drm_i915_private_t *dev_priv = dev->dev_private;
  71         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  72
  73         /*
  74          * Program Hardware Status Page
  75          * XXXKIB Keep 4GB limit for allocation for now.  This method
  76          * of allocation is used on <= 965 hardware, that has several
  77          * erratas regarding the use of physical memory > 4 GB.
  78          */
  79         DRM_UNLOCK(dev);
  80         dev_priv->status_page_dmah =
  81                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  82         DRM_LOCK(dev);
  83         if (!dev_priv->status_page_dmah) {
  84                 DRM_ERROR("Can not allocate hardware status page\n");
  85                 return -ENOMEM;
  86         }
  87         ring->status_page.page_addr = dev_priv->hw_status_page =
  88             dev_priv->status_page_dmah->vaddr;
  89         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  90
  91         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  92
  93         i915_write_hws_pga(dev);
  94         DRM_DEBUG("Enabled hardware status page, phys %jx\n",
  95             (uintmax_t)dev_priv->dma_status_page);
  96         return 0;
  97 }
  98
  99 /**
 100  * Frees the hardware status page, whether it's a physical address or a virtual
 101  * address set up by the X Server.
 102  */
 103 static void i915_free_hws(struct drm_device *dev)
 104 {
 105         drm_i915_private_t *dev_priv = dev->dev_private;
 106         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 107
 108         if (dev_priv->status_page_dmah) {
 109                 drm_pci_free(dev, dev_priv->status_page_dmah);
 110                 dev_priv->status_page_dmah = NULL;
 111         }
 112
 113         if (dev_priv->status_gfx_addr) {
 114                 dev_priv->status_gfx_addr = 0;
 115                 ring->status_page.gfx_addr = 0;
 116                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 117         }
 118
 119         /* Need to rewrite hardware status page */
 120         I915_WRITE(HWS_PGA, 0x1ffff000);
 121 }
 122
 123 void i915_kernel_lost_context(struct drm_device * dev)
 124 {
 125         drm_i915_private_t *dev_priv = dev->dev_private;
 126         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 127
 128         /*
 129          * We should never lose context on the ring with modesetting
 130          * as we don't expose it to userspace
 131          */
 132         if (drm_core_check_feature(dev, DRIVER_MODESET))
 133                 return;
 134
 135         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 136         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 137         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 138         if (ring->space < 0)
 139                 ring->space += ring->size;
 140
 141 #if 1
 142         KIB_NOTYET();
 143 #else
 144         if (!dev->primary->master)
 145                 return;
 146 #endif
 147
 148         if (ring->head == ring->tail && dev_priv->sarea_priv)
 149                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 150 }
 151
 152 static int i915_dma_cleanup(struct drm_device * dev)
 153 {
 154         drm_i915_private_t *dev_priv = dev->dev_private;
 155         int i;
 156
 157
 158         /* Make sure interrupts are disabled here because the uninstall ioctl
 159          * may not have been called from userspace and after dev_private
 160          * is freed, it's too late.
 161          */
 162         if (dev->irq_enabled)
 163                 drm_irq_uninstall(dev);
 164
 165         DRM_LOCK(dev);
 166         for (i = 0; i < I915_NUM_RINGS; i++)
 167                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 168         DRM_UNLOCK(dev);
 169
 170         /* Clear the HWS virtual address at teardown */
 171         if (I915_NEED_GFX_HWS(dev))
 172                 i915_free_hws(dev);
 173
 174         return 0;
 175 }
 176
 177 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 178 {
 179         drm_i915_private_t *dev_priv = dev->dev_private;
 180         int ret;
 181
 182         dev_priv->sarea = drm_getsarea(dev);
 183         if (!dev_priv->sarea) {
 184                 DRM_ERROR("can not find sarea!\n");
 185                 i915_dma_cleanup(dev);
 186                 return -EINVAL;
 187         }
 188
 189         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 190             ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
 191
 192         if (init->ring_size != 0) {
 193                 if (LP_RING(dev_priv)->obj != NULL) {
 194                         i915_dma_cleanup(dev);
 195                         DRM_ERROR("Client tried to initialize ringbuffer in "
 196                                   "GEM mode\n");
 197                         return -EINVAL;
 198                 }
 199
 200                 ret = intel_render_ring_init_dri(dev,
 201                                                  init->ring_start,
 202                                                  init->ring_size);
 203                 if (ret) {
 204                         i915_dma_cleanup(dev);
 205                         return ret;
 206                 }
 207         }
 208
 209         dev_priv->cpp = init->cpp;
 210         dev_priv->back_offset = init->back_offset;
 211         dev_priv->front_offset = init->front_offset;
 212         dev_priv->current_page = 0;
 213         dev_priv->sarea_priv->pf_current_page = 0;
 214
 215         /* Allow hardware batchbuffers unless told otherwise.
 216          */
 217         dev_priv->dri1.allow_batchbuffer = 1;
 218
 219         return 0;
 220 }
 221
 222 static int i915_dma_resume(struct drm_device * dev)
 223 {
 224         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 225         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 226
 227         DRM_DEBUG("\n");
 228
 229         if (ring->virtual_start == NULL) {
 230                 DRM_ERROR("can not ioremap virtual address for"
 231                           " ring buffer\n");
 232                 return -ENOMEM;
 233         }
 234
 235         /* Program Hardware Status Page */
 236         if (!ring->status_page.page_addr) {
 237                 DRM_ERROR("Can not find hardware status page\n");
 238                 return -EINVAL;
 239         }
 240         DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
 241         if (ring->status_page.gfx_addr != 0)
 242                 intel_ring_setup_status_page(ring);
 243         else
 244                 i915_write_hws_pga(dev);
 245
 246         DRM_DEBUG("Enabled hardware status page\n");
 247
 248         return 0;
 249 }
 250
 251 static int i915_dma_init(struct drm_device *dev, void *data,
 252                          struct drm_file *file_priv)
 253 {
 254         drm_i915_init_t *init = data;
 255         int retcode = 0;
 256
 257         switch (init->func) {
 258         case I915_INIT_DMA:
 259                 retcode = i915_initialize(dev, init);
 260                 break;
 261         case I915_CLEANUP_DMA:
 262                 retcode = i915_dma_cleanup(dev);
 263                 break;
 264         case I915_RESUME_DMA:
 265                 retcode = i915_dma_resume(dev);
 266                 break;
 267         default:
 268                 retcode = -EINVAL;
 269                 break;
 270         }
 271
 272         return retcode;
 273 }
 274
 275 /* Implement basically the same security restrictions as hardware does
 276  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 277  *
 278  * Most of the calculations below involve calculating the size of a
 279  * particular instruction.  It's important to get the size right as
 280  * that tells us where the next instruction to check is.  Any illegal
 281  * instruction detected will be given a size of zero, which is a
 282  * signal to abort the rest of the buffer.
 283  */
 284 static int do_validate_cmd(int cmd)
 285 {
 286         switch (((cmd >> 29) & 0x7)) {
 287         case 0x0:
 288                 switch ((cmd >> 23) & 0x3f) {
 289                 case 0x0:
 290                         return 1;       /* MI_NOOP */
 291                 case 0x4:
 292                         return 1;       /* MI_FLUSH */
 293                 default:
 294                         return 0;       /* disallow everything else */
 295                 }
 296                 break;
 297         case 0x1:
 298                 return 0;       /* reserved */
 299         case 0x2:
 300                 return (cmd & 0xff) + 2;        /* 2d commands */
 301         case 0x3:
 302                 if (((cmd >> 24) & 0x1f) <= 0x18)
 303                         return 1;
 304
 305                 switch ((cmd >> 24) & 0x1f) {
 306                 case 0x1c:
 307                         return 1;
 308                 case 0x1d:
 309                         switch ((cmd >> 16) & 0xff) {
 310                         case 0x3:
 311                                 return (cmd & 0x1f) + 2;
 312                         case 0x4:
 313                                 return (cmd & 0xf) + 2;
 314                         default:
 315                                 return (cmd & 0xffff) + 2;
 316                         }
 317                 case 0x1e:
 318                         if (cmd & (1 << 23))
 319                                 return (cmd & 0xffff) + 1;
 320                         else
 321                                 return 1;
 322                 case 0x1f:
 323                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 324                                 return (cmd & 0x1ffff) + 2;
 325                         else if (cmd & (1 << 17))       /* indirect random */
 326                                 if ((cmd & 0xffff) == 0)
 327                                         return 0;       /* unknown length, too hard */
 328                                 else
 329                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 330                         else
 331                                 return 2;       /* indirect sequential */
 332                 default:
 333                         return 0;
 334                 }
 335         default:
 336                 return 0;
 337         }
 338
 339         return 0;
 340 }
 341
 342 static int validate_cmd(int cmd)
 343 {
 344         int ret = do_validate_cmd(cmd);
 345
 346 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 347
 348         return ret;
 349 }
 350
 351 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 352                           int dwords)
 353 {
 354         drm_i915_private_t *dev_priv = dev->dev_private;
 355         int i, ret;
 356
 357         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 358                 return -EINVAL;
 359
 360         ret = BEGIN_LP_RING((dwords+1)&~1);
 361         if (ret)
 362                 return ret;
 363
 364         for (i = 0; i < dwords;) {
 365                 int cmd, sz;
 366
 367                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 368                         return -EINVAL;
 369
 370                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 371                         return -EINVAL;
 372
 373                 OUT_RING(cmd);
 374
 375                 while (++i, --sz) {
 376                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 377                                                          sizeof(cmd))) {
 378                                 return -EINVAL;
 379                         }
 380                         OUT_RING(cmd);
 381                 }
 382         }
 383
 384         if (dwords & 1)
 385                 OUT_RING(0);
 386
 387         ADVANCE_LP_RING();
 388
 389         return 0;
 390 }
 391
 392 int i915_emit_box(struct drm_device * dev,
 393                   struct drm_clip_rect *boxes,
 394                   int i, int DR1, int DR4)
 395 {
 396         struct drm_clip_rect box;
 397
 398         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 399                 return -EFAULT;
 400         }
 401
 402         return (i915_emit_box_p(dev, &box, DR1, DR4));
 403 }
 404
 405 int
 406 i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box,
 407     int DR1, int DR4)
 408 {
 409         drm_i915_private_t *dev_priv = dev->dev_private;
 410         int ret;
 411
 412         if (box->y2 <= box->y1 || box->x2 <= box->x1 || box->y2 <= 0 ||
 413             box->x2 <= 0) {
 414                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 415                           box->x1, box->y1, box->x2, box->y2);
 416                 return -EINVAL;
 417         }
 418
 419         if (INTEL_INFO(dev)->gen >= 4) {
 420                 ret = BEGIN_LP_RING(4);
 421                 if (ret != 0)
 422                         return (ret);
 423
 424                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 425                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 426                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 427                 OUT_RING(DR4);
 428         } else {
 429                 ret = BEGIN_LP_RING(6);
 430                 if (ret != 0)
 431                         return (ret);
 432
 433                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 434                 OUT_RING(DR1);
 435                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 436                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 437                 OUT_RING(DR4);
 438                 OUT_RING(0);
 439         }
 440         ADVANCE_LP_RING();
 441
 442         return 0;
 443 }
 444
 445 /* XXX: Emitting the counter should really be moved to part of the IRQ
 446  * emit. For now, do it in both places:
 447  */
 448
 449 static void i915_emit_breadcrumb(struct drm_device *dev)
 450 {
 451         drm_i915_private_t *dev_priv = dev->dev_private;
 452
 453         if (++dev_priv->counter > 0x7FFFFFFFUL)
 454                 dev_priv->counter = 0;
 455         if (dev_priv->sarea_priv)
 456                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 457
 458         if (BEGIN_LP_RING(4) == 0) {
 459                 OUT_RING(MI_STORE_DWORD_INDEX);
 460                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 461                 OUT_RING(dev_priv->counter);
 462                 OUT_RING(0);
 463                 ADVANCE_LP_RING();
 464         }
 465 }
 466
 467 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 468     drm_i915_cmdbuffer_t * cmd, struct drm_clip_rect *cliprects, void *cmdbuf)
 469 {
 470         int nbox = cmd->num_cliprects;
 471         int i = 0, count, ret;
 472
 473         if (cmd->sz & 0x3) {
 474                 DRM_ERROR("alignment\n");
 475                 return -EINVAL;
 476         }
 477
 478         i915_kernel_lost_context(dev);
 479
 480         count = nbox ? nbox : 1;
 481
 482         for (i = 0; i < count; i++) {
 483                 if (i < nbox) {
 484                         ret = i915_emit_box_p(dev, &cmd->cliprects[i],
 485                             cmd->DR1, cmd->DR4);
 486                         if (ret)
 487                                 return ret;
 488                 }
 489
 490                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 491                 if (ret)
 492                         return ret;
 493         }
 494
 495         i915_emit_breadcrumb(dev);
 496         return 0;
 497 }
 498
 499 static int
 500 i915_dispatch_batchbuffer(struct drm_device * dev,
 501     drm_i915_batchbuffer_t * batch, struct drm_clip_rect *cliprects)
 502 {
 503         drm_i915_private_t *dev_priv = dev->dev_private;
 504         int nbox = batch->num_cliprects;
 505         int i, count, ret;
 506
 507         if ((batch->start | batch->used) & 0x7) {
 508                 DRM_ERROR("alignment\n");
 509                 return -EINVAL;
 510         }
 511
 512         i915_kernel_lost_context(dev);
 513
 514         count = nbox ? nbox : 1;
 515
 516         for (i = 0; i < count; i++) {
 517                 if (i < nbox) {
 518                         int ret = i915_emit_box_p(dev, &cliprects[i],
 519                             batch->DR1, batch->DR4);
 520                         if (ret)
 521                                 return ret;
 522                 }
 523
 524                 if (!IS_I830(dev) && !IS_845G(dev)) {
 525                         ret = BEGIN_LP_RING(2);
 526                         if (ret != 0)
 527                                 return (ret);
 528
 529                         if (INTEL_INFO(dev)->gen >= 4) {
 530                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) |
 531                                     MI_BATCH_NON_SECURE_I965);
 532                                 OUT_RING(batch->start);
 533                         } else {
 534                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 535                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 536                         }
 537                 } else {
 538                         ret = BEGIN_LP_RING(4);
 539                         if (ret != 0)
 540                                 return (ret);
 541
 542                         OUT_RING(MI_BATCH_BUFFER);
 543                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 544                         OUT_RING(batch->start + batch->used - 4);
 545                         OUT_RING(0);
 546                 }
 547                 ADVANCE_LP_RING();
 548         }
 549
 550         i915_emit_breadcrumb(dev);
 551
 552         return 0;
 553 }
 554
 555 static int i915_dispatch_flip(struct drm_device * dev)
 556 {
 557         drm_i915_private_t *dev_priv = dev->dev_private;
 558         int ret;
 559
 560         if (!dev_priv->sarea_priv)
 561                 return -EINVAL;
 562
 563         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 564                   __func__,
 565                   dev_priv->current_page,
 566                   dev_priv->sarea_priv->pf_current_page);
 567
 568         i915_kernel_lost_context(dev);
 569
 570         ret = BEGIN_LP_RING(10);
 571         if (ret)
 572                 return ret;
 573         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 574         OUT_RING(0);
 575
 576         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 577         OUT_RING(0);
 578         if (dev_priv->current_page == 0) {
 579                 OUT_RING(dev_priv->back_offset);
 580                 dev_priv->current_page = 1;
 581         } else {
 582                 OUT_RING(dev_priv->front_offset);
 583                 dev_priv->current_page = 0;
 584         }
 585         OUT_RING(0);
 586
 587         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 588         OUT_RING(0);
 589
 590         ADVANCE_LP_RING();
 591
 592         if (++dev_priv->counter > 0x7FFFFFFFUL)
 593                 dev_priv->counter = 0;
 594         if (dev_priv->sarea_priv)
 595                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 596
 597         if (BEGIN_LP_RING(4) == 0) {
 598                 OUT_RING(MI_STORE_DWORD_INDEX);
 599                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 600                 OUT_RING(dev_priv->counter);
 601                 OUT_RING(0);
 602                 ADVANCE_LP_RING();
 603         }
 604
 605         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 606         return 0;
 607 }
 608
 609 static int i915_quiescent(struct drm_device *dev)
 610 {
 611         i915_kernel_lost_context(dev);
 612         return intel_ring_idle(LP_RING(dev->dev_private));
 613 }
 614
 615 static int
 616 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
 617 {
 618         int ret;
 619
 620         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 621
 622         DRM_LOCK(dev);
 623         ret = i915_quiescent(dev);
 624         DRM_UNLOCK(dev);
 625
 626         return (ret);
 627 }
 628
 629 static int i915_batchbuffer(struct drm_device *dev, void *data,
 630                             struct drm_file *file_priv)
 631 {
 632         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 633         drm_i915_sarea_t *sarea_priv;
 634         drm_i915_batchbuffer_t *batch = data;
 635         struct drm_clip_rect *cliprects;
 636         size_t cliplen;
 637         int ret;
 638
 639         if (!dev_priv->dri1.allow_batchbuffer) {
 640                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 641                 return -EINVAL;
 642         }
 643
 644         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 645                   batch->start, batch->used, batch->num_cliprects);
 646
 647         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 648
 649         cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
 650         if (batch->num_cliprects < 0)
 651                 return -EFAULT;
 652         if (batch->num_cliprects != 0) {
 653                 cliprects = kmalloc(batch->num_cliprects *
 654                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 655                     M_WAITOK | M_ZERO);
 656
 657                 ret = -copyin(batch->cliprects, cliprects,
 658                     batch->num_cliprects * sizeof(struct drm_clip_rect));
 659                 if (ret != 0) {
 660                         ret = -EFAULT;
 661                         goto fail_free;
 662                 }
 663         } else
 664                 cliprects = NULL;
 665
 666         DRM_LOCK(dev);
 667         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 668         DRM_UNLOCK(dev);
 669
 670         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 671         if (sarea_priv)
 672                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 673
 674 fail_free:
 675         drm_free(cliprects, DRM_MEM_DMA);
 676         return ret;
 677 }
 678
 679 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 680                           struct drm_file *file_priv)
 681 {
 682         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 683         drm_i915_sarea_t *sarea_priv;
 684         drm_i915_cmdbuffer_t *cmdbuf = data;
 685         struct drm_clip_rect *cliprects = NULL;
 686         void *batch_data;
 687         int ret;
 688
 689         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 690                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 691
 692         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 693
 694         if (cmdbuf->num_cliprects < 0)
 695                 return -EINVAL;
 696
 697         batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
 698
 699         ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
 700         if (ret != 0) {
 701                 ret = -EFAULT;
 702                 goto fail_batch_free;
 703         }
 704
 705         if (cmdbuf->num_cliprects) {
 706                 cliprects = kmalloc(cmdbuf->num_cliprects *
 707                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 708                     M_WAITOK | M_ZERO);
 709                 ret = -copyin(cmdbuf->cliprects, cliprects,
 710                     cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
 711
 712                 if (ret != 0) {
 713                         ret = -EFAULT;
 714                         goto fail_clip_free;
 715                 }
 716         }
 717
 718         DRM_LOCK(dev);
 719         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 720         DRM_UNLOCK(dev);
 721         if (ret) {
 722                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 723                 goto fail_clip_free;
 724         }
 725
 726         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 727         if (sarea_priv)
 728                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 729
 730 fail_clip_free:
 731         drm_free(cliprects, DRM_MEM_DMA);
 732 fail_batch_free:
 733         drm_free(batch_data, DRM_MEM_DMA);
 734         return ret;
 735 }
 736
 737 static int i915_emit_irq(struct drm_device * dev)
 738 {
 739         drm_i915_private_t *dev_priv = dev->dev_private;
 740 #if 0
 741         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 742 #endif
 743
 744         i915_kernel_lost_context(dev);
 745
 746         DRM_DEBUG("i915: emit_irq\n");
 747
 748         dev_priv->counter++;
 749         if (dev_priv->counter > 0x7FFFFFFFUL)
 750                 dev_priv->counter = 1;
 751 #if 0
 752         if (master_priv->sarea_priv)
 753                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 754 #else
 755         if (dev_priv->sarea_priv)
 756                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 757 #endif
 758
 759         if (BEGIN_LP_RING(4) == 0) {
 760                 OUT_RING(MI_STORE_DWORD_INDEX);
 761                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 762                 OUT_RING(dev_priv->counter);
 763                 OUT_RING(MI_USER_INTERRUPT);
 764                 ADVANCE_LP_RING();
 765         }
 766
 767         return dev_priv->counter;
 768 }
 769
 770 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 771 {
 772         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 773 #if 0
 774         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 775 #endif
 776         int ret = 0;
 777         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 778
 779         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 780                   READ_BREADCRUMB(dev_priv));
 781
 782 #if 0
 783         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 784                 if (master_priv->sarea_priv)
 785                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 786                 return 0;
 787         }
 788
 789         if (master_priv->sarea_priv)
 790                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 791 #else
 792         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 793                 if (dev_priv->sarea_priv) {
 794                         dev_priv->sarea_priv->last_dispatch =
 795                                 READ_BREADCRUMB(dev_priv);
 796                 }
 797                 return 0;
 798         }
 799
 800         if (dev_priv->sarea_priv)
 801                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 802 #endif
 803
 804         if (ring->irq_get(ring)) {
 805                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 806                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 807                 ring->irq_put(ring);
 808         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 809                 ret = -EBUSY;
 810
 811         if (ret == -EBUSY) {
 812                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 813                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 814         }
 815
 816         return ret;
 817 }
 818
 819 /* Needs the lock as it touches the ring.
 820  */
 821 int i915_irq_emit(struct drm_device *dev, void *data,
 822                          struct drm_file *file_priv)
 823 {
 824         drm_i915_private_t *dev_priv = dev->dev_private;
 825         drm_i915_irq_emit_t *emit = data;
 826         int result;
 827
 828         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 829                 DRM_ERROR("called with no initialization\n");
 830                 return -EINVAL;
 831         }
 832
 833         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 834
 835         DRM_LOCK(dev);
 836         result = i915_emit_irq(dev);
 837         DRM_UNLOCK(dev);
 838
 839         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 840                 DRM_ERROR("copy_to_user\n");
 841                 return -EFAULT;
 842         }
 843
 844         return 0;
 845 }
 846
 847 /* Doesn't need the hardware lock.
 848  */
 849 int i915_irq_wait(struct drm_device *dev, void *data,
 850                          struct drm_file *file_priv)
 851 {
 852         drm_i915_private_t *dev_priv = dev->dev_private;
 853         drm_i915_irq_wait_t *irqwait = data;
 854
 855         if (!dev_priv) {
 856                 DRM_ERROR("called with no initialization\n");
 857                 return -EINVAL;
 858         }
 859
 860         return i915_wait_irq(dev, irqwait->irq_seq);
 861 }
 862
 863 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 864                          struct drm_file *file_priv)
 865 {
 866         drm_i915_private_t *dev_priv = dev->dev_private;
 867         drm_i915_vblank_pipe_t *pipe = data;
 868
 869         if (drm_core_check_feature(dev, DRIVER_MODESET))
 870                 return -ENODEV;
 871
 872         if (!dev_priv) {
 873                 DRM_ERROR("called with no initialization\n");
 874                 return -EINVAL;
 875         }
 876
 877         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 878
 879         return 0;
 880 }
 881
 882 /**
 883  * Schedule buffer swap at given vertical blank.
 884  */
 885 static int i915_vblank_swap(struct drm_device *dev, void *data,
 886                      struct drm_file *file_priv)
 887 {
 888         /* The delayed swap mechanism was fundamentally racy, and has been
 889          * removed.  The model was that the client requested a delayed flip/swap
 890          * from the kernel, then waited for vblank before continuing to perform
 891          * rendering.  The problem was that the kernel might wake the client
 892          * up before it dispatched the vblank swap (since the lock has to be
 893          * held while touching the ringbuffer), in which case the client would
 894          * clear and start the next frame before the swap occurred, and
 895          * flicker would occur in addition to likely missing the vblank.
 896          *
 897          * In the absence of this ioctl, userland falls back to a correct path
 898          * of waiting for a vblank, then dispatching the swap on its own.
 899          * Context switching to userland and back is plenty fast enough for
 900          * meeting the requirements of vblank swapping.
 901          */
 902         return -EINVAL;
 903 }
 904
 905 static int i915_flip_bufs(struct drm_device *dev, void *data,
 906                           struct drm_file *file_priv)
 907 {
 908         int ret;
 909
 910         DRM_DEBUG("%s\n", __func__);
 911
 912         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 913
 914         DRM_LOCK(dev);
 915         ret = i915_dispatch_flip(dev);
 916         DRM_UNLOCK(dev);
 917
 918         return ret;
 919 }
 920
 921 static int i915_getparam(struct drm_device *dev, void *data,
 922                          struct drm_file *file_priv)
 923 {
 924         drm_i915_private_t *dev_priv = dev->dev_private;
 925         drm_i915_getparam_t *param = data;
 926         int value;
 927
 928         if (!dev_priv) {
 929                 DRM_ERROR("called with no initialization\n");
 930                 return -EINVAL;
 931         }
 932
 933         switch (param->param) {
 934         case I915_PARAM_IRQ_ACTIVE:
 935                 value = dev->irq_enabled ? 1 : 0;
 936                 break;
 937         case I915_PARAM_ALLOW_BATCHBUFFER:
 938                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 939                 break;
 940         case I915_PARAM_LAST_DISPATCH:
 941                 value = READ_BREADCRUMB(dev_priv);
 942                 break;
 943         case I915_PARAM_CHIPSET_ID:
 944                 value = dev->pci_device;
 945                 break;
 946         case I915_PARAM_HAS_GEM:
 947                 value = 1;
 948                 break;
 949         case I915_PARAM_NUM_FENCES_AVAIL:
 950                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 951                 break;
 952         case I915_PARAM_HAS_OVERLAY:
 953                 value = dev_priv->overlay ? 1 : 0;
 954                 break;
 955         case I915_PARAM_HAS_PAGEFLIPPING:
 956                 value = 1;
 957                 break;
 958         case I915_PARAM_HAS_EXECBUF2:
 959                 /* depends on GEM */
 960                 value = 1;
 961                 break;
 962         case I915_PARAM_HAS_BSD:
 963                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 964                 break;
 965         case I915_PARAM_HAS_BLT:
 966                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 967                 break;
 968         case I915_PARAM_HAS_RELAXED_FENCING:
 969                 value = 1;
 970                 break;
 971         case I915_PARAM_HAS_COHERENT_RINGS:
 972                 value = 1;
 973                 break;
 974         case I915_PARAM_HAS_EXEC_CONSTANTS:
 975                 value = INTEL_INFO(dev)->gen >= 4;
 976                 break;
 977         case I915_PARAM_HAS_RELAXED_DELTA:
 978                 value = 1;
 979                 break;
 980         case I915_PARAM_HAS_GEN7_SOL_RESET:
 981                 value = 1;
 982                 break;
 983         case I915_PARAM_HAS_LLC:
 984                 value = HAS_LLC(dev);
 985                 break;
 986         case I915_PARAM_HAS_ALIASING_PPGTT:
 987                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 988                 break;
 989         case I915_PARAM_HAS_PINNED_BATCHES:
 990                 value = 1;
 991                 break;
 992         default:
 993                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 994                                  param->param);
 995                 return -EINVAL;
 996         }
 997
 998         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 999                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1000                 return -EFAULT;
1001         }
1002
1003         return 0;
1004 }
1005
1006 static int i915_setparam(struct drm_device *dev, void *data,
1007                          struct drm_file *file_priv)
1008 {
1009         drm_i915_private_t *dev_priv = dev->dev_private;
1010         drm_i915_setparam_t *param = data;
1011
1012         if (!dev_priv) {
1013                 DRM_ERROR("called with no initialization\n");
1014                 return -EINVAL;
1015         }
1016
1017         switch (param->param) {
1018         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1019                 break;
1020         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1021                 dev_priv->tex_lru_log_granularity = param->value;
1022                 break;
1023         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1024                 dev_priv->dri1.allow_batchbuffer = param->value;
1025                 break;
1026         case I915_SETPARAM_NUM_USED_FENCES:
1027                 if (param->value > dev_priv->num_fence_regs ||
1028                     param->value < 0)
1029                         return -EINVAL;
1030                 /* Userspace can use first N regs */
1031                 dev_priv->fence_reg_start = param->value;
1032                 break;
1033         default:
1034                 DRM_DEBUG("unknown parameter %d\n", param->param);
1035                 return -EINVAL;
1036         }
1037
1038         return 0;
1039 }
1040
1041 static int i915_set_status_page(struct drm_device *dev, void *data,
1042                                 struct drm_file *file_priv)
1043 {
1044         drm_i915_private_t *dev_priv = dev->dev_private;
1045         drm_i915_hws_addr_t *hws = data;
1046         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1047
1048         if (!I915_NEED_GFX_HWS(dev))
1049                 return -EINVAL;
1050
1051         if (!dev_priv) {
1052                 DRM_ERROR("called with no initialization\n");
1053                 return -EINVAL;
1054         }
1055
1056         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1057         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1058                 DRM_ERROR("tried to set status page when mode setting active\n");
1059                 return 0;
1060         }
1061
1062         ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
1063             hws->addr & (0x1ffff<<12);
1064
1065         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1066         dev_priv->hws_map.size = 4*1024;
1067         dev_priv->hws_map.type = 0;
1068         dev_priv->hws_map.flags = 0;
1069         dev_priv->hws_map.mtrr = 0;
1070
1071         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
1072         if (dev_priv->hws_map.virtual == NULL) {
1073                 i915_dma_cleanup(dev);
1074                 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
1075                 DRM_ERROR("can not ioremap virtual address for"
1076                                 " G33 hw status page\n");
1077                 return -ENOMEM;
1078         }
1079         ring->status_page.page_addr = dev_priv->hw_status_page =
1080             dev_priv->hws_map.virtual;
1081
1082         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1083         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
1084         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
1085                         dev_priv->status_gfx_addr);
1086         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1087         return 0;
1088 }
1089
1090 static int i915_load_modeset_init(struct drm_device *dev)
1091 {
1092         struct drm_i915_private *dev_priv = dev->dev_private;
1093         int ret;
1094
1095         ret = intel_parse_bios(dev);
1096         if (ret)
1097                 DRM_INFO("failed to find VBIOS tables\n");
1098
1099 #if 0
1100         /* If we have > 1 VGA cards, then we need to arbitrate access
1101          * to the common VGA resources.
1102          *
1103          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1104          * then we do not take part in VGA arbitration and the
1105          * vga_client_register() fails with -ENODEV.
1106          */
1107         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1108         if (ret && ret != -ENODEV)
1109                 goto out;
1110
1111         intel_register_dsm_handler();
1112
1113         ret = vga_switcheroo_register_client(dev->pdev,
1114                                              i915_switcheroo_set_state,
1115                                              NULL,
1116                                              i915_switcheroo_can_switch);
1117         if (ret)
1118                 goto cleanup_vga_client;
1119
1120         /* Initialise stolen first so that we may reserve preallocated
1121          * objects for the BIOS to KMS transition.
1122          */
1123         ret = i915_gem_init_stolen(dev);
1124         if (ret)
1125                 goto cleanup_vga_switcheroo;
1126 #endif
1127
1128         intel_modeset_init(dev);
1129
1130         ret = i915_gem_init(dev);
1131         if (ret)
1132                 goto cleanup_gem_stolen;
1133
1134         intel_modeset_gem_init(dev);
1135
1136         ret = drm_irq_install(dev);
1137         if (ret)
1138                 goto cleanup_gem;
1139
1140         /* Always safe in the mode setting case. */
1141         /* FIXME: do pre/post-mode set stuff in core KMS code */
1142         dev->vblank_disable_allowed = 1;
1143
1144         ret = intel_fbdev_init(dev);
1145         if (ret)
1146                 goto cleanup_irq;
1147
1148         drm_kms_helper_poll_init(dev);
1149
1150         /* We're off and running w/KMS */
1151         dev_priv->mm.suspended = 0;
1152
1153         return 0;
1154
1155 cleanup_irq:
1156         drm_irq_uninstall(dev);
1157 cleanup_gem:
1158         DRM_LOCK(dev);
1159         i915_gem_cleanup_ringbuffer(dev);
1160         DRM_UNLOCK(dev);
1161         i915_gem_cleanup_aliasing_ppgtt(dev);
1162 cleanup_gem_stolen:
1163 #if 0
1164         i915_gem_cleanup_stolen(dev);
1165 cleanup_vga_switcheroo:
1166         vga_switcheroo_unregister_client(dev->pdev);
1167 cleanup_vga_client:
1168         vga_client_register(dev->pdev, NULL, NULL, NULL);
1169 out:
1170 #endif
1171         return ret;
1172 }
1173
1174 static int
1175 i915_get_bridge_dev(struct drm_device *dev)
1176 {
1177         struct drm_i915_private *dev_priv;
1178
1179         dev_priv = dev->dev_private;
1180
1181         dev_priv->bridge_dev = intel_gtt_get_bridge_device();
1182         if (dev_priv->bridge_dev == NULL) {
1183                 DRM_ERROR("bridge device not found\n");
1184                 return (-1);
1185         }
1186         return (0);
1187 }
1188
1189 #define MCHBAR_I915 0x44
1190 #define MCHBAR_I965 0x48
1191 #define MCHBAR_SIZE (4*4096)
1192
1193 #define DEVEN_REG 0x54
1194 #define   DEVEN_MCHBAR_EN (1 << 28)
1195
1196 /* Allocate space for the MCH regs if needed, return nonzero on error */
1197 static int
1198 intel_alloc_mchbar_resource(struct drm_device *dev)
1199 {
1200         drm_i915_private_t *dev_priv;
1201         device_t vga;
1202         int reg;
1203         u32 temp_lo, temp_hi;
1204         u64 mchbar_addr, temp;
1205
1206         dev_priv = dev->dev_private;
1207         reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1208
1209         if (INTEL_INFO(dev)->gen >= 4)
1210                 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1211         else
1212                 temp_hi = 0;
1213         temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1214         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1215
1216         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1217 #ifdef XXX_CONFIG_PNP
1218         if (mchbar_addr &&
1219             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1220                 return 0;
1221 #endif
1222
1223         /* Get some space for it */
1224         vga = device_get_parent(dev->dev);
1225         dev_priv->mch_res_rid = 0x100;
1226         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1227             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1228             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1229         if (dev_priv->mch_res == NULL) {
1230                 DRM_ERROR("failed mchbar resource alloc\n");
1231                 return (-ENOMEM);
1232         }
1233
1234         if (INTEL_INFO(dev)->gen >= 4) {
1235                 temp = rman_get_start(dev_priv->mch_res);
1236                 temp >>= 32;
1237                 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1238         }
1239         pci_write_config(dev_priv->bridge_dev, reg,
1240             rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1241         return (0);
1242 }
1243
1244 static void
1245 intel_setup_mchbar(struct drm_device *dev)
1246 {
1247         drm_i915_private_t *dev_priv;
1248         int mchbar_reg;
1249         u32 temp;
1250         bool enabled;
1251
1252         dev_priv = dev->dev_private;
1253         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1254
1255         dev_priv->mchbar_need_disable = false;
1256
1257         if (IS_I915G(dev) || IS_I915GM(dev)) {
1258                 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1259                 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1260         } else {
1261                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1262                 enabled = temp & 1;
1263         }
1264
1265         /* If it's already enabled, don't have to do anything */
1266         if (enabled) {
1267                 DRM_DEBUG("mchbar already enabled\n");
1268                 return;
1269         }
1270
1271         if (intel_alloc_mchbar_resource(dev))
1272                 return;
1273
1274         dev_priv->mchbar_need_disable = true;
1275
1276         /* Space is allocated or reserved, so enable it. */
1277         if (IS_I915G(dev) || IS_I915GM(dev)) {
1278                 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1279                     temp | DEVEN_MCHBAR_EN, 4);
1280         } else {
1281                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1282                 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1283         }
1284 }
1285
1286 static void
1287 intel_teardown_mchbar(struct drm_device *dev)
1288 {
1289         drm_i915_private_t *dev_priv;
1290         device_t vga;
1291         int mchbar_reg;
1292         u32 temp;
1293
1294         dev_priv = dev->dev_private;
1295         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1296
1297         if (dev_priv->mchbar_need_disable) {
1298                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1299                         temp = pci_read_config(dev_priv->bridge_dev,
1300                             DEVEN_REG, 4);
1301                         temp &= ~DEVEN_MCHBAR_EN;
1302                         pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1303                             temp, 4);
1304                 } else {
1305                         temp = pci_read_config(dev_priv->bridge_dev,
1306                             mchbar_reg, 4);
1307                         temp &= ~1;
1308                         pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1309                             temp, 4);
1310                 }
1311         }
1312
1313         if (dev_priv->mch_res != NULL) {
1314                 vga = device_get_parent(dev->dev);
1315                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1316                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1317                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1318                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1319                 dev_priv->mch_res = NULL;
1320         }
1321 }
1322
1323 /**
1324  * i915_driver_load - setup chip and create an initial config
1325  * @dev: DRM device
1326  * @flags: startup flags
1327  *
1328  * The driver load routine has to do several things:
1329  *   - drive output discovery via intel_modeset_init()
1330  *   - initialize the memory manager
1331  *   - allocate initial config memory
1332  *   - setup the DRM framebuffer with the allocated memory
1333  */
1334 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1335 {
1336         struct drm_i915_private *dev_priv = dev->dev_private;
1337         unsigned long base, size;
1338         int mmio_bar, ret;
1339
1340         ret = 0;
1341
1342         /* i915 has 4 more counters */
1343         dev->counters += 4;
1344         dev->types[6] = _DRM_STAT_IRQ;
1345         dev->types[7] = _DRM_STAT_PRIMARY;
1346         dev->types[8] = _DRM_STAT_SECONDARY;
1347         dev->types[9] = _DRM_STAT_DMA;
1348
1349         dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1350             M_ZERO | M_WAITOK);
1351         if (dev_priv == NULL)
1352                 return -ENOMEM;
1353
1354         dev->dev_private = (void *)dev_priv;
1355         dev_priv->dev = dev;
1356         dev_priv->info = i915_get_device_id(dev->pci_device);
1357
1358         if (i915_get_bridge_dev(dev)) {
1359                 drm_free(dev_priv, DRM_MEM_DRIVER);
1360                 return (-EIO);
1361         }
1362         dev_priv->mm.gtt = intel_gtt_get();
1363
1364         /* Add register map (needed for suspend/resume) */
1365         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1366         base = drm_get_resource_start(dev, mmio_bar);
1367         size = drm_get_resource_len(dev, mmio_bar);
1368
1369         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1370             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1371
1372         /* The i915 workqueue is primarily used for batched retirement of
1373          * requests (and thus managing bo) once the task has been completed
1374          * by the GPU. i915_gem_retire_requests() is called directly when we
1375          * need high-priority retirement, such as waiting for an explicit
1376          * bo.
1377          *
1378          * It is also used for periodic low-priority events, such as
1379          * idle-timers and recording error state.
1380          *
1381          * All tasks on the workqueue are expected to acquire the dev mutex
1382          * so there is no point in running more than one instance of the
1383          * workqueue at any time.  Use an ordered one.
1384          */
1385         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1386         if (dev_priv->wq == NULL) {
1387                 DRM_ERROR("Failed to create our workqueue.\n");
1388                 ret = -ENOMEM;
1389                 goto out_mtrrfree;
1390         }
1391
1392         /* This must be called before any calls to HAS_PCH_* */
1393         intel_detect_pch(dev);
1394
1395         intel_irq_init(dev);
1396         intel_gt_init(dev);
1397
1398         /* Try to make sure MCHBAR is enabled before poking at it */
1399         intel_setup_mchbar(dev);
1400         intel_setup_gmbus(dev);
1401         intel_opregion_setup(dev);
1402
1403         intel_setup_bios(dev);
1404
1405         i915_gem_load(dev);
1406
1407         /* On the 945G/GM, the chipset reports the MSI capability on the
1408          * integrated graphics even though the support isn't actually there
1409          * according to the published specs.  It doesn't appear to function
1410          * correctly in testing on 945G.
1411          * This may be a side effect of MSI having been made available for PEG
1412          * and the registers being closely associated.
1413          *
1414          * According to chipset errata, on the 965GM, MSI interrupts may
1415          * be lost or delayed, but we use them anyways to avoid
1416          * stuck interrupts on some machines.
1417          */
1418
1419         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1420         lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1421         spin_init(&dev_priv->rps.lock);
1422
1423         lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1424
1425         /* Init HWS */
1426         if (!I915_NEED_GFX_HWS(dev)) {
1427                 ret = i915_init_phys_hws(dev);
1428                 if (ret != 0) {
1429                         drm_rmmap(dev, dev_priv->mmio_map);
1430                         drm_free(dev_priv, DRM_MEM_DRIVER);
1431                         return ret;
1432                 }
1433         }
1434
1435         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1436                 dev_priv->num_pipe = 3;
1437         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1438                 dev_priv->num_pipe = 2;
1439         else
1440                 dev_priv->num_pipe = 1;
1441
1442         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1443         if (ret)
1444                 goto out_gem_unload;
1445
1446         /* Start out suspended */
1447         dev_priv->mm.suspended = 1;
1448
1449         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1450                 ret = i915_load_modeset_init(dev);
1451                 if (ret < 0) {
1452                         DRM_ERROR("failed to init modeset\n");
1453                         goto out_gem_unload;
1454                 }
1455         }
1456
1457         /* Must be done after probing outputs */
1458         intel_opregion_init(dev);
1459
1460         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1461                     (unsigned long) dev);
1462
1463         if (IS_GEN5(dev)) {
1464                 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1465                 i915_mch_dev = dev_priv;
1466                 dev_priv->mchdev_lock = &mchdev_lock;
1467                 lockmgr(&mchdev_lock, LK_RELEASE);
1468         }
1469
1470         return 0;
1471
1472 out_gem_unload:
1473         intel_teardown_gmbus(dev);
1474         intel_teardown_mchbar(dev);
1475         destroy_workqueue(dev_priv->wq);
1476 out_mtrrfree:
1477         return ret;
1478 }
1479
1480 int i915_driver_unload(struct drm_device *dev)
1481 {
1482         struct drm_i915_private *dev_priv = dev->dev_private;
1483         int ret;
1484
1485         intel_gpu_ips_teardown();
1486
1487         DRM_LOCK(dev);
1488         ret = i915_gpu_idle(dev);
1489         if (ret)
1490                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1491         i915_gem_retire_requests(dev);
1492         DRM_UNLOCK(dev);
1493
1494         /* Cancel the retire work handler, which should be idle now. */
1495         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1496
1497         i915_free_hws(dev);
1498
1499         intel_teardown_mchbar(dev);
1500
1501         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1502                 intel_fbdev_fini(dev);
1503                 intel_modeset_cleanup(dev);
1504         }
1505
1506         /* Free error state after interrupts are fully disabled. */
1507         del_timer_sync(&dev_priv->hangcheck_timer);
1508         cancel_work_sync(&dev_priv->error_work);
1509         i915_destroy_error_state(dev);
1510
1511         intel_opregion_fini(dev);
1512
1513         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1514                 /* Flush any outstanding unpin_work. */
1515                 flush_workqueue(dev_priv->wq);
1516
1517                 DRM_LOCK(dev);
1518                 i915_gem_free_all_phys_object(dev);
1519                 i915_gem_cleanup_ringbuffer(dev);
1520                 DRM_UNLOCK(dev);
1521                 i915_gem_cleanup_aliasing_ppgtt(dev);
1522                 drm_mm_takedown(&dev_priv->mm.stolen);
1523
1524                 intel_cleanup_overlay(dev);
1525
1526                 if (!I915_NEED_GFX_HWS(dev))
1527                         i915_free_hws(dev);
1528         }
1529
1530         i915_gem_unload(dev);
1531
1532         bus_generic_detach(dev->dev);
1533         drm_rmmap(dev, dev_priv->mmio_map);
1534         intel_teardown_gmbus(dev);
1535
1536         destroy_workqueue(dev_priv->wq);
1537
1538         drm_free(dev->dev_private, DRM_MEM_DRIVER);
1539
1540         return 0;
1541 }
1542
1543 int
1544 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1545 {
1546         struct drm_i915_file_private *i915_file_priv;
1547
1548         i915_file_priv = kmalloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1549             M_WAITOK | M_ZERO);
1550
1551         spin_init(&i915_file_priv->mm.lock);
1552         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1553         file_priv->driver_priv = i915_file_priv;
1554
1555         return (0);
1556 }
1557
1558 void
1559 i915_driver_lastclose(struct drm_device * dev)
1560 {
1561         drm_i915_private_t *dev_priv = dev->dev_private;
1562
1563         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1564 #if 1
1565                 KIB_NOTYET();
1566 #else
1567                 drm_fb_helper_restore();
1568                 vga_switcheroo_process_delayed_switch();
1569 #endif
1570                 return;
1571         }
1572         i915_gem_lastclose(dev);
1573         i915_dma_cleanup(dev);
1574 }
1575
1576 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1577 {
1578
1579         i915_gem_release(dev, file_priv);
1580 }
1581
1582 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1583 {
1584         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1585
1586         spin_uninit(&i915_file_priv->mm.lock);
1587         drm_free(i915_file_priv, DRM_MEM_FILES);
1588 }
1589
1590 struct drm_ioctl_desc i915_ioctls[] = {
1591         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1592         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1593         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1594         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1595         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1596         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1597         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1598         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1599         DRM_IOCTL_DEF(DRM_I915_ALLOC, drm_noop, DRM_AUTH),
1600         DRM_IOCTL_DEF(DRM_I915_FREE, drm_noop, DRM_AUTH),
1601         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1602         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1603         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1604         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1605         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1606         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1607         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1608         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1609         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH | DRM_UNLOCKED),
1610         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH | DRM_UNLOCKED),
1611         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1612         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1613         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1614         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1615         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1616         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1617         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1618         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1619         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1620         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1621         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1622         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1623         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1624         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1625         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1626         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1627         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1628         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1629         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1630         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1631         DRM_IOCTL_DEF(DRM_I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1632         DRM_IOCTL_DEF(DRM_I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1633 };
1634
1635 struct drm_driver i915_driver_info = {
1636         .driver_features =   DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1637             DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1638             DRIVER_GEM /*| DRIVER_MODESET*/,
1639
1640         .buf_priv_size  = sizeof(drm_i915_private_t),
1641         .load           = i915_driver_load,
1642         .open           = i915_driver_open,
1643         .unload         = i915_driver_unload,
1644         .preclose       = i915_driver_preclose,
1645         .lastclose      = i915_driver_lastclose,
1646         .postclose      = i915_driver_postclose,
1647         .device_is_agp  = i915_driver_device_is_agp,
1648         .gem_init_object = i915_gem_init_object,
1649         .gem_free_object = i915_gem_free_object,
1650         .gem_pager_ops  = &i915_gem_pager_ops,
1651         .dumb_create    = i915_gem_dumb_create,
1652         .dumb_map_offset = i915_gem_mmap_gtt,
1653         .dumb_destroy   = i915_gem_dumb_destroy,
1654         .sysctl_init    = i915_sysctl_init,
1655         .sysctl_cleanup = i915_sysctl_cleanup,
1656
1657         .ioctls         = i915_ioctls,
1658         .max_ioctl      = DRM_ARRAY_SIZE(i915_ioctls),
1659
1660         .name           = DRIVER_NAME,
1661         .desc           = DRIVER_DESC,
1662         .date           = DRIVER_DATE,
1663         .major          = DRIVER_MAJOR,
1664         .minor          = DRIVER_MINOR,
1665         .patchlevel     = DRIVER_PATCHLEVEL,
1666 };
1667
1668 /**
1669  * Determine if the device really is AGP or not.
1670  *
1671  * All Intel graphics chipsets are treated as AGP, even if they are really
1672  * built-in.
1673  *
1674  * \param dev   The device to be tested.
1675  *
1676  * \returns
1677  * A value of 1 is always retured to indictate every i9x5 is AGP.
1678  */
1679 int i915_driver_device_is_agp(struct drm_device * dev)
1680 {
1681         return 1;
1682 }