sys/dev/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *
  26  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_display.c 254885 2013-08-25 19:37:15Z dumbbell $
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <uapi_drm/radeon_drm.h>
  31 #include "radeon.h"
  32
  33 #include "atom.h"
  34
  35 #ifdef PM_TODO
  36 #include <linux/pm_runtime.h>
  37 #endif
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <linux/err.h>
  41
  42 #include <linux/gcd.h>
  43
  44 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  45 {
  46         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  47         struct drm_device *dev = crtc->dev;
  48         struct radeon_device *rdev = dev->dev_private;
  49         int i;
  50
  51         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  52         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  53
  54         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  55         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  56         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  57
  58         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  59         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  60         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  61
  62         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  63         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  64         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  65
  66         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  67         for (i = 0; i < 256; i++) {
  68                 WREG32(AVIVO_DC_LUT_30_COLOR,
  69                              (radeon_crtc->lut_r[i] << 20) |
  70                              (radeon_crtc->lut_g[i] << 10) |
  71                              (radeon_crtc->lut_b[i] << 0));
  72         }
  73
  74         /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
  75         WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
  76 }
  77
  78 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  79 {
  80         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  81         struct drm_device *dev = crtc->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83         int i;
  84
  85         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  86         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  87
  88         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  89         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  90         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  91
  92         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  93         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  94         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  95
  96         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  97         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  98
  99         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 100         for (i = 0; i < 256; i++) {
 101                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 102                        (radeon_crtc->lut_r[i] << 20) |
 103                        (radeon_crtc->lut_g[i] << 10) |
 104                        (radeon_crtc->lut_b[i] << 0));
 105         }
 106 }
 107
 108 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 109 {
 110         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 111         struct drm_device *dev = crtc->dev;
 112         struct radeon_device *rdev = dev->dev_private;
 113         int i;
 114
 115         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 116
 117         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 118                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 119                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 120         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 121                NI_GRPH_PRESCALE_BYPASS);
 122         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 123                NI_OVL_PRESCALE_BYPASS);
 124         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 125                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 126                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 127
 128         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 129
 130         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 131         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 132         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 133
 134         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 135         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 136         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 137
 138         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 139         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 140
 141         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 142         for (i = 0; i < 256; i++) {
 143                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 144                        (radeon_crtc->lut_r[i] << 20) |
 145                        (radeon_crtc->lut_g[i] << 10) |
 146                        (radeon_crtc->lut_b[i] << 0));
 147         }
 148
 149         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 150                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 151                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 152                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 153                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 154         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 155                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 156                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 157         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 158                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 159                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 160         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 161                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 162                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 163         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 164         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 165         if (ASIC_IS_DCE8(rdev)) {
 166                 /* XXX this only needs to be programmed once per crtc at startup,
 167                  * not sure where the best place for it is
 168                  */
 169                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 170                        CIK_CURSOR_ALPHA_BLND_ENA);
 171         }
 172 }
 173
 174 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 175 {
 176         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 177         struct drm_device *dev = crtc->dev;
 178         struct radeon_device *rdev = dev->dev_private;
 179         int i;
 180         uint32_t dac2_cntl;
 181
 182         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 183         if (radeon_crtc->crtc_id == 0)
 184                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 185         else
 186                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 187         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 188
 189         WREG8(RADEON_PALETTE_INDEX, 0);
 190         for (i = 0; i < 256; i++) {
 191                 WREG32(RADEON_PALETTE_30_DATA,
 192                              (radeon_crtc->lut_r[i] << 20) |
 193                              (radeon_crtc->lut_g[i] << 10) |
 194                              (radeon_crtc->lut_b[i] << 0));
 195         }
 196 }
 197
 198 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 199 {
 200         struct drm_device *dev = crtc->dev;
 201         struct radeon_device *rdev = dev->dev_private;
 202
 203         if (!crtc->enabled)
 204                 return;
 205
 206         if (ASIC_IS_DCE5(rdev))
 207                 dce5_crtc_load_lut(crtc);
 208         else if (ASIC_IS_DCE4(rdev))
 209                 dce4_crtc_load_lut(crtc);
 210         else if (ASIC_IS_AVIVO(rdev))
 211                 avivo_crtc_load_lut(crtc);
 212         else
 213                 legacy_crtc_load_lut(crtc);
 214 }
 215
 216 /** Sets the color ramps on behalf of fbcon */
 217 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 218                               u16 blue, int regno)
 219 {
 220         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 221
 222         radeon_crtc->lut_r[regno] = red >> 6;
 223         radeon_crtc->lut_g[regno] = green >> 6;
 224         radeon_crtc->lut_b[regno] = blue >> 6;
 225 }
 226
 227 /** Gets the color ramps on behalf of fbcon */
 228 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 229                               u16 *blue, int regno)
 230 {
 231         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 232
 233         *red = radeon_crtc->lut_r[regno] << 6;
 234         *green = radeon_crtc->lut_g[regno] << 6;
 235         *blue = radeon_crtc->lut_b[regno] << 6;
 236 }
 237
 238 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 239                                   u16 *blue, uint32_t start, uint32_t size)
 240 {
 241         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 242         int end = (start + size > 256) ? 256 : start + size, i;
 243
 244         /* userspace palettes are always correct as is */
 245         for (i = start; i < end; i++) {
 246                 radeon_crtc->lut_r[i] = red[i] >> 6;
 247                 radeon_crtc->lut_g[i] = green[i] >> 6;
 248                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 249         }
 250         radeon_crtc_load_lut(crtc);
 251 }
 252
 253 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 254 {
 255         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 256
 257         drm_crtc_cleanup(crtc);
 258         destroy_workqueue(radeon_crtc->flip_queue);
 259         kfree(radeon_crtc);
 260 }
 261
 262 /**
 263  * radeon_unpin_work_func - unpin old buffer object
 264  *
 265  * @__work - kernel work item
 266  *
 267  * Unpin the old frame buffer object outside of the interrupt handler
 268  */
 269 static void radeon_unpin_work_func(struct work_struct *__work)
 270 {
 271         struct radeon_flip_work *work =
 272                 container_of(__work, struct radeon_flip_work, unpin_work);
 273         int r;
 274
 275         /* unpin of the old buffer */
 276         r = radeon_bo_reserve(work->old_rbo, false);
 277         if (likely(r == 0)) {
 278                 r = radeon_bo_unpin(work->old_rbo);
 279                 if (unlikely(r != 0)) {
 280                         DRM_ERROR("failed to unpin buffer after flip\n");
 281                 }
 282                 radeon_bo_unreserve(work->old_rbo);
 283         } else
 284                 DRM_ERROR("failed to reserve buffer after flip\n");
 285
 286         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 287         kfree(work);
 288 }
 289
 290 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
 291 {
 292         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 293         u32 update_pending;
 294         int vpos, hpos;
 295
 296         /* can happen during initialization */
 297         if (radeon_crtc == NULL)
 298                 return;
 299
 300         /* Skip the pageflip completion check below (based on polling) on
 301          * asics which reliably support hw pageflip completion irqs. pflip
 302          * irqs are a reliable and race-free method of handling pageflip
 303          * completion detection. A use_pflipirq module parameter < 2 allows
 304          * to override this in case of asics with faulty pflip irqs.
 305          * A module parameter of 0 would only use this polling based path,
 306          * a parameter of 1 would use pflip irq only as a backup to this
 307          * path, as in Linux 3.16.
 308          */
 309         if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
 310                 return;
 311
 312         lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE);
 313         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 314                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 315                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 316                                  radeon_crtc->flip_status,
 317                                  RADEON_FLIP_SUBMITTED);
 318                 lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
 319                 return;
 320         }
 321
 322         update_pending = radeon_page_flip_pending(rdev, crtc_id);
 323
 324         /* Has the pageflip already completed in crtc, or is it certain
 325          * to complete in this vblank?
 326          */
 327         if (update_pending &&
 328             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
 329                                                                &vpos, &hpos, NULL, NULL)) &&
 330             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 331              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 332                 /* crtc didn't flip in this target vblank interval,
 333                  * but flip is pending in crtc. Based on the current
 334                  * scanout position we know that the current frame is
 335                  * (nearly) complete and the flip will (likely)
 336                  * complete before the start of the next frame.
 337                  */
 338                 update_pending = 0;
 339         }
 340         lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
 341         if (!update_pending)
 342                 radeon_crtc_handle_flip(rdev, crtc_id);
 343 }
 344
 345 /**
 346  * radeon_crtc_handle_flip - page flip completed
 347  *
 348  * @rdev: radeon device pointer
 349  * @crtc_id: crtc number this event is for
 350  *
 351  * Called when we are sure that a page flip for this crtc is completed.
 352  */
 353 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 354 {
 355         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 356         struct radeon_flip_work *work;
 357
 358         /* this can happen at init */
 359         if (radeon_crtc == NULL)
 360                 return;
 361
 362         lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE);
 363         work = radeon_crtc->flip_work;
 364         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 365                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 366                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 367                                  radeon_crtc->flip_status,
 368                                  RADEON_FLIP_SUBMITTED);
 369                 lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
 370                 return;
 371         }
 372
 373         /* Pageflip completed. Clean up. */
 374         radeon_crtc->flip_status = RADEON_FLIP_NONE;
 375         radeon_crtc->flip_work = NULL;
 376
 377         /* wakeup userspace */
 378         if (work->event)
 379                 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
 380
 381         lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
 382
 383         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 384         radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
 385         queue_work(radeon_crtc->flip_queue, &work->unpin_work);
 386 }
 387
 388 /**
 389  * radeon_flip_work_func - page flip framebuffer
 390  *
 391  * @work - kernel work item
 392  *
 393  * Wait for the buffer object to become idle and do the actual page flip
 394  */
 395 static void radeon_flip_work_func(struct work_struct *__work)
 396 {
 397         struct radeon_flip_work *work =
 398                 container_of(__work, struct radeon_flip_work, flip_work);
 399         struct radeon_device *rdev = work->rdev;
 400         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
 401
 402         struct drm_crtc *crtc = &radeon_crtc->base;
 403         int r;
 404
 405         lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE);
 406         if (work->fence) {
 407                 r = radeon_fence_wait(work->fence, false);
 408                 if (r == -EDEADLK) {
 409                         lockmgr(&rdev->exclusive_lock, LK_RELEASE);
 410                         r = radeon_gpu_reset(rdev);
 411                         lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE);
 412                 }
 413                 if (r)
 414                         DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
 415
 416                 /* We continue with the page flip even if we failed to wait on
 417                  * the fence, otherwise the DRM core and userspace will be
 418                  * confused about which BO the CRTC is scanning out
 419                  */
 420
 421                 radeon_fence_unref(&work->fence);
 422         }
 423
 424         /* We borrow the event spin lock for protecting flip_status */
 425         lockmgr(&crtc->dev->event_lock, LK_EXCLUSIVE);
 426
 427         /* set the proper interrupt */
 428         radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
 429
 430         /* do the flip (mmio) */
 431         radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base);
 432
 433         radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
 434         lockmgr(&crtc->dev->event_lock, LK_RELEASE);
 435         lockmgr(&rdev->exclusive_lock, LK_RELEASE);
 436 }
 437
 438 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 439                                  struct drm_framebuffer *fb,
 440                                  struct drm_pending_vblank_event *event,
 441                                  uint32_t page_flip_flags)
 442 {
 443         struct drm_device *dev = crtc->dev;
 444         struct radeon_device *rdev = dev->dev_private;
 445         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 446         struct radeon_framebuffer *old_radeon_fb;
 447         struct radeon_framebuffer *new_radeon_fb;
 448         struct drm_gem_object *obj;
 449         struct radeon_flip_work *work;
 450         struct radeon_bo *new_rbo;
 451         uint32_t tiling_flags, pitch_pixels;
 452         uint64_t base;
 453         int r;
 454
 455         work = kzalloc(sizeof *work, GFP_KERNEL);
 456         if (work == NULL)
 457                 return -ENOMEM;
 458
 459         INIT_WORK(&work->flip_work, radeon_flip_work_func);
 460         INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
 461
 462         work->rdev = rdev;
 463         work->crtc_id = radeon_crtc->crtc_id;
 464         work->event = event;
 465
 466         /* schedule unpin of the old buffer */
 467         old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 468         obj = old_radeon_fb->obj;
 469
 470         /* take a reference to the old object */
 471         drm_gem_object_reference(obj);
 472         work->old_rbo = gem_to_radeon_bo(obj);
 473
 474         new_radeon_fb = to_radeon_framebuffer(fb);
 475         obj = new_radeon_fb->obj;
 476         new_rbo = gem_to_radeon_bo(obj);
 477
 478         lockmgr(&new_rbo->tbo.bdev->fence_lock, LK_EXCLUSIVE);
 479         if (new_rbo->tbo.sync_obj)
 480                 work->fence = radeon_fence_ref(new_rbo->tbo.sync_obj);
 481         lockmgr(&new_rbo->tbo.bdev->fence_lock, LK_RELEASE);
 482
 483         /* pin the new buffer */
 484         DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
 485                          work->old_rbo, new_rbo);
 486
 487         r = radeon_bo_reserve(new_rbo, false);
 488         if (unlikely(r != 0)) {
 489                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 490                 goto cleanup;
 491         }
 492         /* Only 27 bit offset for legacy CRTC */
 493         r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
 494                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 495         if (unlikely(r != 0)) {
 496                 radeon_bo_unreserve(new_rbo);
 497                 r = -EINVAL;
 498                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 499                 goto cleanup;
 500         }
 501         radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
 502         radeon_bo_unreserve(new_rbo);
 503
 504         if (!ASIC_IS_AVIVO(rdev)) {
 505                 /* crtc offset is from display base addr not FB location */
 506                 base -= radeon_crtc->legacy_display_base_addr;
 507                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 508
 509                 if (tiling_flags & RADEON_TILING_MACRO) {
 510                         if (ASIC_IS_R300(rdev)) {
 511                                 base &= ~0x7ff;
 512                         } else {
 513                                 int byteshift = fb->bits_per_pixel >> 4;
 514                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 515                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 516                         }
 517                 } else {
 518                         int offset = crtc->y * pitch_pixels + crtc->x;
 519                         switch (fb->bits_per_pixel) {
 520                         case 8:
 521                         default:
 522                                 offset *= 1;
 523                                 break;
 524                         case 15:
 525                         case 16:
 526                                 offset *= 2;
 527                                 break;
 528                         case 24:
 529                                 offset *= 3;
 530                                 break;
 531                         case 32:
 532                                 offset *= 4;
 533                                 break;
 534                         }
 535                         base += offset;
 536                 }
 537                 base &= ~7;
 538         }
 539         work->base = base;
 540
 541         r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id);
 542         if (r) {
 543                 DRM_ERROR("failed to get vblank before flip\n");
 544                 goto pflip_cleanup;
 545         }
 546
 547         /* We borrow the event spin lock for protecting flip_work */
 548         lockmgr(&crtc->dev->event_lock, LK_EXCLUSIVE);
 549
 550         if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
 551                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 552                 lockmgr(&crtc->dev->event_lock, LK_RELEASE);
 553                 r = -EBUSY;
 554                 goto vblank_cleanup;
 555         }
 556         radeon_crtc->flip_status = RADEON_FLIP_PENDING;
 557         radeon_crtc->flip_work = work;
 558
 559         /* update crtc fb */
 560         crtc->primary->fb = fb;
 561
 562         lockmgr(&crtc->dev->event_lock, LK_RELEASE);
 563
 564         queue_work(radeon_crtc->flip_queue, &work->flip_work);
 565         return 0;
 566
 567 vblank_cleanup:
 568         drm_vblank_put(crtc->dev, radeon_crtc->crtc_id);
 569
 570 pflip_cleanup:
 571         if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
 572                 DRM_ERROR("failed to reserve new rbo in error path\n");
 573                 goto cleanup;
 574         }
 575         if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
 576                 DRM_ERROR("failed to unpin new rbo in error path\n");
 577         }
 578         radeon_bo_unreserve(new_rbo);
 579
 580 cleanup:
 581         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 582         radeon_fence_unref(&work->fence);
 583         kfree(work);
 584
 585         return r;
 586 }
 587
 588 static int
 589 radeon_crtc_set_config(struct drm_mode_set *set)
 590 {
 591         struct drm_device *dev;
 592         struct radeon_device *rdev;
 593         struct drm_crtc *crtc;
 594         bool active = false;
 595         int ret;
 596
 597         if (!set || !set->crtc)
 598                 return -EINVAL;
 599
 600         dev = set->crtc->dev;
 601
 602 #ifdef PM_TODO
 603         ret = pm_runtime_get_sync(dev->dev);
 604         if (ret < 0)
 605                 return ret;
 606 #endif
 607
 608         ret = drm_crtc_helper_set_config(set);
 609
 610         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 611                 if (crtc->enabled)
 612                         active = true;
 613
 614 #ifdef PM_TODO
 615         pm_runtime_mark_last_busy(dev->dev);
 616 #endif
 617
 618         rdev = dev->dev_private;
 619         /* if we have active crtcs and we don't have a power ref,
 620            take the current one */
 621         if (active && !rdev->have_disp_power_ref) {
 622                 rdev->have_disp_power_ref = true;
 623                 return ret;
 624         }
 625         /* if we have no active crtcs, then drop the power ref
 626            we got before */
 627         if (!active && rdev->have_disp_power_ref) {
 628 #ifdef PM_TODO
 629                 pm_runtime_put_autosuspend(dev->dev);
 630 #endif
 631                 rdev->have_disp_power_ref = false;
 632         }
 633
 634         /* drop the power reference we got coming in here */
 635 #ifdef PM_TODO
 636         pm_runtime_put_autosuspend(dev->dev);
 637 #endif
 638         return ret;
 639 }
 640 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 641         .cursor_set = radeon_crtc_cursor_set,
 642         .cursor_move = radeon_crtc_cursor_move,
 643         .gamma_set = radeon_crtc_gamma_set,
 644         .set_config = radeon_crtc_set_config,
 645         .destroy = radeon_crtc_destroy,
 646         .page_flip = radeon_crtc_page_flip,
 647 };
 648
 649 static void radeon_crtc_init(struct drm_device *dev, int index)
 650 {
 651         struct radeon_device *rdev = dev->dev_private;
 652         struct radeon_crtc *radeon_crtc;
 653         int i;
 654
 655         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 656         if (radeon_crtc == NULL)
 657                 return;
 658
 659         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 660
 661         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 662         radeon_crtc->crtc_id = index;
 663         radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc");
 664         rdev->mode_info.crtcs[index] = radeon_crtc;
 665
 666         if (rdev->family >= CHIP_BONAIRE) {
 667                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 668                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 669         } else {
 670                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 671                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 672         }
 673         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 674         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 675
 676 #if 0
 677         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 678         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 679         radeon_crtc->mode_set.num_connectors = 0;
 680 #endif
 681
 682         for (i = 0; i < 256; i++) {
 683                 radeon_crtc->lut_r[i] = i << 2;
 684                 radeon_crtc->lut_g[i] = i << 2;
 685                 radeon_crtc->lut_b[i] = i << 2;
 686         }
 687
 688         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 689                 radeon_atombios_init_crtc(dev, radeon_crtc);
 690         else
 691                 radeon_legacy_init_crtc(dev, radeon_crtc);
 692 }
 693
 694 static const char *encoder_names[38] = {
 695         "NONE",
 696         "INTERNAL_LVDS",
 697         "INTERNAL_TMDS1",
 698         "INTERNAL_TMDS2",
 699         "INTERNAL_DAC1",
 700         "INTERNAL_DAC2",
 701         "INTERNAL_SDVOA",
 702         "INTERNAL_SDVOB",
 703         "SI170B",
 704         "CH7303",
 705         "CH7301",
 706         "INTERNAL_DVO1",
 707         "EXTERNAL_SDVOA",
 708         "EXTERNAL_SDVOB",
 709         "TITFP513",
 710         "INTERNAL_LVTM1",
 711         "VT1623",
 712         "HDMI_SI1930",
 713         "HDMI_INTERNAL",
 714         "INTERNAL_KLDSCP_TMDS1",
 715         "INTERNAL_KLDSCP_DVO1",
 716         "INTERNAL_KLDSCP_DAC1",
 717         "INTERNAL_KLDSCP_DAC2",
 718         "SI178",
 719         "MVPU_FPGA",
 720         "INTERNAL_DDI",
 721         "VT1625",
 722         "HDMI_SI1932",
 723         "DP_AN9801",
 724         "DP_DP501",
 725         "INTERNAL_UNIPHY",
 726         "INTERNAL_KLDSCP_LVTMA",
 727         "INTERNAL_UNIPHY1",
 728         "INTERNAL_UNIPHY2",
 729         "NUTMEG",
 730         "TRAVIS",
 731         "INTERNAL_VCE",
 732         "INTERNAL_UNIPHY3",
 733 };
 734
 735 static const char *hpd_names[6] = {
 736         "HPD1",
 737         "HPD2",
 738         "HPD3",
 739         "HPD4",
 740         "HPD5",
 741         "HPD6",
 742 };
 743
 744 static void radeon_print_display_setup(struct drm_device *dev)
 745 {
 746         struct drm_connector *connector;
 747         struct radeon_connector *radeon_connector;
 748         struct drm_encoder *encoder;
 749         struct radeon_encoder *radeon_encoder;
 750         uint32_t devices;
 751         int i = 0;
 752
 753         DRM_INFO("Radeon Display Connectors\n");
 754         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 755                 radeon_connector = to_radeon_connector(connector);
 756                 DRM_INFO("Connector %d:\n", i);
 757                 DRM_INFO("  %s\n", connector->name);
 758                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 759                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 760                 if (radeon_connector->ddc_bus) {
 761                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 762                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 763                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 764                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 765                                  radeon_connector->ddc_bus->rec.a_data_reg,
 766                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 767                                  radeon_connector->ddc_bus->rec.en_data_reg,
 768                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 769                                  radeon_connector->ddc_bus->rec.y_data_reg);
 770                         if (radeon_connector->router.ddc_valid)
 771                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 772                                          radeon_connector->router.ddc_mux_control_pin,
 773                                          radeon_connector->router.ddc_mux_state);
 774                         if (radeon_connector->router.cd_valid)
 775                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 776                                          radeon_connector->router.cd_mux_control_pin,
 777                                          radeon_connector->router.cd_mux_state);
 778                 } else {
 779                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 780                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 781                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 782                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 783                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 784                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 785                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 786                 }
 787                 DRM_INFO("  Encoders:\n");
 788                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 789                         radeon_encoder = to_radeon_encoder(encoder);
 790                         devices = radeon_encoder->devices & radeon_connector->devices;
 791                         if (devices) {
 792                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 793                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 794                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 795                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 796                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 797                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 798                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 799                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 800                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 801                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 802                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 803                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 804                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 805                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 806                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 807                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 808                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 809                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 810                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 811                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 812                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 813                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 814                         }
 815                 }
 816                 i++;
 817         }
 818 }
 819
 820 static bool radeon_setup_enc_conn(struct drm_device *dev)
 821 {
 822         struct radeon_device *rdev = dev->dev_private;
 823         bool ret = false;
 824
 825         if (rdev->bios) {
 826                 if (rdev->is_atom_bios) {
 827                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 828                         if (ret == false)
 829                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 830                 } else {
 831                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 832                         if (ret == false)
 833                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 834                 }
 835         } else {
 836                 if (!ASIC_IS_AVIVO(rdev))
 837                         ret = radeon_get_legacy_connector_info_from_table(dev);
 838         }
 839         if (ret) {
 840                 radeon_setup_encoder_clones(dev);
 841                 radeon_print_display_setup(dev);
 842         }
 843
 844         return ret;
 845 }
 846
 847 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 848 {
 849         struct drm_device *dev = radeon_connector->base.dev;
 850         struct radeon_device *rdev = dev->dev_private;
 851         int ret = 0;
 852
 853         /* don't leak the edid if we already fetched it in detect() */
 854         if (radeon_connector->edid)
 855                 goto got_edid;
 856
 857         /* on hw with routers, select right port */
 858         if (radeon_connector->router.ddc_valid)
 859                 radeon_router_select_ddc_port(radeon_connector);
 860
 861         if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 862             ENCODER_OBJECT_ID_NONE) {
 863                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 864
 865                 if (dig->dp_i2c_bus)
 866                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 867                                                               dig->dp_i2c_bus->adapter);
 868         } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 869                    (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 870                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 871
 872                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 873                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 874                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 875                                                               dig->dp_i2c_bus->adapter);
 876                 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 877                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 878                                                               radeon_connector->ddc_bus->adapter);
 879         } else {
 880                 if (radeon_connector->ddc_bus && !radeon_connector->edid)
 881                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 882                                                               radeon_connector->ddc_bus->adapter);
 883         }
 884
 885         if (!radeon_connector->edid) {
 886                 if (rdev->is_atom_bios) {
 887                         /* some laptops provide a hardcoded edid in rom for LCDs */
 888                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 889                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 890                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 891                 } else
 892                         /* some servers provide a hardcoded edid in rom for KVMs */
 893                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 894         }
 895         if (radeon_connector->edid) {
 896 got_edid:
 897                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 898                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 899                 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
 900 #if 0
 901                 /* XXX Dragonfly does not support HDMI deep colors safely for now */
 902                 if (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 903                         radeon_connector->base.display_info.bpc = 8;
 904                 }
 905 #endif
 906                 return ret;
 907         }
 908         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 909         return 0;
 910 }
 911
 912 /* avivo */
 913
 914 /**
 915  * avivo_reduce_ratio - fractional number reduction
 916  *
 917  * @nom: nominator
 918  * @den: denominator
 919  * @nom_min: minimum value for nominator
 920  * @den_min: minimum value for denominator
 921  *
 922  * Find the greatest common divisor and apply it on both nominator and
 923  * denominator, but make nominator and denominator are at least as large
 924  * as their minimum values.
 925  */
 926 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 927                                unsigned nom_min, unsigned den_min)
 928 {
 929         unsigned tmp;
 930
 931         /* reduce the numbers to a simpler ratio */
 932         tmp = gcd64(*nom, *den);
 933         *nom /= tmp;
 934         *den /= tmp;
 935
 936         /* make sure nominator is large enough */
 937         if (*nom < nom_min) {
 938                 tmp = DIV_ROUND_UP(nom_min, *nom);
 939                 *nom *= tmp;
 940                 *den *= tmp;
 941         }
 942
 943         /* make sure the denominator is large enough */
 944         if (*den < den_min) {
 945                 tmp = DIV_ROUND_UP(den_min, *den);
 946                 *nom *= tmp;
 947                 *den *= tmp;
 948         }
 949 }
 950
 951 /**
 952  * avivo_get_fb_ref_div - feedback and ref divider calculation
 953  *
 954  * @nom: nominator
 955  * @den: denominator
 956  * @post_div: post divider
 957  * @fb_div_max: feedback divider maximum
 958  * @ref_div_max: reference divider maximum
 959  * @fb_div: resulting feedback divider
 960  * @ref_div: resulting reference divider
 961  *
 962  * Calculate feedback and reference divider for a given post divider. Makes
 963  * sure we stay within the limits.
 964  */
 965 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
 966                                  unsigned fb_div_max, unsigned ref_div_max,
 967                                  unsigned *fb_div, unsigned *ref_div)
 968 {
 969         /* limit reference * post divider to a maximum */
 970         ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
 971
 972         /* get matching reference and feedback divider */
 973         *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
 974         *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
 975
 976         /* limit fb divider to its maximum */
 977         if (*fb_div > fb_div_max) {
 978                 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
 979                 *fb_div = fb_div_max;
 980         }
 981 }
 982
 983 /**
 984  * radeon_compute_pll_avivo - compute PLL paramaters
 985  *
 986  * @pll: information about the PLL
 987  * @dot_clock_p: resulting pixel clock
 988  * fb_div_p: resulting feedback divider
 989  * frac_fb_div_p: fractional part of the feedback divider
 990  * ref_div_p: resulting reference divider
 991  * post_div_p: resulting reference divider
 992  *
 993  * Try to calculate the PLL parameters to generate the given frequency:
 994  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 995  */
 996 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 997                               u32 freq,
 998                               u32 *dot_clock_p,
 999                               u32 *fb_div_p,
1000                               u32 *frac_fb_div_p,
1001                               u32 *ref_div_p,
1002                               u32 *post_div_p)
1003 {
1004         unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
1005                 freq : freq / 10;
1006
1007         unsigned fb_div_min, fb_div_max, fb_div;
1008         unsigned post_div_min, post_div_max, post_div;
1009         unsigned ref_div_min, ref_div_max, ref_div;
1010         unsigned post_div_best, diff_best;
1011         unsigned nom, den;
1012
1013         /* determine allowed feedback divider range */
1014         fb_div_min = pll->min_feedback_div;
1015         fb_div_max = pll->max_feedback_div;
1016
1017         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1018                 fb_div_min *= 10;
1019                 fb_div_max *= 10;
1020         }
1021
1022         /* determine allowed ref divider range */
1023         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1024                 ref_div_min = pll->reference_div;
1025         else
1026                 ref_div_min = pll->min_ref_div;
1027
1028         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
1029             pll->flags & RADEON_PLL_USE_REF_DIV)
1030                 ref_div_max = pll->reference_div;
1031         else
1032                 ref_div_max = pll->max_ref_div;
1033
1034         /* determine allowed post divider range */
1035         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1036                 post_div_min = pll->post_div;
1037                 post_div_max = pll->post_div;
1038         } else {
1039                 unsigned vco_min, vco_max;
1040
1041                 if (pll->flags & RADEON_PLL_IS_LCD) {
1042                         vco_min = pll->lcd_pll_out_min;
1043                         vco_max = pll->lcd_pll_out_max;
1044                 } else {
1045                         vco_min = pll->pll_out_min;
1046                         vco_max = pll->pll_out_max;
1047                 }
1048
1049                 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1050                         vco_min *= 10;
1051                         vco_max *= 10;
1052                 }
1053
1054                 post_div_min = vco_min / target_clock;
1055                 if ((target_clock * post_div_min) < vco_min)
1056                         ++post_div_min;
1057                 if (post_div_min < pll->min_post_div)
1058                         post_div_min = pll->min_post_div;
1059
1060                 post_div_max = vco_max / target_clock;
1061                 if ((target_clock * post_div_max) > vco_max)
1062                         --post_div_max;
1063                 if (post_div_max > pll->max_post_div)
1064                         post_div_max = pll->max_post_div;
1065         }
1066
1067         /* represent the searched ratio as fractional number */
1068         nom = target_clock;
1069         den = pll->reference_freq;
1070
1071         /* reduce the numbers to a simpler ratio */
1072         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1073
1074         /* now search for a post divider */
1075         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1076                 post_div_best = post_div_min;
1077         else
1078                 post_div_best = post_div_max;
1079         diff_best = ~0;
1080
1081         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1082                 unsigned diff;
1083                 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1084                                      ref_div_max, &fb_div, &ref_div);
1085                 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1086                         (ref_div * post_div));
1087
1088                 if (diff < diff_best || (diff == diff_best &&
1089                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1090
1091                         post_div_best = post_div;
1092                         diff_best = diff;
1093                 }
1094         }
1095         post_div = post_div_best;
1096
1097         /* get the feedback and reference divider for the optimal value */
1098         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1099                              &fb_div, &ref_div);
1100
1101         /* reduce the numbers to a simpler ratio once more */
1102         /* this also makes sure that the reference divider is large enough */
1103         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1104
1105         /* avoid high jitter with small fractional dividers */
1106         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1107                 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1108                 if (fb_div < fb_div_min) {
1109                         unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1110                         fb_div *= tmp;
1111                         ref_div *= tmp;
1112                 }
1113         }
1114
1115         /* and finally save the result */
1116         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1117                 *fb_div_p = fb_div / 10;
1118                 *frac_fb_div_p = fb_div % 10;
1119         } else {
1120                 *fb_div_p = fb_div;
1121                 *frac_fb_div_p = 0;
1122         }
1123
1124         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1125                         (pll->reference_freq * *frac_fb_div_p)) /
1126                        (ref_div * post_div * 10);
1127         *ref_div_p = ref_div;
1128         *post_div_p = post_div;
1129
1130         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1131                       freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1132                       ref_div, post_div);
1133 }
1134
1135 /* pre-avivo */
1136 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1137 {
1138         uint64_t mod;
1139
1140         n += d / 2;
1141
1142         mod = do_div(n, d);
1143         return n;
1144 }
1145
1146 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1147                                uint64_t freq,
1148                                uint32_t *dot_clock_p,
1149                                uint32_t *fb_div_p,
1150                                uint32_t *frac_fb_div_p,
1151                                uint32_t *ref_div_p,
1152                                uint32_t *post_div_p)
1153 {
1154         uint32_t min_ref_div = pll->min_ref_div;
1155         uint32_t max_ref_div = pll->max_ref_div;
1156         uint32_t min_post_div = pll->min_post_div;
1157         uint32_t max_post_div = pll->max_post_div;
1158         uint32_t min_fractional_feed_div = 0;
1159         uint32_t max_fractional_feed_div = 0;
1160         uint32_t best_vco = pll->best_vco;
1161         uint32_t best_post_div = 1;
1162         uint32_t best_ref_div = 1;
1163         uint32_t best_feedback_div = 1;
1164         uint32_t best_frac_feedback_div = 0;
1165         uint32_t best_freq = -1;
1166         uint32_t best_error = 0xffffffff;
1167         uint32_t best_vco_diff = 1;
1168         uint32_t post_div;
1169         u32 pll_out_min, pll_out_max;
1170
1171         DRM_DEBUG_KMS("PLL freq %ju %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1172         freq = freq * 1000;
1173
1174         if (pll->flags & RADEON_PLL_IS_LCD) {
1175                 pll_out_min = pll->lcd_pll_out_min;
1176                 pll_out_max = pll->lcd_pll_out_max;
1177         } else {
1178                 pll_out_min = pll->pll_out_min;
1179                 pll_out_max = pll->pll_out_max;
1180         }
1181
1182         if (pll_out_min > 64800)
1183                 pll_out_min = 64800;
1184
1185         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1186                 min_ref_div = max_ref_div = pll->reference_div;
1187         else {
1188                 while (min_ref_div < max_ref_div-1) {
1189                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1190                         uint32_t pll_in = pll->reference_freq / mid;
1191                         if (pll_in < pll->pll_in_min)
1192                                 max_ref_div = mid;
1193                         else if (pll_in > pll->pll_in_max)
1194                                 min_ref_div = mid;
1195                         else
1196                                 break;
1197                 }
1198         }
1199
1200         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1201                 min_post_div = max_post_div = pll->post_div;
1202
1203         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1204                 min_fractional_feed_div = pll->min_frac_feedback_div;
1205                 max_fractional_feed_div = pll->max_frac_feedback_div;
1206         }
1207
1208         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1209                 uint32_t ref_div;
1210
1211                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1212                         continue;
1213
1214                 /* legacy radeons only have a few post_divs */
1215                 if (pll->flags & RADEON_PLL_LEGACY) {
1216                         if ((post_div == 5) ||
1217                             (post_div == 7) ||
1218                             (post_div == 9) ||
1219                             (post_div == 10) ||
1220                             (post_div == 11) ||
1221                             (post_div == 13) ||
1222                             (post_div == 14) ||
1223                             (post_div == 15))
1224                                 continue;
1225                 }
1226
1227                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1228                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1229                         uint32_t pll_in = pll->reference_freq / ref_div;
1230                         uint32_t min_feed_div = pll->min_feedback_div;
1231                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1232
1233                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1234                                 continue;
1235
1236                         while (min_feed_div < max_feed_div) {
1237                                 uint32_t vco;
1238                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1239                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1240                                 uint32_t frac_feedback_div;
1241                                 uint64_t tmp;
1242
1243                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1244
1245                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1246                                 vco = radeon_div(tmp, ref_div);
1247
1248                                 if (vco < pll_out_min) {
1249                                         min_feed_div = feedback_div + 1;
1250                                         continue;
1251                                 } else if (vco > pll_out_max) {
1252                                         max_feed_div = feedback_div;
1253                                         continue;
1254                                 }
1255
1256                                 while (min_frac_feed_div < max_frac_feed_div) {
1257                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1258                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1259                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1260                                         current_freq = radeon_div(tmp, ref_div * post_div);
1261
1262                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1263                                                 if (freq < current_freq)
1264                                                         error = 0xffffffff;
1265                                                 else
1266                                                         error = freq - current_freq;
1267                                         } else
1268                                                 error = abs(current_freq - freq);
1269                                         vco_diff = abs(vco - best_vco);
1270
1271                                         if ((best_vco == 0 && error < best_error) ||
1272                                             (best_vco != 0 &&
1273                                              ((best_error > 100 && error < best_error - 100) ||
1274                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1275                                                 best_post_div = post_div;
1276                                                 best_ref_div = ref_div;
1277                                                 best_feedback_div = feedback_div;
1278                                                 best_frac_feedback_div = frac_feedback_div;
1279                                                 best_freq = current_freq;
1280                                                 best_error = error;
1281                                                 best_vco_diff = vco_diff;
1282                                         } else if (current_freq == freq) {
1283                                                 if (best_freq == -1) {
1284                                                         best_post_div = post_div;
1285                                                         best_ref_div = ref_div;
1286                                                         best_feedback_div = feedback_div;
1287                                                         best_frac_feedback_div = frac_feedback_div;
1288                                                         best_freq = current_freq;
1289                                                         best_error = error;
1290                                                         best_vco_diff = vco_diff;
1291                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1292                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1293                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1294                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1295                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1296                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1297                                                         best_post_div = post_div;
1298                                                         best_ref_div = ref_div;
1299                                                         best_feedback_div = feedback_div;
1300                                                         best_frac_feedback_div = frac_feedback_div;
1301                                                         best_freq = current_freq;
1302                                                         best_error = error;
1303                                                         best_vco_diff = vco_diff;
1304                                                 }
1305                                         }
1306                                         if (current_freq < freq)
1307                                                 min_frac_feed_div = frac_feedback_div + 1;
1308                                         else
1309                                                 max_frac_feed_div = frac_feedback_div;
1310                                 }
1311                                 if (current_freq < freq)
1312                                         min_feed_div = feedback_div + 1;
1313                                 else
1314                                         max_feed_div = feedback_div;
1315                         }
1316                 }
1317         }
1318
1319         *dot_clock_p = best_freq / 10000;
1320         *fb_div_p = best_feedback_div;
1321         *frac_fb_div_p = best_frac_feedback_div;
1322         *ref_div_p = best_ref_div;
1323         *post_div_p = best_post_div;
1324         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1325                       (long long)freq,
1326                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1327                       best_ref_div, best_post_div);
1328
1329 }
1330
1331 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1332 {
1333         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1334
1335         if (radeon_fb->obj) {
1336                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1337         }
1338         drm_framebuffer_cleanup(fb);
1339         kfree(radeon_fb);
1340 }
1341
1342 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1343                                                   struct drm_file *file_priv,
1344                                                   unsigned int *handle)
1345 {
1346         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1347
1348         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1349 }
1350
1351 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1352         .destroy = radeon_user_framebuffer_destroy,
1353         .create_handle = radeon_user_framebuffer_create_handle,
1354 };
1355
1356 int
1357 radeon_framebuffer_init(struct drm_device *dev,
1358                         struct radeon_framebuffer *rfb,
1359                         struct drm_mode_fb_cmd2 *mode_cmd,
1360                         struct drm_gem_object *obj)
1361 {
1362         int ret;
1363         rfb->obj = obj;
1364         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1365         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1366         if (ret) {
1367                 rfb->obj = NULL;
1368                 return ret;
1369         }
1370         return 0;
1371 }
1372
1373 static struct drm_framebuffer *
1374 radeon_user_framebuffer_create(struct drm_device *dev,
1375                                struct drm_file *file_priv,
1376                                struct drm_mode_fb_cmd2 *mode_cmd)
1377 {
1378         struct drm_gem_object *obj;
1379         struct radeon_framebuffer *radeon_fb;
1380         int ret;
1381
1382         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1383         if (obj ==  NULL) {
1384                 dev_err(dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1385                         "can't create framebuffer\n", mode_cmd->handles[0]);
1386                 return ERR_PTR(-ENOENT);
1387         }
1388
1389         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1390         if (radeon_fb == NULL) {
1391                 drm_gem_object_unreference_unlocked(obj);
1392                 return ERR_PTR(-ENOMEM);
1393         }
1394
1395         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1396         if (ret) {
1397                 kfree(radeon_fb);
1398                 drm_gem_object_unreference_unlocked(obj);
1399                 return ERR_PTR(ret);
1400         }
1401
1402         return &radeon_fb->base;
1403 }
1404
1405 static void radeon_output_poll_changed(struct drm_device *dev)
1406 {
1407         struct radeon_device *rdev = dev->dev_private;
1408         radeon_fb_output_poll_changed(rdev);
1409 }
1410
1411 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1412         .fb_create = radeon_user_framebuffer_create,
1413         .output_poll_changed = radeon_output_poll_changed
1414 };
1415
1416 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1417 {       { 0, "driver" },
1418         { 1, "bios" },
1419 };
1420
1421 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1422 {       { TV_STD_NTSC, "ntsc" },
1423         { TV_STD_PAL, "pal" },
1424         { TV_STD_PAL_M, "pal-m" },
1425         { TV_STD_PAL_60, "pal-60" },
1426         { TV_STD_NTSC_J, "ntsc-j" },
1427         { TV_STD_SCART_PAL, "scart-pal" },
1428         { TV_STD_PAL_CN, "pal-cn" },
1429         { TV_STD_SECAM, "secam" },
1430 };
1431
1432 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1433 {       { UNDERSCAN_OFF, "off" },
1434         { UNDERSCAN_ON, "on" },
1435         { UNDERSCAN_AUTO, "auto" },
1436 };
1437
1438 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1439 {       { RADEON_AUDIO_DISABLE, "off" },
1440         { RADEON_AUDIO_ENABLE, "on" },
1441         { RADEON_AUDIO_AUTO, "auto" },
1442 };
1443
1444 /* XXX support different dither options? spatial, temporal, both, etc. */
1445 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1446 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1447         { RADEON_FMT_DITHER_ENABLE, "on" },
1448 };
1449
1450 static int radeon_modeset_create_props(struct radeon_device *rdev)
1451 {
1452         int sz;
1453
1454         if (rdev->is_atom_bios) {
1455                 rdev->mode_info.coherent_mode_property =
1456                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1457                 if (!rdev->mode_info.coherent_mode_property)
1458                         return -ENOMEM;
1459         }
1460
1461         if (!ASIC_IS_AVIVO(rdev)) {
1462                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1463                 rdev->mode_info.tmds_pll_property =
1464                         drm_property_create_enum(rdev->ddev, 0,
1465                                             "tmds_pll",
1466                                             radeon_tmds_pll_enum_list, sz);
1467         }
1468
1469         rdev->mode_info.load_detect_property =
1470                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1471         if (!rdev->mode_info.load_detect_property)
1472                 return -ENOMEM;
1473
1474         drm_mode_create_scaling_mode_property(rdev->ddev);
1475
1476         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1477         rdev->mode_info.tv_std_property =
1478                 drm_property_create_enum(rdev->ddev, 0,
1479                                     "tv standard",
1480                                     radeon_tv_std_enum_list, sz);
1481
1482         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1483         rdev->mode_info.underscan_property =
1484                 drm_property_create_enum(rdev->ddev, 0,
1485                                     "underscan",
1486                                     radeon_underscan_enum_list, sz);
1487
1488         rdev->mode_info.underscan_hborder_property =
1489                 drm_property_create_range(rdev->ddev, 0,
1490                                         "underscan hborder", 0, 128);
1491         if (!rdev->mode_info.underscan_hborder_property)
1492                 return -ENOMEM;
1493
1494         rdev->mode_info.underscan_vborder_property =
1495                 drm_property_create_range(rdev->ddev, 0,
1496                                         "underscan vborder", 0, 128);
1497         if (!rdev->mode_info.underscan_vborder_property)
1498                 return -ENOMEM;
1499
1500         sz = ARRAY_SIZE(radeon_audio_enum_list);
1501         rdev->mode_info.audio_property =
1502                 drm_property_create_enum(rdev->ddev, 0,
1503                                          "audio",
1504                                          radeon_audio_enum_list, sz);
1505
1506         sz = ARRAY_SIZE(radeon_dither_enum_list);
1507         rdev->mode_info.dither_property =
1508                 drm_property_create_enum(rdev->ddev, 0,
1509                                          "dither",
1510                                          radeon_dither_enum_list, sz);
1511
1512         return 0;
1513 }
1514
1515 void radeon_update_display_priority(struct radeon_device *rdev)
1516 {
1517         /* adjustment options for the display watermarks */
1518         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1519                 /* set display priority to high for r3xx, rv515 chips
1520                  * this avoids flickering due to underflow to the
1521                  * display controllers during heavy acceleration.
1522                  * Don't force high on rs4xx igp chips as it seems to
1523                  * affect the sound card.  See kernel bug 15982.
1524                  */
1525                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1526                     !(rdev->flags & RADEON_IS_IGP))
1527                         rdev->disp_priority = 2;
1528                 else
1529                         rdev->disp_priority = 0;
1530         } else
1531                 rdev->disp_priority = radeon_disp_priority;
1532
1533 }
1534
1535 /*
1536  * Allocate hdmi structs and determine register offsets
1537  */
1538 static void radeon_afmt_init(struct radeon_device *rdev)
1539 {
1540         int i;
1541
1542         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1543                 rdev->mode_info.afmt[i] = NULL;
1544
1545         if (ASIC_IS_NODCE(rdev)) {
1546                 /* nothing to do */
1547         } else if (ASIC_IS_DCE4(rdev)) {
1548                 static uint32_t eg_offsets[] = {
1549                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1550                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1551                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1552                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1553                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1554                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1555                         0x13830 - 0x7030,
1556                 };
1557                 int num_afmt;
1558
1559                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1560                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1561                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1562                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1563                 if (ASIC_IS_DCE8(rdev))
1564                         num_afmt = 7;
1565                 else if (ASIC_IS_DCE6(rdev))
1566                         num_afmt = 6;
1567                 else if (ASIC_IS_DCE5(rdev))
1568                         num_afmt = 6;
1569                 else if (ASIC_IS_DCE41(rdev))
1570                         num_afmt = 2;
1571                 else /* DCE4 */
1572                         num_afmt = 6;
1573
1574                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1575                 for (i = 0; i < num_afmt; i++) {
1576                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1577                         if (rdev->mode_info.afmt[i]) {
1578                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1579                                 rdev->mode_info.afmt[i]->id = i;
1580                         }
1581                 }
1582         } else if (ASIC_IS_DCE3(rdev)) {
1583                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1584                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1585                 if (rdev->mode_info.afmt[0]) {
1586                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1587                         rdev->mode_info.afmt[0]->id = 0;
1588                 }
1589                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1590                 if (rdev->mode_info.afmt[1]) {
1591                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1592                         rdev->mode_info.afmt[1]->id = 1;
1593                 }
1594         } else if (ASIC_IS_DCE2(rdev)) {
1595                 /* DCE2 has at least 1 routable audio block */
1596                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1597                 if (rdev->mode_info.afmt[0]) {
1598                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1599                         rdev->mode_info.afmt[0]->id = 0;
1600                 }
1601                 /* r6xx has 2 routable audio blocks */
1602                 if (rdev->family >= CHIP_R600) {
1603                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1604                         if (rdev->mode_info.afmt[1]) {
1605                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1606                                 rdev->mode_info.afmt[1]->id = 1;
1607                         }
1608                 }
1609         }
1610 }
1611
1612 static void radeon_afmt_fini(struct radeon_device *rdev)
1613 {
1614         int i;
1615
1616         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1617                 kfree(rdev->mode_info.afmt[i]);
1618                 rdev->mode_info.afmt[i] = NULL;
1619         }
1620 }
1621
1622 int radeon_modeset_init(struct radeon_device *rdev)
1623 {
1624         int i;
1625         int ret;
1626
1627         drm_mode_config_init(rdev->ddev);
1628         rdev->mode_info.mode_config_initialized = true;
1629
1630         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1631
1632         if (ASIC_IS_DCE5(rdev)) {
1633                 rdev->ddev->mode_config.max_width = 16384;
1634                 rdev->ddev->mode_config.max_height = 16384;
1635         } else if (ASIC_IS_AVIVO(rdev)) {
1636                 rdev->ddev->mode_config.max_width = 8192;
1637                 rdev->ddev->mode_config.max_height = 8192;
1638         } else {
1639                 rdev->ddev->mode_config.max_width = 4096;
1640                 rdev->ddev->mode_config.max_height = 4096;
1641         }
1642
1643         rdev->ddev->mode_config.preferred_depth = 24;
1644         rdev->ddev->mode_config.prefer_shadow = 1;
1645
1646         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1647
1648         ret = radeon_modeset_create_props(rdev);
1649         if (ret) {
1650                 return ret;
1651         }
1652
1653         /* init i2c buses */
1654         radeon_i2c_init(rdev);
1655
1656         /* check combios for a valid hardcoded EDID - Sun servers */
1657         if (!rdev->is_atom_bios) {
1658                 /* check for hardcoded EDID in BIOS */
1659                 radeon_combios_check_hardcoded_edid(rdev);
1660         }
1661
1662         /* allocate crtcs */
1663         for (i = 0; i < rdev->num_crtc; i++) {
1664                 radeon_crtc_init(rdev->ddev, i);
1665         }
1666
1667         /* okay we should have all the bios connectors */
1668         ret = radeon_setup_enc_conn(rdev->ddev);
1669         if (!ret) {
1670                 return ret;
1671         }
1672
1673         /* init dig PHYs, disp eng pll */
1674         if (rdev->is_atom_bios) {
1675                 radeon_atom_encoder_init(rdev);
1676                 radeon_atom_disp_eng_pll_init(rdev);
1677         }
1678
1679         /* initialize hpd */
1680         radeon_hpd_init(rdev);
1681
1682         /* setup afmt */
1683         radeon_afmt_init(rdev);
1684
1685         radeon_fbdev_init(rdev);
1686         drm_kms_helper_poll_init(rdev->ddev);
1687
1688         if (rdev->pm.dpm_enabled) {
1689                 /* do dpm late init */
1690                 ret = radeon_pm_late_init(rdev);
1691                 if (ret) {
1692                         rdev->pm.dpm_enabled = false;
1693                         DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1694                 }
1695                 /* set the dpm state for PX since there won't be
1696                  * a modeset to call this.
1697                  */
1698                 radeon_pm_compute_clocks(rdev);
1699         }
1700
1701         return 0;
1702 }
1703
1704 void radeon_modeset_fini(struct radeon_device *rdev)
1705 {
1706         radeon_fbdev_fini(rdev);
1707         kfree(rdev->mode_info.bios_hardcoded_edid);
1708
1709         if (rdev->mode_info.mode_config_initialized) {
1710                 radeon_afmt_fini(rdev);
1711                 drm_kms_helper_poll_fini(rdev->ddev);
1712                 radeon_hpd_fini(rdev);
1713                 DRM_UNLOCK(rdev->ddev); /* Work around lock recursion. dumbbell@ */
1714                 drm_mode_config_cleanup(rdev->ddev);
1715                 DRM_LOCK(rdev->ddev);
1716                 rdev->mode_info.mode_config_initialized = false;
1717         }
1718         /* free i2c buses */
1719         radeon_i2c_fini(rdev);
1720 }
1721
1722 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1723 {
1724         /* try and guess if this is a tv or a monitor */
1725         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1726             (mode->vdisplay == 576) || /* 576p */
1727             (mode->vdisplay == 720) || /* 720p */
1728             (mode->vdisplay == 1080)) /* 1080p */
1729                 return true;
1730         else
1731                 return false;
1732 }
1733
1734 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1735                                 const struct drm_display_mode *mode,
1736                                 struct drm_display_mode *adjusted_mode)
1737 {
1738         struct drm_device *dev = crtc->dev;
1739         struct radeon_device *rdev = dev->dev_private;
1740         struct drm_encoder *encoder;
1741         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1742         struct radeon_encoder *radeon_encoder;
1743         struct drm_connector *connector;
1744         struct radeon_connector *radeon_connector;
1745         bool first = true;
1746         u32 src_v = 1, dst_v = 1;
1747         u32 src_h = 1, dst_h = 1;
1748
1749         radeon_crtc->h_border = 0;
1750         radeon_crtc->v_border = 0;
1751
1752         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1753                 if (encoder->crtc != crtc)
1754                         continue;
1755                 radeon_encoder = to_radeon_encoder(encoder);
1756                 connector = radeon_get_connector_for_encoder(encoder);
1757                 radeon_connector = to_radeon_connector(connector);
1758
1759                 if (first) {
1760                         /* set scaling */
1761                         if (radeon_encoder->rmx_type == RMX_OFF)
1762                                 radeon_crtc->rmx_type = RMX_OFF;
1763                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1764                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1765                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1766                         else
1767                                 radeon_crtc->rmx_type = RMX_OFF;
1768                         /* copy native mode */
1769                         memcpy(&radeon_crtc->native_mode,
1770                                &radeon_encoder->native_mode,
1771                                 sizeof(struct drm_display_mode));
1772                         src_v = crtc->mode.vdisplay;
1773                         dst_v = radeon_crtc->native_mode.vdisplay;
1774                         src_h = crtc->mode.hdisplay;
1775                         dst_h = radeon_crtc->native_mode.hdisplay;
1776
1777                         /* fix up for overscan on hdmi */
1778                         if (ASIC_IS_AVIVO(rdev) &&
1779                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1780                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1781                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1782                               drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1783                               is_hdtv_mode(mode)))) {
1784                                 if (radeon_encoder->underscan_hborder != 0)
1785                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1786                                 else
1787                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1788                                 if (radeon_encoder->underscan_vborder != 0)
1789                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1790                                 else
1791                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1792                                 radeon_crtc->rmx_type = RMX_FULL;
1793                                 src_v = crtc->mode.vdisplay;
1794                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1795                                 src_h = crtc->mode.hdisplay;
1796                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1797                         }
1798                         first = false;
1799                 } else {
1800                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1801                                 /* WARNING: Right now this can't happen but
1802                                  * in the future we need to check that scaling
1803                                  * are consistent across different encoder
1804                                  * (ie all encoder can work with the same
1805                                  *  scaling).
1806                                  */
1807                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1808                                 return false;
1809                         }
1810                 }
1811         }
1812         if (radeon_crtc->rmx_type != RMX_OFF) {
1813                 fixed20_12 a, b;
1814                 a.full = dfixed_const(src_v);
1815                 b.full = dfixed_const(dst_v);
1816                 radeon_crtc->vsc.full = dfixed_div(a, b);
1817                 a.full = dfixed_const(src_h);
1818                 b.full = dfixed_const(dst_h);
1819                 radeon_crtc->hsc.full = dfixed_div(a, b);
1820         } else {
1821                 radeon_crtc->vsc.full = dfixed_const(1);
1822                 radeon_crtc->hsc.full = dfixed_const(1);
1823         }
1824         return true;
1825 }
1826
1827 /*
1828  * Retrieve current video scanout position of crtc on a given gpu, and
1829  * an optional accurate timestamp of when query happened.
1830  *
1831  * \param dev Device to query.
1832  * \param crtc Crtc to query.
1833  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1834  * \param *vpos Location where vertical scanout position should be stored.
1835  * \param *hpos Location where horizontal scanout position should go.
1836  * \param *stime Target location for timestamp taken immediately before
1837  *               scanout position query. Can be NULL to skip timestamp.
1838  * \param *etime Target location for timestamp taken immediately after
1839  *               scanout position query. Can be NULL to skip timestamp.
1840  *
1841  * Returns vpos as a positive number while in active scanout area.
1842  * Returns vpos as a negative number inside vblank, counting the number
1843  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1844  * until start of active scanout / end of vblank."
1845  *
1846  * \return Flags, or'ed together as follows:
1847  *
1848  * DRM_SCANOUTPOS_VALID = Query successful.
1849  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1850  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1851  * this flag means that returned position may be offset by a constant but
1852  * unknown small number of scanlines wrt. real scanout position.
1853  *
1854  */
1855 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1856                                int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1857 {
1858         u32 stat_crtc = 0, vbl = 0, position = 0;
1859         int vbl_start, vbl_end, vtotal, ret = 0;
1860         bool in_vbl = true;
1861
1862         struct radeon_device *rdev = dev->dev_private;
1863
1864         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1865
1866         /* Get optional system timestamp before query. */
1867         if (stime)
1868                 *stime = ktime_get();
1869
1870         if (ASIC_IS_DCE4(rdev)) {
1871                 if (crtc == 0) {
1872                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1873                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1874                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1875                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1876                         ret |= DRM_SCANOUTPOS_VALID;
1877                 }
1878                 if (crtc == 1) {
1879                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1880                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1881                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1882                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1883                         ret |= DRM_SCANOUTPOS_VALID;
1884                 }
1885                 if (crtc == 2) {
1886                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1887                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1888                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1889                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1890                         ret |= DRM_SCANOUTPOS_VALID;
1891                 }
1892                 if (crtc == 3) {
1893                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1894                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1895                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1896                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1897                         ret |= DRM_SCANOUTPOS_VALID;
1898                 }
1899                 if (crtc == 4) {
1900                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1901                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1902                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1903                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1904                         ret |= DRM_SCANOUTPOS_VALID;
1905                 }
1906                 if (crtc == 5) {
1907                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1908                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1909                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1910                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1911                         ret |= DRM_SCANOUTPOS_VALID;
1912                 }
1913         } else if (ASIC_IS_AVIVO(rdev)) {
1914                 if (crtc == 0) {
1915                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1916                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1917                         ret |= DRM_SCANOUTPOS_VALID;
1918                 }
1919                 if (crtc == 1) {
1920                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1921                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1922                         ret |= DRM_SCANOUTPOS_VALID;
1923                 }
1924         } else {
1925                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1926                 if (crtc == 0) {
1927                         /* Assume vbl_end == 0, get vbl_start from
1928                          * upper 16 bits.
1929                          */
1930                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1931                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1932                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1933                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1934                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1935                         if (!(stat_crtc & 1))
1936                                 in_vbl = false;
1937
1938                         ret |= DRM_SCANOUTPOS_VALID;
1939                 }
1940                 if (crtc == 1) {
1941                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1942                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1943                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1944                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1945                         if (!(stat_crtc & 1))
1946                                 in_vbl = false;
1947
1948                         ret |= DRM_SCANOUTPOS_VALID;
1949                 }
1950         }
1951
1952         /* Get optional system timestamp after query. */
1953         if (etime)
1954                 *etime = ktime_get();
1955
1956         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1957
1958         /* Decode into vertical and horizontal scanout position. */
1959         *vpos = position & 0x1fff;
1960         *hpos = (position >> 16) & 0x1fff;
1961
1962         /* Valid vblank area boundaries from gpu retrieved? */
1963         if (vbl > 0) {
1964                 /* Yes: Decode. */
1965                 ret |= DRM_SCANOUTPOS_ACCURATE;
1966                 vbl_start = vbl & 0x1fff;
1967                 vbl_end = (vbl >> 16) & 0x1fff;
1968         }
1969         else {
1970                 /* No: Fake something reasonable which gives at least ok results. */
1971                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1972                 vbl_end = 0;
1973         }
1974
1975         /* Test scanout position against vblank region. */
1976         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1977                 in_vbl = false;
1978
1979         /* Check if inside vblank area and apply corrective offsets:
1980          * vpos will then be >=0 in video scanout area, but negative
1981          * within vblank area, counting down the number of lines until
1982          * start of scanout.
1983          */
1984
1985         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1986         if (in_vbl && (*vpos >= vbl_start)) {
1987                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1988                 *vpos = *vpos - vtotal;
1989         }
1990
1991         /* Correct for shifted end of vbl at vbl_end. */
1992         *vpos = *vpos - vbl_end;
1993
1994         /* In vblank? */
1995         if (in_vbl)
1996                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1997
1998         /* Is vpos outside nominal vblank area, but less than
1999          * 1/100 of a frame height away from start of vblank?
2000          * If so, assume this isn't a massively delayed vblank
2001          * interrupt, but a vblank interrupt that fired a few
2002          * microseconds before true start of vblank. Compensate
2003          * by adding a full frame duration to the final timestamp.
2004          * Happens, e.g., on ATI R500, R600.
2005          *
2006          * We only do this if DRM_CALLED_FROM_VBLIRQ.
2007          */
2008         if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
2009                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
2010                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
2011
2012                 if (vbl_start - *vpos < vtotal / 100) {
2013                         *vpos -= vtotal;
2014
2015                         /* Signal this correction as "applied". */
2016                         ret |= 0x8;
2017                 }
2018         }
2019
2020         return ret;
2021 }