sys/dev/crypto/hifn/hifn7751.c

   1 /* $FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.5.2.5 2003/06/04 17:56:59 sam Exp $ */
   2 /* $DragonFly: src/sys/dev/crypto/hifn/hifn7751.c,v 1.2 2003/06/17 04:28:27 dillon Exp $ */
   3 /*      $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $  */
   4
   5 /*
   6  * Invertex AEON / Hifn 7751 driver
   7  * Copyright (c) 1999 Invertex Inc. All rights reserved.
   8  * Copyright (c) 1999 Theo de Raadt
   9  * Copyright (c) 2000-2001 Network Security Technologies, Inc.
  10  *                      http://www.netsec.net
  11  *
  12  * This driver is based on a previous driver by Invertex, for which they
  13  * requested:  Please send any comments, feedback, bug-fixes, or feature
  14  * requests to software@invertex.com.
  15  *
  16  * Redistribution and use in source and binary forms, with or without
  17  * modification, are permitted provided that the following conditions
  18  * are met:
  19  *
  20  * 1. Redistributions of source code must retain the above copyright
  21  *   notice, this list of conditions and the following disclaimer.
  22  * 2. Redistributions in binary form must reproduce the above copyright
  23  *   notice, this list of conditions and the following disclaimer in the
  24  *   documentation and/or other materials provided with the distribution.
  25  * 3. The name of the author may not be used to endorse or promote products
  26  *   derived from this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  29  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  30  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  31  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  32  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  33  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  34  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  35  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  36  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  37  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38  *
  39  * Effort sponsored in part by the Defense Advanced Research Projects
  40  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  41  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  42  *
  43  */
  44
  45 /*
  46  * Driver for the Hifn 7751 encryption processor.
  47  */
  48 #include "opt_hifn.h"
  49
  50 #include <sys/param.h>
  51 #include <sys/systm.h>
  52 #include <sys/proc.h>
  53 #include <sys/errno.h>
  54 #include <sys/malloc.h>
  55 #include <sys/kernel.h>
  56 #include <sys/mbuf.h>
  57 #include <sys/sysctl.h>
  58
  59 #include <vm/vm.h>
  60 #include <vm/pmap.h>
  61
  62 #include <machine/clock.h>
  63 #include <machine/bus.h>
  64 #include <machine/resource.h>
  65 #include <sys/bus.h>
  66 #include <sys/rman.h>
  67
  68 #include <opencrypto/cryptodev.h>
  69 #include <sys/random.h>
  70
  71 #include <pci/pcivar.h>
  72 #include <pci/pcireg.h>
  73
  74 #ifdef HIFN_RNDTEST
  75 #include <dev/rndtest/rndtest.h>
  76 #endif
  77 #include <dev/hifn/hifn7751reg.h>
  78 #include <dev/hifn/hifn7751var.h>
  79
  80 /*
  81  * Prototypes and count for the pci_device structure
  82  */
  83 static  int hifn_probe(device_t);
  84 static  int hifn_attach(device_t);
  85 static  int hifn_detach(device_t);
  86 static  int hifn_suspend(device_t);
  87 static  int hifn_resume(device_t);
  88 static  void hifn_shutdown(device_t);
  89
  90 static device_method_t hifn_methods[] = {
  91         /* Device interface */
  92         DEVMETHOD(device_probe,         hifn_probe),
  93         DEVMETHOD(device_attach,        hifn_attach),
  94         DEVMETHOD(device_detach,        hifn_detach),
  95         DEVMETHOD(device_suspend,       hifn_suspend),
  96         DEVMETHOD(device_resume,        hifn_resume),
  97         DEVMETHOD(device_shutdown,      hifn_shutdown),
  98
  99         /* bus interface */
 100         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 101         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 102
 103         { 0, 0 }
 104 };
 105 static driver_t hifn_driver = {
 106         "hifn",
 107         hifn_methods,
 108         sizeof (struct hifn_softc)
 109 };
 110 static devclass_t hifn_devclass;
 111
 112 DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0);
 113 MODULE_DEPEND(hifn, crypto, 1, 1, 1);
 114 #ifdef HIFN_RNDTEST
 115 MODULE_DEPEND(hifn, rndtest, 1, 1, 1);
 116 #endif
 117
 118 static  void hifn_reset_board(struct hifn_softc *, int);
 119 static  void hifn_reset_puc(struct hifn_softc *);
 120 static  void hifn_puc_wait(struct hifn_softc *);
 121 static  int hifn_enable_crypto(struct hifn_softc *);
 122 static  void hifn_set_retry(struct hifn_softc *sc);
 123 static  void hifn_init_dma(struct hifn_softc *);
 124 static  void hifn_init_pci_registers(struct hifn_softc *);
 125 static  int hifn_sramsize(struct hifn_softc *);
 126 static  int hifn_dramsize(struct hifn_softc *);
 127 static  int hifn_ramtype(struct hifn_softc *);
 128 static  void hifn_sessions(struct hifn_softc *);
 129 static  void hifn_intr(void *);
 130 static  u_int hifn_write_command(struct hifn_command *, u_int8_t *);
 131 static  u_int32_t hifn_next_signature(u_int32_t a, u_int cnt);
 132 static  int hifn_newsession(void *, u_int32_t *, struct cryptoini *);
 133 static  int hifn_freesession(void *, u_int64_t);
 134 static  int hifn_process(void *, struct cryptop *, int);
 135 static  void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *);
 136 static  int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int);
 137 static  int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *);
 138 static  int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *);
 139 static  int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *);
 140 static  int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *);
 141 static  int hifn_init_pubrng(struct hifn_softc *);
 142 #ifndef HIFN_NO_RNG
 143 static  void hifn_rng(void *);
 144 #endif
 145 static  void hifn_tick(void *);
 146 static  void hifn_abort(struct hifn_softc *);
 147 static  void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *);
 148
 149 static  void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t);
 150 static  void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t);
 151
 152 static __inline__ u_int32_t
 153 READ_REG_0(struct hifn_softc *sc, bus_size_t reg)
 154 {
 155     u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg);
 156     sc->sc_bar0_lastreg = (bus_size_t) -1;
 157     return (v);
 158 }
 159 #define WRITE_REG_0(sc, reg, val)       hifn_write_reg_0(sc, reg, val)
 160
 161 static __inline__ u_int32_t
 162 READ_REG_1(struct hifn_softc *sc, bus_size_t reg)
 163 {
 164     u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg);
 165     sc->sc_bar1_lastreg = (bus_size_t) -1;
 166     return (v);
 167 }
 168 #define WRITE_REG_1(sc, reg, val)       hifn_write_reg_1(sc, reg, val)
 169
 170 SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters");
 171
 172 #ifdef HIFN_DEBUG
 173 static  int hifn_debug = 0;
 174 SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug,
 175             0, "control debugging msgs");
 176 #endif
 177
 178 static  struct hifn_stats hifnstats;
 179 SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats,
 180             hifn_stats, "driver statistics");
 181 static  int hifn_maxbatch = 1;
 182 SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch,
 183             0, "max ops to batch w/o interrupt");
 184
 185 /*
 186  * Probe for a supported device.  The PCI vendor and device
 187  * IDs are used to detect devices we know how to handle.
 188  */
 189 static int
 190 hifn_probe(device_t dev)
 191 {
 192         if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX &&
 193             pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON)
 194                 return (0);
 195         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 196             (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 ||
 197              pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
 198              pci_get_device(dev) == PCI_PRODUCT_HIFN_7811))
 199                 return (0);
 200         if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
 201             pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751)
 202                 return (0);
 203         return (ENXIO);
 204 }
 205
 206 static void
 207 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 208 {
 209         bus_addr_t *paddr = (bus_addr_t*) arg;
 210         *paddr = segs->ds_addr;
 211 }
 212
 213 static const char*
 214 hifn_partname(struct hifn_softc *sc)
 215 {
 216         /* XXX sprintf numbers when not decoded */
 217         switch (pci_get_vendor(sc->sc_dev)) {
 218         case PCI_VENDOR_HIFN:
 219                 switch (pci_get_device(sc->sc_dev)) {
 220                 case PCI_PRODUCT_HIFN_6500:     return "Hifn 6500";
 221                 case PCI_PRODUCT_HIFN_7751:     return "Hifn 7751";
 222                 case PCI_PRODUCT_HIFN_7811:     return "Hifn 7811";
 223                 case PCI_PRODUCT_HIFN_7951:     return "Hifn 7951";
 224                 }
 225                 return "Hifn unknown-part";
 226         case PCI_VENDOR_INVERTEX:
 227                 switch (pci_get_device(sc->sc_dev)) {
 228                 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON";
 229                 }
 230                 return "Invertex unknown-part";
 231         case PCI_VENDOR_NETSEC:
 232                 switch (pci_get_device(sc->sc_dev)) {
 233                 case PCI_PRODUCT_NETSEC_7751:   return "NetSec 7751";
 234                 }
 235                 return "NetSec unknown-part";
 236         }
 237         return "Unknown-vendor unknown-part";
 238 }
 239
 240 static void
 241 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
 242 {
 243         u_int32_t *p = (u_int32_t *)buf;
 244         for (count /= sizeof (u_int32_t); count; count--)
 245                 add_true_randomness(*p++);
 246 }
 247
 248 /*
 249  * Attach an interface that successfully probed.
 250  */
 251 static int
 252 hifn_attach(device_t dev)
 253 {
 254         struct hifn_softc *sc = device_get_softc(dev);
 255         u_int32_t cmd;
 256         caddr_t kva;
 257         int rseg, rid;
 258         char rbase;
 259         u_int16_t ena, rev;
 260
 261         KASSERT(sc != NULL, ("hifn_attach: null software carrier!"));
 262         bzero(sc, sizeof (*sc));
 263         sc->sc_dev = dev;
 264
 265         /* XXX handle power management */
 266
 267         /*
 268          * The 7951 has a random number generator and
 269          * public key support; note this.
 270          */
 271         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 272             pci_get_device(dev) == PCI_PRODUCT_HIFN_7951)
 273                 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC;
 274         /*
 275          * The 7811 has a random number generator and
 276          * we also note it's identity 'cuz of some quirks.
 277          */
 278         if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
 279             pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)
 280                 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG;
 281
 282         /*
 283          * Configure support for memory-mapped access to
 284          * registers and for DMA operations.
 285          */
 286 #define PCIM_ENA        (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN)
 287         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
 288         cmd |= PCIM_ENA;
 289         pci_write_config(dev, PCIR_COMMAND, cmd, 4);
 290         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
 291         if ((cmd & PCIM_ENA) != PCIM_ENA) {
 292                 device_printf(dev, "failed to enable %s\n",
 293                         (cmd & PCIM_ENA) == 0 ?
 294                                 "memory mapping & bus mastering" :
 295                         (cmd & PCIM_CMD_MEMEN) == 0 ?
 296                                 "memory mapping" : "bus mastering");
 297                 goto fail_pci;
 298         }
 299 #undef PCIM_ENA
 300
 301         /*
 302          * Setup PCI resources. Note that we record the bus
 303          * tag and handle for each register mapping, this is
 304          * used by the READ_REG_0, WRITE_REG_0, READ_REG_1,
 305          * and WRITE_REG_1 macros throughout the driver.
 306          */
 307         rid = HIFN_BAR0;
 308         sc->sc_bar0res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
 309                                             0, ~0, 1, RF_ACTIVE);
 310         if (sc->sc_bar0res == NULL) {
 311                 device_printf(dev, "cannot map bar%d register space\n", 0);
 312                 goto fail_pci;
 313         }
 314         sc->sc_st0 = rman_get_bustag(sc->sc_bar0res);
 315         sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res);
 316         sc->sc_bar0_lastreg = (bus_size_t) -1;
 317
 318         rid = HIFN_BAR1;
 319         sc->sc_bar1res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
 320                                             0, ~0, 1, RF_ACTIVE);
 321         if (sc->sc_bar1res == NULL) {
 322                 device_printf(dev, "cannot map bar%d register space\n", 1);
 323                 goto fail_io0;
 324         }
 325         sc->sc_st1 = rman_get_bustag(sc->sc_bar1res);
 326         sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res);
 327         sc->sc_bar1_lastreg = (bus_size_t) -1;
 328
 329         hifn_set_retry(sc);
 330
 331         /*
 332          * Setup the area where the Hifn DMA's descriptors
 333          * and associated data structures.
 334          */
 335         if (bus_dma_tag_create(NULL,                    /* parent */
 336                                1, 0,                    /* alignment,boundary */
 337                                BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
 338                                BUS_SPACE_MAXADDR,       /* highaddr */
 339                                NULL, NULL,              /* filter, filterarg */
 340                                HIFN_MAX_DMALEN,         /* maxsize */
 341                                MAX_SCATTER,             /* nsegments */
 342                                HIFN_MAX_SEGLEN,         /* maxsegsize */
 343                                BUS_DMA_ALLOCNOW,        /* flags */
 344                                &sc->sc_dmat)) {
 345                 device_printf(dev, "cannot allocate DMA tag\n");
 346                 goto fail_io1;
 347         }
 348         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
 349                 device_printf(dev, "cannot create dma map\n");
 350                 bus_dma_tag_destroy(sc->sc_dmat);
 351                 goto fail_io1;
 352         }
 353         if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
 354                 device_printf(dev, "cannot alloc dma buffer\n");
 355                 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 356                 bus_dma_tag_destroy(sc->sc_dmat);
 357                 goto fail_io1;
 358         }
 359         if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva,
 360                              sizeof (*sc->sc_dma),
 361                              hifn_dmamap_cb, &sc->sc_dma_physaddr,
 362                              BUS_DMA_NOWAIT)) {
 363                 device_printf(dev, "cannot load dma map\n");
 364                 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap);
 365                 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 366                 bus_dma_tag_destroy(sc->sc_dmat);
 367                 goto fail_io1;
 368         }
 369         sc->sc_dma = (struct hifn_dma *)kva;
 370         bzero(sc->sc_dma, sizeof(*sc->sc_dma));
 371
 372         KASSERT(sc->sc_st0 != NULL, ("hifn_attach: null bar0 tag!"));
 373         KASSERT(sc->sc_sh0 != NULL, ("hifn_attach: null bar0 handle!"));
 374         KASSERT(sc->sc_st1 != NULL, ("hifn_attach: null bar1 tag!"));
 375         KASSERT(sc->sc_sh1 != NULL, ("hifn_attach: null bar1 handle!"));
 376
 377         /*
 378          * Reset the board and do the ``secret handshake''
 379          * to enable the crypto support.  Then complete the
 380          * initialization procedure by setting up the interrupt
 381          * and hooking in to the system crypto support so we'll
 382          * get used for system services like the crypto device,
 383          * IPsec, RNG device, etc.
 384          */
 385         hifn_reset_board(sc, 0);
 386
 387         if (hifn_enable_crypto(sc) != 0) {
 388                 device_printf(dev, "crypto enabling failed\n");
 389                 goto fail_mem;
 390         }
 391         hifn_reset_puc(sc);
 392
 393         hifn_init_dma(sc);
 394         hifn_init_pci_registers(sc);
 395
 396         if (hifn_ramtype(sc))
 397                 goto fail_mem;
 398
 399         if (sc->sc_drammodel == 0)
 400                 hifn_sramsize(sc);
 401         else
 402                 hifn_dramsize(sc);
 403
 404         /*
 405          * Workaround for NetSec 7751 rev A: half ram size because two
 406          * of the address lines were left floating
 407          */
 408         if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
 409             pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 &&
 410             pci_get_revid(dev) == 0x61) /*XXX???*/
 411                 sc->sc_ramsize >>= 1;
 412
 413         /*
 414          * Arrange the interrupt line.
 415          */
 416         rid = 0;
 417         sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
 418                                         0, ~0, 1, RF_SHAREABLE|RF_ACTIVE);
 419         if (sc->sc_irq == NULL) {
 420                 device_printf(dev, "could not map interrupt\n");
 421                 goto fail_mem;
 422         }
 423         /*
 424          * NB: Network code assumes we are blocked with splimp()
 425          *     so make sure the IRQ is marked appropriately.
 426          */
 427         if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET,
 428                            hifn_intr, sc, &sc->sc_intrhand)) {
 429                 device_printf(dev, "could not setup interrupt\n");
 430                 goto fail_intr2;
 431         }
 432
 433         hifn_sessions(sc);
 434
 435         /*
 436          * NB: Keep only the low 16 bits; this masks the chip id
 437          *     from the 7951.
 438          */
 439         rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff;
 440
 441         rseg = sc->sc_ramsize / 1024;
 442         rbase = 'K';
 443         if (sc->sc_ramsize >= (1024 * 1024)) {
 444                 rbase = 'M';
 445                 rseg /= 1024;
 446         }
 447         device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram, %u sessions\n",
 448                 hifn_partname(sc), rev,
 449                 rseg, rbase, sc->sc_drammodel ? 'd' : 's',
 450                 sc->sc_maxses);
 451
 452         sc->sc_cid = crypto_get_driverid(0);
 453         if (sc->sc_cid < 0) {
 454                 device_printf(dev, "could not get crypto driver id\n");
 455                 goto fail_intr;
 456         }
 457
 458         WRITE_REG_0(sc, HIFN_0_PUCNFG,
 459             READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID);
 460         ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
 461
 462         switch (ena) {
 463         case HIFN_PUSTAT_ENA_2:
 464                 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0,
 465                     hifn_newsession, hifn_freesession, hifn_process, sc);
 466                 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0,
 467                     hifn_newsession, hifn_freesession, hifn_process, sc);
 468                 /*FALLTHROUGH*/
 469         case HIFN_PUSTAT_ENA_1:
 470                 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0,
 471                     hifn_newsession, hifn_freesession, hifn_process, sc);
 472                 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0,
 473                     hifn_newsession, hifn_freesession, hifn_process, sc);
 474                 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0,
 475                     hifn_newsession, hifn_freesession, hifn_process, sc);
 476                 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0,
 477                     hifn_newsession, hifn_freesession, hifn_process, sc);
 478                 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0,
 479                     hifn_newsession, hifn_freesession, hifn_process, sc);
 480                 break;
 481         }
 482
 483         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
 484             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 485
 486         if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG))
 487                 hifn_init_pubrng(sc);
 488
 489         /* NB: 1 means the callout runs w/o Giant locked */
 490         callout_init(&sc->sc_tickto);
 491         callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
 492
 493         return (0);
 494
 495 fail_intr:
 496         bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
 497 fail_intr2:
 498         /* XXX don't store rid */
 499         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 500 fail_mem:
 501         bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
 502         bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
 503         bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 504         bus_dma_tag_destroy(sc->sc_dmat);
 505
 506         /* Turn off DMA polling */
 507         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 508             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 509 fail_io1:
 510         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
 511 fail_io0:
 512         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
 513 fail_pci:
 514         return (ENXIO);
 515 }
 516
 517 /*
 518  * Detach an interface that successfully probed.
 519  */
 520 static int
 521 hifn_detach(device_t dev)
 522 {
 523         struct hifn_softc *sc = device_get_softc(dev);
 524         int s;
 525
 526         KASSERT(sc != NULL, ("hifn_detach: null software carrier!"));
 527
 528         s = splimp();
 529
 530         /*XXX other resources */
 531         callout_stop(&sc->sc_tickto);
 532         callout_stop(&sc->sc_rngto);
 533 #ifdef HIFN_RNDTEST
 534         if (sc->sc_rndtest)
 535                 rndtest_detach(sc->sc_rndtest);
 536 #endif
 537
 538         /* Turn off DMA polling */
 539         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 540             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 541
 542         crypto_unregister_all(sc->sc_cid);
 543
 544         bus_generic_detach(dev);        /*XXX should be no children, right? */
 545
 546         bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
 547         /* XXX don't store rid */
 548         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 549
 550         bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
 551         bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
 552         bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
 553         bus_dma_tag_destroy(sc->sc_dmat);
 554
 555         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
 556         bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
 557
 558         splx(s);
 559
 560         return (0);
 561 }
 562
 563 /*
 564  * Stop all chip I/O so that the kernel's probe routines don't
 565  * get confused by errant DMAs when rebooting.
 566  */
 567 static void
 568 hifn_shutdown(device_t dev)
 569 {
 570 #ifdef notyet
 571         hifn_stop(device_get_softc(dev));
 572 #endif
 573 }
 574
 575 /*
 576  * Device suspend routine.  Stop the interface and save some PCI
 577  * settings in case the BIOS doesn't restore them properly on
 578  * resume.
 579  */
 580 static int
 581 hifn_suspend(device_t dev)
 582 {
 583         struct hifn_softc *sc = device_get_softc(dev);
 584 #ifdef notyet
 585         int i;
 586
 587         hifn_stop(sc);
 588         for (i = 0; i < 5; i++)
 589                 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
 590         sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
 591         sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
 592         sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
 593         sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
 594 #endif
 595         sc->sc_suspended = 1;
 596
 597         return (0);
 598 }
 599
 600 /*
 601  * Device resume routine.  Restore some PCI settings in case the BIOS
 602  * doesn't, re-enable busmastering, and restart the interface if
 603  * appropriate.
 604  */
 605 static int
 606 hifn_resume(device_t dev)
 607 {
 608         struct hifn_softc *sc = device_get_softc(dev);
 609 #ifdef notyet
 610         int i;
 611
 612         /* better way to do this? */
 613         for (i = 0; i < 5; i++)
 614                 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
 615         pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
 616         pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
 617         pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
 618         pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
 619
 620         /* reenable busmastering */
 621         pci_enable_busmaster(dev);
 622         pci_enable_io(dev, HIFN_RES);
 623
 624         /* reinitialize interface if necessary */
 625         if (ifp->if_flags & IFF_UP)
 626                 rl_init(sc);
 627 #endif
 628         sc->sc_suspended = 0;
 629
 630         return (0);
 631 }
 632
 633 static int
 634 hifn_init_pubrng(struct hifn_softc *sc)
 635 {
 636         u_int32_t r;
 637         int i;
 638
 639 #ifdef HIFN_RNDTEST
 640         sc->sc_rndtest = rndtest_attach(sc->sc_dev);
 641         if (sc->sc_rndtest)
 642                 sc->sc_harvest = rndtest_harvest;
 643         else
 644                 sc->sc_harvest = default_harvest;
 645 #else
 646         sc->sc_harvest = default_harvest;
 647 #endif
 648         if ((sc->sc_flags & HIFN_IS_7811) == 0) {
 649                 /* Reset 7951 public key/rng engine */
 650                 WRITE_REG_1(sc, HIFN_1_PUB_RESET,
 651                     READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET);
 652
 653                 for (i = 0; i < 100; i++) {
 654                         DELAY(1000);
 655                         if ((READ_REG_1(sc, HIFN_1_PUB_RESET) &
 656                             HIFN_PUBRST_RESET) == 0)
 657                                 break;
 658                 }
 659
 660                 if (i == 100) {
 661                         device_printf(sc->sc_dev, "public key init failed\n");
 662                         return (1);
 663                 }
 664         }
 665
 666 #ifndef HIFN_NO_RNG
 667         /* Enable the rng, if available */
 668         if (sc->sc_flags & HIFN_HAS_RNG) {
 669                 if (sc->sc_flags & HIFN_IS_7811) {
 670                         r = READ_REG_1(sc, HIFN_1_7811_RNGENA);
 671                         if (r & HIFN_7811_RNGENA_ENA) {
 672                                 r &= ~HIFN_7811_RNGENA_ENA;
 673                                 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
 674                         }
 675                         WRITE_REG_1(sc, HIFN_1_7811_RNGCFG,
 676                             HIFN_7811_RNGCFG_DEFL);
 677                         r |= HIFN_7811_RNGENA_ENA;
 678                         WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
 679                 } else
 680                         WRITE_REG_1(sc, HIFN_1_RNG_CONFIG,
 681                             READ_REG_1(sc, HIFN_1_RNG_CONFIG) |
 682                             HIFN_RNGCFG_ENA);
 683
 684                 sc->sc_rngfirst = 1;
 685                 if (hz >= 100)
 686                         sc->sc_rnghz = hz / 100;
 687                 else
 688                         sc->sc_rnghz = 1;
 689                 /* NB: 1 means the callout runs w/o Giant locked */
 690                 callout_init(&sc->sc_rngto);
 691                 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
 692         }
 693 #endif
 694
 695         /* Enable public key engine, if available */
 696         if (sc->sc_flags & HIFN_HAS_PUBLIC) {
 697                 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
 698                 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE;
 699                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
 700         }
 701
 702         return (0);
 703 }
 704
 705 #ifndef HIFN_NO_RNG
 706 static void
 707 hifn_rng(void *vsc)
 708 {
 709 #define RANDOM_BITS(n)  (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0
 710         struct hifn_softc *sc = vsc;
 711         u_int32_t sts, num[2];
 712         int i;
 713
 714         if (sc->sc_flags & HIFN_IS_7811) {
 715                 for (i = 0; i < 5; i++) {
 716                         sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS);
 717                         if (sts & HIFN_7811_RNGSTS_UFL) {
 718                                 device_printf(sc->sc_dev,
 719                                               "RNG underflow: disabling\n");
 720                                 return;
 721                         }
 722                         if ((sts & HIFN_7811_RNGSTS_RDY) == 0)
 723                                 break;
 724
 725                         /*
 726                          * There are at least two words in the RNG FIFO
 727                          * at this point.
 728                          */
 729                         num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
 730                         num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
 731                         /* NB: discard first data read */
 732                         if (sc->sc_rngfirst)
 733                                 sc->sc_rngfirst = 0;
 734                         else
 735                                 (*sc->sc_harvest)(sc->sc_rndtest,
 736                                         num, sizeof (num));
 737                 }
 738         } else {
 739                 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA);
 740
 741                 /* NB: discard first data read */
 742                 if (sc->sc_rngfirst)
 743                         sc->sc_rngfirst = 0;
 744                 else
 745                         (*sc->sc_harvest)(sc->sc_rndtest,
 746                                 num, sizeof (num[0]));
 747         }
 748
 749         callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
 750 #undef RANDOM_BITS
 751 }
 752 #endif
 753
 754 static void
 755 hifn_puc_wait(struct hifn_softc *sc)
 756 {
 757         int i;
 758
 759         for (i = 5000; i > 0; i--) {
 760                 DELAY(1);
 761                 if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET))
 762                         break;
 763         }
 764         if (!i)
 765                 device_printf(sc->sc_dev, "proc unit did not reset\n");
 766 }
 767
 768 /*
 769  * Reset the processing unit.
 770  */
 771 static void
 772 hifn_reset_puc(struct hifn_softc *sc)
 773 {
 774         /* Reset processing unit */
 775         WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
 776         hifn_puc_wait(sc);
 777 }
 778
 779 /*
 780  * Set the Retry and TRDY registers; note that we set them to
 781  * zero because the 7811 locks up when forced to retry (section
 782  * 3.6 of "Specification Update SU-0014-04".  Not clear if we
 783  * should do this for all Hifn parts, but it doesn't seem to hurt.
 784  */
 785 static void
 786 hifn_set_retry(struct hifn_softc *sc)
 787 {
 788         /* NB: RETRY only responds to 8-bit reads/writes */
 789         pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1);
 790         pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4);
 791 }
 792
 793 /*
 794  * Resets the board.  Values in the regesters are left as is
 795  * from the reset (i.e. initial values are assigned elsewhere).
 796  */
 797 static void
 798 hifn_reset_board(struct hifn_softc *sc, int full)
 799 {
 800         u_int32_t reg;
 801
 802         /*
 803          * Set polling in the DMA configuration register to zero.  0x7 avoids
 804          * resetting the board and zeros out the other fields.
 805          */
 806         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 807             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 808
 809         /*
 810          * Now that polling has been disabled, we have to wait 1 ms
 811          * before resetting the board.
 812          */
 813         DELAY(1000);
 814
 815         /* Reset the DMA unit */
 816         if (full) {
 817                 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
 818                 DELAY(1000);
 819         } else {
 820                 WRITE_REG_1(sc, HIFN_1_DMA_CNFG,
 821                     HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET);
 822                 hifn_reset_puc(sc);
 823         }
 824
 825         KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!"));
 826         bzero(sc->sc_dma, sizeof(*sc->sc_dma));
 827
 828         /* Bring dma unit out of reset */
 829         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 830             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 831
 832         hifn_puc_wait(sc);
 833         hifn_set_retry(sc);
 834
 835         if (sc->sc_flags & HIFN_IS_7811) {
 836                 for (reg = 0; reg < 1000; reg++) {
 837                         if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) &
 838                             HIFN_MIPSRST_CRAMINIT)
 839                                 break;
 840                         DELAY(1000);
 841                 }
 842                 if (reg == 1000)
 843                         printf(": cram init timeout\n");
 844         }
 845 }
 846
 847 static u_int32_t
 848 hifn_next_signature(u_int32_t a, u_int cnt)
 849 {
 850         int i;
 851         u_int32_t v;
 852
 853         for (i = 0; i < cnt; i++) {
 854
 855                 /* get the parity */
 856                 v = a & 0x80080125;
 857                 v ^= v >> 16;
 858                 v ^= v >> 8;
 859                 v ^= v >> 4;
 860                 v ^= v >> 2;
 861                 v ^= v >> 1;
 862
 863                 a = (v & 1) ^ (a << 1);
 864         }
 865
 866         return a;
 867 }
 868
 869 struct pci2id {
 870         u_short         pci_vendor;
 871         u_short         pci_prod;
 872         char            card_id[13];
 873 };
 874 static struct pci2id pci2id[] = {
 875         {
 876                 PCI_VENDOR_HIFN,
 877                 PCI_PRODUCT_HIFN_7951,
 878                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 879                   0x00, 0x00, 0x00, 0x00, 0x00 }
 880         }, {
 881                 PCI_VENDOR_NETSEC,
 882                 PCI_PRODUCT_NETSEC_7751,
 883                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 884                   0x00, 0x00, 0x00, 0x00, 0x00 }
 885         }, {
 886                 PCI_VENDOR_INVERTEX,
 887                 PCI_PRODUCT_INVERTEX_AEON,
 888                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 889                   0x00, 0x00, 0x00, 0x00, 0x00 }
 890         }, {
 891                 PCI_VENDOR_HIFN,
 892                 PCI_PRODUCT_HIFN_7811,
 893                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 894                   0x00, 0x00, 0x00, 0x00, 0x00 }
 895         }, {
 896                 /*
 897                  * Other vendors share this PCI ID as well, such as
 898                  * http://www.powercrypt.com, and obviously they also
 899                  * use the same key.
 900                  */
 901                 PCI_VENDOR_HIFN,
 902                 PCI_PRODUCT_HIFN_7751,
 903                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 904                   0x00, 0x00, 0x00, 0x00, 0x00 }
 905         },
 906 };
 907
 908 /*
 909  * Checks to see if crypto is already enabled.  If crypto isn't enable,
 910  * "hifn_enable_crypto" is called to enable it.  The check is important,
 911  * as enabling crypto twice will lock the board.
 912  */
 913 static int
 914 hifn_enable_crypto(struct hifn_softc *sc)
 915 {
 916         u_int32_t dmacfg, ramcfg, encl, addr, i;
 917         char *offtbl = NULL;
 918
 919         for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) {
 920                 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) &&
 921                     pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) {
 922                         offtbl = pci2id[i].card_id;
 923                         break;
 924                 }
 925         }
 926         if (offtbl == NULL) {
 927                 device_printf(sc->sc_dev, "Unknown card!\n");
 928                 return (1);
 929         }
 930
 931         ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG);
 932         dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG);
 933
 934         /*
 935          * The RAM config register's encrypt level bit needs to be set before
 936          * every read performed on the encryption level register.
 937          */
 938         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
 939
 940         encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
 941
 942         /*
 943          * Make sure we don't re-unlock.  Two unlocks kills chip until the
 944          * next reboot.
 945          */
 946         if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) {
 947 #ifdef HIFN_DEBUG
 948                 if (hifn_debug)
 949                         device_printf(sc->sc_dev,
 950                             "Strong crypto already enabled!\n");
 951 #endif
 952                 goto report;
 953         }
 954
 955         if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) {
 956 #ifdef HIFN_DEBUG
 957                 if (hifn_debug)
 958                         device_printf(sc->sc_dev,
 959                               "Unknown encryption level 0x%x\n", encl);
 960 #endif
 961                 return 1;
 962         }
 963
 964         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK |
 965             HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 966         DELAY(1000);
 967         addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1);
 968         DELAY(1000);
 969         WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0);
 970         DELAY(1000);
 971
 972         for (i = 0; i <= 12; i++) {
 973                 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
 974                 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr);
 975
 976                 DELAY(1000);
 977         }
 978
 979         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
 980         encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
 981
 982 #ifdef HIFN_DEBUG
 983         if (hifn_debug) {
 984                 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2)
 985                         device_printf(sc->sc_dev, "Engine is permanently "
 986                                 "locked until next system reset!\n");
 987                 else
 988                         device_printf(sc->sc_dev, "Engine enabled "
 989                                 "successfully!\n");
 990         }
 991 #endif
 992
 993 report:
 994         WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg);
 995         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg);
 996
 997         switch (encl) {
 998         case HIFN_PUSTAT_ENA_1:
 999         case HIFN_PUSTAT_ENA_2:
1000                 break;
1001         case HIFN_PUSTAT_ENA_0:
1002         default:
1003                 device_printf(sc->sc_dev, "disabled");
1004                 break;
1005         }
1006
1007         return 0;
1008 }
1009
1010 /*
1011  * Give initial values to the registers listed in the "Register Space"
1012  * section of the HIFN Software Development reference manual.
1013  */
1014 static void
1015 hifn_init_pci_registers(struct hifn_softc *sc)
1016 {
1017         /* write fixed values needed by the Initialization registers */
1018         WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1019         WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1020         WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1021
1022         /* write all 4 ring address registers */
1023         WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr +
1024             offsetof(struct hifn_dma, cmdr[0]));
1025         WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr +
1026             offsetof(struct hifn_dma, srcr[0]));
1027         WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr +
1028             offsetof(struct hifn_dma, dstr[0]));
1029         WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr +
1030             offsetof(struct hifn_dma, resr[0]));
1031
1032         DELAY(2000);
1033
1034         /* write status register */
1035         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1036             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1037             HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1038             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1039             HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1040             HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1041             HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1042             HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1043             HIFN_DMACSR_S_WAIT |
1044             HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1045             HIFN_DMACSR_C_WAIT |
1046             HIFN_DMACSR_ENGINE |
1047             ((sc->sc_flags & HIFN_HAS_PUBLIC) ?
1048                 HIFN_DMACSR_PUBDONE : 0) |
1049             ((sc->sc_flags & HIFN_IS_7811) ?
1050                 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0));
1051
1052         sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0;
1053         sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1054             HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1055             HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1056             ((sc->sc_flags & HIFN_IS_7811) ?
1057                 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0);
1058         sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
1059         WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1060
1061         WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1062             HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1063             HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1064             (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM));
1065
1066         WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1067         WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1068             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1069             ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1070             ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1071 }
1072
1073 /*
1074  * The maximum number of sessions supported by the card
1075  * is dependent on the amount of context ram, which
1076  * encryption algorithms are enabled, and how compression
1077  * is configured.  This should be configured before this
1078  * routine is called.
1079  */
1080 static void
1081 hifn_sessions(struct hifn_softc *sc)
1082 {
1083         u_int32_t pucnfg;
1084         int ctxsize;
1085
1086         pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1087
1088         if (pucnfg & HIFN_PUCNFG_COMPSING) {
1089                 if (pucnfg & HIFN_PUCNFG_ENCCNFG)
1090                         ctxsize = 128;
1091                 else
1092                         ctxsize = 512;
1093                 sc->sc_maxses = 1 +
1094                     ((sc->sc_ramsize - 32768) / ctxsize);
1095         } else
1096                 sc->sc_maxses = sc->sc_ramsize / 16384;
1097
1098         if (sc->sc_maxses > 2048)
1099                 sc->sc_maxses = 2048;
1100 }
1101
1102 /*
1103  * Determine ram type (sram or dram).  Board should be just out of a reset
1104  * state when this is called.
1105  */
1106 static int
1107 hifn_ramtype(struct hifn_softc *sc)
1108 {
1109         u_int8_t data[8], dataexpect[8];
1110         int i;
1111
1112         for (i = 0; i < sizeof(data); i++)
1113                 data[i] = dataexpect[i] = 0x55;
1114         if (hifn_writeramaddr(sc, 0, data))
1115                 return (-1);
1116         if (hifn_readramaddr(sc, 0, data))
1117                 return (-1);
1118         if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1119                 sc->sc_drammodel = 1;
1120                 return (0);
1121         }
1122
1123         for (i = 0; i < sizeof(data); i++)
1124                 data[i] = dataexpect[i] = 0xaa;
1125         if (hifn_writeramaddr(sc, 0, data))
1126                 return (-1);
1127         if (hifn_readramaddr(sc, 0, data))
1128                 return (-1);
1129         if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1130                 sc->sc_drammodel = 1;
1131                 return (0);
1132         }
1133
1134         return (0);
1135 }
1136
1137 #define HIFN_SRAM_MAX           (32 << 20)
1138 #define HIFN_SRAM_STEP_SIZE     16384
1139 #define HIFN_SRAM_GRANULARITY   (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE)
1140
1141 static int
1142 hifn_sramsize(struct hifn_softc *sc)
1143 {
1144         u_int32_t a;
1145         u_int8_t data[8];
1146         u_int8_t dataexpect[sizeof(data)];
1147         int32_t i;
1148
1149         for (i = 0; i < sizeof(data); i++)
1150                 data[i] = dataexpect[i] = i ^ 0x5a;
1151
1152         for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) {
1153                 a = i * HIFN_SRAM_STEP_SIZE;
1154                 bcopy(&i, data, sizeof(i));
1155                 hifn_writeramaddr(sc, a, data);
1156         }
1157
1158         for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) {
1159                 a = i * HIFN_SRAM_STEP_SIZE;
1160                 bcopy(&i, dataexpect, sizeof(i));
1161                 if (hifn_readramaddr(sc, a, data) < 0)
1162                         return (0);
1163                 if (bcmp(data, dataexpect, sizeof(data)) != 0)
1164                         return (0);
1165                 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE;
1166         }
1167
1168         return (0);
1169 }
1170
1171 /*
1172  * XXX For dram boards, one should really try all of the
1173  * HIFN_PUCNFG_DSZ_*'s.  This just assumes that PUCNFG
1174  * is already set up correctly.
1175  */
1176 static int
1177 hifn_dramsize(struct hifn_softc *sc)
1178 {
1179         u_int32_t cnfg;
1180
1181         cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
1182             HIFN_PUCNFG_DRAMMASK;
1183         sc->sc_ramsize = 1 << ((cnfg >> 13) + 18);
1184         return (0);
1185 }
1186
1187 static void
1188 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp)
1189 {
1190         struct hifn_dma *dma = sc->sc_dma;
1191
1192         if (dma->cmdi == HIFN_D_CMD_RSIZE) {
1193                 dma->cmdi = 0;
1194                 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1195                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1196                 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1197                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1198         }
1199         *cmdp = dma->cmdi++;
1200         dma->cmdk = dma->cmdi;
1201
1202         if (dma->srci == HIFN_D_SRC_RSIZE) {
1203                 dma->srci = 0;
1204                 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID |
1205                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1206                 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1207                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1208         }
1209         *srcp = dma->srci++;
1210         dma->srck = dma->srci;
1211
1212         if (dma->dsti == HIFN_D_DST_RSIZE) {
1213                 dma->dsti = 0;
1214                 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID |
1215                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1216                 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE,
1217                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1218         }
1219         *dstp = dma->dsti++;
1220         dma->dstk = dma->dsti;
1221
1222         if (dma->resi == HIFN_D_RES_RSIZE) {
1223                 dma->resi = 0;
1224                 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1225                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1226                 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1227                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1228         }
1229         *resp = dma->resi++;
1230         dma->resk = dma->resi;
1231 }
1232
1233 static int
1234 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1235 {
1236         struct hifn_dma *dma = sc->sc_dma;
1237         hifn_base_command_t wc;
1238         const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1239         int r, cmdi, resi, srci, dsti;
1240
1241         wc.masks = htole16(3 << 13);
1242         wc.session_num = htole16(addr >> 14);
1243         wc.total_source_count = htole16(8);
1244         wc.total_dest_count = htole16(addr & 0x3fff);
1245
1246         hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1247
1248         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1249             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1250             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1251
1252         /* build write command */
1253         bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1254         *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc;
1255         bcopy(data, &dma->test_src, sizeof(dma->test_src));
1256
1257         dma->srcr[srci].p = htole32(sc->sc_dma_physaddr
1258             + offsetof(struct hifn_dma, test_src));
1259         dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr
1260             + offsetof(struct hifn_dma, test_dst));
1261
1262         dma->cmdr[cmdi].l = htole32(16 | masks);
1263         dma->srcr[srci].l = htole32(8 | masks);
1264         dma->dstr[dsti].l = htole32(4 | masks);
1265         dma->resr[resi].l = htole32(4 | masks);
1266
1267         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1268             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1269
1270         for (r = 10000; r >= 0; r--) {
1271                 DELAY(10);
1272                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1273                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1274                 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1275                         break;
1276                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1277                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1278         }
1279         if (r == 0) {
1280                 device_printf(sc->sc_dev, "writeramaddr -- "
1281                     "result[%d](addr %d) still valid\n", resi, addr);
1282                 r = -1;
1283                 return (-1);
1284         } else
1285                 r = 0;
1286
1287         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1288             HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1289             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1290
1291         return (r);
1292 }
1293
1294 static int
1295 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1296 {
1297         struct hifn_dma *dma = sc->sc_dma;
1298         hifn_base_command_t rc;
1299         const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1300         int r, cmdi, srci, dsti, resi;
1301
1302         rc.masks = htole16(2 << 13);
1303         rc.session_num = htole16(addr >> 14);
1304         rc.total_source_count = htole16(addr & 0x3fff);
1305         rc.total_dest_count = htole16(8);
1306
1307         hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1308
1309         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1310             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1311             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1312
1313         bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1314         *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc;
1315
1316         dma->srcr[srci].p = htole32(sc->sc_dma_physaddr +
1317             offsetof(struct hifn_dma, test_src));
1318         dma->test_src = 0;
1319         dma->dstr[dsti].p =  htole32(sc->sc_dma_physaddr +
1320             offsetof(struct hifn_dma, test_dst));
1321         dma->test_dst = 0;
1322         dma->cmdr[cmdi].l = htole32(8 | masks);
1323         dma->srcr[srci].l = htole32(8 | masks);
1324         dma->dstr[dsti].l = htole32(8 | masks);
1325         dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks);
1326
1327         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1328             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1329
1330         for (r = 10000; r >= 0; r--) {
1331                 DELAY(10);
1332                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1333                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1334                 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1335                         break;
1336                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1337                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1338         }
1339         if (r == 0) {
1340                 device_printf(sc->sc_dev, "readramaddr -- "
1341                     "result[%d](addr %d) still valid\n", resi, addr);
1342                 r = -1;
1343         } else {
1344                 r = 0;
1345                 bcopy(&dma->test_dst, data, sizeof(dma->test_dst));
1346         }
1347
1348         WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1349             HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1350             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1351
1352         return (r);
1353 }
1354
1355 /*
1356  * Initialize the descriptor rings.
1357  */
1358 static void
1359 hifn_init_dma(struct hifn_softc *sc)
1360 {
1361         struct hifn_dma *dma = sc->sc_dma;
1362         int i;
1363
1364         hifn_set_retry(sc);
1365
1366         /* initialize static pointer values */
1367         for (i = 0; i < HIFN_D_CMD_RSIZE; i++)
1368                 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr +
1369                     offsetof(struct hifn_dma, command_bufs[i][0]));
1370         for (i = 0; i < HIFN_D_RES_RSIZE; i++)
1371                 dma->resr[i].p = htole32(sc->sc_dma_physaddr +
1372                     offsetof(struct hifn_dma, result_bufs[i][0]));
1373
1374         dma->cmdr[HIFN_D_CMD_RSIZE].p =
1375             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0]));
1376         dma->srcr[HIFN_D_SRC_RSIZE].p =
1377             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0]));
1378         dma->dstr[HIFN_D_DST_RSIZE].p =
1379             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0]));
1380         dma->resr[HIFN_D_RES_RSIZE].p =
1381             htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0]));
1382
1383         dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
1384         dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
1385         dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
1386 }
1387
1388 /*
1389  * Writes out the raw command buffer space.  Returns the
1390  * command buffer size.
1391  */
1392 static u_int
1393 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf)
1394 {
1395 #define MIN(a,b)        ((a)<(b)?(a):(b))
1396         u_int8_t *buf_pos;
1397         hifn_base_command_t *base_cmd;
1398         hifn_mac_command_t *mac_cmd;
1399         hifn_crypt_command_t *cry_cmd;
1400         int using_mac, using_crypt, len;
1401         u_int32_t dlen, slen;
1402
1403         buf_pos = buf;
1404         using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC;
1405         using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT;
1406
1407         base_cmd = (hifn_base_command_t *)buf_pos;
1408         base_cmd->masks = htole16(cmd->base_masks);
1409         slen = cmd->src_mapsize;
1410         if (cmd->sloplen)
1411                 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t);
1412         else
1413                 dlen = cmd->dst_mapsize;
1414         base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO);
1415         base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1416         dlen >>= 16;
1417         slen >>= 16;
1418         base_cmd->session_num = htole16(cmd->session_num |
1419             ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1420             ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1421         buf_pos += sizeof(hifn_base_command_t);
1422
1423         if (using_mac) {
1424                 mac_cmd = (hifn_mac_command_t *)buf_pos;
1425                 dlen = cmd->maccrd->crd_len;
1426                 mac_cmd->source_count = htole16(dlen & 0xffff);
1427                 dlen >>= 16;
1428                 mac_cmd->masks = htole16(cmd->mac_masks |
1429                     ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M));
1430                 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip);
1431                 mac_cmd->reserved = 0;
1432                 buf_pos += sizeof(hifn_mac_command_t);
1433         }
1434
1435         if (using_crypt) {
1436                 cry_cmd = (hifn_crypt_command_t *)buf_pos;
1437                 dlen = cmd->enccrd->crd_len;
1438                 cry_cmd->source_count = htole16(dlen & 0xffff);
1439                 dlen >>= 16;
1440                 cry_cmd->masks = htole16(cmd->cry_masks |
1441                     ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M));
1442                 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip);
1443                 cry_cmd->reserved = 0;
1444                 buf_pos += sizeof(hifn_crypt_command_t);
1445         }
1446
1447         if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) {
1448                 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH);
1449                 buf_pos += HIFN_MAC_KEY_LENGTH;
1450         }
1451
1452         if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) {
1453                 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1454                 case HIFN_CRYPT_CMD_ALG_3DES:
1455                         bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH);
1456                         buf_pos += HIFN_3DES_KEY_LENGTH;
1457                         break;
1458                 case HIFN_CRYPT_CMD_ALG_DES:
1459                         bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH);
1460                         buf_pos += cmd->cklen;
1461                         break;
1462                 case HIFN_CRYPT_CMD_ALG_RC4:
1463                         len = 256;
1464                         do {
1465                                 int clen;
1466
1467                                 clen = MIN(cmd->cklen, len);
1468                                 bcopy(cmd->ck, buf_pos, clen);
1469                                 len -= clen;
1470                                 buf_pos += clen;
1471                         } while (len > 0);
1472                         bzero(buf_pos, 4);
1473                         buf_pos += 4;
1474                         break;
1475                 }
1476         }
1477
1478         if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) {
1479                 bcopy(cmd->iv, buf_pos, HIFN_IV_LENGTH);
1480                 buf_pos += HIFN_IV_LENGTH;
1481         }
1482
1483         if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) {
1484                 bzero(buf_pos, 8);
1485                 buf_pos += 8;
1486         }
1487
1488         return (buf_pos - buf);
1489 #undef  MIN
1490 }
1491
1492 static int
1493 hifn_dmamap_aligned(struct hifn_operand *op)
1494 {
1495         int i;
1496
1497         for (i = 0; i < op->nsegs; i++) {
1498                 if (op->segs[i].ds_addr & 3)
1499                         return (0);
1500                 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3))
1501                         return (0);
1502         }
1503         return (1);
1504 }
1505
1506 static int
1507 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd)
1508 {
1509         struct hifn_dma *dma = sc->sc_dma;
1510         struct hifn_operand *dst = &cmd->dst;
1511         u_int32_t p, l;
1512         int idx, used = 0, i;
1513
1514         idx = dma->dsti;
1515         for (i = 0; i < dst->nsegs - 1; i++) {
1516                 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1517                 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1518                     HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len);
1519                 HIFN_DSTR_SYNC(sc, idx,
1520                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1521                 used++;
1522
1523                 if (++idx == HIFN_D_DST_RSIZE) {
1524                         dma->dstr[idx].l = htole32(HIFN_D_VALID |
1525                             HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1526                         HIFN_DSTR_SYNC(sc, idx,
1527                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1528                         idx = 0;
1529                 }
1530         }
1531
1532         if (cmd->sloplen == 0) {
1533                 p = dst->segs[i].ds_addr;
1534                 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1535                     dst->segs[i].ds_len;
1536         } else {
1537                 p = sc->sc_dma_physaddr +
1538                     offsetof(struct hifn_dma, slop[cmd->slopidx]);
1539                 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1540                     sizeof(u_int32_t);
1541
1542                 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) {
1543                         dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1544                         dma->dstr[idx].l = htole32(HIFN_D_VALID |
1545                             HIFN_D_MASKDONEIRQ |
1546                             (dst->segs[i].ds_len - cmd->sloplen));
1547                         HIFN_DSTR_SYNC(sc, idx,
1548                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1549                         used++;
1550
1551                         if (++idx == HIFN_D_DST_RSIZE) {
1552                                 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1553                                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1554                                 HIFN_DSTR_SYNC(sc, idx,
1555                                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1556                                 idx = 0;
1557                         }
1558                 }
1559         }
1560         dma->dstr[idx].p = htole32(p);
1561         dma->dstr[idx].l = htole32(l);
1562         HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1563         used++;
1564
1565         if (++idx == HIFN_D_DST_RSIZE) {
1566                 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP |
1567                     HIFN_D_MASKDONEIRQ);
1568                 HIFN_DSTR_SYNC(sc, idx,
1569                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1570                 idx = 0;
1571         }
1572
1573         dma->dsti = idx;
1574         dma->dstu += used;
1575         return (idx);
1576 }
1577
1578 static int
1579 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd)
1580 {
1581         struct hifn_dma *dma = sc->sc_dma;
1582         struct hifn_operand *src = &cmd->src;
1583         int idx, i;
1584         u_int32_t last = 0;
1585
1586         idx = dma->srci;
1587         for (i = 0; i < src->nsegs; i++) {
1588                 if (i == src->nsegs - 1)
1589                         last = HIFN_D_LAST;
1590
1591                 dma->srcr[idx].p = htole32(src->segs[i].ds_addr);
1592                 dma->srcr[idx].l = htole32(src->segs[i].ds_len |
1593                     HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last);
1594                 HIFN_SRCR_SYNC(sc, idx,
1595                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1596
1597                 if (++idx == HIFN_D_SRC_RSIZE) {
1598                         dma->srcr[idx].l = htole32(HIFN_D_VALID |
1599                             HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1600                         HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1601                             BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1602                         idx = 0;
1603                 }
1604         }
1605         dma->srci = idx;
1606         dma->srcu += src->nsegs;
1607         return (idx);
1608 }
1609
1610 static void
1611 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1612 {
1613         struct hifn_operand *op = arg;
1614
1615         KASSERT(nsegs <= MAX_SCATTER,
1616                 ("hifn_op_cb: too many DMA segments (%u > %u) "
1617                  "returned when mapping operand", nsegs, MAX_SCATTER));
1618         op->mapsize = mapsize;
1619         op->nsegs = nsegs;
1620         bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1621 }
1622
1623 static int
1624 hifn_crypto(
1625         struct hifn_softc *sc,
1626         struct hifn_command *cmd,
1627         struct cryptop *crp,
1628         int hint)
1629 {
1630         struct  hifn_dma *dma = sc->sc_dma;
1631         u_int32_t cmdlen;
1632         int cmdi, resi, err = 0;
1633
1634         /*
1635          * need 1 cmd, and 1 res
1636          *
1637          * NB: check this first since it's easy.
1638          */
1639         if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE ||
1640             (dma->resu + 1) > HIFN_D_RES_RSIZE) {
1641 #ifdef HIFN_DEBUG
1642                 if (hifn_debug) {
1643                         device_printf(sc->sc_dev,
1644                                 "cmd/result exhaustion, cmdu %u resu %u\n",
1645                                 dma->cmdu, dma->resu);
1646                 }
1647 #endif
1648                 hifnstats.hst_nomem_cr++;
1649                 return (ERESTART);
1650         }
1651
1652         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) {
1653                 hifnstats.hst_nomem_map++;
1654                 return (ENOMEM);
1655         }
1656
1657         if (crp->crp_flags & CRYPTO_F_IMBUF) {
1658                 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map,
1659                     cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1660                         hifnstats.hst_nomem_load++;
1661                         err = ENOMEM;
1662                         goto err_srcmap1;
1663                 }
1664         } else if (crp->crp_flags & CRYPTO_F_IOV) {
1665                 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map,
1666                     cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1667                         hifnstats.hst_nomem_load++;
1668                         err = ENOMEM;
1669                         goto err_srcmap1;
1670                 }
1671         } else {
1672                 err = EINVAL;
1673                 goto err_srcmap1;
1674         }
1675
1676         if (hifn_dmamap_aligned(&cmd->src)) {
1677                 cmd->sloplen = cmd->src_mapsize & 3;
1678                 cmd->dst = cmd->src;
1679         } else {
1680                 if (crp->crp_flags & CRYPTO_F_IOV) {
1681                         err = EINVAL;
1682                         goto err_srcmap;
1683                 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1684                         int totlen, len;
1685                         struct mbuf *m, *m0, *mlast;
1686
1687                         KASSERT(cmd->dst_m == cmd->src_m,
1688                                 ("hifn_crypto: dst_m initialized improperly"));
1689                         hifnstats.hst_unaligned++;
1690                         /*
1691                          * Source is not aligned on a longword boundary.
1692                          * Copy the data to insure alignment.  If we fail
1693                          * to allocate mbufs or clusters while doing this
1694                          * we return ERESTART so the operation is requeued
1695                          * at the crypto later, but only if there are
1696                          * ops already posted to the hardware; otherwise we
1697                          * have no guarantee that we'll be re-entered.
1698                          */
1699                         totlen = cmd->src_mapsize;
1700                         if (cmd->src_m->m_flags & M_PKTHDR) {
1701                                 len = MHLEN;
1702                                 MGETHDR(m0, M_DONTWAIT, MT_DATA);
1703                                 if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) {
1704                                         m_free(m0);
1705                                         m0 = NULL;
1706                                 }
1707                         } else {
1708                                 len = MLEN;
1709                                 MGET(m0, M_DONTWAIT, MT_DATA);
1710                         }
1711                         if (m0 == NULL) {
1712                                 hifnstats.hst_nomem_mbuf++;
1713                                 err = dma->cmdu ? ERESTART : ENOMEM;
1714                                 goto err_srcmap;
1715                         }
1716                         if (totlen >= MINCLSIZE) {
1717                                 MCLGET(m0, M_DONTWAIT);
1718                                 if ((m0->m_flags & M_EXT) == 0) {
1719                                         hifnstats.hst_nomem_mcl++;
1720                                         err = dma->cmdu ? ERESTART : ENOMEM;
1721                                         m_freem(m0);
1722                                         goto err_srcmap;
1723                                 }
1724                                 len = MCLBYTES;
1725                         }
1726                         totlen -= len;
1727                         m0->m_pkthdr.len = m0->m_len = len;
1728                         mlast = m0;
1729
1730                         while (totlen > 0) {
1731                                 MGET(m, M_DONTWAIT, MT_DATA);
1732                                 if (m == NULL) {
1733                                         hifnstats.hst_nomem_mbuf++;
1734                                         err = dma->cmdu ? ERESTART : ENOMEM;
1735                                         m_freem(m0);
1736                                         goto err_srcmap;
1737                                 }
1738                                 len = MLEN;
1739                                 if (totlen >= MINCLSIZE) {
1740                                         MCLGET(m, M_DONTWAIT);
1741                                         if ((m->m_flags & M_EXT) == 0) {
1742                                                 hifnstats.hst_nomem_mcl++;
1743                                                 err = dma->cmdu ? ERESTART : ENOMEM;
1744                                                 mlast->m_next = m;
1745                                                 m_freem(m0);
1746                                                 goto err_srcmap;
1747                                         }
1748                                         len = MCLBYTES;
1749                                 }
1750
1751                                 m->m_len = len;
1752                                 m0->m_pkthdr.len += len;
1753                                 totlen -= len;
1754
1755                                 mlast->m_next = m;
1756                                 mlast = m;
1757                         }
1758                         cmd->dst_m = m0;
1759                 }
1760         }
1761
1762         if (cmd->dst_map == NULL) {
1763                 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) {
1764                         hifnstats.hst_nomem_map++;
1765                         err = ENOMEM;
1766                         goto err_srcmap;
1767                 }
1768                 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1769                         if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map,
1770                             cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1771                                 hifnstats.hst_nomem_map++;
1772                                 err = ENOMEM;
1773                                 goto err_dstmap1;
1774                         }
1775                 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1776                         if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map,
1777                             cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1778                                 hifnstats.hst_nomem_load++;
1779                                 err = ENOMEM;
1780                                 goto err_dstmap1;
1781                         }
1782                 }
1783         }
1784
1785 #ifdef HIFN_DEBUG
1786         if (hifn_debug) {
1787                 device_printf(sc->sc_dev,
1788                     "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n",
1789                     READ_REG_1(sc, HIFN_1_DMA_CSR),
1790                     READ_REG_1(sc, HIFN_1_DMA_IER),
1791                     dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1792                     cmd->src_nsegs, cmd->dst_nsegs);
1793         }
1794 #endif
1795
1796         if (cmd->src_map == cmd->dst_map) {
1797                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1798                     BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1799         } else {
1800                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1801                     BUS_DMASYNC_PREWRITE);
1802                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
1803                     BUS_DMASYNC_PREREAD);
1804         }
1805
1806         /*
1807          * need N src, and N dst
1808          */
1809         if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE ||
1810             (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) {
1811 #ifdef HIFN_DEBUG
1812                 if (hifn_debug) {
1813                         device_printf(sc->sc_dev,
1814                                 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n",
1815                                 dma->srcu, cmd->src_nsegs,
1816                                 dma->dstu, cmd->dst_nsegs);
1817                 }
1818 #endif
1819                 hifnstats.hst_nomem_sd++;
1820                 err = ERESTART;
1821                 goto err_dstmap;
1822         }
1823
1824         if (dma->cmdi == HIFN_D_CMD_RSIZE) {
1825                 dma->cmdi = 0;
1826                 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1827                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1828                 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1829                     BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1830         }
1831         cmdi = dma->cmdi++;
1832         cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]);
1833         HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE);
1834
1835         /* .p for command/result already set */
1836         dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST |
1837             HIFN_D_MASKDONEIRQ);
1838         HIFN_CMDR_SYNC(sc, cmdi,
1839             BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1840         dma->cmdu++;
1841         if (sc->sc_c_busy == 0) {
1842                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1843                 sc->sc_c_busy = 1;
1844         }
1845
1846         /*
1847          * We don't worry about missing an interrupt (which a "command wait"
1848          * interrupt salvages us from), unless there is more than one command
1849          * in the queue.
1850          */
1851         if (dma->cmdu > 1) {
1852                 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT;
1853                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1854         }
1855
1856         hifnstats.hst_ipackets++;
1857         hifnstats.hst_ibytes += cmd->src_mapsize;
1858
1859         hifn_dmamap_load_src(sc, cmd);
1860         if (sc->sc_s_busy == 0) {
1861                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1862                 sc->sc_s_busy = 1;
1863         }
1864
1865         /*
1866          * Unlike other descriptors, we don't mask done interrupt from
1867          * result descriptor.
1868          */
1869 #ifdef HIFN_DEBUG
1870         if (hifn_debug)
1871                 printf("load res\n");
1872 #endif
1873         if (dma->resi == HIFN_D_RES_RSIZE) {
1874                 dma->resi = 0;
1875                 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1876                     HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1877                 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1878                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1879         }
1880         resi = dma->resi++;
1881         KASSERT(dma->hifn_commands[resi] == NULL,
1882                 ("hifn_crypto: command slot %u busy", resi));
1883         dma->hifn_commands[resi] = cmd;
1884         HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD);
1885         if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) {
1886                 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
1887                     HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
1888                 sc->sc_curbatch++;
1889                 if (sc->sc_curbatch > hifnstats.hst_maxbatch)
1890                         hifnstats.hst_maxbatch = sc->sc_curbatch;
1891                 hifnstats.hst_totbatch++;
1892         } else {
1893                 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
1894                     HIFN_D_VALID | HIFN_D_LAST);
1895                 sc->sc_curbatch = 0;
1896         }
1897         HIFN_RESR_SYNC(sc, resi,
1898             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1899         dma->resu++;
1900         if (sc->sc_r_busy == 0) {
1901                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
1902                 sc->sc_r_busy = 1;
1903         }
1904
1905         if (cmd->sloplen)
1906                 cmd->slopidx = resi;
1907
1908         hifn_dmamap_load_dst(sc, cmd);
1909
1910         if (sc->sc_d_busy == 0) {
1911                 WRITE_REG_1(sc, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
1912                 sc->sc_d_busy = 1;
1913         }
1914
1915 #ifdef HIFN_DEBUG
1916         if (hifn_debug) {
1917                 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n",
1918                     READ_REG_1(sc, HIFN_1_DMA_CSR),
1919                     READ_REG_1(sc, HIFN_1_DMA_IER));
1920         }
1921 #endif
1922
1923         sc->sc_active = 5;
1924         KASSERT(err == 0, ("hifn_crypto: success with error %u", err));
1925         return (err);           /* success */
1926
1927 err_dstmap:
1928         if (cmd->src_map != cmd->dst_map)
1929                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
1930 err_dstmap1:
1931         if (cmd->src_map != cmd->dst_map)
1932                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
1933 err_srcmap:
1934         if (crp->crp_flags & CRYPTO_F_IMBUF) {
1935                 if (cmd->src_m != cmd->dst_m)
1936                         m_freem(cmd->dst_m);
1937         }
1938         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
1939 err_srcmap1:
1940         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
1941         return (err);
1942 }
1943
1944 static void
1945 hifn_tick(void* vsc)
1946 {
1947         struct hifn_softc *sc = vsc;
1948         int s;
1949
1950         s = splimp();
1951         if (sc->sc_active == 0) {
1952                 struct hifn_dma *dma = sc->sc_dma;
1953                 u_int32_t r = 0;
1954
1955                 if (dma->cmdu == 0 && sc->sc_c_busy) {
1956                         sc->sc_c_busy = 0;
1957                         r |= HIFN_DMACSR_C_CTRL_DIS;
1958                 }
1959                 if (dma->srcu == 0 && sc->sc_s_busy) {
1960                         sc->sc_s_busy = 0;
1961                         r |= HIFN_DMACSR_S_CTRL_DIS;
1962                 }
1963                 if (dma->dstu == 0 && sc->sc_d_busy) {
1964                         sc->sc_d_busy = 0;
1965                         r |= HIFN_DMACSR_D_CTRL_DIS;
1966                 }
1967                 if (dma->resu == 0 && sc->sc_r_busy) {
1968                         sc->sc_r_busy = 0;
1969                         r |= HIFN_DMACSR_R_CTRL_DIS;
1970                 }
1971                 if (r)
1972                         WRITE_REG_1(sc, HIFN_1_DMA_CSR, r);
1973         } else
1974                 sc->sc_active--;
1975         splx(s);
1976         callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
1977 }
1978
1979 static void
1980 hifn_intr(void *arg)
1981 {
1982         struct hifn_softc *sc = arg;
1983         struct hifn_dma *dma;
1984         u_int32_t dmacsr, restart;
1985         int i, u;
1986
1987         dma = sc->sc_dma;
1988
1989         dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR);
1990
1991 #ifdef HIFN_DEBUG
1992         if (hifn_debug) {
1993                 device_printf(sc->sc_dev,
1994                     "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n",
1995                     dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier,
1996                     dma->cmdi, dma->srci, dma->dsti, dma->resi,
1997                     dma->cmdk, dma->srck, dma->dstk, dma->resk,
1998                     dma->cmdu, dma->srcu, dma->dstu, dma->resu);
1999         }
2000 #endif
2001
2002         /* Nothing in the DMA unit interrupted */
2003         if ((dmacsr & sc->sc_dmaier) == 0) {
2004                 hifnstats.hst_noirq++;
2005                 return;
2006         }
2007
2008         WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier);
2009
2010         if ((sc->sc_flags & HIFN_HAS_PUBLIC) &&
2011             (dmacsr & HIFN_DMACSR_PUBDONE))
2012                 WRITE_REG_1(sc, HIFN_1_PUB_STATUS,
2013                     READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
2014
2015         restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER);
2016         if (restart)
2017                 device_printf(sc->sc_dev, "overrun %x\n", dmacsr);
2018
2019         if (sc->sc_flags & HIFN_IS_7811) {
2020                 if (dmacsr & HIFN_DMACSR_ILLR)
2021                         device_printf(sc->sc_dev, "illegal read\n");
2022                 if (dmacsr & HIFN_DMACSR_ILLW)
2023                         device_printf(sc->sc_dev, "illegal write\n");
2024         }
2025
2026         restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
2027             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
2028         if (restart) {
2029                 device_printf(sc->sc_dev, "abort, resetting.\n");
2030                 hifnstats.hst_abort++;
2031                 hifn_abort(sc);
2032                 return;
2033         }
2034
2035         if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
2036                 /*
2037                  * If no slots to process and we receive a "waiting on
2038                  * command" interrupt, we disable the "waiting on command"
2039                  * (by clearing it).
2040                  */
2041                 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
2042                 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2043         }
2044
2045         /* clear the rings */
2046         i = dma->resk; u = dma->resu;
2047         while (u != 0) {
2048                 HIFN_RESR_SYNC(sc, i,
2049                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2050                 if (dma->resr[i].l & htole32(HIFN_D_VALID)) {
2051                         HIFN_RESR_SYNC(sc, i,
2052                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2053                         break;
2054                 }
2055
2056                 if (i != HIFN_D_RES_RSIZE) {
2057                         struct hifn_command *cmd;
2058                         u_int8_t *macbuf = NULL;
2059
2060                         HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD);
2061                         cmd = dma->hifn_commands[i];
2062                         KASSERT(cmd != NULL,
2063                                 ("hifn_intr: null command slot %u", i));
2064                         dma->hifn_commands[i] = NULL;
2065
2066                         if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2067                                 macbuf = dma->result_bufs[i];
2068                                 macbuf += 12;
2069                         }
2070
2071                         hifn_callback(sc, cmd, macbuf);
2072                         hifnstats.hst_opackets++;
2073                         u--;
2074                 }
2075
2076                 if (++i == (HIFN_D_RES_RSIZE + 1))
2077                         i = 0;
2078         }
2079         dma->resk = i; dma->resu = u;
2080
2081         i = dma->srck; u = dma->srcu;
2082         while (u != 0) {
2083                 if (i == HIFN_D_SRC_RSIZE)
2084                         i = 0;
2085                 HIFN_SRCR_SYNC(sc, i,
2086                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2087                 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) {
2088                         HIFN_SRCR_SYNC(sc, i,
2089                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2090                         break;
2091                 }
2092                 i++, u--;
2093         }
2094         dma->srck = i; dma->srcu = u;
2095
2096         i = dma->cmdk; u = dma->cmdu;
2097         while (u != 0) {
2098                 HIFN_CMDR_SYNC(sc, i,
2099                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2100                 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) {
2101                         HIFN_CMDR_SYNC(sc, i,
2102                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2103                         break;
2104                 }
2105                 if (i != HIFN_D_CMD_RSIZE) {
2106                         u--;
2107                         HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE);
2108                 }
2109                 if (++i == (HIFN_D_CMD_RSIZE + 1))
2110                         i = 0;
2111         }
2112         dma->cmdk = i; dma->cmdu = u;
2113
2114         if (sc->sc_needwakeup) {                /* XXX check high watermark */
2115                 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
2116 #ifdef HIFN_DEBUG
2117                 if (hifn_debug)
2118                         device_printf(sc->sc_dev,
2119                                 "wakeup crypto (%x) u %d/%d/%d/%d\n",
2120                                 sc->sc_needwakeup,
2121                                 dma->cmdu, dma->srcu, dma->dstu, dma->resu);
2122 #endif
2123                 sc->sc_needwakeup &= ~wakeup;
2124                 crypto_unblock(sc->sc_cid, wakeup);
2125         }
2126 }
2127
2128 /*
2129  * Allocate a new 'session' and return an encoded session id.  'sidp'
2130  * contains our registration id, and should contain an encoded session
2131  * id on successful allocation.
2132  */
2133 static int
2134 hifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
2135 {
2136         struct cryptoini *c;
2137         struct hifn_softc *sc = arg;
2138         int i, mac = 0, cry = 0;
2139
2140         KASSERT(sc != NULL, ("hifn_newsession: null softc"));
2141         if (sidp == NULL || cri == NULL || sc == NULL)
2142                 return (EINVAL);
2143
2144         for (i = 0; i < sc->sc_maxses; i++)
2145                 if (sc->sc_sessions[i].hs_state == HS_STATE_FREE)
2146                         break;
2147         if (i == sc->sc_maxses)
2148                 return (ENOMEM);
2149
2150         for (c = cri; c != NULL; c = c->cri_next) {
2151                 switch (c->cri_alg) {
2152                 case CRYPTO_MD5:
2153                 case CRYPTO_SHA1:
2154                 case CRYPTO_MD5_HMAC:
2155                 case CRYPTO_SHA1_HMAC:
2156                         if (mac)
2157                                 return (EINVAL);
2158                         mac = 1;
2159                         break;
2160                 case CRYPTO_DES_CBC:
2161                 case CRYPTO_3DES_CBC:
2162                         /* XXX this may read fewer, does it matter? */
2163                         read_random(sc->sc_sessions[i].hs_iv, HIFN_IV_LENGTH);
2164                         /*FALLTHROUGH*/
2165                 case CRYPTO_ARC4:
2166                         if (cry)
2167                                 return (EINVAL);
2168                         cry = 1;
2169                         break;
2170                 default:
2171                         return (EINVAL);
2172                 }
2173         }
2174         if (mac == 0 && cry == 0)
2175                 return (EINVAL);
2176
2177         *sidp = HIFN_SID(device_get_unit(sc->sc_dev), i);
2178         sc->sc_sessions[i].hs_state = HS_STATE_USED;
2179
2180         return (0);
2181 }
2182
2183 /*
2184  * Deallocate a session.
2185  * XXX this routine should run a zero'd mac/encrypt key into context ram.
2186  * XXX to blow away any keys already stored there.
2187  */
2188 static int
2189 hifn_freesession(void *arg, u_int64_t tid)
2190 {
2191         struct hifn_softc *sc = arg;
2192         int session;
2193         u_int32_t sid = ((u_int32_t) tid) & 0xffffffff;
2194
2195         KASSERT(sc != NULL, ("hifn_freesession: null softc"));
2196         if (sc == NULL)
2197                 return (EINVAL);
2198
2199         session = HIFN_SESSION(sid);
2200         if (session >= sc->sc_maxses)
2201                 return (EINVAL);
2202
2203         bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
2204         return (0);
2205 }
2206
2207 static int
2208 hifn_process(void *arg, struct cryptop *crp, int hint)
2209 {
2210         struct hifn_softc *sc = arg;
2211         struct hifn_command *cmd = NULL;
2212         int session, err;
2213         struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
2214
2215         if (crp == NULL || crp->crp_callback == NULL) {
2216                 hifnstats.hst_invalid++;
2217                 return (EINVAL);
2218         }
2219         session = HIFN_SESSION(crp->crp_sid);
2220
2221         if (sc == NULL || session >= sc->sc_maxses) {
2222                 err = EINVAL;
2223                 goto errout;
2224         }
2225
2226         cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO);
2227         if (cmd == NULL) {
2228                 hifnstats.hst_nomem++;
2229                 err = ENOMEM;
2230                 goto errout;
2231         }
2232
2233         if (crp->crp_flags & CRYPTO_F_IMBUF) {
2234                 cmd->src_m = (struct mbuf *)crp->crp_buf;
2235                 cmd->dst_m = (struct mbuf *)crp->crp_buf;
2236         } else if (crp->crp_flags & CRYPTO_F_IOV) {
2237                 cmd->src_io = (struct uio *)crp->crp_buf;
2238                 cmd->dst_io = (struct uio *)crp->crp_buf;
2239         } else {
2240                 err = EINVAL;
2241                 goto errout;    /* XXX we don't handle contiguous buffers! */
2242         }
2243
2244         crd1 = crp->crp_desc;
2245         if (crd1 == NULL) {
2246                 err = EINVAL;
2247                 goto errout;
2248         }
2249         crd2 = crd1->crd_next;
2250
2251         if (crd2 == NULL) {
2252                 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
2253                     crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2254                     crd1->crd_alg == CRYPTO_SHA1 ||
2255                     crd1->crd_alg == CRYPTO_MD5) {
2256                         maccrd = crd1;
2257                         enccrd = NULL;
2258                 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
2259                     crd1->crd_alg == CRYPTO_3DES_CBC ||
2260                     crd1->crd_alg == CRYPTO_ARC4) {
2261                         if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0)
2262                                 cmd->base_masks |= HIFN_BASE_CMD_DECODE;
2263                         maccrd = NULL;
2264                         enccrd = crd1;
2265                 } else {
2266                         err = EINVAL;
2267                         goto errout;
2268                 }
2269         } else {
2270                 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
2271                      crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2272                      crd1->crd_alg == CRYPTO_MD5 ||
2273                      crd1->crd_alg == CRYPTO_SHA1) &&
2274                     (crd2->crd_alg == CRYPTO_DES_CBC ||
2275                      crd2->crd_alg == CRYPTO_3DES_CBC ||
2276                      crd2->crd_alg == CRYPTO_ARC4) &&
2277                     ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
2278                         cmd->base_masks = HIFN_BASE_CMD_DECODE;
2279                         maccrd = crd1;
2280                         enccrd = crd2;
2281                 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
2282                      crd1->crd_alg == CRYPTO_ARC4 ||
2283                      crd1->crd_alg == CRYPTO_3DES_CBC) &&
2284                     (crd2->crd_alg == CRYPTO_MD5_HMAC ||
2285                      crd2->crd_alg == CRYPTO_SHA1_HMAC ||
2286                      crd2->crd_alg == CRYPTO_MD5 ||
2287                      crd2->crd_alg == CRYPTO_SHA1) &&
2288                     (crd1->crd_flags & CRD_F_ENCRYPT)) {
2289                         enccrd = crd1;
2290                         maccrd = crd2;
2291                 } else {
2292                         /*
2293                          * We cannot order the 7751 as requested
2294                          */
2295                         err = EINVAL;
2296                         goto errout;
2297                 }
2298         }
2299
2300         if (enccrd) {
2301                 cmd->enccrd = enccrd;
2302                 cmd->base_masks |= HIFN_BASE_CMD_CRYPT;
2303                 switch (enccrd->crd_alg) {
2304                 case CRYPTO_ARC4:
2305                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4;
2306                         if ((enccrd->crd_flags & CRD_F_ENCRYPT)
2307                             != sc->sc_sessions[session].hs_prev_op)
2308                                 sc->sc_sessions[session].hs_state =
2309                                     HS_STATE_USED;
2310                         break;
2311                 case CRYPTO_DES_CBC:
2312                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES |
2313                             HIFN_CRYPT_CMD_MODE_CBC |
2314                             HIFN_CRYPT_CMD_NEW_IV;
2315                         break;
2316                 case CRYPTO_3DES_CBC:
2317                         cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES |
2318                             HIFN_CRYPT_CMD_MODE_CBC |
2319                             HIFN_CRYPT_CMD_NEW_IV;
2320                         break;
2321                 default:
2322                         err = EINVAL;
2323                         goto errout;
2324                 }
2325                 if (enccrd->crd_alg != CRYPTO_ARC4) {
2326                         if (enccrd->crd_flags & CRD_F_ENCRYPT) {
2327                                 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2328                                         bcopy(enccrd->crd_iv, cmd->iv,
2329                                             HIFN_IV_LENGTH);
2330                                 else
2331                                         bcopy(sc->sc_sessions[session].hs_iv,
2332                                             cmd->iv, HIFN_IV_LENGTH);
2333
2334                                 if ((enccrd->crd_flags & CRD_F_IV_PRESENT)
2335                                     == 0) {
2336                                         if (crp->crp_flags & CRYPTO_F_IMBUF)
2337                                                 m_copyback(cmd->src_m,
2338                                                     enccrd->crd_inject,
2339                                                     HIFN_IV_LENGTH, cmd->iv);
2340                                         else if (crp->crp_flags & CRYPTO_F_IOV)
2341                                                 cuio_copyback(cmd->src_io,
2342                                                     enccrd->crd_inject,
2343                                                     HIFN_IV_LENGTH, cmd->iv);
2344                                 }
2345                         } else {
2346                                 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2347                                         bcopy(enccrd->crd_iv, cmd->iv,
2348                                             HIFN_IV_LENGTH);
2349                                 else if (crp->crp_flags & CRYPTO_F_IMBUF)
2350                                         m_copydata(cmd->src_m,
2351                                             enccrd->crd_inject,
2352                                             HIFN_IV_LENGTH, cmd->iv);
2353                                 else if (crp->crp_flags & CRYPTO_F_IOV)
2354                                         cuio_copydata(cmd->src_io,
2355                                             enccrd->crd_inject,
2356                                             HIFN_IV_LENGTH, cmd->iv);
2357                         }
2358                 }
2359
2360                 cmd->ck = enccrd->crd_key;
2361                 cmd->cklen = enccrd->crd_klen >> 3;
2362
2363                 if (sc->sc_sessions[session].hs_state == HS_STATE_USED)
2364                         cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2365         }
2366
2367         if (maccrd) {
2368                 cmd->maccrd = maccrd;
2369                 cmd->base_masks |= HIFN_BASE_CMD_MAC;
2370
2371                 switch (maccrd->crd_alg) {
2372                 case CRYPTO_MD5:
2373                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2374                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2375                             HIFN_MAC_CMD_POS_IPSEC;
2376                        break;
2377                 case CRYPTO_MD5_HMAC:
2378                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2379                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2380                             HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2381                         break;
2382                 case CRYPTO_SHA1:
2383                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2384                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2385                             HIFN_MAC_CMD_POS_IPSEC;
2386                         break;
2387                 case CRYPTO_SHA1_HMAC:
2388                         cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2389                             HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2390                             HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2391                         break;
2392                 }
2393
2394                 if ((maccrd->crd_alg == CRYPTO_SHA1_HMAC ||
2395                      maccrd->crd_alg == CRYPTO_MD5_HMAC) &&
2396                     sc->sc_sessions[session].hs_state == HS_STATE_USED) {
2397                         cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY;
2398                         bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3);
2399                         bzero(cmd->mac + (maccrd->crd_klen >> 3),
2400                             HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3));
2401                 }
2402         }
2403
2404         cmd->crp = crp;
2405         cmd->session_num = session;
2406         cmd->softc = sc;
2407
2408         err = hifn_crypto(sc, cmd, crp, hint);
2409         if (!err) {
2410                 if (enccrd)
2411                         sc->sc_sessions[session].hs_prev_op =
2412                                 enccrd->crd_flags & CRD_F_ENCRYPT;
2413                 if (sc->sc_sessions[session].hs_state == HS_STATE_USED)
2414                         sc->sc_sessions[session].hs_state = HS_STATE_KEY;
2415                 return 0;
2416         } else if (err == ERESTART) {
2417                 /*
2418                  * There weren't enough resources to dispatch the request
2419                  * to the part.  Notify the caller so they'll requeue this
2420                  * request and resubmit it again soon.
2421                  */
2422 #ifdef HIFN_DEBUG
2423                 if (hifn_debug)
2424                         device_printf(sc->sc_dev, "requeue request\n");
2425 #endif
2426                 free(cmd, M_DEVBUF);
2427                 sc->sc_needwakeup |= CRYPTO_SYMQ;
2428                 return (err);
2429         }
2430
2431 errout:
2432         if (cmd != NULL)
2433                 free(cmd, M_DEVBUF);
2434         if (err == EINVAL)
2435                 hifnstats.hst_invalid++;
2436         else
2437                 hifnstats.hst_nomem++;
2438         crp->crp_etype = err;
2439         crypto_done(crp);
2440         return (err);
2441 }
2442
2443 static void
2444 hifn_abort(struct hifn_softc *sc)
2445 {
2446         struct hifn_dma *dma = sc->sc_dma;
2447         struct hifn_command *cmd;
2448         struct cryptop *crp;
2449         int i, u;
2450
2451         i = dma->resk; u = dma->resu;
2452         while (u != 0) {
2453                 cmd = dma->hifn_commands[i];
2454                 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i));
2455                 dma->hifn_commands[i] = NULL;
2456                 crp = cmd->crp;
2457
2458                 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) {
2459                         /* Salvage what we can. */
2460                         u_int8_t *macbuf;
2461
2462                         if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2463                                 macbuf = dma->result_bufs[i];
2464                                 macbuf += 12;
2465                         } else
2466                                 macbuf = NULL;
2467                         hifnstats.hst_opackets++;
2468                         hifn_callback(sc, cmd, macbuf);
2469                 } else {
2470                         if (cmd->src_map == cmd->dst_map) {
2471                                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2472                                     BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2473                         } else {
2474                                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2475                                     BUS_DMASYNC_POSTWRITE);
2476                                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2477                                     BUS_DMASYNC_POSTREAD);
2478                         }
2479
2480                         if (cmd->src_m != cmd->dst_m) {
2481                                 m_freem(cmd->src_m);
2482                                 crp->crp_buf = (caddr_t)cmd->dst_m;
2483                         }
2484
2485                         /* non-shared buffers cannot be restarted */
2486                         if (cmd->src_map != cmd->dst_map) {
2487                                 /*
2488                                  * XXX should be EAGAIN, delayed until
2489                                  * after the reset.
2490                                  */
2491                                 crp->crp_etype = ENOMEM;
2492                                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2493                                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2494                         } else
2495                                 crp->crp_etype = ENOMEM;
2496
2497                         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2498                         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2499
2500                         free(cmd, M_DEVBUF);
2501                         if (crp->crp_etype != EAGAIN)
2502                                 crypto_done(crp);
2503                 }
2504
2505                 if (++i == HIFN_D_RES_RSIZE)
2506                         i = 0;
2507                 u--;
2508         }
2509         dma->resk = i; dma->resu = u;
2510
2511         /* Force upload of key next time */
2512         for (i = 0; i < sc->sc_maxses; i++)
2513                 if (sc->sc_sessions[i].hs_state == HS_STATE_KEY)
2514                         sc->sc_sessions[i].hs_state = HS_STATE_USED;
2515
2516         hifn_reset_board(sc, 1);
2517         hifn_init_dma(sc);
2518         hifn_init_pci_registers(sc);
2519 }
2520
2521 static void
2522 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf)
2523 {
2524         struct hifn_dma *dma = sc->sc_dma;
2525         struct cryptop *crp = cmd->crp;
2526         struct cryptodesc *crd;
2527         struct mbuf *m;
2528         int totlen, i, u;
2529
2530         if (cmd->src_map == cmd->dst_map) {
2531                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2532                     BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2533         } else {
2534                 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2535                     BUS_DMASYNC_POSTWRITE);
2536                 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2537                     BUS_DMASYNC_POSTREAD);
2538         }
2539
2540         if (crp->crp_flags & CRYPTO_F_IMBUF) {
2541                 if (cmd->src_m != cmd->dst_m) {
2542                         crp->crp_buf = (caddr_t)cmd->dst_m;
2543                         totlen = cmd->src_mapsize;
2544                         for (m = cmd->dst_m; m != NULL; m = m->m_next) {
2545                                 if (totlen < m->m_len) {
2546                                         m->m_len = totlen;
2547                                         totlen = 0;
2548                                 } else
2549                                         totlen -= m->m_len;
2550                         }
2551                         cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len;
2552                         m_freem(cmd->src_m);
2553                 }
2554         }
2555
2556         if (cmd->sloplen != 0) {
2557                 if (crp->crp_flags & CRYPTO_F_IMBUF)
2558                         m_copyback((struct mbuf *)crp->crp_buf,
2559                             cmd->src_mapsize - cmd->sloplen,
2560                             cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]);
2561                 else if (crp->crp_flags & CRYPTO_F_IOV)
2562                         cuio_copyback((struct uio *)crp->crp_buf,
2563                             cmd->src_mapsize - cmd->sloplen,
2564                             cmd->sloplen, (caddr_t)&dma->slop[cmd->slopidx]);
2565         }
2566
2567         i = dma->dstk; u = dma->dstu;
2568         while (u != 0) {
2569                 if (i == HIFN_D_DST_RSIZE)
2570                         i = 0;
2571                 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2572                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2573                 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) {
2574                         bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2575                             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2576                         break;
2577                 }
2578                 i++, u--;
2579         }
2580         dma->dstk = i; dma->dstu = u;
2581
2582         hifnstats.hst_obytes += cmd->dst_mapsize;
2583
2584         if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) ==
2585             HIFN_BASE_CMD_CRYPT) {
2586                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2587                         if (crd->crd_alg != CRYPTO_DES_CBC &&
2588                             crd->crd_alg != CRYPTO_3DES_CBC)
2589                                 continue;
2590                         if (crp->crp_flags & CRYPTO_F_IMBUF)
2591                                 m_copydata((struct mbuf *)crp->crp_buf,
2592                                     crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH,
2593                                     HIFN_IV_LENGTH,
2594                                     cmd->softc->sc_sessions[cmd->session_num].hs_iv);
2595                         else if (crp->crp_flags & CRYPTO_F_IOV) {
2596                                 cuio_copydata((struct uio *)crp->crp_buf,
2597                                     crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH,
2598                                     HIFN_IV_LENGTH,
2599                                     cmd->softc->sc_sessions[cmd->session_num].hs_iv);
2600                         }
2601                         break;
2602                 }
2603         }
2604
2605         if (macbuf != NULL) {
2606                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2607                         int len;
2608
2609                         if (crd->crd_alg == CRYPTO_MD5)
2610                                 len = 16;
2611                         else if (crd->crd_alg == CRYPTO_SHA1)
2612                                 len = 20;
2613                         else if (crd->crd_alg == CRYPTO_MD5_HMAC ||
2614                             crd->crd_alg == CRYPTO_SHA1_HMAC)
2615                                 len = 12;
2616                         else
2617                                 continue;
2618
2619                         if (crp->crp_flags & CRYPTO_F_IMBUF)
2620                                 m_copyback((struct mbuf *)crp->crp_buf,
2621                                    crd->crd_inject, len, macbuf);
2622                         else if ((crp->crp_flags & CRYPTO_F_IOV) && crp->crp_mac)
2623                                 bcopy((caddr_t)macbuf, crp->crp_mac, len);
2624                         break;
2625                 }
2626         }
2627
2628         if (cmd->src_map != cmd->dst_map) {
2629                 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2630                 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2631         }
2632         bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2633         bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2634         free(cmd, M_DEVBUF);
2635         crypto_done(crp);
2636 }
2637
2638 /*
2639  * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0
2640  * and Group 1 registers; avoid conditions that could create
2641  * burst writes by doing a read in between the writes.
2642  *
2643  * NB: The read we interpose is always to the same register;
2644  *     we do this because reading from an arbitrary (e.g. last)
2645  *     register may not always work.
2646  */
2647 static void
2648 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2649 {
2650         if (sc->sc_flags & HIFN_IS_7811) {
2651                 if (sc->sc_bar0_lastreg == reg - 4)
2652                         bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG);
2653                 sc->sc_bar0_lastreg = reg;
2654         }
2655         bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val);
2656 }
2657
2658 static void
2659 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2660 {
2661         if (sc->sc_flags & HIFN_IS_7811) {
2662                 if (sc->sc_bar1_lastreg == reg - 4)
2663                         bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID);
2664                 sc->sc_bar1_lastreg = reg;
2665         }
2666         bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);
2667 }