sys/dev/disk/advansys/adwcam.c

   1 /*
   2  * CAM SCSI interface for the the Advanced Systems Inc.
   3  * Second Generation SCSI controllers.
   4  *
   5  * Product specific probe and attach routines can be found in:
   6  *
   7  * adw_pci.c    ABP[3]940UW, ABP950UW, ABP3940U2W
   8  *
   9  * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
  10  * All rights reserved.
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions, and the following disclaimer,
  17  *    without modification.
  18  * 2. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  25  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/advansys/adwcam.c,v 1.7.2.2 2001/03/05 13:08:55 obrien Exp $
  34  * $DragonFly: src/sys/dev/disk/advansys/adwcam.c,v 1.2 2003/06/17 04:28:21 dillon Exp $
  35  */
  36 /*
  37  * Ported from:
  38  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
  39  *
  40  * Copyright (c) 1995-1998 Advanced System Products, Inc.
  41  * All Rights Reserved.
  42  *
  43  * Redistribution and use in source and binary forms, with or without
  44  * modification, are permitted provided that redistributions of source
  45  * code retain the above copyright notice and this comment without
  46  * modification.
  47  */
  48
  49 #include <sys/param.h>
  50 #include <sys/systm.h>
  51 #include <sys/kernel.h>
  52 #include <sys/malloc.h>
  53 #include <sys/bus.h>
  54
  55 #include <machine/bus_pio.h>
  56 #include <machine/bus_memio.h>
  57 #include <machine/bus.h>
  58 #include <machine/clock.h>
  59 #include <machine/resource.h>
  60
  61 #include <sys/rman.h>
  62
  63 #include <cam/cam.h>
  64 #include <cam/cam_ccb.h>
  65 #include <cam/cam_sim.h>
  66 #include <cam/cam_xpt_sim.h>
  67 #include <cam/cam_debug.h>
  68
  69 #include <cam/scsi/scsi_message.h>
  70
  71 #include <dev/advansys/adwvar.h>
  72
  73 /* Definitions for our use of the SIM private CCB area */
  74 #define ccb_acb_ptr spriv_ptr0
  75 #define ccb_adw_ptr spriv_ptr1
  76
  77 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
  78
  79 u_long adw_unit;
  80
  81 static __inline cam_status      adwccbstatus(union ccb*);
  82 static __inline struct acb*     adwgetacb(struct adw_softc *adw);
  83 static __inline void            adwfreeacb(struct adw_softc *adw,
  84                                            struct acb *acb);
  85
  86 static void             adwmapmem(void *arg, bus_dma_segment_t *segs,
  87                                   int nseg, int error);
  88 static struct sg_map_node*
  89                         adwallocsgmap(struct adw_softc *adw);
  90 static int              adwallocacbs(struct adw_softc *adw);
  91
  92 static void             adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs,
  93                                       int nseg, int error);
  94 static void             adw_action(struct cam_sim *sim, union ccb *ccb);
  95 static void             adw_poll(struct cam_sim *sim);
  96 static void             adw_async(void *callback_arg, u_int32_t code,
  97                                   struct cam_path *path, void *arg);
  98 static void             adwprocesserror(struct adw_softc *adw, struct acb *acb);
  99 static void             adwtimeout(void *arg);
 100 static void             adw_handle_device_reset(struct adw_softc *adw,
 101                                                 u_int target);
 102 static void             adw_handle_bus_reset(struct adw_softc *adw,
 103                                              int initiated);
 104
 105 static __inline cam_status
 106 adwccbstatus(union ccb* ccb)
 107 {
 108         return (ccb->ccb_h.status & CAM_STATUS_MASK);
 109 }
 110
 111 static __inline struct acb*
 112 adwgetacb(struct adw_softc *adw)
 113 {
 114         struct  acb* acb;
 115         int     s;
 116
 117         s = splcam();
 118         if ((acb = SLIST_FIRST(&adw->free_acb_list)) != NULL) {
 119                 SLIST_REMOVE_HEAD(&adw->free_acb_list, links);
 120         } else if (adw->num_acbs < adw->max_acbs) {
 121                 adwallocacbs(adw);
 122                 acb = SLIST_FIRST(&adw->free_acb_list);
 123                 if (acb == NULL)
 124                         printf("%s: Can't malloc ACB\n", adw_name(adw));
 125                 else {
 126                         SLIST_REMOVE_HEAD(&adw->free_acb_list, links);
 127                 }
 128         }
 129         splx(s);
 130
 131         return (acb);
 132 }
 133
 134 static __inline void
 135 adwfreeacb(struct adw_softc *adw, struct acb *acb)
 136 {
 137         int s;
 138
 139         s = splcam();
 140         if ((acb->state & ACB_ACTIVE) != 0)
 141                 LIST_REMOVE(&acb->ccb->ccb_h, sim_links.le);
 142         if ((acb->state & ACB_RELEASE_SIMQ) != 0)
 143                 acb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 144         else if ((adw->state & ADW_RESOURCE_SHORTAGE) != 0
 145               && (acb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) {
 146                 acb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 147                 adw->state &= ~ADW_RESOURCE_SHORTAGE;
 148         }
 149         acb->state = ACB_FREE;
 150         SLIST_INSERT_HEAD(&adw->free_acb_list, acb, links);
 151         splx(s);
 152 }
 153
 154 static void
 155 adwmapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 156 {
 157         bus_addr_t *busaddrp;
 158
 159         busaddrp = (bus_addr_t *)arg;
 160         *busaddrp = segs->ds_addr;
 161 }
 162
 163 static struct sg_map_node *
 164 adwallocsgmap(struct adw_softc *adw)
 165 {
 166         struct sg_map_node *sg_map;
 167
 168         sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
 169
 170         if (sg_map == NULL)
 171                 return (NULL);
 172
 173         /* Allocate S/G space for the next batch of ACBS */
 174         if (bus_dmamem_alloc(adw->sg_dmat, (void **)&sg_map->sg_vaddr,
 175                              BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
 176                 free(sg_map, M_DEVBUF);
 177                 return (NULL);
 178         }
 179
 180         SLIST_INSERT_HEAD(&adw->sg_maps, sg_map, links);
 181
 182         bus_dmamap_load(adw->sg_dmat, sg_map->sg_dmamap, sg_map->sg_vaddr,
 183                         PAGE_SIZE, adwmapmem, &sg_map->sg_physaddr, /*flags*/0);
 184
 185         bzero(sg_map->sg_vaddr, PAGE_SIZE);
 186         return (sg_map);
 187 }
 188
 189 /*
 190  * Allocate another chunk of CCB's. Return count of entries added.
 191  * Assumed to be called at splcam().
 192  */
 193 static int
 194 adwallocacbs(struct adw_softc *adw)
 195 {
 196         struct acb *next_acb;
 197         struct sg_map_node *sg_map;
 198         bus_addr_t busaddr;
 199         struct adw_sg_block *blocks;
 200         int newcount;
 201         int i;
 202
 203         next_acb = &adw->acbs[adw->num_acbs];
 204         sg_map = adwallocsgmap(adw);
 205
 206         if (sg_map == NULL)
 207                 return (0);
 208
 209         blocks = sg_map->sg_vaddr;
 210         busaddr = sg_map->sg_physaddr;
 211
 212         newcount = (PAGE_SIZE / (ADW_SG_BLOCKCNT * sizeof(*blocks)));
 213         for (i = 0; adw->num_acbs < adw->max_acbs && i < newcount; i++) {
 214                 int error;
 215
 216                 error = bus_dmamap_create(adw->buffer_dmat, /*flags*/0,
 217                                           &next_acb->dmamap);
 218                 if (error != 0)
 219                         break;
 220                 next_acb->queue.scsi_req_baddr = acbvtob(adw, next_acb);
 221                 next_acb->queue.scsi_req_bo = acbvtobo(adw, next_acb);
 222                 next_acb->queue.sense_baddr =
 223                     acbvtob(adw, next_acb) + offsetof(struct acb, sense_data);
 224                 next_acb->sg_blocks = blocks;
 225                 next_acb->sg_busaddr = busaddr;
 226                 next_acb->state = ACB_FREE;
 227                 SLIST_INSERT_HEAD(&adw->free_acb_list, next_acb, links);
 228                 blocks += ADW_SG_BLOCKCNT;
 229                 busaddr += ADW_SG_BLOCKCNT * sizeof(*blocks);
 230                 next_acb++;
 231                 adw->num_acbs++;
 232         }
 233         return (i);
 234 }
 235
 236 static void
 237 adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
 238 {
 239         struct   acb *acb;
 240         union    ccb *ccb;
 241         struct   adw_softc *adw;
 242         int      s;
 243
 244         acb = (struct acb *)arg;
 245         ccb = acb->ccb;
 246         adw = (struct adw_softc *)ccb->ccb_h.ccb_adw_ptr;
 247
 248         if (error != 0) {
 249                 if (error != EFBIG)
 250                         printf("%s: Unexepected error 0x%x returned from "
 251                                "bus_dmamap_load\n", adw_name(adw), error);
 252                 if (ccb->ccb_h.status == CAM_REQ_INPROG) {
 253                         xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
 254                         ccb->ccb_h.status = CAM_REQ_TOO_BIG|CAM_DEV_QFRZN;
 255                 }
 256                 adwfreeacb(adw, acb);
 257                 xpt_done(ccb);
 258                 return;
 259         }
 260
 261         if (nseg != 0) {
 262                 bus_dmasync_op_t op;
 263
 264                 acb->queue.data_addr = dm_segs[0].ds_addr;
 265                 acb->queue.data_cnt = ccb->csio.dxfer_len;
 266                 if (nseg > 1) {
 267                         struct adw_sg_block *sg_block;
 268                         struct adw_sg_elm *sg;
 269                         bus_addr_t sg_busaddr;
 270                         u_int sg_index;
 271                         bus_dma_segment_t *end_seg;
 272
 273                         end_seg = dm_segs + nseg;
 274
 275                         sg_busaddr = acb->sg_busaddr;
 276                         sg_index = 0;
 277                         /* Copy the segments into our SG list */
 278                         for (sg_block = acb->sg_blocks;; sg_block++) {
 279                                 u_int i;
 280
 281                                 sg = sg_block->sg_list;
 282                                 for (i = 0; i < ADW_NO_OF_SG_PER_BLOCK; i++) {
 283                                         if (dm_segs >= end_seg)
 284                                                 break;
 285
 286                                         sg->sg_addr = dm_segs->ds_addr;
 287                                         sg->sg_count = dm_segs->ds_len;
 288                                         sg++;
 289                                         dm_segs++;
 290                                 }
 291                                 sg_block->sg_cnt = i;
 292                                 sg_index += i;
 293                                 if (dm_segs == end_seg) {
 294                                         sg_block->sg_busaddr_next = 0;
 295                                         break;
 296                                 } else {
 297                                         sg_busaddr +=
 298                                             sizeof(struct adw_sg_block);
 299                                         sg_block->sg_busaddr_next = sg_busaddr;
 300                                 }
 301                         }
 302                         acb->queue.sg_real_addr = acb->sg_busaddr;
 303                 } else {
 304                         acb->queue.sg_real_addr = 0;
 305                 }
 306
 307                 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
 308                         op = BUS_DMASYNC_PREREAD;
 309                 else
 310                         op = BUS_DMASYNC_PREWRITE;
 311
 312                 bus_dmamap_sync(adw->buffer_dmat, acb->dmamap, op);
 313
 314         } else {
 315                 acb->queue.data_addr = 0;
 316                 acb->queue.data_cnt = 0;
 317                 acb->queue.sg_real_addr = 0;
 318         }
 319
 320         s = splcam();
 321
 322         /*
 323          * Last time we need to check if this CCB needs to
 324          * be aborted.
 325          */
 326         if (ccb->ccb_h.status != CAM_REQ_INPROG) {
 327                 if (nseg != 0)
 328                         bus_dmamap_unload(adw->buffer_dmat, acb->dmamap);
 329                 adwfreeacb(adw, acb);
 330                 xpt_done(ccb);
 331                 splx(s);
 332                 return;
 333         }
 334
 335         acb->state |= ACB_ACTIVE;
 336         ccb->ccb_h.status |= CAM_SIM_QUEUED;
 337         LIST_INSERT_HEAD(&adw->pending_ccbs, &ccb->ccb_h, sim_links.le);
 338         ccb->ccb_h.timeout_ch =
 339             timeout(adwtimeout, (caddr_t)acb,
 340                     (ccb->ccb_h.timeout * hz) / 1000);
 341
 342         adw_send_acb(adw, acb, acbvtob(adw, acb));
 343
 344         splx(s);
 345 }
 346
 347 static void
 348 adw_action(struct cam_sim *sim, union ccb *ccb)
 349 {
 350         struct  adw_softc *adw;
 351
 352         CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("adw_action\n"));
 353
 354         adw = (struct adw_softc *)cam_sim_softc(sim);
 355
 356         switch (ccb->ccb_h.func_code) {
 357         /* Common cases first */
 358         case XPT_SCSI_IO:       /* Execute the requested I/O operation */
 359         {
 360                 struct  ccb_scsiio *csio;
 361                 struct  ccb_hdr *ccbh;
 362                 struct  acb *acb;
 363
 364                 csio = &ccb->csio;
 365                 ccbh = &ccb->ccb_h;
 366
 367                 /* Max supported CDB length is 12 bytes */
 368                 if (csio->cdb_len > 12) {
 369                         ccb->ccb_h.status = CAM_REQ_INVALID;
 370                         xpt_done(ccb);
 371                         return;
 372                 }
 373
 374                 if ((acb = adwgetacb(adw)) == NULL) {
 375                         int s;
 376
 377                         s = splcam();
 378                         adw->state |= ADW_RESOURCE_SHORTAGE;
 379                         splx(s);
 380                         xpt_freeze_simq(sim, /*count*/1);
 381                         ccb->ccb_h.status = CAM_REQUEUE_REQ;
 382                         xpt_done(ccb);
 383                         return;
 384                 }
 385
 386                 /* Link acb and ccb so we can find one from the other */
 387                 acb->ccb = ccb;
 388                 ccb->ccb_h.ccb_acb_ptr = acb;
 389                 ccb->ccb_h.ccb_adw_ptr = adw;
 390
 391                 acb->queue.cntl = 0;
 392                 acb->queue.target_cmd = 0;
 393                 acb->queue.target_id = ccb->ccb_h.target_id;
 394                 acb->queue.target_lun = ccb->ccb_h.target_lun;
 395
 396                 acb->queue.mflag = 0;
 397                 acb->queue.sense_len =
 398                         MIN(csio->sense_len, sizeof(acb->sense_data));
 399                 acb->queue.cdb_len = csio->cdb_len;
 400                 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0) {
 401                         switch (csio->tag_action) {
 402                         case MSG_SIMPLE_Q_TAG:
 403                                 acb->queue.scsi_cntl = ADW_QSC_SIMPLE_Q_TAG;
 404                                 break;
 405                         case MSG_HEAD_OF_Q_TAG:
 406                                 acb->queue.scsi_cntl = ADW_QSC_HEAD_OF_Q_TAG;
 407                                 break;
 408                         case MSG_ORDERED_Q_TAG:
 409                                 acb->queue.scsi_cntl = ADW_QSC_ORDERED_Q_TAG;
 410                                 break;
 411                         default:
 412                                 acb->queue.scsi_cntl = ADW_QSC_NO_TAGMSG;
 413                                 break;
 414                         }
 415                 } else
 416                         acb->queue.scsi_cntl = ADW_QSC_NO_TAGMSG;
 417
 418                 if ((ccb->ccb_h.flags & CAM_DIS_DISCONNECT) != 0)
 419                         acb->queue.scsi_cntl |= ADW_QSC_NO_DISC;
 420
 421                 acb->queue.done_status = 0;
 422                 acb->queue.scsi_status = 0;
 423                 acb->queue.host_status = 0;
 424                 acb->queue.sg_wk_ix = 0;
 425                 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) {
 426                         if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) {
 427                                 bcopy(csio->cdb_io.cdb_ptr,
 428                                       acb->queue.cdb, csio->cdb_len);
 429                         } else {
 430                                 /* I guess I could map it in... */
 431                                 ccb->ccb_h.status = CAM_REQ_INVALID;
 432                                 adwfreeacb(adw, acb);
 433                                 xpt_done(ccb);
 434                                 return;
 435                         }
 436                 } else {
 437                         bcopy(csio->cdb_io.cdb_bytes,
 438                               acb->queue.cdb, csio->cdb_len);
 439                 }
 440
 441                 /*
 442                  * If we have any data to send with this command,
 443                  * map it into bus space.
 444                  */
 445                 if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
 446                         if ((ccbh->flags & CAM_SCATTER_VALID) == 0) {
 447                                 /*
 448                                  * We've been given a pointer
 449                                  * to a single buffer.
 450                                  */
 451                                 if ((ccbh->flags & CAM_DATA_PHYS) == 0) {
 452                                         int s;
 453                                         int error;
 454
 455                                         s = splsoftvm();
 456                                         error =
 457                                             bus_dmamap_load(adw->buffer_dmat,
 458                                                             acb->dmamap,
 459                                                             csio->data_ptr,
 460                                                             csio->dxfer_len,
 461                                                             adwexecuteacb,
 462                                                             acb, /*flags*/0);
 463                                         if (error == EINPROGRESS) {
 464                                                 /*
 465                                                  * So as to maintain ordering,
 466                                                  * freeze the controller queue
 467                                                  * until our mapping is
 468                                                  * returned.
 469                                                  */
 470                                                 xpt_freeze_simq(sim, 1);
 471                                                 acb->state |= CAM_RELEASE_SIMQ;
 472                                         }
 473                                         splx(s);
 474                                 } else {
 475                                         struct bus_dma_segment seg;
 476
 477                                         /* Pointer to physical buffer */
 478                                         seg.ds_addr =
 479                                             (bus_addr_t)csio->data_ptr;
 480                                         seg.ds_len = csio->dxfer_len;
 481                                         adwexecuteacb(acb, &seg, 1, 0);
 482                                 }
 483                         } else {
 484                                 struct bus_dma_segment *segs;
 485
 486                                 if ((ccbh->flags & CAM_DATA_PHYS) != 0)
 487                                         panic("adw_action - Physical "
 488                                               "segment pointers "
 489                                               "unsupported");
 490
 491                                 if ((ccbh->flags&CAM_SG_LIST_PHYS)==0)
 492                                         panic("adw_action - Virtual "
 493                                               "segment addresses "
 494                                               "unsupported");
 495
 496                                 /* Just use the segments provided */
 497                                 segs = (struct bus_dma_segment *)csio->data_ptr;
 498                                 adwexecuteacb(acb, segs, csio->sglist_cnt,
 499                                               (csio->sglist_cnt < ADW_SGSIZE)
 500                                               ? 0 : EFBIG);
 501                         }
 502                 } else {
 503                         adwexecuteacb(acb, NULL, 0, 0);
 504                 }
 505                 break;
 506         }
 507         case XPT_RESET_DEV:     /* Bus Device Reset the specified SCSI device */
 508         {
 509                 adw_idle_cmd_status_t status;
 510
 511                 status = adw_idle_cmd_send(adw, ADW_IDLE_CMD_DEVICE_RESET,
 512                                            ccb->ccb_h.target_id);
 513                 if (status == ADW_IDLE_CMD_SUCCESS) {
 514                         ccb->ccb_h.status = CAM_REQ_CMP;
 515                         if (bootverbose) {
 516                                 xpt_print_path(ccb->ccb_h.path);
 517                                 printf("BDR Delivered\n");
 518                         }
 519                 } else
 520                         ccb->ccb_h.status = CAM_REQ_CMP_ERR;
 521                 xpt_done(ccb);
 522                 break;
 523         }
 524         case XPT_ABORT:                 /* Abort the specified CCB */
 525                 /* XXX Implement */
 526                 ccb->ccb_h.status = CAM_REQ_INVALID;
 527                 xpt_done(ccb);
 528                 break;
 529         case XPT_SET_TRAN_SETTINGS:
 530         {
 531                 struct    ccb_trans_settings *cts;
 532                 u_int     target_mask;
 533                 int       s;
 534
 535                 cts = &ccb->cts;
 536                 target_mask = 0x01 << ccb->ccb_h.target_id;
 537
 538                 s = splcam();
 539                 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) {
 540                         u_int sdtrdone;
 541
 542                         sdtrdone = adw_lram_read_16(adw, ADW_MC_SDTR_DONE);
 543                         if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
 544                                 u_int discenb;
 545
 546                                 discenb =
 547                                     adw_lram_read_16(adw, ADW_MC_DISC_ENABLE);
 548
 549                                 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
 550                                         discenb |= target_mask;
 551                                 else
 552                                         discenb &= ~target_mask;
 553
 554                                 adw_lram_write_16(adw, ADW_MC_DISC_ENABLE,
 555                                                   discenb);
 556                         }
 557
 558                         if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
 559
 560                                 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
 561                                         adw->tagenb |= target_mask;
 562                                 else
 563                                         adw->tagenb &= ~target_mask;
 564                         }
 565
 566                         if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) {
 567                                 u_int wdtrenb_orig;
 568                                 u_int wdtrenb;
 569                                 u_int wdtrdone;
 570
 571                                 wdtrenb_orig =
 572                                     adw_lram_read_16(adw, ADW_MC_WDTR_ABLE);
 573                                 wdtrenb = wdtrenb_orig;
 574                                 wdtrdone = adw_lram_read_16(adw,
 575                                                             ADW_MC_WDTR_DONE);
 576                                 switch (cts->bus_width) {
 577                                 case MSG_EXT_WDTR_BUS_32_BIT:
 578                                 case MSG_EXT_WDTR_BUS_16_BIT:
 579                                         wdtrenb |= target_mask;
 580                                         break;
 581                                 case MSG_EXT_WDTR_BUS_8_BIT:
 582                                 default:
 583                                         wdtrenb &= ~target_mask;
 584                                         break;
 585                                 }
 586                                 if (wdtrenb != wdtrenb_orig) {
 587                                         adw_lram_write_16(adw,
 588                                                           ADW_MC_WDTR_ABLE,
 589                                                           wdtrenb);
 590                                         wdtrdone &= ~target_mask;
 591                                         adw_lram_write_16(adw,
 592                                                           ADW_MC_WDTR_DONE,
 593                                                           wdtrdone);
 594                                         /* Wide negotiation forces async */
 595                                         sdtrdone &= ~target_mask;
 596                                         adw_lram_write_16(adw,
 597                                                           ADW_MC_SDTR_DONE,
 598                                                           sdtrdone);
 599                                 }
 600                         }
 601
 602                         if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
 603                          || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) {
 604                                 u_int sdtr_orig;
 605                                 u_int sdtr;
 606                                 u_int sdtrable_orig;
 607                                 u_int sdtrable;
 608
 609                                 sdtr = adw_get_chip_sdtr(adw,
 610                                                          ccb->ccb_h.target_id);
 611                                 sdtr_orig = sdtr;
 612                                 sdtrable = adw_lram_read_16(adw,
 613                                                             ADW_MC_SDTR_ABLE);
 614                                 sdtrable_orig = sdtrable;
 615
 616                                 if ((cts->valid
 617                                    & CCB_TRANS_SYNC_RATE_VALID) != 0) {
 618
 619                                         sdtr =
 620                                             adw_find_sdtr(adw,
 621                                                           cts->sync_period);
 622                                 }
 623
 624                                 if ((cts->valid
 625                                    & CCB_TRANS_SYNC_OFFSET_VALID) != 0) {
 626                                         if (cts->sync_offset == 0)
 627                                                 sdtr = ADW_MC_SDTR_ASYNC;
 628                                 }
 629
 630                                 if (sdtr == ADW_MC_SDTR_ASYNC)
 631                                         sdtrable &= ~target_mask;
 632                                 else
 633                                         sdtrable |= target_mask;
 634                                 if (sdtr != sdtr_orig
 635                                  || sdtrable != sdtrable_orig) {
 636                                         adw_set_chip_sdtr(adw,
 637                                                           ccb->ccb_h.target_id,
 638                                                           sdtr);
 639                                         sdtrdone &= ~target_mask;
 640                                         adw_lram_write_16(adw, ADW_MC_SDTR_ABLE,
 641                                                           sdtrable);
 642                                         adw_lram_write_16(adw, ADW_MC_SDTR_DONE,
 643                                                           sdtrdone);
 644
 645                                 }
 646                         }
 647                 }
 648                 splx(s);
 649                 ccb->ccb_h.status = CAM_REQ_CMP;
 650                 xpt_done(ccb);
 651                 break;
 652         }
 653         case XPT_GET_TRAN_SETTINGS:
 654         /* Get default/user set transfer settings for the target */
 655         {
 656                 struct  ccb_trans_settings *cts;
 657                 u_int   target_mask;
 658
 659                 cts = &ccb->cts;
 660                 target_mask = 0x01 << ccb->ccb_h.target_id;
 661                 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) {
 662                         u_int mc_sdtr;
 663
 664                         cts->flags = 0;
 665                         if ((adw->user_discenb & target_mask) != 0)
 666                                 cts->flags |= CCB_TRANS_DISC_ENB;
 667
 668                         if ((adw->user_tagenb & target_mask) != 0)
 669                                 cts->flags |= CCB_TRANS_TAG_ENB;
 670
 671                         if ((adw->user_wdtr & target_mask) != 0)
 672                                 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
 673                         else
 674                                 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
 675
 676                         mc_sdtr = adw_get_user_sdtr(adw, ccb->ccb_h.target_id);
 677                         cts->sync_period = adw_find_period(adw, mc_sdtr);
 678                         if (cts->sync_period != 0)
 679                                 cts->sync_offset = 15; /* XXX ??? */
 680                         else
 681                                 cts->sync_offset = 0;
 682
 683                         cts->valid = CCB_TRANS_SYNC_RATE_VALID
 684                                    | CCB_TRANS_SYNC_OFFSET_VALID
 685                                    | CCB_TRANS_BUS_WIDTH_VALID
 686                                    | CCB_TRANS_DISC_VALID
 687                                    | CCB_TRANS_TQ_VALID;
 688                         ccb->ccb_h.status = CAM_REQ_CMP;
 689                 } else {
 690                         u_int targ_tinfo;
 691
 692                         cts->flags = 0;
 693                         if ((adw_lram_read_16(adw, ADW_MC_DISC_ENABLE)
 694                           & target_mask) != 0)
 695                                 cts->flags |= CCB_TRANS_DISC_ENB;
 696
 697                         if ((adw->tagenb & target_mask) != 0)
 698                                 cts->flags |= CCB_TRANS_TAG_ENB;
 699
 700                         targ_tinfo =
 701                             adw_lram_read_16(adw,
 702                                              ADW_MC_DEVICE_HSHK_CFG_TABLE
 703                                              + (2 * ccb->ccb_h.target_id));
 704
 705                         if ((targ_tinfo & ADW_HSHK_CFG_WIDE_XFR) != 0)
 706                                 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
 707                         else
 708                                 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
 709
 710                         cts->sync_period =
 711                             adw_hshk_cfg_period_factor(targ_tinfo);
 712
 713                         cts->sync_offset = targ_tinfo & ADW_HSHK_CFG_OFFSET;
 714                         if (cts->sync_period == 0)
 715                                 cts->sync_offset = 0;
 716
 717                         if (cts->sync_offset == 0)
 718                                 cts->sync_period = 0;
 719                 }
 720                 cts->valid = CCB_TRANS_SYNC_RATE_VALID
 721                            | CCB_TRANS_SYNC_OFFSET_VALID
 722                            | CCB_TRANS_BUS_WIDTH_VALID
 723                            | CCB_TRANS_DISC_VALID
 724                            | CCB_TRANS_TQ_VALID;
 725                 ccb->ccb_h.status = CAM_REQ_CMP;
 726                 xpt_done(ccb);
 727                 break;
 728         }
 729         case XPT_CALC_GEOMETRY:
 730         {
 731                 struct    ccb_calc_geometry *ccg;
 732                 u_int32_t size_mb;
 733                 u_int32_t secs_per_cylinder;
 734                 int       extended;
 735
 736                 /*
 737                  * XXX Use Adaptec translation until I find out how to
 738                  *     get this information from the card.
 739                  */
 740                 ccg = &ccb->ccg;
 741                 size_mb = ccg->volume_size
 742                         / ((1024L * 1024L) / ccg->block_size);
 743                 extended = 1;
 744
 745                 if (size_mb > 1024 && extended) {
 746                         ccg->heads = 255;
 747                         ccg->secs_per_track = 63;
 748                 } else {
 749                         ccg->heads = 64;
 750                         ccg->secs_per_track = 32;
 751                 }
 752                 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
 753                 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
 754                 ccb->ccb_h.status = CAM_REQ_CMP;
 755                 xpt_done(ccb);
 756                 break;
 757         }
 758         case XPT_RESET_BUS:             /* Reset the specified SCSI bus */
 759         {
 760                 int failure;
 761
 762                 failure = adw_reset_bus(adw);
 763                 if (failure != 0) {
 764                         ccb->ccb_h.status = CAM_REQ_CMP_ERR;
 765                 } else {
 766                         if (bootverbose) {
 767                                 xpt_print_path(adw->path);
 768                                 printf("Bus Reset Delivered\n");
 769                         }
 770                         ccb->ccb_h.status = CAM_REQ_CMP;
 771                 }
 772                 xpt_done(ccb);
 773                 break;
 774         }
 775         case XPT_TERM_IO:               /* Terminate the I/O process */
 776                 /* XXX Implement */
 777                 ccb->ccb_h.status = CAM_REQ_INVALID;
 778                 xpt_done(ccb);
 779                 break;
 780         case XPT_PATH_INQ:              /* Path routing inquiry */
 781         {
 782                 struct ccb_pathinq *cpi = &ccb->cpi;
 783
 784                 cpi->version_num = 1;
 785                 cpi->hba_inquiry = PI_WIDE_16|PI_SDTR_ABLE|PI_TAG_ABLE;
 786                 cpi->target_sprt = 0;
 787                 cpi->hba_misc = 0;
 788                 cpi->hba_eng_cnt = 0;
 789                 cpi->max_target = ADW_MAX_TID;
 790                 cpi->max_lun = ADW_MAX_LUN;
 791                 cpi->initiator_id = adw->initiator_id;
 792                 cpi->bus_id = cam_sim_bus(sim);
 793                 cpi->base_transfer_speed = 3300;
 794                 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
 795                 strncpy(cpi->hba_vid, "AdvanSys", HBA_IDLEN);
 796                 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
 797                 cpi->unit_number = cam_sim_unit(sim);
 798                 cpi->ccb_h.status = CAM_REQ_CMP;
 799                 xpt_done(ccb);
 800                 break;
 801         }
 802         default:
 803                 ccb->ccb_h.status = CAM_REQ_INVALID;
 804                 xpt_done(ccb);
 805                 break;
 806         }
 807 }
 808
 809 static void
 810 adw_poll(struct cam_sim *sim)
 811 {
 812         adw_intr(cam_sim_softc(sim));
 813 }
 814
 815 static void
 816 adw_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg)
 817 {
 818 }
 819
 820 struct adw_softc *
 821 adw_alloc(device_t dev, struct resource *regs, int regs_type, int regs_id)
 822 {
 823         struct   adw_softc *adw;
 824         int      i;
 825
 826         /*
 827          * Allocate a storage area for us
 828          */
 829         adw = malloc(sizeof(struct adw_softc), M_DEVBUF, M_NOWAIT | M_ZERO);
 830         if (adw == NULL) {
 831                 printf("adw%d: cannot malloc!\n", device_get_unit(dev));
 832                 return NULL;
 833         }
 834         LIST_INIT(&adw->pending_ccbs);
 835         SLIST_INIT(&adw->sg_maps);
 836         adw->device = dev;
 837         adw->unit = device_get_unit(dev);
 838         adw->regs_res_type = regs_type;
 839         adw->regs_res_id = regs_id;
 840         adw->regs = regs;
 841         adw->tag = rman_get_bustag(regs);
 842         adw->bsh = rman_get_bushandle(regs);
 843         i = adw->unit / 10;
 844         adw->name = malloc(sizeof("adw") + i + 1, M_DEVBUF, M_NOWAIT);
 845         if (adw->name == NULL) {
 846                 printf("adw%d: cannot malloc name!\n", adw->unit);
 847                 free(adw, M_DEVBUF);
 848                 return NULL;
 849         }
 850         sprintf(adw->name, "adw%d", adw->unit);
 851         return(adw);
 852 }
 853
 854 void
 855 adw_free(struct adw_softc *adw)
 856 {
 857         switch (adw->init_level) {
 858         case 9:
 859         {
 860                 struct sg_map_node *sg_map;
 861
 862                 while ((sg_map = SLIST_FIRST(&adw->sg_maps)) != NULL) {
 863                         SLIST_REMOVE_HEAD(&adw->sg_maps, links);
 864                         bus_dmamap_unload(adw->sg_dmat,
 865                                           sg_map->sg_dmamap);
 866                         bus_dmamem_free(adw->sg_dmat, sg_map->sg_vaddr,
 867                                         sg_map->sg_dmamap);
 868                         free(sg_map, M_DEVBUF);
 869                 }
 870                 bus_dma_tag_destroy(adw->sg_dmat);
 871         }
 872         case 8:
 873                 bus_dmamap_unload(adw->acb_dmat, adw->acb_dmamap);
 874         case 7:
 875                 bus_dmamem_free(adw->acb_dmat, adw->acbs,
 876                                 adw->acb_dmamap);
 877                 bus_dmamap_destroy(adw->acb_dmat, adw->acb_dmamap);
 878         case 6:
 879                 bus_dma_tag_destroy(adw->acb_dmat);
 880         case 5:
 881                 bus_dmamap_unload(adw->carrier_dmat, adw->carrier_dmamap);
 882         case 4:
 883                 bus_dmamem_free(adw->carrier_dmat, adw->carriers,
 884                                 adw->carrier_dmamap);
 885                 bus_dmamap_destroy(adw->carrier_dmat, adw->carrier_dmamap);
 886         case 3:
 887                 bus_dma_tag_destroy(adw->carrier_dmat);
 888         case 2:
 889                 bus_dma_tag_destroy(adw->buffer_dmat);
 890         case 1:
 891                 bus_dma_tag_destroy(adw->parent_dmat);
 892         case 0:
 893                 break;
 894         }
 895         free(adw->name, M_DEVBUF);
 896         free(adw, M_DEVBUF);
 897 }
 898
 899 int
 900 adw_init(struct adw_softc *adw)
 901 {
 902         struct    adw_eeprom eep_config;
 903         u_int     tid;
 904         u_int     i;
 905         u_int16_t checksum;
 906         u_int16_t scsicfg1;
 907
 908         checksum = adw_eeprom_read(adw, &eep_config);
 909         bcopy(eep_config.serial_number, adw->serial_number,
 910               sizeof(adw->serial_number));
 911         if (checksum != eep_config.checksum) {
 912                 u_int16_t serial_number[3];
 913
 914                 adw->flags |= ADW_EEPROM_FAILED;
 915                 printf("%s: EEPROM checksum failed.  Restoring Defaults\n",
 916                        adw_name(adw));
 917
 918                 /*
 919                  * Restore the default EEPROM settings.
 920                  * Assume the 6 byte board serial number that was read
 921                  * from EEPROM is correct even if the EEPROM checksum
 922                  * failed.
 923                  */
 924                 bcopy(adw->default_eeprom, &eep_config, sizeof(eep_config));
 925                 bcopy(adw->serial_number, eep_config.serial_number,
 926                       sizeof(serial_number));
 927                 adw_eeprom_write(adw, &eep_config);
 928         }
 929
 930         /* Pull eeprom information into our softc. */
 931         adw->bios_ctrl = eep_config.bios_ctrl;
 932         adw->user_wdtr = eep_config.wdtr_able;
 933         for (tid = 0; tid < ADW_MAX_TID; tid++) {
 934                 u_int     mc_sdtr;
 935                 u_int16_t tid_mask;
 936
 937                 tid_mask = 0x1 << tid;
 938                 if ((adw->features & ADW_ULTRA) != 0) {
 939                         /*
 940                          * Ultra chips store sdtr and ultraenb
 941                          * bits in their seeprom, so we must
 942                          * construct valid mc_sdtr entries for
 943                          * indirectly.
 944                          */
 945                         if (eep_config.sync1.sync_enable & tid_mask) {
 946                                 if (eep_config.sync2.ultra_enable & tid_mask)
 947                                         mc_sdtr = ADW_MC_SDTR_20;
 948                                 else
 949                                         mc_sdtr = ADW_MC_SDTR_10;
 950                         } else
 951                                 mc_sdtr = ADW_MC_SDTR_ASYNC;
 952                 } else {
 953                         switch (ADW_TARGET_GROUP(tid)) {
 954                         case 3:
 955                                 mc_sdtr = eep_config.sync4.sdtr4;
 956                                 break;
 957                         case 2:
 958                                 mc_sdtr = eep_config.sync3.sdtr3;
 959                                 break;
 960                         case 1:
 961                                 mc_sdtr = eep_config.sync2.sdtr2;
 962                                 break;
 963                         default: /* Shut up compiler */
 964                         case 0:
 965                                 mc_sdtr = eep_config.sync1.sdtr1;
 966                                 break;
 967                         }
 968                         mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
 969                         mc_sdtr &= 0xFF;
 970                 }
 971                 adw_set_user_sdtr(adw, tid, mc_sdtr);
 972         }
 973         adw->user_tagenb = eep_config.tagqng_able;
 974         adw->user_discenb = eep_config.disc_enable;
 975         adw->max_acbs = eep_config.max_host_qng;
 976         adw->initiator_id = (eep_config.adapter_scsi_id & ADW_MAX_TID);
 977
 978         /*
 979          * Sanity check the number of host openings.
 980          */
 981         if (adw->max_acbs > ADW_DEF_MAX_HOST_QNG)
 982                 adw->max_acbs = ADW_DEF_MAX_HOST_QNG;
 983         else if (adw->max_acbs < ADW_DEF_MIN_HOST_QNG) {
 984                 /* If the value is zero, assume it is uninitialized. */
 985                 if (adw->max_acbs == 0)
 986                         adw->max_acbs = ADW_DEF_MAX_HOST_QNG;
 987                 else
 988                         adw->max_acbs = ADW_DEF_MIN_HOST_QNG;
 989         }
 990
 991         scsicfg1 = 0;
 992         if ((adw->features & ADW_ULTRA2) != 0) {
 993                 switch (eep_config.termination_lvd) {
 994                 default:
 995                         printf("%s: Invalid EEPROM LVD Termination Settings.\n",
 996                                adw_name(adw));
 997                         printf("%s: Reverting to Automatic LVD Termination\n",
 998                                adw_name(adw));
 999                         /* FALLTHROUGH */
1000                 case ADW_EEPROM_TERM_AUTO:
1001                         break;
1002                 case ADW_EEPROM_TERM_BOTH_ON:
1003                         scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_LO;
1004                         /* FALLTHROUGH */
1005                 case ADW_EEPROM_TERM_HIGH_ON:
1006                         scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_HI;
1007                         /* FALLTHROUGH */
1008                 case ADW_EEPROM_TERM_OFF:
1009                         scsicfg1 |= ADW2_SCSI_CFG1_DIS_TERM_DRV;
1010                         break;
1011                 }
1012         }
1013
1014         switch (eep_config.termination_se) {
1015         default:
1016                 printf("%s: Invalid SE EEPROM Termination Settings.\n",
1017                        adw_name(adw));
1018                 printf("%s: Reverting to Automatic SE Termination\n",
1019                        adw_name(adw));
1020                 /* FALLTHROUGH */
1021         case ADW_EEPROM_TERM_AUTO:
1022                 break;
1023         case ADW_EEPROM_TERM_BOTH_ON:
1024                 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L;
1025                 /* FALLTHROUGH */
1026         case ADW_EEPROM_TERM_HIGH_ON:
1027                 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
1028                 /* FALLTHROUGH */
1029         case ADW_EEPROM_TERM_OFF:
1030                 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_MANUAL;
1031                 break;
1032         }
1033         printf("%s: SCSI ID %d, ", adw_name(adw), adw->initiator_id);
1034
1035         /* DMA tag for mapping buffers into device visible space. */
1036         if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/1, /*boundary*/0,
1037                                /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
1038                                /*highaddr*/BUS_SPACE_MAXADDR,
1039                                /*filter*/NULL, /*filterarg*/NULL,
1040                                /*maxsize*/MAXBSIZE, /*nsegments*/ADW_SGSIZE,
1041                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1042                                /*flags*/BUS_DMA_ALLOCNOW,
1043                                &adw->buffer_dmat) != 0) {
1044                 return (ENOMEM);
1045         }
1046
1047         adw->init_level++;
1048
1049         /* DMA tag for our ccb carrier structures */
1050         if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/0x10,
1051                                /*boundary*/0,
1052                                /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
1053                                /*highaddr*/BUS_SPACE_MAXADDR,
1054                                /*filter*/NULL, /*filterarg*/NULL,
1055                                (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1)
1056                                 * sizeof(struct adw_carrier),
1057                                /*nsegments*/1,
1058                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1059                                /*flags*/0, &adw->carrier_dmat) != 0) {
1060                 return (ENOMEM);
1061         }
1062
1063         adw->init_level++;
1064
1065         /* Allocation for our ccb carrier structures */
1066         if (bus_dmamem_alloc(adw->carrier_dmat, (void **)&adw->carriers,
1067                              BUS_DMA_NOWAIT, &adw->carrier_dmamap) != 0) {
1068                 return (ENOMEM);
1069         }
1070
1071         adw->init_level++;
1072
1073         /* And permanently map them */
1074         bus_dmamap_load(adw->carrier_dmat, adw->carrier_dmamap,
1075                         adw->carriers,
1076                         (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1)
1077                          * sizeof(struct adw_carrier),
1078                         adwmapmem, &adw->carrier_busbase, /*flags*/0);
1079
1080         /* Clear them out. */
1081         bzero(adw->carriers, (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1)
1082                              * sizeof(struct adw_carrier));
1083
1084         /* Setup our free carrier list */
1085         adw->free_carriers = adw->carriers;
1086         for (i = 0; i < adw->max_acbs + ADW_NUM_CARRIER_QUEUES; i++) {
1087                 adw->carriers[i].carr_offset =
1088                         carriervtobo(adw, &adw->carriers[i]);
1089                 adw->carriers[i].carr_ba =
1090                         carriervtob(adw, &adw->carriers[i]);
1091                 adw->carriers[i].areq_ba = 0;
1092                 adw->carriers[i].next_ba =
1093                         carriervtobo(adw, &adw->carriers[i+1]);
1094         }
1095         /* Terminal carrier.  Never leaves the freelist */
1096         adw->carriers[i].carr_offset =
1097                 carriervtobo(adw, &adw->carriers[i]);
1098         adw->carriers[i].carr_ba =
1099                 carriervtob(adw, &adw->carriers[i]);
1100         adw->carriers[i].areq_ba = 0;
1101         adw->carriers[i].next_ba = ~0;
1102
1103         adw->init_level++;
1104
1105         /* DMA tag for our acb structures */
1106         if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/1, /*boundary*/0,
1107                                /*lowaddr*/BUS_SPACE_MAXADDR,
1108                                /*highaddr*/BUS_SPACE_MAXADDR,
1109                                /*filter*/NULL, /*filterarg*/NULL,
1110                                adw->max_acbs * sizeof(struct acb),
1111                                /*nsegments*/1,
1112                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1113                                /*flags*/0, &adw->acb_dmat) != 0) {
1114                 return (ENOMEM);
1115         }
1116
1117         adw->init_level++;
1118
1119         /* Allocation for our ccbs */
1120         if (bus_dmamem_alloc(adw->acb_dmat, (void **)&adw->acbs,
1121                              BUS_DMA_NOWAIT, &adw->acb_dmamap) != 0)
1122                 return (ENOMEM);
1123
1124         adw->init_level++;
1125
1126         /* And permanently map them */
1127         bus_dmamap_load(adw->acb_dmat, adw->acb_dmamap,
1128                         adw->acbs,
1129                         adw->max_acbs * sizeof(struct acb),
1130                         adwmapmem, &adw->acb_busbase, /*flags*/0);
1131
1132         /* Clear them out. */
1133         bzero(adw->acbs, adw->max_acbs * sizeof(struct acb));
1134
1135         /* DMA tag for our S/G structures.  We allocate in page sized chunks */
1136         if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/1, /*boundary*/0,
1137                                /*lowaddr*/BUS_SPACE_MAXADDR,
1138                                /*highaddr*/BUS_SPACE_MAXADDR,
1139                                /*filter*/NULL, /*filterarg*/NULL,
1140                                PAGE_SIZE, /*nsegments*/1,
1141                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1142                                /*flags*/0, &adw->sg_dmat) != 0) {
1143                 return (ENOMEM);
1144         }
1145
1146         adw->init_level++;
1147
1148         /* Allocate our first batch of ccbs */
1149         if (adwallocacbs(adw) == 0)
1150                 return (ENOMEM);
1151
1152         if (adw_init_chip(adw, scsicfg1) != 0)
1153                 return (ENXIO);
1154
1155         printf("Queue Depth %d\n", adw->max_acbs);
1156
1157         return (0);
1158 }
1159
1160 /*
1161  * Attach all the sub-devices we can find
1162  */
1163 int
1164 adw_attach(struct adw_softc *adw)
1165 {
1166         struct ccb_setasync csa;
1167         struct cam_devq *devq;
1168         int s;
1169         int error;
1170
1171         error = 0;
1172         s = splcam();
1173         /* Hook up our interrupt handler */
1174         if ((error = bus_setup_intr(adw->device, adw->irq, INTR_TYPE_CAM,
1175                                     adw_intr, adw, &adw->ih)) != 0) {
1176                 device_printf(adw->device, "bus_setup_intr() failed: %d\n",
1177                               error);
1178                 goto fail;
1179         }
1180
1181         /* Start the Risc processor now that we are fully configured. */
1182         adw_outw(adw, ADW_RISC_CSR, ADW_RISC_CSR_RUN);
1183
1184         /*
1185          * Create the device queue for our SIM.
1186          */
1187         devq = cam_simq_alloc(adw->max_acbs);
1188         if (devq == NULL)
1189                 return (ENOMEM);
1190
1191         /*
1192          * Construct our SIM entry.
1193          */
1194         adw->sim = cam_sim_alloc(adw_action, adw_poll, "adw", adw, adw->unit,
1195                                  1, adw->max_acbs, devq);
1196         if (adw->sim == NULL) {
1197                 error = ENOMEM;
1198                 goto fail;
1199         }
1200
1201         /*
1202          * Register the bus.
1203          */
1204         if (xpt_bus_register(adw->sim, 0) != CAM_SUCCESS) {
1205                 cam_sim_free(adw->sim, /*free devq*/TRUE);
1206                 error = ENOMEM;
1207                 goto fail;
1208         }
1209
1210         if (xpt_create_path(&adw->path, /*periph*/NULL, cam_sim_path(adw->sim),
1211                             CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD)
1212            == CAM_REQ_CMP) {
1213                 xpt_setup_ccb(&csa.ccb_h, adw->path, /*priority*/5);
1214                 csa.ccb_h.func_code = XPT_SASYNC_CB;
1215                 csa.event_enable = AC_LOST_DEVICE;
1216                 csa.callback = adw_async;
1217                 csa.callback_arg = adw;
1218                 xpt_action((union ccb *)&csa);
1219         }
1220
1221 fail:
1222         splx(s);
1223         return (error);
1224 }
1225
1226 void
1227 adw_intr(void *arg)
1228 {
1229         struct  adw_softc *adw;
1230         u_int   int_stat;
1231
1232         adw = (struct adw_softc *)arg;
1233         if ((adw_inw(adw, ADW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR) == 0)
1234                 return;
1235
1236         /* Reading the register clears the interrupt. */
1237         int_stat = adw_inb(adw, ADW_INTR_STATUS_REG);
1238
1239         if ((int_stat & ADW_INTR_STATUS_INTRB) != 0) {
1240                 u_int intrb_code;
1241
1242                 /* Async Microcode Event */
1243                 intrb_code = adw_lram_read_8(adw, ADW_MC_INTRB_CODE);
1244                 switch (intrb_code) {
1245                 case ADW_ASYNC_CARRIER_READY_FAILURE:
1246                         /*
1247                          * The RISC missed our update of
1248                          * the commandq.
1249                          */
1250                         if (LIST_FIRST(&adw->pending_ccbs) != NULL)
1251                                 adw_tickle_risc(adw, ADW_TICKLE_A);
1252                         break;
1253                 case ADW_ASYNC_SCSI_BUS_RESET_DET:
1254                         /*
1255                          * The firmware detected a SCSI Bus reset.
1256                          */
1257                         printf("Someone Reset the Bus\n");
1258                         adw_handle_bus_reset(adw, /*initiated*/FALSE);
1259                         break;
1260                 case ADW_ASYNC_RDMA_FAILURE:
1261                         /*
1262                          * Handle RDMA failure by resetting the
1263                          * SCSI Bus and chip.
1264                          */
1265 #if XXX
1266                         AdvResetChipAndSB(adv_dvc_varp);
1267 #endif
1268                         break;
1269
1270                 case ADW_ASYNC_HOST_SCSI_BUS_RESET:
1271                         /*
1272                          * Host generated SCSI bus reset occurred.
1273                          */
1274                         adw_handle_bus_reset(adw, /*initiated*/TRUE);
1275                         break;
1276                 default:
1277                         printf("adw_intr: unknown async code 0x%x\n",
1278                                intrb_code);
1279                         break;
1280                 }
1281         }
1282
1283         /*
1284          * Run down the RequestQ.
1285          */
1286         while ((adw->responseq->next_ba & ADW_RQ_DONE) != 0) {
1287                 struct adw_carrier *free_carrier;
1288                 struct acb *acb;
1289                 union ccb *ccb;
1290
1291 #if 0
1292                 printf("0x%x, 0x%x, 0x%x, 0x%x\n",
1293                        adw->responseq->carr_offset,
1294                        adw->responseq->carr_ba,
1295                        adw->responseq->areq_ba,
1296                        adw->responseq->next_ba);
1297 #endif
1298                 /*
1299                  * The firmware copies the adw_scsi_req_q.acb_baddr
1300                  * field into the areq_ba field of the carrier.
1301                  */
1302                 acb = acbbotov(adw, adw->responseq->areq_ba);
1303
1304                 /*
1305                  * The least significant four bits of the next_ba
1306                  * field are used as flags.  Mask them out and then
1307                  * advance through the list.
1308                  */
1309                 free_carrier = adw->responseq;
1310                 adw->responseq =
1311                     carrierbotov(adw, free_carrier->next_ba & ADW_NEXT_BA_MASK);
1312                 free_carrier->next_ba = adw->free_carriers->carr_offset;
1313                 adw->free_carriers = free_carrier;
1314
1315                 /* Process CCB */
1316                 ccb = acb->ccb;
1317                 untimeout(adwtimeout, acb, ccb->ccb_h.timeout_ch);
1318                 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1319                         bus_dmasync_op_t op;
1320
1321                         if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
1322                                 op = BUS_DMASYNC_POSTREAD;
1323                         else
1324                                 op = BUS_DMASYNC_POSTWRITE;
1325                         bus_dmamap_sync(adw->buffer_dmat, acb->dmamap, op);
1326                         bus_dmamap_unload(adw->buffer_dmat, acb->dmamap);
1327                         ccb->csio.resid = acb->queue.data_cnt;
1328                 } else
1329                         ccb->csio.resid = 0;
1330
1331                 /* Common Cases inline... */
1332                 if (acb->queue.host_status == QHSTA_NO_ERROR
1333                  && (acb->queue.done_status == QD_NO_ERROR
1334                   || acb->queue.done_status == QD_WITH_ERROR)) {
1335                         ccb->csio.scsi_status = acb->queue.scsi_status;
1336                         ccb->ccb_h.status = 0;
1337                         switch (ccb->csio.scsi_status) {
1338                         case SCSI_STATUS_OK:
1339                                 ccb->ccb_h.status |= CAM_REQ_CMP;
1340                                 break;
1341                         case SCSI_STATUS_CHECK_COND:
1342                         case SCSI_STATUS_CMD_TERMINATED:
1343                                 bcopy(&acb->sense_data, &ccb->csio.sense_data,
1344                                       ccb->csio.sense_len);
1345                                 ccb->ccb_h.status |= CAM_AUTOSNS_VALID;
1346                                 ccb->csio.sense_resid = acb->queue.sense_len;
1347                                 /* FALLTHROUGH */
1348                         default:
1349                                 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR
1350                                                   |  CAM_DEV_QFRZN;
1351                                 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
1352                                 break;
1353                         }
1354                         adwfreeacb(adw, acb);
1355                         xpt_done(ccb);
1356                 } else {
1357                         adwprocesserror(adw, acb);
1358                 }
1359         }
1360 }
1361
1362 static void
1363 adwprocesserror(struct adw_softc *adw, struct acb *acb)
1364 {
1365         union ccb *ccb;
1366
1367         ccb = acb->ccb;
1368         if (acb->queue.done_status == QD_ABORTED_BY_HOST) {
1369                 ccb->ccb_h.status = CAM_REQ_ABORTED;
1370         } else {
1371
1372                 switch (acb->queue.host_status) {
1373                 case QHSTA_M_SEL_TIMEOUT:
1374                         ccb->ccb_h.status = CAM_SEL_TIMEOUT;
1375                         break;
1376                 case QHSTA_M_SXFR_OFF_UFLW:
1377                 case QHSTA_M_SXFR_OFF_OFLW:
1378                 case QHSTA_M_DATA_OVER_RUN:
1379                         ccb->ccb_h.status = CAM_DATA_RUN_ERR;
1380                         break;
1381                 case QHSTA_M_SXFR_DESELECTED:
1382                 case QHSTA_M_UNEXPECTED_BUS_FREE:
1383                         ccb->ccb_h.status = CAM_UNEXP_BUSFREE;
1384                         break;
1385                 case QHSTA_M_SCSI_BUS_RESET:
1386                 case QHSTA_M_SCSI_BUS_RESET_UNSOL:
1387                         ccb->ccb_h.status = CAM_SCSI_BUS_RESET;
1388                         break;
1389                 case QHSTA_M_BUS_DEVICE_RESET:
1390                         ccb->ccb_h.status = CAM_BDR_SENT;
1391                         break;
1392                 case QHSTA_M_QUEUE_ABORTED:
1393                         /* BDR or Bus Reset */
1394                         printf("Saw Queue Aborted\n");
1395                         ccb->ccb_h.status = adw->last_reset;
1396                         break;
1397                 case QHSTA_M_SXFR_SDMA_ERR:
1398                 case QHSTA_M_SXFR_SXFR_PERR:
1399                 case QHSTA_M_RDMA_PERR:
1400                         ccb->ccb_h.status = CAM_UNCOR_PARITY;
1401                         break;
1402                 case QHSTA_M_WTM_TIMEOUT:
1403                 case QHSTA_M_SXFR_WD_TMO:
1404                 {
1405                         /* The SCSI bus hung in a phase */
1406                         xpt_print_path(adw->path);
1407                         printf("Watch Dog timer expired.  Reseting bus\n");
1408                         adw_reset_bus(adw);
1409                         break;
1410                 }
1411                 case QHSTA_M_SXFR_XFR_PH_ERR:
1412                         ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1413                         break;
1414                 case QHSTA_M_SXFR_UNKNOWN_ERROR:
1415                         break;
1416                 case QHSTA_M_BAD_CMPL_STATUS_IN:
1417                         /* No command complete after a status message */
1418                         ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1419                         break;
1420                 case QHSTA_M_AUTO_REQ_SENSE_FAIL:
1421                         ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
1422                         break;
1423                 case QHSTA_M_INVALID_DEVICE:
1424                         ccb->ccb_h.status = CAM_PATH_INVALID;
1425                         break;
1426                 case QHSTA_M_NO_AUTO_REQ_SENSE:
1427                         /*
1428                          * User didn't request sense, but we got a
1429                          * check condition.
1430                          */
1431                         ccb->csio.scsi_status = acb->queue.scsi_status;
1432                         ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1433                         break;
1434                 default:
1435                         panic("%s: Unhandled Host status error %x",
1436                               adw_name(adw), acb->queue.host_status);
1437                         /* NOTREACHED */
1438                 }
1439         }
1440         if ((acb->state & ACB_RECOVERY_ACB) != 0) {
1441                 if (ccb->ccb_h.status == CAM_SCSI_BUS_RESET
1442                  || ccb->ccb_h.status == CAM_BDR_SENT)
1443                         ccb->ccb_h.status = CAM_CMD_TIMEOUT;
1444         }
1445         if (ccb->ccb_h.status != CAM_REQ_CMP) {
1446                 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
1447                 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1448         }
1449         adwfreeacb(adw, acb);
1450         xpt_done(ccb);
1451 }
1452
1453 static void
1454 adwtimeout(void *arg)
1455 {
1456         struct acb           *acb;
1457         union  ccb           *ccb;
1458         struct adw_softc     *adw;
1459         adw_idle_cmd_status_t status;
1460         int                   target_id;
1461         int                   s;
1462
1463         acb = (struct acb *)arg;
1464         ccb = acb->ccb;
1465         adw = (struct adw_softc *)ccb->ccb_h.ccb_adw_ptr;
1466         xpt_print_path(ccb->ccb_h.path);
1467         printf("ACB %p - timed out\n", (void *)acb);
1468
1469         s = splcam();
1470
1471         if ((acb->state & ACB_ACTIVE) == 0) {
1472                 xpt_print_path(ccb->ccb_h.path);
1473                 printf("ACB %p - timed out CCB already completed\n",
1474                        (void *)acb);
1475                 splx(s);
1476                 return;
1477         }
1478
1479         acb->state |= ACB_RECOVERY_ACB;
1480         target_id = ccb->ccb_h.target_id;
1481
1482         /* Attempt a BDR first */
1483         status = adw_idle_cmd_send(adw, ADW_IDLE_CMD_DEVICE_RESET,
1484                                    ccb->ccb_h.target_id);
1485         splx(s);
1486         if (status == ADW_IDLE_CMD_SUCCESS) {
1487                 printf("%s: BDR Delivered.  No longer in timeout\n",
1488                        adw_name(adw));
1489                 adw_handle_device_reset(adw, target_id);
1490         } else {
1491                 adw_reset_bus(adw);
1492                 xpt_print_path(adw->path);
1493                 printf("Bus Reset Delivered.  No longer in timeout\n");
1494         }
1495 }
1496
1497 static void
1498 adw_handle_device_reset(struct adw_softc *adw, u_int target)
1499 {
1500         struct cam_path *path;
1501         cam_status error;
1502
1503         error = xpt_create_path(&path, /*periph*/NULL, cam_sim_path(adw->sim),
1504                                 target, CAM_LUN_WILDCARD);
1505
1506         if (error == CAM_REQ_CMP) {
1507                 xpt_async(AC_SENT_BDR, path, NULL);
1508                 xpt_free_path(path);
1509         }
1510         adw->last_reset = CAM_BDR_SENT;
1511 }
1512
1513 static void
1514 adw_handle_bus_reset(struct adw_softc *adw, int initiated)
1515 {
1516         if (initiated) {
1517                 /*
1518                  * The microcode currently sets the SCSI Bus Reset signal
1519                  * while handling the AscSendIdleCmd() IDLE_CMD_SCSI_RESET
1520                  * command above.  But the SCSI Bus Reset Hold Time in the
1521                  * microcode is not deterministic (it may in fact be for less
1522                  * than the SCSI Spec. minimum of 25 us).  Therefore on return
1523                  * the Adv Library sets the SCSI Bus Reset signal for
1524                  * ADW_SCSI_RESET_HOLD_TIME_US, which is defined to be greater
1525                  * than 25 us.
1526                  */
1527                 u_int scsi_ctrl;
1528
1529                 scsi_ctrl = adw_inw(adw, ADW_SCSI_CTRL) & ~ADW_SCSI_CTRL_RSTOUT;
1530                 adw_outw(adw, ADW_SCSI_CTRL, scsi_ctrl | ADW_SCSI_CTRL_RSTOUT);
1531                 DELAY(ADW_SCSI_RESET_HOLD_TIME_US);
1532                 adw_outw(adw, ADW_SCSI_CTRL, scsi_ctrl);
1533
1534                 /*
1535                  * We will perform the async notification when the
1536                  * SCSI Reset interrupt occurs.
1537                  */
1538         } else
1539                 xpt_async(AC_BUS_RESET, adw->path, NULL);
1540         adw->last_reset = CAM_SCSI_BUS_RESET;
1541 }