4 * Modified by Luigi Rizzo (luigi@iet.unipi.it)
6 * The low level driver for the AD1848/CS4248 codec chip which is used for
7 * example in the MS Sound System.
9 * The CS4231 which is used in the GUS MAX and some other cards is upwards
10 * compatible with AD1848 and this driver is able to drive it.
12 * CS4231A and AD1845 are upward compatible with CS4231. However the new
13 * features of these chips are different.
15 * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU). CS4232A is
16 * an improved version of CS4232.
18 * CS4236 is also a PnP audio chip similar to the 4232
20 * OPTi931 is another high-end 1848-type chip. It differs in the use
21 * of the high 16 registers and configuration stuff. Luckily, being a
22 * PnP device, we can avoid black magic to identify the chip and be
23 * sure of its identity.
25 * Copyright by Hannu Savolainen 1994, 1995
27 * Redistribution and use in source and binary forms, with or without
28 * modification, are permitted provided that the following conditions are
29 * met: 1. Redistributions of source code must retain the above copyright
30 * notice, this list of conditions and the following disclaimer. 2.
31 * Redistributions in binary form must reproduce the above copyright notice,
32 * this list of conditions and the following disclaimer in the documentation
33 * and/or other materials provided with the distribution.
35 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
36 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
37 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
38 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
39 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
41 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
42 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * Modified: Riccardo Facchetti 24 Mar 1995 - Added the Audio Excel DSP 16
48 * initialization routine.
50 * $FreeBSD: src/sys/i386/isa/sound/ad1848.c,v 1.30 1999/12/01 14:15:30 nyan Exp $
51 * $DragonFly: src/sys/dev/sound/isa/i386/Attic/ad1848.c,v 1.2 2003/06/17 04:28:38 dillon Exp $
56 #include <i386/isa/sound/sound_config.h>
58 #if defined(CONFIG_AD1848)
60 #include <i386/isa/sound/ad1848_mixer.h>
61 #include <i386/isa/sound/iwdefs.h>
63 #if defined(CONFIG_CS4232)
64 extern struct isa_driver cssdriver;
66 extern struct isa_driver mssdriver;
69 extern void IwaveStopDma(BYTE path);
74 int dual_dma; /* 1, when two DMA channels allocated */
76 u_char saved_regs[16];
97 /* Mixer parameters */
99 int supported_devices;
100 int supported_rec_devices;
103 volatile u_long timer_ticks;
109 static int nr_ad1848_devs = 0;
110 static volatile char irq2dev[17] =
111 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1};
113 static int timer_installed = -1;
114 static int mute_flag = 0;
115 static char mixer2codec[MAX_MIXER_DEV] = {0};
117 static int ad_format_mask[MD_MAXMODE /* devc->mode */ ] =
120 /* 1 - AD1848 */ AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
123 * AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE |
127 /* 2 - CS4231 */ AFMT_U8 | AFMT_S16_LE | AFMT_U16_LE,
130 * AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE |
134 /* 3 - CS4231A */ AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
135 /* 4 - AD1845 */ AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
136 /* 5 - CS4236 */ AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
139 static ad1848_info dev_info[MAX_AUDIO_DEV];
141 #define io_Index_Addr(d) ((d)->base)
142 #define io_Indexed_Data(d) ((d)->base+1)
143 #define io_Status(d) ((d)->base+2)
144 #define io_Polled_IO(d) ((d)->base+3)
146 static int ad1848_open(int dev, int mode);
147 static void ad1848_close(int dev);
148 static int ad1848_ioctl(int dev, u_int cmd, ioctl_arg arg, int local);
149 static void ad1848_output_block(int dev, u_long buf, int count, int intrflag, int dma_restart);
150 static void ad1848_start_input(int dev, u_long buf, int count, int intrflag, int dma_restart);
151 static int ad1848_prepare_for_IO(int dev, int bsize, int bcount);
152 static void ad1848_reset(int dev);
153 static void ad1848_halt(int dev);
154 static void ad1848_halt_input(int dev);
155 static void ad1848_halt_output(int dev);
156 static void ad1848_trigger(int dev, int bits);
157 static int ad1848_tmr_install(int dev);
158 static void ad1848_tmr_reprogram(int dev);
161 * AD_WAIT_INIT waits if we are initializing the board and we cannot modify
164 #define AD_WAIT_INIT(x) {int t=x; while(t>0 && inb(devc->base) == 0x80) t-- ; }
166 short ipri_to_irq(u_short ipri);
172 /* this isn't ideal but should work */
173 ad1848_interrupt(-1);
175 static short unit_to_irq[4] = {9, -1, -1, -1};
176 struct isa_device *dev;
178 if (unit_to_irq[unit] > 0)
179 ad1848_interrupt(unit_to_irq[unit]);
181 #if defined(CONFIG_CS4232)
182 dev = find_isadev(isa_devtab_null, &cssdriver, unit);
184 dev = find_isadev(isa_devtab_null, &mssdriver, unit);
187 printf("ad1848: Couldn't determine unit\n");
189 unit_to_irq[unit] = ipri_to_irq(dev->id_irq);
190 ad1848_interrupt(unit_to_irq[unit]);
197 ad_read(ad1848_info * devc, int reg)
202 AD_WAIT_INIT(900000);
204 outb(io_Index_Addr(devc), (u_char) (reg & 0xff) | devc->MCE_bit);
205 x = inb(io_Indexed_Data(devc));
212 ad_write(ad1848_info * devc, int reg, u_char data)
219 outb(io_Index_Addr(devc), (u_char) (reg & 0xff) | devc->MCE_bit);
220 outb(io_Indexed_Data(devc), (u_char) (data & 0xff));
225 wait_for_calibration(ad1848_info * devc)
230 * Wait until the auto calibration process has finished.
232 * 1) Wait until the chip becomes ready (reads don't return 0x80).
233 * 2) Wait until the ACI bit of I11 gets on and then off.
236 AD_WAIT_INIT(100000);
237 if (inb(devc->base) & 0x80)
238 printf("ad1848: Auto calibration timed out(1).\n");
241 while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
243 if (!(ad_read(devc, 11) & 0x20))
247 while (timeout > 0 && ad_read(devc, 11) & 0x20)
249 if (ad_read(devc, 11) & 0x20)
250 printf("ad1848: Auto calibration timed out(3).\n");
254 ad_mute(ad1848_info * devc)
262 * Save old register settings and mute output channels
264 for (i = 6; i < 8; i++) {
265 prev = devc->saved_regs[i] = ad_read(devc, i);
266 ad_write(devc, i, prev | 0x80);
271 ad_unmute(ad1848_info * devc)
277 * Restore back old volume registers (unmute)
279 for (i = 6; i < 8; i++)
280 ad_write(devc, i, devc->saved_regs[i] & ~0x80);
284 ad_enter_MCE(ad1848_info * devc)
289 devc->MCE_bit = 0x40;
291 if ( ( inb(io_Index_Addr(devc)) & 0x40) == 0 )
292 outb(io_Index_Addr(devc), devc->MCE_bit);
297 ad_leave_MCE(ad1848_info * devc)
306 devc->MCE_bit = 0x00;
307 prev = inb(io_Index_Addr(devc));
308 /* XXX the next call is redundant ? */
309 outb(io_Index_Addr(devc), 0x00); /* Clear the MCE bit */
311 if ((prev & 0x40) == 0) { /* Not in MCE mode */
315 outb(io_Index_Addr(devc), 0x00); /* Clear the MCE bit */
316 wait_for_calibration(devc);
322 ad1848_set_recmask(ad1848_info * devc, int mask)
327 mask &= devc->supported_rec_devices;
330 for (i = 0; i < 32; i++)/* Count selected device bits */
335 mask = SOUND_MASK_MIC;
336 else if (n != 1) { /* Too many devices selected */
337 mask &= ~devc->recmask; /* Filter out active settings */
340 for (i = 0; i < 32; i++) /* Count selected device bits */
345 mask = SOUND_MASK_MIC;
352 case SOUND_MASK_LINE:
353 case SOUND_MASK_LINE3:
358 case SOUND_MASK_LINE1:
362 case SOUND_MASK_IMIX:
367 mask = SOUND_MASK_MIC;
372 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
373 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
375 devc->recmask = mask;
380 change_bits(u_char *regval, int dev, int chn, int newval)
385 if (mix_devices[dev][chn].polarity == 1) /* Reverse */
386 newval = 100 - newval;
388 mask = (1 << mix_devices[dev][chn].nbits) - 1;
389 shift = mix_devices[dev][chn].bitpos;
390 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
392 *regval &= ~(mask << shift); /* Clear bits */
393 *regval |= (newval & mask) << shift; /* Set new value */
397 ad1848_mixer_get(ad1848_info * devc, int dev)
399 if (!((1 << dev) & devc->supported_devices))
402 return devc->levels[dev];
405 #define CLMICI 0x00781601
406 #define CRMICI 0x00791701
409 ad1848_mixer_set(ad1848_info * devc, int dev, int value)
411 int left = value & 0x000000ff;
412 int right = (value & 0x0000ff00) >> 8;
417 /* u_char clci, crmici, clmici, clici, crici; */
424 if (mix_devices[dev][RIGHT_CHN].nbits == 0) /* Mono control */
427 retvol = left | (right << 8);
430 left = mix_cvt[left];
431 right = mix_cvt[right];
434 left = mix_cvt[left];
435 right = mix_cvt[right];
440 if (!(devc->supported_devices & (1 << dev)))
443 if (mix_devices[dev][LEFT_CHN].nbits == 0)
446 devc->levels[dev] = retvol;
449 * Set the left channel
451 /* IwaveCodecMode(CODEC_MODE3); Default codec mode */
453 regoffs = mix_devices[dev][LEFT_CHN].regno;
454 val = ad_read(devc, regoffs);
456 change_bits(&val, dev, LEFT_CHN, left);
457 ad_write(devc, regoffs, val);
458 devc->saved_regs[regoffs] = val;
461 * Set the right channel
464 if (mix_devices[dev][RIGHT_CHN].nbits == 0)
465 return retvol; /* Was just a mono channel */
467 regoffs = mix_devices[dev][RIGHT_CHN].regno;
468 val = ad_read(devc, regoffs);
469 change_bits(&val, dev, RIGHT_CHN, right);
470 ad_write(devc, regoffs, val);
471 devc->saved_regs[regoffs] = val;
477 ad1848_mixer_reset(ad1848_info * devc)
482 if (devc->mode != MD_1848)
483 devc->supported_devices = MODE2_MIXER_DEVICES;
485 devc->supported_devices = MODE1_MIXER_DEVICES;
487 devc->supported_rec_devices = MODE1_REC_DEVICES;
489 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
490 if (devc->supported_devices & (1 << i))
491 ad1848_mixer_set(devc, i, default_mixer_levels[i]);
492 ad1848_set_recmask(devc, SOUND_MASK_MIC);
496 ad1848_mixer_ioctl(int dev, u_int cmd, ioctl_arg arg)
499 int codec_dev = mixer2codec[dev];
506 devc = (ad1848_info *) audio_devs[codec_dev]->devc;
508 if (((cmd >> 8) & 0xff) == 'M') {
510 switch (cmd & 0xff) {
511 case SOUND_MIXER_RECSRC:
512 return *(int *) arg = ad1848_set_recmask(devc, (*(int *) arg));
516 return *(int *) arg = ad1848_mixer_set(devc, cmd & 0xff, (*(int *) arg));
519 switch (cmd & 0xff) { /* Return parameters */
521 case SOUND_MIXER_RECSRC:
522 return *(int *) arg = devc->recmask;
525 case SOUND_MIXER_DEVMASK:
526 return *(int *) arg = devc->supported_devices;
529 case SOUND_MIXER_STEREODEVS:
530 return *(int *) arg = devc->supported_devices & ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
533 case SOUND_MIXER_RECMASK:
534 return *(int *) arg = devc->supported_rec_devices;
537 case SOUND_MIXER_CAPS:
538 return *(int *) arg = SOUND_CAP_EXCL_INPUT;
542 return *(int *) arg = ad1848_mixer_get(devc, cmd & 0xff);
548 static struct audio_operations ad1848_pcm_operations[MAX_AUDIO_DEV] =
551 "Generic AD1848 codec",
552 /* DMA_AUTOMODE | DMA_DUPLEX, */
554 AFMT_U8, /* Will be set later */
561 ad1848_prepare_for_IO,
562 ad1848_prepare_for_IO,
573 static struct mixer_operations ad1848_mixer_operations =
575 "AD1848/CS4248/CS4231/CS4236",
580 ad1848_open(int dev, int mode)
582 ad1848_info *devc = NULL;
584 int otherside = audio_devs[dev]->otherside;
586 if (dev < 0 || dev >= num_audiodevs)
589 if (otherside != -1) {
590 if (audio_devs[otherside]->busy)
593 if (audio_devs[dev]->busy)
596 devc = (ad1848_info *) audio_devs[dev]->devc;
599 if (audio_devs[dev]->busy) {
605 if (audio_devs[dev]->flags & DMA_DUPLEX) {
608 devc->intr_active = 0;
609 audio_devs[dev]->busy = 1;
611 ad1848_trigger(dev, 0);
614 * Mute output until the playback really starts. This decreases
623 ad1848_close(int dev)
626 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
627 int otherside = audio_devs[dev]->otherside;
629 if (otherside != -1) {
630 if (audio_devs[otherside]->busy)
633 DEB(printf("ad1848_close(void)\n"));
639 ad_write(devc, 9, ad_read(devc, 9) & ~0x1);
640 outb(io_Status(devc), 0); /* Clear interrupt status */
642 * ad_write (devc, 15,0); ad_write (devc, 14,0);
644 devc->irq_mode &= ~PCM_ENABLE_OUTPUT;
646 devc->intr_active = 0;
651 audio_devs[dev]->busy = 0;
657 set_speed(ad1848_info * devc, int arg)
660 * The sampling speed is encoded in the least significant nible of
661 * I8. The LSB selects the clock source (0=24.576 MHz, 1=16.9344 Mhz)
662 * and other three bits select the divisor (indirectly):
664 * The available speeds are in the following table. Keep the speeds in
665 * the increasing order.
672 static speed_struct speed_table[] = {
673 {5510, (0 << 1) | 1},
674 {5510, (0 << 1) | 1},
675 {6620, (7 << 1) | 1},
676 {8000, (0 << 1) | 0},
677 {9600, (7 << 1) | 0},
678 {11025, (1 << 1) | 1},
679 {16000, (1 << 1) | 0},
680 {18900, (2 << 1) | 1},
681 {22050, (3 << 1) | 1},
682 {27420, (2 << 1) | 0},
683 {32000, (3 << 1) | 0},
684 {33075, (6 << 1) | 1},
685 {37800, (4 << 1) | 1},
686 {44100, (5 << 1) | 1},
687 {48000, (6 << 1) | 0}
690 int i, n, selected = -1;
692 n = sizeof(speed_table) / sizeof(speed_struct);
694 if (devc->mode == MD_1845) { /* AD1845 has different timer than others */
695 RANGE (arg, 4000, 50000) ;
698 devc->speed_bits = speed_table[selected].bits;
701 if (arg < speed_table[0].speed)
703 if (arg > speed_table[n - 1].speed)
706 for (i = 1 /* really */ ; selected == -1 && i < n; i++)
707 if (speed_table[i].speed == arg)
709 else if (speed_table[i].speed > arg) {
712 diff1 = arg - speed_table[i - 1].speed;
713 diff2 = speed_table[i].speed - arg;
720 if (selected == -1) {
721 printf("ad1848: Can't find speed???\n");
724 devc->speed = speed_table[selected].speed;
725 devc->speed_bits = speed_table[selected].bits;
730 set_channels(ad1848_info * devc, int arg)
732 if (arg != 1 && arg != 2)
733 return devc->channels;
735 devc->channels = arg;
740 set_format(ad1848_info * devc, int arg)
742 static struct format_tbl {
749 { AFMT_IMA_ADPCM, 5 } ,
757 int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
760 if (!(arg & ad_format_mask[devc->mode]))
763 devc->audio_format = arg;
765 for (i = 0; i < n; i++)
766 if (format2bits[i].format == arg) {
767 if ((devc->format_bits = format2bits[i].bits) == 0)
768 return devc->audio_format = AFMT_U8; /* Was not supported */
771 /* Still hanging here. Something must be terribly wrong */
772 devc->format_bits = 0;
773 return devc->audio_format = AFMT_U8;
776 /* XXX check what is arg, (int) or *(int *) lr970705 */
778 ad1848_ioctl(int dev, u_int cmd, ioctl_arg arg, int local)
780 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
783 case SOUND_PCM_WRITE_RATE:
785 return set_speed(devc, (int) arg);
786 return *(int *) arg = set_speed(devc, (*(int *) arg));
788 case SOUND_PCM_READ_RATE:
791 return *(int *) arg = devc->speed;
793 case SNDCTL_DSP_STEREO:
795 return set_channels(devc, (int) arg + 1) - 1;
796 return *(int *) arg = set_channels(devc, (*(int *) arg) + 1) - 1;
798 case SOUND_PCM_WRITE_CHANNELS:
800 return set_channels(devc, (int) arg);
801 return *(int *) arg = set_channels(devc, (*(int *) arg));
803 case SOUND_PCM_READ_CHANNELS:
805 return devc->channels;
806 return *(int *) arg = devc->channels;
808 case SNDCTL_DSP_SAMPLESIZE:
810 return set_format(devc, (int) arg);
811 return *(int *) arg = set_format(devc, (*(int *) arg));
813 case SOUND_PCM_READ_BITS:
815 return devc->audio_format;
816 return *(int *) arg = devc->audio_format;
822 return *(int *) arg = 1;
827 return *(int *) arg = 1;
836 ad1848_output_block(int dev, u_long buf, int count, int intrflag, int dma_restart)
839 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
842 if (devc->audio_format == AFMT_IMA_ADPCM) {
845 if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
848 if (devc->channels > 1)
854 if ( devc->irq_mode & PCM_ENABLE_OUTPUT &&
855 audio_devs[dev]->flags & DMA_AUTOMODE && intrflag &&
856 cnt == devc->xfer_count) {
857 devc->irq_mode |= PCM_ENABLE_OUTPUT;
858 devc->intr_active = 1;
865 DMAbuf_start_dma(dev, buf, count, 1);
867 ad_write(devc, 15, (u_char) (cnt & 0xff));
868 ad_write(devc, 14, (u_char) ((cnt >> 8) & 0xff));
870 devc->xfer_count = cnt;
871 devc->irq_mode |= PCM_ENABLE_OUTPUT;
872 devc->intr_active = 1;
877 ad1848_start_input(int dev, u_long buf, int count,
878 int intrflag, int dma_restart)
881 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
884 if (devc->audio_format == AFMT_IMA_ADPCM)
886 else if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
888 if (devc->channels > 1)
892 if ( devc->irq_mode & PCM_ENABLE_INPUT &&
893 audio_devs[dev]->flags & DMA_AUTOMODE && intrflag &&
894 cnt == devc->xfer_count) {
895 devc->irq_mode |= PCM_ENABLE_INPUT;
896 devc->intr_active = 1;
897 return; /* Auto DMA mode on. No need to react */
902 /* ad1848_halt (dev); */
903 DMAbuf_start_dma(dev, buf, count, 0);
905 if (devc->mode == MD_1848 || !devc->dual_dma) {/* Single DMA chan. mode */
906 ad_write(devc, 15, (u_char) (cnt & 0xff));
907 ad_write(devc, 14, (u_char) ((cnt >> 8) & 0xff));
908 } else { /* Dual DMA channel mode */
909 ad_write(devc, 31, (u_char) (cnt & 0xff));
910 ad_write(devc, 30, (u_char) ((cnt >> 8) & 0xff));
913 /* ad_write (devc, 9, ad_read (devc, 9) | 0x02); *//* Capture enable */
916 devc->xfer_count = cnt;
917 devc->irq_mode |= PCM_ENABLE_INPUT;
918 devc->intr_active = 1;
923 ad1848_prepare_for_IO(int dev, int bsize, int bcount)
927 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
932 fs = devc->speed_bits | (devc->format_bits << 5);
934 if (devc->channels > 1)
940 if (devc->mode == MD_1845) { /* Use alternate speed select regs */
941 fs &= 0xf0; /* Mask off the rate select bits */
943 ad_write(devc, 22, (devc->speed >> 8) & 0xff); /* Speed MSB */
944 ad_write(devc, 23, devc->speed & 0xff); /* Speed LSB */
947 ad_enter_MCE(devc); /* Enables changes to the format select reg */
949 ad_write(devc, 8, fs);
952 * Write to I8 starts resyncronization. Wait until it completes.
957 * If mode == 2 (CS4231), set I28 also. It's the capture format
960 if (devc->mode != MD_1848) {
961 ad_write(devc, 28, fs);
964 * Write to I28 starts resyncronization. Wait until it completes.
969 ad_write(devc, 9, ad_read(devc, 9) & ~0x08);
975 devc->xfer_count = 0;
976 #ifdef CONFIG_SEQUENCER
977 if (dev == timer_installed && devc->timer_running)
978 if ((fs & 0x01) != (old_fs & 0x01)) {
979 ad1848_tmr_reprogram(dev);
986 ad1848_reset(int dev)
994 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1002 ad_write(devc, 9, ad_read(devc, 9) & ~0x03); /* Stop DMA */
1004 ad_write(devc, 14, 0); /* Clear DMA counter */
1005 ad_write(devc, 15, 0); /* Clear DMA counter */
1007 if (devc->mode != MD_1848) {
1008 ad_write(devc, 30, 0); /* Clear DMA counter */
1009 ad_write(devc, 31, 0); /* Clear DMA counter */
1012 for (timeout = 0; timeout < 1000 && !(inb(io_Status(devc)) & 0x01);
1013 timeout++); /* Wait for interrupt */
1015 outb(io_Status(devc), 0); /* Clear interrupt status */
1019 /* DMAbuf_reset_dma (dev); */
1024 ad1848_halt_input(int dev)
1026 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1029 if (devc->mode == MD_1848) {
1033 playing = ad_read(devc, 9);
1034 if (!(playing & 0x2))
1040 ad_write(devc, 9, playing & ~0x02); /* Stop capture */
1042 outb(io_Status(devc), 0); /* Clear interrupt status */
1043 outb(io_Status(devc), 0); /* Clear interrupt status */
1045 devc->irq_mode &= ~PCM_ENABLE_INPUT;
1051 ad1848_halt_output(int dev)
1053 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1057 playing = ad_read(devc, 9);
1058 if (!(playing & 0x1)) {
1059 devc->irq_mode &= ~PCM_ENABLE_OUTPUT;
1062 /* IwaveStopDma(PLAYBACK); */
1063 if (devc->mode == MD_1848) {
1068 /* ad_mute (devc); */
1070 ad_write(devc, 9, playing & ~0x1);
1071 outb(io_Status(devc), 0); /* Clear interrupt status */
1073 * ad_write (devc, 15,0); ad_write (devc, 14,0);
1075 devc->irq_mode &= ~PCM_ENABLE_OUTPUT;
1081 ad1848_trigger(int dev, int state)
1083 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1088 state &= devc->irq_mode;
1090 tmp = ad_read(devc, 9) & ~0x03;
1091 if (state & PCM_ENABLE_INPUT)
1093 if (state & PCM_ENABLE_OUTPUT) {
1096 ad_write(devc, 9, tmp);
1103 ad1848_detect(int io_base, int *ad_flags, sound_os_info * osp)
1105 static int last_probe_addr=0, last_result=0; /* to avoid multiple probes*/
1107 ad1848_info *devc = &dev_info[nr_ad1848_devs];
1108 u_char tmp, tmp1, tmp2 ;
1110 DDB(printf("ad1848_detect(%x)\n", io_base));
1111 if (io_base == last_probe_addr)
1114 last_result = 0; /* default value for detect */
1115 last_probe_addr = io_base ;
1121 if (nr_ad1848_devs >= MAX_AUDIO_DEV) {
1122 DDB(printf("ad1848 detect error - step 0\n"));
1125 devc->base = io_base;
1127 devc->timer_running = 0;
1128 devc->MCE_bit = 0x40;
1131 devc->chip_name = "AD1848";
1132 devc->mode = MD_1848; /* AD1848 or CS4248 */
1136 * Check that the I/O address is in use.
1138 * The bit 0x80 of the base I/O port is known to be 0 after the chip has
1139 * performed its power on initialization. Just assume this has
1140 * happened before the OS is starting.
1142 * If the I/O address is unused, it typically returns 0xff.
1145 DDB(printf("ad1848_detect() - step A\n"));
1147 if ((inb(devc->base) & 0x80) != 0x00) { /* Not a AD1848 */
1148 DDB(printf("ad1848 detect error - step A,"
1149 " inb(base) = 0x%02x, want 0XXX.XXXX\n",
1154 * Test if it's possible to change contents of the indirect
1155 * registers. Registers 0 and 1 are ADC volume registers. The bit
1156 * 0x10 is read only so try to avoid using it.
1159 DDB(printf("ad1848_detect() - step B, test indirect register\n"));
1161 ad_write(devc, 0, 0xaa);
1162 ad_write(devc, 1, 0x45);/* 0x55 with bit 0x10 clear */
1163 tmp1 = ad_read(devc, 0) ;
1164 tmp2 = ad_read(devc, 1) ;
1165 if ( tmp1 != 0xaa || tmp2 != 0x45) {
1166 DDB(printf("ad1848 detect error - step B (0x%02x/0x%02x) want 0xaa/0x45\n", tmp1, tmp2));
1169 DDB(printf("ad1848_detect() - step C\n"));
1170 ad_write(devc, 0, 0x45);
1171 ad_write(devc, 1, 0xaa);
1172 tmp1 = ad_read(devc, 0) ;
1173 tmp2 = ad_read(devc, 1) ;
1175 if (tmp1 != 0x45 || tmp2 != 0xaa) {
1176 DDB(printf("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1181 * The indirect register I12 has some read only bits. Lets try to
1185 DDB(printf("ad1848_detect() - step D, last 4 bits of I12 readonly\n"));
1186 tmp = ad_read(devc, 12);
1187 ad_write(devc, 12, (~tmp) & 0x0f);
1188 tmp1 = ad_read(devc, 12);
1190 if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
1191 DDB(printf("ad1848 detect error - step D, I12 (0x%02x was 0x%02x)\n",
1197 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1199 * 0x0A=RevC. also CS4231/CS4231A and OPTi931
1204 * The original AD1848/CS4248 has just 15 indirect registers. This
1205 * means that I0 and I16 should return the same value (etc.). Ensure
1206 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1210 DDB(printf("ad1848_detect() - step F\n"));
1211 ad_write(devc, 12, 0); /* Mode2=disabled */
1213 for (i = 0; i < 16; i++)
1214 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
1215 DDB(printf("ad1848 detect warning - step F(I%d/0x%02x/0x%02x)\n",
1218 * note - this seems to fail on the 4232 on I11. So we just break
1221 break ; /* return 0; */
1224 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
1225 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
1227 * On the OPTi931, however, I12 is readonly and only contains the
1228 * chip revision ID (as in the CS4231A). The upper bits return 0.
1231 DDB(printf("ad1848_detect() - step G\n"));
1232 ad_write(devc, 12, 0x40); /* Set mode2, clear 0x80 */
1234 tmp1 = ad_read(devc, 12);
1237 *ad_flags |= AD_F_CS4248;
1239 devc->chip_name = "CS4248"; /* Our best knowledge just now */
1241 if ((tmp1 & 0xf0) == 0x00) {
1242 printf("this should be an OPTi931\n");
1243 } else if ((tmp1 & 0xc0) == 0xC0) {
1245 * The 4231 has bit7=1 always, and bit6 we just set to 1.
1246 * We want to check that this is really a CS4231
1247 * Verify that setting I0 doesn't change I16.
1249 DDB(printf("ad1848_detect() - step H\n"));
1250 ad_write(devc, 16, 0); /* Set I16 to known value */
1252 ad_write(devc, 0, 0x45);
1253 if ((tmp1 = ad_read(devc, 16)) != 0x45) { /* No change -> CS4231? */
1255 ad_write(devc, 0, 0xaa);
1256 if ((tmp1 = ad_read(devc, 16)) == 0xaa) { /* Rotten bits? */
1257 DDB(printf("ad1848 detect error - step H(%x)\n", tmp1));
1261 * Verify that some bits of I25 are read only.
1264 DDB(printf("ad1848_detect() - step I\n"));
1265 tmp1 = ad_read(devc, 25); /* Original bits */
1266 ad_write(devc, 25, ~tmp1); /* Invert all bits */
1267 if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7)) {
1271 * It's at least CS4231
1273 devc->chip_name = "CS4231";
1274 devc->mode = MD_4231;
1277 * It could be an AD1845 or CS4231A as well.
1278 * CS4231 and AD1845 report the same revision info in I25
1279 * while the CS4231A reports different.
1282 DDB(printf("ad1848_detect() - step I\n"));
1283 id = ad_read(devc, 25) & 0xe7;
1285 * b7-b5 = version number;
1294 devc->chip_name = "CS4231A";
1295 devc->mode = MD_4231A;
1299 devc->chip_name = "CS4232";
1300 devc->mode = MD_4231A;
1304 /* strange: the 4231 data sheet says b4-b3 are XX
1305 * so this should be the same as 0xa2
1307 devc->chip_name = "CS4232A";
1308 devc->mode = MD_4231A;
1313 * It must be a CS4231 or AD1845. The register I23
1314 * of CS4231 is undefined and it appears to be read
1315 * only. AD1845 uses I23 for setting sample rate.
1316 * Assume the chip is AD1845 if I23 is changeable.
1319 tmp = ad_read(devc, 23);
1321 ad_write(devc, 23, ~tmp);
1322 if (ad_read(devc, 23) != tmp) { /* AD1845 ? */
1323 devc->chip_name = "AD1845";
1324 devc->mode = MD_1845;
1326 ad_write(devc, 23, tmp); /* Restore */
1329 case 0x83: /* CS4236 */
1330 case 0x03: /* Mutant CS4236 on Intel PR440fx board */
1331 devc->chip_name = "CS4236";
1332 devc->mode = MD_4236;
1335 default: /* Assume CS4231 */
1336 printf("unknown id 0x%02x, assuming CS4231\n", id);
1337 devc->mode = MD_4231;
1341 ad_write(devc, 25, tmp1); /* Restore bits */
1343 DDB(printf("ad1848_detect() - step K\n"));
1346 DDB(printf("ad1848_detect() - step L\n"));
1349 if (devc->mode != MD_1848)
1350 *ad_flags |= AD_F_CS4231;
1352 DDB(printf("ad1848_detect() - Detected OK\n"));
1353 return (last_result = 1);
1357 ad1848_init(char *name, int io_base, int irq,
1358 int dma_playback, int dma_capture, int share_dma, sound_os_info * osp)
1362 * NOTE! If irq < 0, there is another driver which has allocated the
1363 * IRQ so that this driver doesn't need to allocate/deallocate it.
1364 * The actually used IRQ is ABS(irq).
1368 * Initial values for the indirect registers of CS4248/AD1848.
1370 static int init_values[] = {
1371 0xa8, /* MIXOUTL: src:mic, +20dB, gain +12dB */
1372 0xa8, /* MIXOUTR: src:mic, +20dB, gain +12dB */
1373 0x08, /* CDL Input: mute, +6dB */
1374 0x08, /* CDR Input: mute, +6dB */
1375 0x08, /* FML Input: mute, +6dB */
1376 0x08, /* FMR Input: mute, +6dB */
1377 0x80, /* DAC-L Input: enable, 0dB */
1378 0x80, /* DAC-R Input: enable, 0dB */
1379 /* 0xa8, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, */
1380 0x00, /* 8bit, lin, uns, mono, 8KHz */
1381 0x0c, /* dma-cap, dma-pb, autocal, single dma, disable cap/pb */
1382 0x02, /* int enable */
1383 0x00, /* clear error status */
1384 0x8a, /* rev. id (low bytes readonly) */
1386 0x00, /* playback upper base count */
1387 0x00, /* playback lower base count */
1389 /* Positions 16 to 31 just for CS4231 and newer devices */
1390 /* I16-I17: alt. feature enable on the 4231, but AUXL Input
1391 * on the OPTi931 (where the features are set elsewhere
1393 0x81, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
1394 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1398 ad1848_info *devc = &dev_info[nr_ad1848_devs];
1400 if (!ad1848_detect(io_base, NULL, osp))
1403 devc->irq = (irq > 0) ? irq : 0;
1405 devc->timer_ticks = 0;
1408 if (nr_ad1848_devs != 0) {
1409 bcopy((char *) &ad1848_pcm_operations[0],
1410 (char *) &ad1848_pcm_operations[nr_ad1848_devs],
1411 sizeof(struct audio_operations));
1413 for (i = 0; i < 16; i++)
1414 ad_write(devc, i, init_values[i]);
1416 ad_mute(devc); /* Initialize some variables */
1417 ad_unmute(devc); /* Leave it unmuted now */
1419 if (devc->mode > MD_1848) {
1420 if (dma_capture == dma_playback ||
1421 dma_capture == -1 || dma_playback == -1) {
1422 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1423 ad1848_pcm_operations[nr_ad1848_devs].flags &= ~DMA_DUPLEX;
1425 ad_write(devc, 9, ad_read(devc, 9) & ~0x04); /* Dual DMA mode */
1426 ad1848_pcm_operations[nr_ad1848_devs].flags |= DMA_DUPLEX;
1429 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1430 for (i = 16; i < 32; i++)
1431 ad_write(devc, i, init_values[i]);
1433 if (devc->mode == MD_4231A) {
1434 /* Enable full * calibration */
1435 ad_write(devc, 9, init_values[9] | 0x18);
1438 if (devc->mode == MD_1845) {
1439 /* Alternate freq select enabled */
1440 ad_write(devc, 27, init_values[27] | 0x08);
1443 ad1848_pcm_operations[nr_ad1848_devs].flags &= ~DMA_DUPLEX;
1444 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1447 outb(io_Status(devc), 0); /* Clear pending interrupts */
1449 if (name != NULL && name[0] != 0)
1450 snprintf(ad1848_pcm_operations[nr_ad1848_devs].name,
1451 sizeof(ad1848_pcm_operations[nr_ad1848_devs].name),
1452 "%s (%s)", name, devc->chip_name);
1454 snprintf(ad1848_pcm_operations[nr_ad1848_devs].name,
1455 sizeof(ad1848_pcm_operations[nr_ad1848_devs].name),
1456 "Generic audio codec (%s)", devc->chip_name);
1458 conf_printf2(ad1848_pcm_operations[nr_ad1848_devs].name,
1459 devc->base, devc->irq, dma_playback, dma_capture);
1462 /* ad1848_pcm_operations[nr_ad1848_devs].flags |= DMA_AUTOMODE ; */
1464 if (num_audiodevs < MAX_AUDIO_DEV) {
1465 audio_devs[my_dev = num_audiodevs++] =
1466 &ad1848_pcm_operations[nr_ad1848_devs];
1468 audio_devs[my_dev]->devc = devc;
1469 irq2dev[irq] = my_dev;
1470 if (snd_set_irq_handler(devc->irq, ad1848_interrupt, devc->osp)<0) {
1471 printf("ad1848: IRQ in use\n");
1474 if (devc->mode != MD_1848) {
1476 u_char tmp = ad_read(devc, 16);
1478 devc->timer_ticks = 0;
1480 ad_write(devc, 21, 0x00); /* Timer msb */
1481 ad_write(devc, 20, 0x10); /* Timer lsb */
1483 ad_write(devc, 16, tmp | 0x40); /* Enable timer */
1484 for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
1485 ad_write(devc, 16, tmp & ~0x40); /* Disable timer */
1487 if (devc->timer_ticks == 0)
1488 printf("[IRQ conflict???]");
1493 devc->irq_ok = 1; /* Couldn't test. assume it's OK */
1498 irq2dev[-irq] = devc->dev_no = my_dev;
1500 audio_devs[my_dev]->otherside = -1 ;
1501 audio_devs[my_dev]->flags |= DMA_AUTOMODE;
1502 audio_devs[my_dev]->dmachan1 = dma_playback;
1503 audio_devs[my_dev]->dmachan2 = dma_capture;
1504 audio_devs[my_dev]->buffsize = DSP_BUFFSIZE;
1505 audio_devs[my_dev]->devc = devc;
1506 audio_devs[my_dev]->format_mask = ad_format_mask[devc->mode];
1509 #ifdef CONFIG_SEQUENCER
1510 if (devc->mode != MD_1848 && devc->irq_ok)
1511 ad1848_tmr_install(my_dev);
1515 * Toggle the MCE bit. It completes the initialization phase.
1518 ad_enter_MCE(devc); /* In case the bit was off */
1521 if (num_mixers < MAX_MIXER_DEV) {
1522 mixer2codec[num_mixers] = my_dev + 1;
1523 audio_devs[my_dev]->mixer_dev = num_mixers;
1524 mixer_devs[num_mixers++] = &ad1848_mixer_operations;
1525 ad1848_mixer_reset(devc);
1528 printf("AD1848: Too many PCM devices available\n");
1532 ad1848_interrupt(int irq)
1538 if (irq < 0 || irq > 15)
1543 if (dev < 0 || dev >= num_audiodevs) {
1544 for (irq = 0; irq < 17; irq++)
1545 if (irq2dev[irq] != -1)
1549 printf("ad1848.c: Bogus interrupt %d\n", irq);
1554 devc = (ad1848_info *) audio_devs[dev]->devc;
1556 status = inb(io_Status(devc));
1558 if (status & 0x01) { /* we have an interrupt */
1559 int alt_stat = 0xff ;
1561 if (devc->mode != MD_1848) {
1563 * high-end devices have full-duplex dma and timer.
1564 * the exact reason for the interrupt is in reg. I24.
1565 * For old devices, we fake the interrupt bits, and
1566 * determine the real reason basing on the device mode.
1568 alt_stat = ad_read(devc, 24);
1569 if (alt_stat & 0x40) { /* Timer interrupt */
1570 devc->timer_ticks++;
1571 #ifdef CONFIG_SEQUENCER
1572 if (timer_installed == dev && devc->timer_running)
1573 sound_timer_interrupt();
1578 outb(io_Status(devc), 0); /* Clear interrupt status */
1580 if (audio_devs[dev]->busy) {
1582 if (devc->irq_mode & PCM_ENABLE_OUTPUT && alt_stat & 0x10)
1583 DMAbuf_outputintr(dev, 1);
1585 if (devc->irq_mode & PCM_ENABLE_INPUT && alt_stat & 0x20)
1586 DMAbuf_inputintr(dev);
1592 * Some extra code for the MS Sound System
1597 check_opl3(int base, struct address_info * hw_config)
1600 if (!opl3_detect(base, hw_config->osp))
1603 opl3_init(0, base, hw_config->osp);
1608 * this is the probe routine. Note, it is not necessary to
1609 * go through this for PnP devices, since they are already
1610 * indentified precisely using their PnP id.
1615 probe_mss(struct address_info * hw_config)
1619 DDB(printf("Entered probe_mss(io 0x%x, type %d)\n",
1620 hw_config->io_base, hw_config->card_subtype));
1622 if (hw_config->card_subtype == 1) { /* Has no IRQ/DMA registers */
1623 /* check_opl3(0x388, hw_config); */
1627 #if defined(CONFIG_AEDSP16) && defined(AEDSP16_MSS)
1629 * Initialize Audio Excel DSP 16 to MSS: before any operation we must
1630 * enable MSS I/O ports.
1632 InitAEDSP16_MSS(hw_config);
1636 * Check if the IO port returns valid signature. The original MS
1637 * Sound system returns 0x04 while some cards (AudioTriX Pro for
1638 * example) return 0x00 or 0x0f.
1641 if ((tmp = inb(hw_config->io_base + 3)) == 0xff) { /* Bus float */
1642 DDB(printf("I/O address inactive (%x), force type 1\n", tmp));
1643 hw_config->card_subtype = 1 ;
1647 if ((tmp & 0x3f) != 0x04 &&
1648 (tmp & 0x3f) != 0x0f &&
1649 (tmp & 0x3f) != 0x00) {
1650 DDB(printf("No MSS signature detected on port 0x%x (0x%x)\n",
1651 hw_config->io_base, inb(hw_config->io_base + 3)));
1654 if (hw_config->irq > 11) {
1655 printf("MSS: Bad IRQ %d\n", hw_config->irq);
1658 if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3) {
1659 printf("MSS: Bad DMA %d\n", hw_config->dma);
1663 * Check that DMA0 is not in use with a 8 bit board.
1666 if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80) {
1667 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1670 if (hw_config->irq > 7 && hw_config->irq != 9 &&
1671 inb(hw_config->io_base + 3) & 0x80) {
1672 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
1676 return ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp);
1680 attach_mss(struct address_info * hw_config)
1685 * XXX do we really need to detect it again ? - lr970712
1687 if (!ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp))
1691 if (hw_config->card_subtype == 1) { /* Has no IRQ/DMA registers */
1692 ad1848_init("MS Sound System1", hw_config->io_base + 4,
1695 hw_config->dma2, 0, hw_config->osp);
1698 * Set the IRQ and DMA addresses.
1701 static char interrupt_bits[13] = {
1702 -1, -1, -1, 0x08, -1, 0x10, -1, -1, -1, -1, 0x18, -1, 0x20
1705 static char interrupt_bits[12] = {
1706 -1, -1, -1, -1, -1, -1, -1, 0x08, -1, 0x10, 0x18, 0x20
1709 static char dma_bits[4] = {
1713 int config_port = hw_config->io_base + 0;
1714 int version_port = hw_config->io_base + 3;
1715 char bits = interrupt_bits[hw_config->irq];
1721 outb(config_port, bits | 0x40);
1722 if ((inb(version_port) & 0x40) == 0)
1723 printf("[IRQ Conflict?]");
1726 /* Write IRQ+DMA setup */
1727 outb(config_port, bits | dma_bits[hw_config->dma]);
1729 ad1848_init("MS Sound System0", hw_config->io_base + 4,
1732 hw_config->dma, 0, hw_config->osp);
1738 * WSS compatible PnP codec support.
1739 * XXX I doubt it works now - lr970712
1743 probe_pnp_ad1848(struct address_info * hw_config)
1745 return ad1848_detect(hw_config->io_base, NULL, hw_config->osp);
1749 attach_pnp_ad1848(struct address_info * hw_config)
1752 ad1848_init(hw_config->name, hw_config->io_base,
1755 hw_config->dma2, 0, hw_config->osp);
1758 #ifdef CONFIG_SEQUENCER
1760 * Timer stuff (for /dev/music).
1763 static u_int current_interval = 0;
1766 ad1848_tmr_start(int dev, u_int usecs)
1769 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1770 u_long xtal_nsecs; /* nanoseconds per xtal oscillaror tick */
1776 * Length of the timer interval (in nanoseconds) depends on the
1777 * selected crystal oscillator. Check this from bit 0x01 of I8.
1779 * AD1845 has just one oscillator which has cycle time of 10.050 us
1780 * (when a 24.576 MHz xtal oscillator is used).
1782 * Convert requested interval to nanoseconds before computing the timer
1786 if (devc->mode == MD_1845)
1788 else if (ad_read(devc, 8) & 0x01)
1793 divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
1795 if (divider < 100) /* Don't allow shorter intervals than about 1ms */
1798 if (divider > 65535) /* Overflow check */
1801 ad_write(devc, 21, (divider >> 8) & 0xff); /* Set upper bits */
1802 ad_write(devc, 20, divider & 0xff); /* Set lower bits */
1803 ad_write(devc, 16, ad_read(devc, 16) | 0x40); /* Start the timer */
1804 devc->timer_running = 1;
1807 return current_interval = (divider * xtal_nsecs + 500) / 1000;
1811 ad1848_tmr_reprogram(int dev)
1814 * Audio driver has changed sampling rate so that a different xtal
1815 * oscillator was selected. We have to reprogram the timer rate.
1818 ad1848_tmr_start(dev, current_interval);
1819 sound_timer_syncinterval(current_interval);
1823 ad1848_tmr_disable(int dev)
1826 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1829 ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
1830 devc->timer_running = 0;
1835 ad1848_tmr_restart(int dev)
1838 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1840 if (current_interval == 0)
1844 ad_write(devc, 16, ad_read(devc, 16) | 0x40);
1845 devc->timer_running = 1;
1849 static struct sound_lowlev_timer ad1848_tmr = {
1857 ad1848_tmr_install(int dev)
1859 if (timer_installed != -1)
1860 return 0; /* Don't install another timer */
1862 timer_installed = ad1848_tmr.dev = dev;
1863 sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);