2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
26 * The order of pokes in the initiation sequence is based on Linux
27 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom
28 * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org)
29 * contributed towards power management.
31 * $FreeBSD: src/sys/dev/sound/pci/cs4281.c,v 1.2.2.8 2002/08/27 00:25:55 orion Exp $
32 * $DragonFly: src/sys/dev/sound/pci/cs4281.c,v 1.2 2003/06/17 04:28:30 dillon Exp $
35 #include <dev/sound/pcm/sound.h>
36 #include <dev/sound/pcm/ac97.h>
38 #include <pci/pcireg.h>
39 #include <pci/pcivar.h>
41 #include <dev/sound/pci/cs4281.h>
43 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/cs4281.c,v 1.2 2003/06/17 04:28:30 dillon Exp $");
45 #define CS4281_DEFAULT_BUFSZ 16384
47 /* Max fifo size for full duplex is 64 */
48 #define CS4281_FIFO_SIZE 15
50 /* DMA Engine Indices */
51 #define CS4281_DMA_PLAY 0
52 #define CS4281_DMA_REC 1
56 #define MIN(x,y) (x) < (y) ? (x) : (y)
57 #define MAX(x,y) (x) > (y) ? (x) : (y)
59 #define inline __inline
62 #define DEB(x) /* x */
65 /* ------------------------------------------------------------------------- */
70 /* channel registers */
72 struct sc_info *parent;
74 struct snd_dbuf *buffer;
75 struct pcm_channel *channel;
77 u_int32_t spd, fmt, bps, blksz;
79 int dma_setup, dma_active, dma_chan;
82 /* device private data */
88 bus_space_handle_t sh;
89 bus_dma_tag_t parent_dmat;
91 struct resource *reg, *irq, *mem;
92 int regtype, regid, irqid, memid;
101 /* -------------------------------------------------------------------- */
104 /* ADC/DAC control */
105 static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go);
106 static void adcdac_prog(struct sc_chinfo *ch);
108 /* power management and interrupt control */
109 static void cs4281_intr(void *);
110 static int cs4281_power(struct sc_info *, int);
111 static int cs4281_init(struct sc_info *);
113 /* talk to the card */
114 static u_int32_t cs4281_rd(struct sc_info *, int);
115 static void cs4281_wr(struct sc_info *, int, u_int32_t);
118 static u_int8_t cs4281_rate_to_rv(u_int32_t);
119 static u_int32_t cs4281_format_to_dmr(u_int32_t);
120 static u_int32_t cs4281_format_to_bps(u_int32_t);
122 /* -------------------------------------------------------------------- */
123 /* formats (do not add formats without editing cs_fmt_tab) */
125 static u_int32_t cs4281_fmts[] = {
127 AFMT_U8 | AFMT_STEREO,
129 AFMT_S8 | AFMT_STEREO,
131 AFMT_S16_LE | AFMT_STEREO,
133 AFMT_U16_LE | AFMT_STEREO,
135 AFMT_S16_BE | AFMT_STEREO,
137 AFMT_U16_BE | AFMT_STEREO,
141 static struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0};
143 /* -------------------------------------------------------------------- */
146 static inline u_int32_t
147 cs4281_rd(struct sc_info *sc, int regno)
149 return bus_space_read_4(sc->st, sc->sh, regno);
153 cs4281_wr(struct sc_info *sc, int regno, u_int32_t data)
155 bus_space_write_4(sc->st, sc->sh, regno, data);
160 cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask)
163 r = cs4281_rd(sc, regno);
164 cs4281_wr(sc, regno, r & ~mask);
168 cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask)
171 v = cs4281_rd(sc, regno);
172 cs4281_wr(sc, regno, v | mask);
176 cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries)
182 v = cs4281_rd(sc, regno);
183 if ((v & mask) == mask) break;
190 cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries)
196 v = ~ cs4281_rd(sc, regno);
203 /* ------------------------------------------------------------------------- */
204 /* Register value mapping functions */
206 static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000};
207 #define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0])
210 cs4281_rate_to_rv(u_int32_t rate)
214 for (v = 0; v < CS4281_NUM_RATES; v++) {
215 if (rate == cs4281_rates[v]) return v;
219 if (v > 255 || v < 32) v = 5; /* default to 8k */
224 cs4281_rv_to_rate(u_int8_t rv)
228 if (rv < CS4281_NUM_RATES) return cs4281_rates[rv];
233 static inline u_int32_t
234 cs4281_format_to_dmr(u_int32_t format)
237 if (AFMT_8BIT & format) dmr |= CS4281PCI_DMR_SIZE8;
238 if (!(AFMT_STEREO & format)) dmr |= CS4281PCI_DMR_MONO;
239 if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND;
240 if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN;
244 static inline u_int32_t
245 cs4281_format_to_bps(u_int32_t format)
247 return ((AFMT_8BIT & format) ? 1 : 2) * ((AFMT_STEREO & format) ? 2 : 1);
250 /* -------------------------------------------------------------------- */
254 cs4281_rdcd(kobj_t obj, void *devinfo, int regno)
256 struct sc_info *sc = (struct sc_info *)devinfo;
259 codecno = regno >> 8;
262 /* Remove old state */
263 cs4281_rd(sc, CS4281PCI_ACSDA);
265 /* Fill in AC97 register value request form */
266 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
267 cs4281_wr(sc, CS4281PCI_ACCDA, 0);
268 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
269 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV |
270 CS4281PCI_ACCTL_CRW);
272 /* Wait for read to complete */
273 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
274 device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n");
278 /* Wait for valid status */
279 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) {
280 device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n");
284 return cs4281_rd(sc, CS4281PCI_ACSDA);
288 cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
290 struct sc_info *sc = (struct sc_info *)devinfo;
293 codecno = regno >> 8;
296 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
297 cs4281_wr(sc, CS4281PCI_ACCDA, data);
298 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
299 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV);
301 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
302 device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n");
306 static kobj_method_t cs4281_ac97_methods[] = {
307 KOBJMETHOD(ac97_read, cs4281_rdcd),
308 KOBJMETHOD(ac97_write, cs4281_wrcd),
311 AC97_DECLARE(cs4281_ac97);
313 /* ------------------------------------------------------------------------- */
314 /* shared rec/play channel interface */
317 cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
319 struct sc_info *sc = devinfo;
320 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
323 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) {
330 ch->spd = DSP_DEFAULT_SPEED;
332 ch->blksz = sndbuf_getsize(ch->buffer);
334 ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC;
344 cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
346 struct sc_chinfo *ch = data;
347 struct sc_info *sc = ch->parent;
350 go = adcdac_go(ch, 0);
352 /* 2 interrupts are possible and used in buffer (half-empty,empty),
353 * hence factor of 2. */
354 ch->blksz = MIN(blocksize, sc->bufsz / 2);
355 sndbuf_resize(ch->buffer, 2, ch->blksz);
360 DEB(printf("cs4281chan_setblocksize: blksz %d Setting %d\n", blocksize, ch->blksz));
366 cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
368 struct sc_chinfo *ch = data;
369 struct sc_info *sc = ch->parent;
372 go = adcdac_go(ch, 0); /* pause */
373 r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR;
374 v = cs4281_rate_to_rv(speed);
376 adcdac_go(ch, go); /* unpause */
378 ch->spd = cs4281_rv_to_rate(v);
383 cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format)
385 struct sc_chinfo *ch = data;
386 struct sc_info *sc = ch->parent;
389 go = adcdac_go(ch, 0); /* pause */
391 if (ch->dma_chan == CS4281_DMA_PLAY)
392 v = CS4281PCI_DMR_TR_PLAY;
394 v = CS4281PCI_DMR_TR_REC;
395 v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO;
396 v |= cs4281_format_to_dmr(format);
397 cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v);
399 adcdac_go(ch, go); /* unpause */
402 ch->bps = cs4281_format_to_bps(format);
409 cs4281chan_getptr(kobj_t obj, void *data)
411 struct sc_chinfo *ch = data;
412 struct sc_info *sc = ch->parent;
413 u_int32_t dba, dca, ptr;
416 sz = sndbuf_getsize(ch->buffer);
417 dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan));
418 dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan));
419 ptr = (dca - dba + sz) % sz;
425 cs4281chan_trigger(kobj_t obj, void *data, int go)
427 struct sc_chinfo *ch = data;
445 static struct pcmchan_caps *
446 cs4281chan_getcaps(kobj_t obj, void *data)
451 static kobj_method_t cs4281chan_methods[] = {
452 KOBJMETHOD(channel_init, cs4281chan_init),
453 KOBJMETHOD(channel_setformat, cs4281chan_setformat),
454 KOBJMETHOD(channel_setspeed, cs4281chan_setspeed),
455 KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize),
456 KOBJMETHOD(channel_trigger, cs4281chan_trigger),
457 KOBJMETHOD(channel_getptr, cs4281chan_getptr),
458 KOBJMETHOD(channel_getcaps, cs4281chan_getcaps),
461 CHANNEL_DECLARE(cs4281chan);
463 /* -------------------------------------------------------------------- */
464 /* ADC/DAC control */
466 /* adcdac_go enables/disable DMA channel, returns non-zero if DMA was
467 * active before call */
470 adcdac_go(struct sc_chinfo *ch, u_int32_t go)
472 struct sc_info *sc = ch->parent;
475 going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK);
478 cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
480 cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
482 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
488 adcdac_prog(struct sc_chinfo *ch)
490 struct sc_info *sc = ch->parent;
493 if (!ch->dma_setup) {
494 go = adcdac_go(ch, 0);
495 cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan),
496 vtophys(sndbuf_getbuf(ch->buffer)));
497 cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan),
498 sndbuf_getsize(ch->buffer) / ch->bps - 1);
504 /* -------------------------------------------------------------------- */
505 /* The interrupt handler */
510 struct sc_info *sc = (struct sc_info *)p;
513 hisr = cs4281_rd(sc, CS4281PCI_HISR);
515 if (hisr == 0) return;
517 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) {
518 chn_intr(sc->pch.channel);
519 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */
522 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) {
523 chn_intr(sc->rch.channel);
524 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */
527 /* Signal End-of-Interrupt */
528 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
531 /* -------------------------------------------------------------------- */
532 /* power management related */
535 cs4281_power(struct sc_info *sc, int state)
540 /* Permit r/w access to all BA0 registers */
541 cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC);
543 cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
546 /* Power off card and codec */
547 cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
548 cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
552 DEB(printf("cs4281_power %d -> %d\n", sc->power, state));
559 cs4281_init(struct sc_info *sc)
563 /* (0) Blast clock register and serial port */
564 cs4281_wr(sc, CS4281PCI_CLKCR1, 0);
565 cs4281_wr(sc, CS4281PCI_SERMC, 0);
567 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */
568 cs4281_wr(sc, CS4281PCI_ACCTL, 0);
571 /* (2) Effect Reset */
572 cs4281_wr(sc, CS4281PCI_SPMC, 0);
574 cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
575 /* Wait 50ms for ABITCLK to become stable */
578 /* (3) Enable Sound System Clocks */
579 cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP);
580 DELAY(50000); /* Wait for PLL to stabilize */
581 cs4281_wr(sc, CS4281PCI_CLKCR1,
582 CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE);
584 /* (4) Power Up - this combination is essential. */
585 cs4281_set4(sc, CS4281PCI_SSPM,
586 CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN |
587 CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN);
589 /* (5) Wait for clock stabilization */
590 if (cs4281_waitset(sc,
592 CS4281PCI_CLKCR1_DLLRDY,
594 device_printf(sc->dev, "Clock stabilization failed\n");
598 /* (6) Enable ASYNC generation. */
599 cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN);
601 /* Wait to allow AC97 to start generating clock bit */
604 /* Set AC97 timing */
605 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
607 /* (7) Wait for AC97 ready signal */
608 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) {
609 device_printf(sc->dev, "codec did not avail\n");
613 /* (8) Assert valid frame signal to begin sending commands to
617 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN);
619 /* (9) Wait for codec calibration */
620 for(i = 0 ; i < 1000; i++) {
622 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
623 if ((v & 0x0f) == 0x0f) {
628 device_printf(sc->dev, "codec failed to calibrate\n");
632 /* (10) Set AC97 timing */
633 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
635 /* (11) Wait for valid data to arrive */
636 if (cs4281_waitset(sc,
638 CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4),
640 device_printf(sc->dev, "cs4281 never got valid data\n");
644 /* (12) Start digital data transfer of audio data to codec */
647 CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4));
649 /* Set Master and headphone to max */
650 cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0);
651 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0);
653 /* Power on the DAC */
654 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff;
655 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
657 /* Wait until DAC state ready */
658 for(i = 0; i < 320; i++) {
660 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
664 /* Power on the ADC */
665 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff;
666 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
668 /* Wait until ADC state ready */
669 for(i = 0; i < 320; i++) {
671 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
675 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */
678 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) |
679 CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) |
680 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
682 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v);
684 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN);
687 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) |
688 CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) |
689 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
690 CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1);
691 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH);
692 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN);
694 /* Match AC97 slots to FIFOs */
695 v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) |
696 CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) |
697 CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) |
698 CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT);
699 cs4281_wr(sc, CS4281PCI_SRCSA, v);
701 /* Set Auto-Initialize and set directions */
703 CS4281PCI_DMR(CS4281_DMA_PLAY),
706 CS4281PCI_DMR_TR_PLAY);
708 CS4281PCI_DMR(CS4281_DMA_REC),
711 CS4281PCI_DMR_TR_REC);
713 /* Enable half and empty buffer interrupts keeping DMA paused */
715 CS4281PCI_DCR(CS4281_DMA_PLAY),
716 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
718 CS4281PCI_DCR(CS4281_DMA_REC),
719 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
721 /* Enable Interrupts */
724 CS4281PCI_HIMR_DMAI |
725 CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) |
726 CS4281PCI_HIMR_DMA(CS4281_DMA_REC));
728 /* Set playback volume */
729 cs4281_wr(sc, CS4281PCI_PPLVC, 7);
730 cs4281_wr(sc, CS4281PCI_PPRVC, 7);
735 /* -------------------------------------------------------------------- */
736 /* Probe and attach the card */
739 cs4281_pci_probe(device_t dev)
743 switch (pci_get_devid(dev)) {
745 s = "Crystal Semiconductor CS4281";
750 device_set_desc(dev, s);
751 return s ? 0 : ENXIO;
755 cs4281_pci_attach(device_t dev)
758 struct ac97_info *codec = NULL;
760 char status[SND_STATUSLEN];
762 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
763 device_printf(dev, "cannot allocate softc\n");
768 sc->type = pci_get_devid(dev);
770 data = pci_read_config(dev, PCIR_COMMAND, 2);
771 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
772 pci_write_config(dev, PCIR_COMMAND, data, 2);
774 #if __FreeBSD_version > 500000
775 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
776 /* Reset the power state. */
777 device_printf(dev, "chip is in D%d power mode "
778 "-- setting to D0\n", pci_get_powerstate(dev));
780 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
783 data = pci_read_config(dev, CS4281PCI_PMCS_OFFSET, 4);
784 if (data & CS4281PCI_PMCS_PS_MASK) {
785 /* Reset the power state. */
786 device_printf(dev, "chip is in D%d power mode "
787 "-- setting to D0\n",
788 data & CS4281PCI_PMCS_PS_MASK);
789 pci_write_config(dev, CS4281PCI_PMCS_OFFSET,
790 data & ~CS4281PCI_PMCS_PS_MASK, 4);
794 sc->regid = PCIR_MAPS;
795 sc->regtype = SYS_RES_MEMORY;
796 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
797 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
799 sc->regtype = SYS_RES_IOPORT;
800 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
801 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
803 device_printf(dev, "unable to allocate register space\n");
807 sc->st = rman_get_bustag(sc->reg);
808 sc->sh = rman_get_bushandle(sc->reg);
810 sc->memid = PCIR_MAPS + 4;
811 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid, 0,
812 ~0, CS4281PCI_BA1_SIZE, RF_ACTIVE);
813 if (sc->mem == NULL) {
814 device_printf(dev, "unable to allocate fifo space\n");
819 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid,
820 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
822 device_printf(dev, "unable to allocate interrupt\n");
826 if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) {
827 device_printf(dev, "unable to setup interrupt\n");
831 sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536);
833 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
834 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
835 /*highaddr*/BUS_SPACE_MAXADDR,
836 /*filter*/NULL, /*filterarg*/NULL,
837 /*maxsize*/sc->bufsz, /*nsegments*/1,
839 /*flags*/0, &sc->parent_dmat) != 0) {
840 device_printf(dev, "unable to create dma tag\n");
848 if (cs4281_init(sc) == -1) {
849 device_printf(dev, "unable to initialize the card\n");
853 /* create/init mixer */
854 codec = AC97_CREATE(dev, sc, cs4281_ac97);
858 mixer_init(dev, ac97_getmixerclass(), codec);
860 if (pcm_register(dev, sc, 1, 1))
863 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc);
864 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc);
866 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld",
867 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
868 rman_get_start(sc->reg), rman_get_start(sc->irq));
869 pcm_setstatus(dev, status);
877 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
879 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
881 bus_teardown_intr(dev, sc->irq, sc->ih);
883 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
885 bus_dma_tag_destroy(sc->parent_dmat);
892 cs4281_pci_detach(device_t dev)
897 r = pcm_unregister(dev);
901 sc = pcm_getdevinfo(dev);
906 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
907 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
908 bus_teardown_intr(dev, sc->irq, sc->ih);
909 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
910 bus_dma_tag_destroy(sc->parent_dmat);
917 cs4281_pci_suspend(device_t dev)
921 sc = pcm_getdevinfo(dev);
923 sc->rch.dma_active = adcdac_go(&sc->rch, 0);
924 sc->pch.dma_active = adcdac_go(&sc->pch, 0);
932 cs4281_pci_resume(device_t dev)
936 sc = pcm_getdevinfo(dev);
941 /* initialize chip */
942 if (cs4281_init(sc) == -1) {
943 device_printf(dev, "unable to reinitialize the card\n");
947 /* restore mixer state */
948 if (mixer_reinit(dev) == -1) {
949 device_printf(dev, "unable to reinitialize the mixer\n");
953 /* restore chip state */
954 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd);
955 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz);
956 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt);
957 adcdac_go(&sc->rch, sc->rch.dma_active);
959 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd);
960 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz);
961 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt);
962 adcdac_go(&sc->pch, sc->pch.dma_active);
967 static device_method_t cs4281_methods[] = {
968 /* Device interface */
969 DEVMETHOD(device_probe, cs4281_pci_probe),
970 DEVMETHOD(device_attach, cs4281_pci_attach),
971 DEVMETHOD(device_detach, cs4281_pci_detach),
972 DEVMETHOD(device_suspend, cs4281_pci_suspend),
973 DEVMETHOD(device_resume, cs4281_pci_resume),
977 static driver_t cs4281_driver = {
983 DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, 0, 0);
984 MODULE_DEPEND(snd_cs4281, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
985 MODULE_VERSION(snd_cs4281, 1);