sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_ringbuffer.h"
  34 #include <linux/workqueue.h>
  35
  36 extern struct drm_i915_private *i915_mch_dev;
  37
  38 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  39
  40 #define BEGIN_LP_RING(n) \
  41         intel_ring_begin(LP_RING(dev_priv), (n))
  42
  43 #define OUT_RING(x) \
  44         intel_ring_emit(LP_RING(dev_priv), x)
  45
  46 #define ADVANCE_LP_RING() \
  47         __intel_ring_advance(LP_RING(dev_priv))
  48
  49 /**
  50  * Lock test for when it's just for synchronization of ring access.
  51  *
  52  * In that case, we don't need to do it when GEM is initialized as nobody else
  53  * has access to the ring.
  54  */
  55 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  56         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  57                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  58 } while (0)
  59
  60 static inline u32
  61 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  62 {
  63         if (I915_NEED_GFX_HWS(dev_priv->dev))
  64                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  65         else
  66                 return intel_read_status_page(LP_RING(dev_priv), reg);
  67 }
  68
  69 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  70 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  71 #define I915_BREADCRUMB_INDEX           0x21
  72
  73 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  74 {
  75         /* XXX: We don't care about dri1 */
  76         return;
  77 }
  78
  79 static void i915_write_hws_pga(struct drm_device *dev)
  80 {
  81         drm_i915_private_t *dev_priv = dev->dev_private;
  82         u32 addr;
  83
  84         addr = dev_priv->status_page_dmah->busaddr;
  85         if (INTEL_INFO(dev)->gen >= 4)
  86                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  87         I915_WRITE(HWS_PGA, addr);
  88 }
  89
  90 /**
  91  * Frees the hardware status page, whether it's a physical address or a virtual
  92  * address set up by the X Server.
  93  */
  94 static void i915_free_hws(struct drm_device *dev)
  95 {
  96         drm_i915_private_t *dev_priv = dev->dev_private;
  97         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  98
  99         if (dev_priv->status_page_dmah) {
 100                 drm_pci_free(dev, dev_priv->status_page_dmah);
 101                 dev_priv->status_page_dmah = NULL;
 102         }
 103
 104         if (ring->status_page.gfx_addr) {
 105                 ring->status_page.gfx_addr = 0;
 106 #if 0   /* We don't care about dri1 */
 107                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 108 #endif
 109         }
 110
 111         /* Need to rewrite hardware status page */
 112         I915_WRITE(HWS_PGA, 0x1ffff000);
 113 }
 114
 115 void i915_kernel_lost_context(struct drm_device * dev)
 116 {
 117         drm_i915_private_t *dev_priv = dev->dev_private;
 118         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 119
 120         /*
 121          * We should never lose context on the ring with modesetting
 122          * as we don't expose it to userspace
 123          */
 124         if (drm_core_check_feature(dev, DRIVER_MODESET))
 125                 return;
 126
 127         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 128         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 129         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 130         if (ring->space < 0)
 131                 ring->space += ring->size;
 132
 133 #if 0
 134         if (!dev->primary->master)
 135                 return;
 136 #endif
 137
 138         if (ring->head == ring->tail && dev_priv->sarea_priv)
 139                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 140 }
 141
 142 static int i915_dma_cleanup(struct drm_device * dev)
 143 {
 144         drm_i915_private_t *dev_priv = dev->dev_private;
 145         int i;
 146
 147         /* Make sure interrupts are disabled here because the uninstall ioctl
 148          * may not have been called from userspace and after dev_private
 149          * is freed, it's too late.
 150          */
 151         if (dev->irq_enabled)
 152                 drm_irq_uninstall(dev);
 153
 154         mutex_lock(&dev->struct_mutex);
 155         for (i = 0; i < I915_NUM_RINGS; i++)
 156                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 157         mutex_unlock(&dev->struct_mutex);
 158
 159         /* Clear the HWS virtual address at teardown */
 160         if (I915_NEED_GFX_HWS(dev))
 161                 i915_free_hws(dev);
 162
 163         return 0;
 164 }
 165
 166 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 167 {
 168         drm_i915_private_t *dev_priv = dev->dev_private;
 169         int ret;
 170
 171         dev_priv->sarea = drm_getsarea(dev);
 172         if (!dev_priv->sarea) {
 173                 DRM_ERROR("can not find sarea!\n");
 174                 i915_dma_cleanup(dev);
 175                 return -EINVAL;
 176         }
 177
 178         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 179             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 180
 181         if (init->ring_size != 0) {
 182                 if (LP_RING(dev_priv)->obj != NULL) {
 183                         i915_dma_cleanup(dev);
 184                         DRM_ERROR("Client tried to initialize ringbuffer in "
 185                                   "GEM mode\n");
 186                         return -EINVAL;
 187                 }
 188
 189                 ret = intel_render_ring_init_dri(dev,
 190                                                  init->ring_start,
 191                                                  init->ring_size);
 192                 if (ret) {
 193                         i915_dma_cleanup(dev);
 194                         return ret;
 195                 }
 196         }
 197
 198         dev_priv->dri1.cpp = init->cpp;
 199         dev_priv->dri1.back_offset = init->back_offset;
 200         dev_priv->dri1.front_offset = init->front_offset;
 201         dev_priv->dri1.current_page = 0;
 202         dev_priv->sarea_priv->pf_current_page = 0;
 203
 204
 205         /* Allow hardware batchbuffers unless told otherwise.
 206          */
 207         dev_priv->dri1.allow_batchbuffer = 1;
 208
 209         return 0;
 210 }
 211
 212 static int i915_dma_resume(struct drm_device * dev)
 213 {
 214         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 215         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 216
 217         DRM_DEBUG_DRIVER("%s\n", __func__);
 218
 219         if (ring->virtual_start == NULL) {
 220                 DRM_ERROR("can not ioremap virtual address for"
 221                           " ring buffer\n");
 222                 return -ENOMEM;
 223         }
 224
 225         /* Program Hardware Status Page */
 226         if (!ring->status_page.page_addr) {
 227                 DRM_ERROR("Can not find hardware status page\n");
 228                 return -EINVAL;
 229         }
 230         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 231                                 ring->status_page.page_addr);
 232         if (ring->status_page.gfx_addr != 0)
 233                 intel_ring_setup_status_page(ring);
 234         else
 235                 i915_write_hws_pga(dev);
 236
 237         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 238
 239         return 0;
 240 }
 241
 242 static int i915_dma_init(struct drm_device *dev, void *data,
 243                          struct drm_file *file_priv)
 244 {
 245         drm_i915_init_t *init = data;
 246         int retcode = 0;
 247
 248         if (drm_core_check_feature(dev, DRIVER_MODESET))
 249                 return -ENODEV;
 250
 251         switch (init->func) {
 252         case I915_INIT_DMA:
 253                 retcode = i915_initialize(dev, init);
 254                 break;
 255         case I915_CLEANUP_DMA:
 256                 retcode = i915_dma_cleanup(dev);
 257                 break;
 258         case I915_RESUME_DMA:
 259                 retcode = i915_dma_resume(dev);
 260                 break;
 261         default:
 262                 retcode = -EINVAL;
 263                 break;
 264         }
 265
 266         return retcode;
 267 }
 268
 269 /* Implement basically the same security restrictions as hardware does
 270  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 271  *
 272  * Most of the calculations below involve calculating the size of a
 273  * particular instruction.  It's important to get the size right as
 274  * that tells us where the next instruction to check is.  Any illegal
 275  * instruction detected will be given a size of zero, which is a
 276  * signal to abort the rest of the buffer.
 277  */
 278 static int validate_cmd(int cmd)
 279 {
 280         switch (((cmd >> 29) & 0x7)) {
 281         case 0x0:
 282                 switch ((cmd >> 23) & 0x3f) {
 283                 case 0x0:
 284                         return 1;       /* MI_NOOP */
 285                 case 0x4:
 286                         return 1;       /* MI_FLUSH */
 287                 default:
 288                         return 0;       /* disallow everything else */
 289                 }
 290                 break;
 291         case 0x1:
 292                 return 0;       /* reserved */
 293         case 0x2:
 294                 return (cmd & 0xff) + 2;        /* 2d commands */
 295         case 0x3:
 296                 if (((cmd >> 24) & 0x1f) <= 0x18)
 297                         return 1;
 298
 299                 switch ((cmd >> 24) & 0x1f) {
 300                 case 0x1c:
 301                         return 1;
 302                 case 0x1d:
 303                         switch ((cmd >> 16) & 0xff) {
 304                         case 0x3:
 305                                 return (cmd & 0x1f) + 2;
 306                         case 0x4:
 307                                 return (cmd & 0xf) + 2;
 308                         default:
 309                                 return (cmd & 0xffff) + 2;
 310                         }
 311                 case 0x1e:
 312                         if (cmd & (1 << 23))
 313                                 return (cmd & 0xffff) + 1;
 314                         else
 315                                 return 1;
 316                 case 0x1f:
 317                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 318                                 return (cmd & 0x1ffff) + 2;
 319                         else if (cmd & (1 << 17))       /* indirect random */
 320                                 if ((cmd & 0xffff) == 0)
 321                                         return 0;       /* unknown length, too hard */
 322                                 else
 323                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 324                         else
 325                                 return 2;       /* indirect sequential */
 326                 default:
 327                         return 0;
 328                 }
 329         default:
 330                 return 0;
 331         }
 332
 333         return 0;
 334 }
 335
 336 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 337 {
 338         drm_i915_private_t *dev_priv = dev->dev_private;
 339         int i, ret;
 340
 341         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 342                 return -EINVAL;
 343
 344         for (i = 0; i < dwords;) {
 345                 int sz = validate_cmd(buffer[i]);
 346                 if (sz == 0 || i + sz > dwords)
 347                         return -EINVAL;
 348                 i += sz;
 349         }
 350
 351         ret = BEGIN_LP_RING((dwords+1)&~1);
 352         if (ret)
 353                 return ret;
 354
 355         for (i = 0; i < dwords; i++)
 356                 OUT_RING(buffer[i]);
 357         if (dwords & 1)
 358                 OUT_RING(0);
 359
 360         ADVANCE_LP_RING();
 361
 362         return 0;
 363 }
 364
 365 int
 366 i915_emit_box(struct drm_device *dev,
 367               struct drm_clip_rect *box,
 368               int DR1, int DR4)
 369 {
 370         struct drm_i915_private *dev_priv = dev->dev_private;
 371         int ret;
 372
 373         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 374             box->y2 <= 0 || box->x2 <= 0) {
 375                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 376                           box->x1, box->y1, box->x2, box->y2);
 377                 return -EINVAL;
 378         }
 379
 380         if (INTEL_INFO(dev)->gen >= 4) {
 381                 ret = BEGIN_LP_RING(4);
 382                 if (ret)
 383                         return ret;
 384
 385                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 386                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 387                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 388                 OUT_RING(DR4);
 389         } else {
 390                 ret = BEGIN_LP_RING(6);
 391                 if (ret)
 392                         return ret;
 393
 394                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 395                 OUT_RING(DR1);
 396                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 397                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 398                 OUT_RING(DR4);
 399                 OUT_RING(0);
 400         }
 401         ADVANCE_LP_RING();
 402
 403         return 0;
 404 }
 405
 406 /* XXX: Emitting the counter should really be moved to part of the IRQ
 407  * emit. For now, do it in both places:
 408  */
 409
 410 static void i915_emit_breadcrumb(struct drm_device *dev)
 411 {
 412         drm_i915_private_t *dev_priv = dev->dev_private;
 413
 414         dev_priv->dri1.counter++;
 415         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 416                 dev_priv->dri1.counter = 0;
 417         if (dev_priv->sarea_priv)
 418                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 419
 420         if (BEGIN_LP_RING(4) == 0) {
 421                 OUT_RING(MI_STORE_DWORD_INDEX);
 422                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 423                 OUT_RING(dev_priv->dri1.counter);
 424                 OUT_RING(0);
 425                 ADVANCE_LP_RING();
 426         }
 427 }
 428
 429 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 430                                    drm_i915_cmdbuffer_t *cmd,
 431                                    struct drm_clip_rect *cliprects,
 432                                    void *cmdbuf)
 433 {
 434         int nbox = cmd->num_cliprects;
 435         int i = 0, count, ret;
 436
 437         if (cmd->sz & 0x3) {
 438                 DRM_ERROR("alignment");
 439                 return -EINVAL;
 440         }
 441
 442         i915_kernel_lost_context(dev);
 443
 444         count = nbox ? nbox : 1;
 445
 446         for (i = 0; i < count; i++) {
 447                 if (i < nbox) {
 448                         ret = i915_emit_box(dev, &cliprects[i],
 449                                             cmd->DR1, cmd->DR4);
 450                         if (ret)
 451                                 return ret;
 452                 }
 453
 454                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 455                 if (ret)
 456                         return ret;
 457         }
 458
 459         i915_emit_breadcrumb(dev);
 460         return 0;
 461 }
 462
 463 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 464                                      drm_i915_batchbuffer_t * batch,
 465                                      struct drm_clip_rect *cliprects)
 466 {
 467         struct drm_i915_private *dev_priv = dev->dev_private;
 468         int nbox = batch->num_cliprects;
 469         int i, count, ret;
 470
 471         if ((batch->start | batch->used) & 0x7) {
 472                 DRM_ERROR("alignment");
 473                 return -EINVAL;
 474         }
 475
 476         i915_kernel_lost_context(dev);
 477
 478         count = nbox ? nbox : 1;
 479         for (i = 0; i < count; i++) {
 480                 if (i < nbox) {
 481                         ret = i915_emit_box(dev, &cliprects[i],
 482                                             batch->DR1, batch->DR4);
 483                         if (ret)
 484                                 return ret;
 485                 }
 486
 487                 if (!IS_I830(dev) && !IS_845G(dev)) {
 488                         ret = BEGIN_LP_RING(2);
 489                         if (ret)
 490                                 return ret;
 491
 492                         if (INTEL_INFO(dev)->gen >= 4) {
 493                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 494                                 OUT_RING(batch->start);
 495                         } else {
 496                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 497                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 498                         }
 499                 } else {
 500                         ret = BEGIN_LP_RING(4);
 501                         if (ret)
 502                                 return ret;
 503
 504                         OUT_RING(MI_BATCH_BUFFER);
 505                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 506                         OUT_RING(batch->start + batch->used - 4);
 507                         OUT_RING(0);
 508                 }
 509                 ADVANCE_LP_RING();
 510         }
 511
 512
 513         if (IS_G4X(dev) || IS_GEN5(dev)) {
 514                 if (BEGIN_LP_RING(2) == 0) {
 515                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 516                         OUT_RING(MI_NOOP);
 517                         ADVANCE_LP_RING();
 518                 }
 519         }
 520
 521         i915_emit_breadcrumb(dev);
 522         return 0;
 523 }
 524
 525 static int i915_dispatch_flip(struct drm_device * dev)
 526 {
 527         drm_i915_private_t *dev_priv = dev->dev_private;
 528         int ret;
 529
 530         if (!dev_priv->sarea_priv)
 531                 return -EINVAL;
 532
 533         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 534                           __func__,
 535                          dev_priv->dri1.current_page,
 536                          dev_priv->sarea_priv->pf_current_page);
 537
 538         i915_kernel_lost_context(dev);
 539
 540         ret = BEGIN_LP_RING(10);
 541         if (ret)
 542                 return ret;
 543
 544         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 545         OUT_RING(0);
 546
 547         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 548         OUT_RING(0);
 549         if (dev_priv->dri1.current_page == 0) {
 550                 OUT_RING(dev_priv->dri1.back_offset);
 551                 dev_priv->dri1.current_page = 1;
 552         } else {
 553                 OUT_RING(dev_priv->dri1.front_offset);
 554                 dev_priv->dri1.current_page = 0;
 555         }
 556         OUT_RING(0);
 557
 558         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 559         OUT_RING(0);
 560
 561         ADVANCE_LP_RING();
 562
 563         dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 564
 565         if (BEGIN_LP_RING(4) == 0) {
 566                 OUT_RING(MI_STORE_DWORD_INDEX);
 567                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 568                 OUT_RING(dev_priv->dri1.counter);
 569                 OUT_RING(0);
 570                 ADVANCE_LP_RING();
 571         }
 572
 573         dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 574         return 0;
 575 }
 576
 577 static int i915_quiescent(struct drm_device *dev)
 578 {
 579         i915_kernel_lost_context(dev);
 580         return intel_ring_idle(LP_RING(dev->dev_private));
 581 }
 582
 583 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 584                             struct drm_file *file_priv)
 585 {
 586         int ret;
 587
 588         if (drm_core_check_feature(dev, DRIVER_MODESET))
 589                 return -ENODEV;
 590
 591         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 592
 593         mutex_lock(&dev->struct_mutex);
 594         ret = i915_quiescent(dev);
 595         mutex_unlock(&dev->struct_mutex);
 596
 597         return ret;
 598 }
 599
 600 static int i915_batchbuffer(struct drm_device *dev, void *data,
 601                             struct drm_file *file_priv)
 602 {
 603         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 604         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 605         drm_i915_batchbuffer_t *batch = data;
 606         int ret;
 607         struct drm_clip_rect *cliprects = NULL;
 608
 609         if (drm_core_check_feature(dev, DRIVER_MODESET))
 610                 return -ENODEV;
 611
 612         if (!dev_priv->dri1.allow_batchbuffer) {
 613                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 614                 return -EINVAL;
 615         }
 616
 617         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 618                         batch->start, batch->used, batch->num_cliprects);
 619
 620         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 621
 622         if (batch->num_cliprects < 0)
 623                 return -EINVAL;
 624
 625         if (batch->num_cliprects) {
 626                 cliprects = kcalloc(batch->num_cliprects,
 627                                     sizeof(*cliprects),
 628                                     GFP_KERNEL);
 629                 if (cliprects == NULL)
 630                         return -ENOMEM;
 631
 632                 ret = copy_from_user(cliprects, batch->cliprects,
 633                                      batch->num_cliprects *
 634                                      sizeof(struct drm_clip_rect));
 635                 if (ret != 0) {
 636                         ret = -EFAULT;
 637                         goto fail_free;
 638                 }
 639         }
 640
 641         mutex_lock(&dev->struct_mutex);
 642         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 643         mutex_unlock(&dev->struct_mutex);
 644
 645         if (sarea_priv)
 646                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 647
 648 fail_free:
 649         kfree(cliprects);
 650
 651         return ret;
 652 }
 653
 654 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 655                           struct drm_file *file_priv)
 656 {
 657         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 658         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 659         drm_i915_cmdbuffer_t *cmdbuf = data;
 660         struct drm_clip_rect *cliprects = NULL;
 661         void *batch_data;
 662         int ret;
 663
 664         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 665                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 666
 667         if (drm_core_check_feature(dev, DRIVER_MODESET))
 668                 return -ENODEV;
 669
 670         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 671
 672         if (cmdbuf->num_cliprects < 0)
 673                 return -EINVAL;
 674
 675         batch_data = kmalloc(cmdbuf->sz, M_DRM, M_WAITOK);
 676         if (batch_data == NULL)
 677                 return -ENOMEM;
 678
 679         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 680         if (ret != 0) {
 681                 ret = -EFAULT;
 682                 goto fail_batch_free;
 683         }
 684
 685         if (cmdbuf->num_cliprects) {
 686                 cliprects = kcalloc(cmdbuf->num_cliprects,
 687                                     sizeof(*cliprects), GFP_KERNEL);
 688                 if (cliprects == NULL) {
 689                         ret = -ENOMEM;
 690                         goto fail_batch_free;
 691                 }
 692
 693                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 694                                      cmdbuf->num_cliprects *
 695                                      sizeof(struct drm_clip_rect));
 696                 if (ret != 0) {
 697                         ret = -EFAULT;
 698                         goto fail_clip_free;
 699                 }
 700         }
 701
 702         mutex_lock(&dev->struct_mutex);
 703         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 704         mutex_unlock(&dev->struct_mutex);
 705         if (ret) {
 706                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 707                 goto fail_clip_free;
 708         }
 709
 710         if (sarea_priv)
 711                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 712
 713 fail_clip_free:
 714         kfree(cliprects);
 715 fail_batch_free:
 716         kfree(batch_data);
 717         return ret;
 718 }
 719
 720 static int i915_emit_irq(struct drm_device * dev)
 721 {
 722         drm_i915_private_t *dev_priv = dev->dev_private;
 723 #if 0
 724         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 725 #endif
 726
 727         i915_kernel_lost_context(dev);
 728
 729         DRM_DEBUG_DRIVER("\n");
 730
 731         dev_priv->dri1.counter++;
 732         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 733                 dev_priv->dri1.counter = 1;
 734         if (dev_priv->sarea_priv)
 735                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 736
 737         if (BEGIN_LP_RING(4) == 0) {
 738                 OUT_RING(MI_STORE_DWORD_INDEX);
 739                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 740                 OUT_RING(dev_priv->dri1.counter);
 741                 OUT_RING(MI_USER_INTERRUPT);
 742                 ADVANCE_LP_RING();
 743         }
 744
 745         return dev_priv->dri1.counter;
 746 }
 747
 748 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 749 {
 750         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 751 #if 0
 752         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 753 #endif
 754         int ret = 0;
 755         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 756
 757         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 758                   READ_BREADCRUMB(dev_priv));
 759
 760 #if 0
 761         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 762                 if (master_priv->sarea_priv)
 763                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 764                 return 0;
 765         }
 766
 767         if (master_priv->sarea_priv)
 768                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 769 #else
 770         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 771                 if (dev_priv->sarea_priv) {
 772                         dev_priv->sarea_priv->last_dispatch =
 773                                 READ_BREADCRUMB(dev_priv);
 774                 }
 775                 return 0;
 776         }
 777
 778         if (dev_priv->sarea_priv)
 779                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 780 #endif
 781
 782         if (ring->irq_get(ring)) {
 783                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ,
 784                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 785                 ring->irq_put(ring);
 786         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 787                 ret = -EBUSY;
 788
 789         if (ret == -EBUSY) {
 790                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 791                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 792         }
 793
 794         return ret;
 795 }
 796
 797 /* Needs the lock as it touches the ring.
 798  */
 799 static int i915_irq_emit(struct drm_device *dev, void *data,
 800                          struct drm_file *file_priv)
 801 {
 802         drm_i915_private_t *dev_priv = dev->dev_private;
 803         drm_i915_irq_emit_t *emit = data;
 804         int result;
 805
 806         if (drm_core_check_feature(dev, DRIVER_MODESET))
 807                 return -ENODEV;
 808
 809         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 810                 DRM_ERROR("called with no initialization\n");
 811                 return -EINVAL;
 812         }
 813
 814         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 815
 816         mutex_lock(&dev->struct_mutex);
 817         result = i915_emit_irq(dev);
 818         mutex_unlock(&dev->struct_mutex);
 819
 820         if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
 821                 DRM_ERROR("copy_to_user\n");
 822                 return -EFAULT;
 823         }
 824
 825         return 0;
 826 }
 827
 828 /* Doesn't need the hardware lock.
 829  */
 830 static int i915_irq_wait(struct drm_device *dev, void *data,
 831                          struct drm_file *file_priv)
 832 {
 833         drm_i915_private_t *dev_priv = dev->dev_private;
 834         drm_i915_irq_wait_t *irqwait = data;
 835
 836         if (drm_core_check_feature(dev, DRIVER_MODESET))
 837                 return -ENODEV;
 838
 839         if (!dev_priv) {
 840                 DRM_ERROR("called with no initialization\n");
 841                 return -EINVAL;
 842         }
 843
 844         return i915_wait_irq(dev, irqwait->irq_seq);
 845 }
 846
 847 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 848                          struct drm_file *file_priv)
 849 {
 850         drm_i915_private_t *dev_priv = dev->dev_private;
 851         drm_i915_vblank_pipe_t *pipe = data;
 852
 853         if (drm_core_check_feature(dev, DRIVER_MODESET))
 854                 return -ENODEV;
 855
 856         if (!dev_priv) {
 857                 DRM_ERROR("called with no initialization\n");
 858                 return -EINVAL;
 859         }
 860
 861         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 862
 863         return 0;
 864 }
 865
 866 /**
 867  * Schedule buffer swap at given vertical blank.
 868  */
 869 static int i915_vblank_swap(struct drm_device *dev, void *data,
 870                      struct drm_file *file_priv)
 871 {
 872         /* The delayed swap mechanism was fundamentally racy, and has been
 873          * removed.  The model was that the client requested a delayed flip/swap
 874          * from the kernel, then waited for vblank before continuing to perform
 875          * rendering.  The problem was that the kernel might wake the client
 876          * up before it dispatched the vblank swap (since the lock has to be
 877          * held while touching the ringbuffer), in which case the client would
 878          * clear and start the next frame before the swap occurred, and
 879          * flicker would occur in addition to likely missing the vblank.
 880          *
 881          * In the absence of this ioctl, userland falls back to a correct path
 882          * of waiting for a vblank, then dispatching the swap on its own.
 883          * Context switching to userland and back is plenty fast enough for
 884          * meeting the requirements of vblank swapping.
 885          */
 886         return -EINVAL;
 887 }
 888
 889 static int i915_flip_bufs(struct drm_device *dev, void *data,
 890                           struct drm_file *file_priv)
 891 {
 892         int ret;
 893
 894         if (drm_core_check_feature(dev, DRIVER_MODESET))
 895                 return -ENODEV;
 896
 897         DRM_DEBUG_DRIVER("%s\n", __func__);
 898
 899         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 900
 901         mutex_lock(&dev->struct_mutex);
 902         ret = i915_dispatch_flip(dev);
 903         mutex_unlock(&dev->struct_mutex);
 904
 905         return ret;
 906 }
 907
 908 static int i915_getparam(struct drm_device *dev, void *data,
 909                          struct drm_file *file_priv)
 910 {
 911         drm_i915_private_t *dev_priv = dev->dev_private;
 912         drm_i915_getparam_t *param = data;
 913         int value;
 914
 915         if (!dev_priv) {
 916                 DRM_ERROR("called with no initialization\n");
 917                 return -EINVAL;
 918         }
 919
 920         switch (param->param) {
 921         case I915_PARAM_IRQ_ACTIVE:
 922                 value = dev->irq_enabled ? 1 : 0;
 923                 break;
 924         case I915_PARAM_ALLOW_BATCHBUFFER:
 925                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 926                 break;
 927         case I915_PARAM_LAST_DISPATCH:
 928                 value = READ_BREADCRUMB(dev_priv);
 929                 break;
 930         case I915_PARAM_CHIPSET_ID:
 931                 value = dev->pdev->device;
 932                 break;
 933         case I915_PARAM_HAS_GEM:
 934                 value = 1;
 935                 break;
 936         case I915_PARAM_NUM_FENCES_AVAIL:
 937                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 938                 break;
 939         case I915_PARAM_HAS_OVERLAY:
 940                 value = dev_priv->overlay ? 1 : 0;
 941                 break;
 942         case I915_PARAM_HAS_PAGEFLIPPING:
 943                 value = 1;
 944                 break;
 945         case I915_PARAM_HAS_EXECBUF2:
 946                 /* depends on GEM */
 947                 value = 1;
 948                 break;
 949         case I915_PARAM_HAS_BSD:
 950                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 951                 break;
 952         case I915_PARAM_HAS_BLT:
 953                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 954                 break;
 955         case I915_PARAM_HAS_VEBOX:
 956                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
 957                 break;
 958         case I915_PARAM_HAS_RELAXED_FENCING:
 959                 value = 1;
 960                 break;
 961         case I915_PARAM_HAS_COHERENT_RINGS:
 962                 value = 1;
 963                 break;
 964         case I915_PARAM_HAS_EXEC_CONSTANTS:
 965                 value = INTEL_INFO(dev)->gen >= 4;
 966                 break;
 967         case I915_PARAM_HAS_RELAXED_DELTA:
 968                 value = 1;
 969                 break;
 970         case I915_PARAM_HAS_GEN7_SOL_RESET:
 971                 value = 1;
 972                 break;
 973         case I915_PARAM_HAS_LLC:
 974                 value = HAS_LLC(dev);
 975                 break;
 976         case I915_PARAM_HAS_WT:
 977                 value = HAS_WT(dev);
 978                 break;
 979         case I915_PARAM_HAS_ALIASING_PPGTT:
 980                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 981                 break;
 982         case I915_PARAM_HAS_WAIT_TIMEOUT:
 983                 value = 1;
 984                 break;
 985         case I915_PARAM_HAS_SEMAPHORES:
 986                 value = i915_semaphore_is_enabled(dev);
 987                 break;
 988         case I915_PARAM_HAS_PINNED_BATCHES:
 989                 value = 1;
 990                 break;
 991         case I915_PARAM_HAS_EXEC_NO_RELOC:
 992                 value = 1;
 993                 break;
 994         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 995                 value = 1;
 996                 break;
 997         default:
 998                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 999                 return -EINVAL;
1000         }
1001
1002         if (copy_to_user(param->value, &value, sizeof(int))) {
1003                 DRM_ERROR("copy_to_user failed\n");
1004                 return -EFAULT;
1005         }
1006
1007         return 0;
1008 }
1009
1010 static int i915_setparam(struct drm_device *dev, void *data,
1011                          struct drm_file *file_priv)
1012 {
1013         drm_i915_private_t *dev_priv = dev->dev_private;
1014         drm_i915_setparam_t *param = data;
1015
1016         if (!dev_priv) {
1017                 DRM_ERROR("called with no initialization\n");
1018                 return -EINVAL;
1019         }
1020
1021         switch (param->param) {
1022         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1023                 break;
1024         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1025                 break;
1026         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1027                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1028                 break;
1029         case I915_SETPARAM_NUM_USED_FENCES:
1030                 if (param->value > dev_priv->num_fence_regs ||
1031                     param->value < 0)
1032                         return -EINVAL;
1033                 /* Userspace can use first N regs */
1034                 dev_priv->fence_reg_start = param->value;
1035                 break;
1036         default:
1037                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1038                                         param->param);
1039                 return -EINVAL;
1040         }
1041
1042         return 0;
1043 }
1044
1045 static int i915_set_status_page(struct drm_device *dev, void *data,
1046                                 struct drm_file *file_priv)
1047 {
1048 #if 0   /* We don't care about dri1 */
1049         drm_i915_private_t *dev_priv = dev->dev_private;
1050         drm_i915_hws_addr_t *hws = data;
1051         struct intel_ring_buffer *ring;
1052
1053         if (drm_core_check_feature(dev, DRIVER_MODESET))
1054                 return -ENODEV;
1055
1056         if (!I915_NEED_GFX_HWS(dev))
1057                 return -EINVAL;
1058
1059         if (!dev_priv) {
1060                 DRM_ERROR("called with no initialization\n");
1061                 return -EINVAL;
1062         }
1063
1064         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1065                 WARN(1, "tried to set status page when mode setting active\n");
1066                 return 0;
1067         }
1068
1069         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1070
1071         ring = LP_RING(dev_priv);
1072         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1073
1074         dev_priv->dri1.gfx_hws_cpu_addr =
1075                 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1076         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1077                 i915_dma_cleanup(dev);
1078                 ring->status_page.gfx_addr = 0;
1079                 DRM_ERROR("can not ioremap virtual address for"
1080                                 " G33 hw status page\n");
1081                 return -ENOMEM;
1082         }
1083
1084         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1085         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1086
1087         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1088                          ring->status_page.gfx_addr);
1089         DRM_DEBUG_DRIVER("load hws at %p\n",
1090                          ring->status_page.page_addr);
1091         return 0;
1092 #endif
1093         return -EINVAL;
1094 }
1095
1096 static int i915_get_bridge_dev(struct drm_device *dev)
1097 {
1098         struct drm_i915_private *dev_priv = dev->dev_private;
1099         static struct pci_dev i915_bridge_dev;
1100
1101         i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
1102         if (!i915_bridge_dev.dev) {
1103                 DRM_ERROR("bridge device not found\n");
1104                 return -1;
1105         }
1106
1107         dev_priv->bridge_dev = &i915_bridge_dev;
1108         return 0;
1109 }
1110
1111 #define MCHBAR_I915 0x44
1112 #define MCHBAR_I965 0x48
1113 #define MCHBAR_SIZE (4*4096)
1114
1115 #define DEVEN_REG 0x54
1116 #define   DEVEN_MCHBAR_EN (1 << 28)
1117
1118 /* Allocate space for the MCH regs if needed, return nonzero on error */
1119 static int
1120 intel_alloc_mchbar_resource(struct drm_device *dev)
1121 {
1122         drm_i915_private_t *dev_priv = dev->dev_private;
1123         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1124         device_t vga;
1125         u32 temp_lo, temp_hi = 0;
1126         u64 mchbar_addr;
1127
1128         if (INTEL_INFO(dev)->gen >= 4)
1129                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1130         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1131         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1132
1133         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1134 #ifdef CONFIG_PNP
1135         if (mchbar_addr &&
1136             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1137                 return 0;
1138 #endif
1139
1140         /* Get some space for it */
1141         vga = device_get_parent(dev->dev);
1142         dev_priv->mch_res_rid = 0x100;
1143         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1144             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1145             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1146         if (dev_priv->mch_res == NULL) {
1147                 DRM_ERROR("failed mchbar resource alloc\n");
1148                 return (-ENOMEM);
1149         }
1150
1151         if (INTEL_INFO(dev)->gen >= 4)
1152                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1153                                        upper_32_bits(rman_get_start(dev_priv->mch_res)));
1154
1155         pci_write_config_dword(dev_priv->bridge_dev, reg,
1156                                lower_32_bits(rman_get_start(dev_priv->mch_res)));
1157         return 0;
1158 }
1159
1160 /* Setup MCHBAR if possible, return true if we should disable it again */
1161 static void
1162 intel_setup_mchbar(struct drm_device *dev)
1163 {
1164         drm_i915_private_t *dev_priv = dev->dev_private;
1165         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1166         u32 temp;
1167         bool enabled;
1168
1169         dev_priv->mchbar_need_disable = false;
1170
1171         if (IS_I915G(dev) || IS_I915GM(dev)) {
1172                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1173                 enabled = !!(temp & DEVEN_MCHBAR_EN);
1174         } else {
1175                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1176                 enabled = temp & 1;
1177         }
1178
1179         /* If it's already enabled, don't have to do anything */
1180         if (enabled)
1181                 return;
1182
1183         if (intel_alloc_mchbar_resource(dev))
1184                 return;
1185
1186         dev_priv->mchbar_need_disable = true;
1187
1188         /* Space is allocated or reserved, so enable it. */
1189         if (IS_I915G(dev) || IS_I915GM(dev)) {
1190                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1191                                        temp | DEVEN_MCHBAR_EN);
1192         } else {
1193                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1194                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1195         }
1196 }
1197
1198 static void
1199 intel_teardown_mchbar(struct drm_device *dev)
1200 {
1201         drm_i915_private_t *dev_priv = dev->dev_private;
1202         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1203         device_t vga;
1204         u32 temp;
1205
1206         if (dev_priv->mchbar_need_disable) {
1207                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1208                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1209                         temp &= ~DEVEN_MCHBAR_EN;
1210                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1211                 } else {
1212                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1213                         temp &= ~1;
1214                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1215                 }
1216         }
1217
1218         if (dev_priv->mch_res != NULL) {
1219                 vga = device_get_parent(dev->dev);
1220                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1221                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1222                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1223                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1224                 dev_priv->mch_res = NULL;
1225         }
1226 }
1227
1228 #if 0
1229 /* true = enable decode, false = disable decoder */
1230 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1231 {
1232         struct drm_device *dev = cookie;
1233
1234         intel_modeset_vga_set_state(dev, state);
1235         if (state)
1236                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1237                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1238         else
1239                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1240 }
1241
1242 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1243 {
1244         struct drm_device *dev = pci_get_drvdata(pdev);
1245         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1246         if (state == VGA_SWITCHEROO_ON) {
1247                 pr_info("switched on\n");
1248                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1249                 /* i915 resume handler doesn't set to D0 */
1250                 pci_set_power_state(dev->pdev, PCI_D0);
1251                 i915_resume(dev);
1252                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1253         } else {
1254                 pr_err("switched off\n");
1255                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1256                 i915_suspend(dev, pmm);
1257                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1258         }
1259 }
1260
1261 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1262 {
1263         struct drm_device *dev = pci_get_drvdata(pdev);
1264         bool can_switch;
1265
1266         spin_lock(&dev->count_lock);
1267         can_switch = (dev->open_count == 0);
1268         spin_unlock(&dev->count_lock);
1269         return can_switch;
1270 }
1271
1272 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1273         .set_gpu_state = i915_switcheroo_set_state,
1274         .reprobe = NULL,
1275         .can_switch = i915_switcheroo_can_switch,
1276 };
1277 #endif
1278
1279 static int i915_load_modeset_init(struct drm_device *dev)
1280 {
1281         struct drm_i915_private *dev_priv = dev->dev_private;
1282         int ret;
1283
1284         ret = intel_parse_bios(dev);
1285         if (ret)
1286                 DRM_INFO("failed to find VBIOS tables\n");
1287
1288 #if 0
1289         /* If we have > 1 VGA cards, then we need to arbitrate access
1290          * to the common VGA resources.
1291          *
1292          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1293          * then we do not take part in VGA arbitration and the
1294          * vga_client_register() fails with -ENODEV.
1295          */
1296         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1297         if (ret && ret != -ENODEV)
1298                 goto out;
1299
1300         intel_register_dsm_handler();
1301
1302         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1303         if (ret)
1304                 goto cleanup_vga_client;
1305
1306         /* Initialise stolen first so that we may reserve preallocated
1307          * objects for the BIOS to KMS transition.
1308          */
1309         ret = i915_gem_init_stolen(dev);
1310         if (ret)
1311                 goto cleanup_vga_switcheroo;
1312 #endif
1313
1314         ret = drm_irq_install(dev);
1315         if (ret)
1316                 goto cleanup_gem_stolen;
1317
1318         intel_power_domains_init_hw(dev);
1319
1320         /* Important: The output setup functions called by modeset_init need
1321          * working irqs for e.g. gmbus and dp aux transfers. */
1322         intel_modeset_init(dev);
1323
1324         ret = i915_gem_init(dev);
1325         if (ret)
1326                 goto cleanup_power;
1327
1328 #if 0
1329         INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1330 #endif
1331
1332         intel_modeset_gem_init(dev);
1333
1334         /* Always safe in the mode setting case. */
1335         /* FIXME: do pre/post-mode set stuff in core KMS code */
1336         dev->vblank_disable_allowed = 1;
1337         if (INTEL_INFO(dev)->num_pipes == 0) {
1338                 intel_display_power_put(dev, POWER_DOMAIN_VGA);
1339                 return 0;
1340         }
1341
1342         ret = intel_fbdev_init(dev);
1343         if (ret)
1344                 goto cleanup_gem;
1345
1346         /* Only enable hotplug handling once the fbdev is fully set up. */
1347         intel_hpd_init(dev);
1348
1349         /*
1350          * Some ports require correctly set-up hpd registers for detection to
1351          * work properly (leading to ghost connected connector status), e.g. VGA
1352          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1353          * irqs are fully enabled. Now we should scan for the initial config
1354          * only once hotplug handling is enabled, but due to screwed-up locking
1355          * around kms/fbdev init we can't protect the fdbev initial config
1356          * scanning against hotplug events. Hence do this first and ignore the
1357          * tiny window where we will loose hotplug notifactions.
1358          */
1359         intel_fbdev_initial_config(dev);
1360
1361         /* Only enable hotplug handling once the fbdev is fully set up. */
1362         dev_priv->enable_hotplug_processing = true;
1363
1364         drm_kms_helper_poll_init(dev);
1365
1366         return 0;
1367
1368 cleanup_gem:
1369         mutex_lock(&dev->struct_mutex);
1370         i915_gem_cleanup_ringbuffer(dev);
1371         i915_gem_context_fini(dev);
1372         mutex_unlock(&dev->struct_mutex);
1373         i915_gem_cleanup_aliasing_ppgtt(dev);
1374         drm_mm_takedown(&dev_priv->gtt.base.mm);
1375 cleanup_power:
1376         intel_display_power_put(dev, POWER_DOMAIN_VGA);
1377         drm_irq_uninstall(dev);
1378 cleanup_gem_stolen:
1379 #if 0
1380         i915_gem_cleanup_stolen(dev);
1381 cleanup_vga_switcheroo:
1382         vga_switcheroo_unregister_client(dev->pdev);
1383 cleanup_vga_client:
1384         vga_client_register(dev->pdev, NULL, NULL, NULL);
1385 out:
1386 #endif
1387         return ret;
1388 }
1389
1390 #if 0
1391 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1392 {
1393         struct drm_i915_master_private *master_priv;
1394
1395         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1396         if (!master_priv)
1397                 return -ENOMEM;
1398
1399         master->driver_priv = master_priv;
1400         return 0;
1401 }
1402
1403 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1404 {
1405         struct drm_i915_master_private *master_priv = master->driver_priv;
1406
1407         if (!master_priv)
1408                 return;
1409
1410         kfree(master_priv);
1411
1412         master->driver_priv = NULL;
1413 }
1414 #endif
1415
1416 #if IS_ENABLED(CONFIG_FB)
1417 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1418 {
1419         struct apertures_struct *ap;
1420         struct pci_dev *pdev = dev_priv->dev->pdev;
1421         bool primary;
1422
1423         ap = alloc_apertures(1);
1424         if (!ap)
1425                 return;
1426
1427         ap->ranges[0].base = dev_priv->gtt.mappable_base;
1428         ap->ranges[0].size = dev_priv->gtt.mappable_end;
1429
1430         primary =
1431                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1432
1433         remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1434
1435         kfree(ap);
1436 }
1437 #else
1438 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1439 {
1440 }
1441 #endif
1442
1443 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1444 {
1445 #if 0
1446         const struct intel_device_info *info = dev_priv->info;
1447
1448 #define PRINT_S(name) "%s"
1449 #define SEP_EMPTY
1450 #define PRINT_FLAG(name) info->name ? #name "," : ""
1451 #define SEP_COMMA ,
1452         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1453                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1454                          info->gen,
1455                          dev_priv->dev->pdev->device,
1456                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1457 #undef PRINT_S
1458 #undef SEP_EMPTY
1459 #undef PRINT_FLAG
1460 #undef SEP_COMMA
1461 #endif
1462 }
1463
1464 /**
1465  * i915_driver_load - setup chip and create an initial config
1466  * @dev: DRM device
1467  * @flags: startup flags
1468  *
1469  * The driver load routine has to do several things:
1470  *   - drive output discovery via intel_modeset_init()
1471  *   - initialize the memory manager
1472  *   - allocate initial config memory
1473  *   - setup the DRM framebuffer with the allocated memory
1474  */
1475 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1476 {
1477         struct drm_i915_private *dev_priv = dev->dev_private;
1478         const struct intel_device_info *info;
1479         unsigned long base, size;
1480         int ret = 0, mmio_bar, mmio_size;
1481         uint32_t aperture_size;
1482         static struct pci_dev i915_pdev;
1483
1484         /* XXX: dev->pci_device not present in Linux drm */
1485         info = i915_get_device_id(dev->pci_device);
1486
1487         /* XXX: struct pci_dev */
1488         i915_pdev.dev = dev->dev;
1489         dev->pdev = &i915_pdev;
1490         dev->pdev->device = dev->pci_device;
1491
1492         /* Refuse to load on gen6+ without kms enabled. */
1493         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1494                 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1495                 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1496                 return -ENODEV;
1497         }
1498
1499         /* UMS needs agp support. */
1500         if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp)
1501                 return -EINVAL;
1502
1503         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1504         if (dev_priv == NULL)
1505                 return -ENOMEM;
1506
1507         dev->dev_private = (void *)dev_priv;
1508         dev_priv->dev = dev;
1509         dev_priv->info = info;
1510
1511         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1512         lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
1513         spin_init(&dev_priv->backlight_lock, "i915bl");
1514         lockinit(&dev_priv->uncore.lock, "915gt", 0, LK_CANRECURSE);
1515         spin_init(&dev_priv->mm.object_stat_lock, "i915osl");
1516         lockinit(&dev_priv->dpio_lock, "i915dpio", 0, LK_CANRECURSE);
1517         lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
1518
1519         intel_pm_setup(dev);
1520
1521         intel_display_crc_init(dev);
1522
1523         i915_dump_device_info(dev_priv);
1524
1525         /* Not all pre-production machines fall into this category, only the
1526          * very first ones. Almost everything should work, except for maybe
1527          * suspend/resume. And we don't implement workarounds that affect only
1528          * pre-production machines. */
1529         if (IS_HSW_EARLY_SDV(dev))
1530                 DRM_INFO("This is an early pre-production Haswell machine. "
1531                          "It may not be fully functional.\n");
1532
1533         if (i915_get_bridge_dev(dev)) {
1534                 ret = -EIO;
1535                 goto free_priv;
1536         }
1537
1538         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1539         /* Before gen4, the registers and the GTT are behind different BARs.
1540          * However, from gen4 onwards, the registers and the GTT are shared
1541          * in the same BAR, so we want to restrict this ioremap from
1542          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1543          * the register BAR remains the same size for all the earlier
1544          * generations up to Ironlake.
1545          */
1546         if (info->gen < 5)
1547                 mmio_size = 512*1024;
1548         else
1549                 mmio_size = 2*1024*1024;
1550
1551 #if 0
1552         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1553         if (!dev_priv->regs) {
1554                 DRM_ERROR("failed to map registers\n");
1555                 ret = -EIO;
1556                 goto put_bridge;
1557         }
1558 #else
1559         base = drm_get_resource_start(dev, mmio_bar);
1560         size = drm_get_resource_len(dev, mmio_bar);
1561
1562         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1563             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1564 #endif
1565
1566         intel_uncore_early_sanitize(dev);
1567
1568         /* This must be called before any calls to HAS_PCH_* */
1569         intel_detect_pch(dev);
1570
1571         intel_uncore_init(dev);
1572
1573         ret = i915_gem_gtt_init(dev);
1574         if (ret)
1575                 goto out_regs;
1576
1577         if (drm_core_check_feature(dev, DRIVER_MODESET))
1578                 i915_kick_out_firmware_fb(dev_priv);
1579
1580 #if 0
1581         pci_set_master(dev->pdev);
1582
1583         /* overlay on gen2 is broken and can't address above 1G */
1584         if (IS_GEN2(dev))
1585                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1586
1587         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1588          * using 32bit addressing, overwriting memory if HWS is located
1589          * above 4GB.
1590          *
1591          * The documentation also mentions an issue with undefined
1592          * behaviour if any general state is accessed within a page above 4GB,
1593          * which also needs to be handled carefully.
1594          */
1595         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1596                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1597 #endif
1598
1599         aperture_size = dev_priv->gtt.mappable_end;
1600
1601         dev_priv->gtt.mappable =
1602                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1603                                      aperture_size);
1604         if (dev_priv->gtt.mappable == NULL) {
1605                 ret = -EIO;
1606                 goto out_gtt;
1607         }
1608
1609         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1610                                               aperture_size);
1611
1612         /* The i915 workqueue is primarily used for batched retirement of
1613          * requests (and thus managing bo) once the task has been completed
1614          * by the GPU. i915_gem_retire_requests() is called directly when we
1615          * need high-priority retirement, such as waiting for an explicit
1616          * bo.
1617          *
1618          * It is also used for periodic low-priority events, such as
1619          * idle-timers and recording error state.
1620          *
1621          * All tasks on the workqueue are expected to acquire the dev mutex
1622          * so there is no point in running more than one instance of the
1623          * workqueue at any time.  Use an ordered one.
1624          */
1625         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1626         if (dev_priv->wq == NULL) {
1627                 DRM_ERROR("Failed to create our workqueue.\n");
1628                 ret = -ENOMEM;
1629                 goto out_mtrrfree;
1630         }
1631
1632         intel_irq_init(dev);
1633         intel_uncore_sanitize(dev);
1634
1635         /* Try to make sure MCHBAR is enabled before poking at it */
1636         intel_setup_mchbar(dev);
1637         intel_setup_gmbus(dev);
1638         intel_opregion_setup(dev);
1639
1640         intel_setup_bios(dev);
1641
1642         i915_gem_load(dev);
1643
1644         /* On the 945G/GM, the chipset reports the MSI capability on the
1645          * integrated graphics even though the support isn't actually there
1646          * according to the published specs.  It doesn't appear to function
1647          * correctly in testing on 945G.
1648          * This may be a side effect of MSI having been made available for PEG
1649          * and the registers being closely associated.
1650          *
1651          * According to chipset errata, on the 965GM, MSI interrupts may
1652          * be lost or delayed, but we use them anyways to avoid
1653          * stuck interrupts on some machines.
1654          */
1655 #if 0
1656         if (!IS_I945G(dev) && !IS_I945GM(dev))
1657                 pci_enable_msi(dev->pdev);
1658 #endif
1659
1660         dev_priv->num_plane = 1;
1661         if (IS_VALLEYVIEW(dev))
1662                 dev_priv->num_plane = 2;
1663
1664         if (INTEL_INFO(dev)->num_pipes) {
1665                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1666                 if (ret)
1667                         goto out_gem_unload;
1668         }
1669
1670         intel_power_domains_init(dev);
1671
1672         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1673                 ret = i915_load_modeset_init(dev);
1674                 if (ret < 0) {
1675                         DRM_ERROR("failed to init modeset\n");
1676                         goto out_power_well;
1677                 }
1678         } else {
1679                 /* Start out suspended in ums mode. */
1680                 dev_priv->ums.mm_suspended = 1;
1681         }
1682
1683 #if 0
1684         i915_setup_sysfs(dev);
1685 #endif
1686
1687         if (INTEL_INFO(dev)->num_pipes) {
1688                 /* Must be done after probing outputs */
1689                 intel_opregion_init(dev);
1690 #if 0
1691                 acpi_video_register();
1692 #endif
1693         }
1694
1695         if (IS_GEN5(dev))
1696                 intel_gpu_ips_init(dev_priv);
1697
1698         intel_init_runtime_pm(dev_priv);
1699
1700         return 0;
1701
1702 out_power_well:
1703         intel_power_domains_remove(dev);
1704         drm_vblank_cleanup(dev);
1705 out_gem_unload:
1706
1707         intel_teardown_gmbus(dev);
1708         intel_teardown_mchbar(dev);
1709         pm_qos_remove_request(&dev_priv->pm_qos);
1710         destroy_workqueue(dev_priv->wq);
1711 out_mtrrfree:
1712         arch_phys_wc_del(dev_priv->gtt.mtrr);
1713 #if 0
1714         io_mapping_free(dev_priv->gtt.mappable);
1715 #endif
1716 out_gtt:
1717         list_del(&dev_priv->gtt.base.global_link);
1718         drm_mm_takedown(&dev_priv->gtt.base.mm);
1719         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1720 out_regs:
1721         intel_uncore_fini(dev);
1722 free_priv:
1723         kfree(dev_priv);
1724         return ret;
1725 }
1726
1727 int i915_driver_unload(struct drm_device *dev)
1728 {
1729         struct drm_i915_private *dev_priv = dev->dev_private;
1730         int ret;
1731
1732         ret = i915_gem_suspend(dev);
1733         if (ret) {
1734                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1735                 return ret;
1736         }
1737
1738         intel_fini_runtime_pm(dev_priv);
1739
1740         intel_gpu_ips_teardown();
1741
1742         /* The i915.ko module is still not prepared to be loaded when
1743          * the power well is not enabled, so just enable it in case
1744          * we're going to unload/reload. */
1745         intel_display_set_init_power(dev, true);
1746         intel_power_domains_remove(dev);
1747
1748 #if 0
1749         i915_teardown_sysfs(dev);
1750
1751         if (dev_priv->mm.inactive_shrinker.scan_objects)
1752                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1753
1754         io_mapping_free(dev_priv->gtt.mappable);
1755 #endif
1756         arch_phys_wc_del(dev_priv->gtt.mtrr);
1757
1758 #if 0
1759         acpi_video_unregister();
1760 #endif
1761
1762         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1763                 intel_fbdev_fini(dev);
1764                 intel_modeset_cleanup(dev);
1765 #if 0
1766                 cancel_work_sync(&dev_priv->console_resume_work);
1767 #endif
1768
1769                 /*
1770                  * free the memory space allocated for the child device
1771                  * config parsed from VBT
1772                  */
1773                 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1774                         kfree(dev_priv->vbt.child_dev);
1775                         dev_priv->vbt.child_dev = NULL;
1776                         dev_priv->vbt.child_dev_num = 0;
1777                 }
1778
1779         }
1780
1781         /* Free error state after interrupts are fully disabled. */
1782         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1783         cancel_work_sync(&dev_priv->gpu_error.work);
1784 #if 0
1785         i915_destroy_error_state(dev);
1786 #endif
1787
1788         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
1789
1790         intel_opregion_fini(dev);
1791
1792         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1793                 /* Flush any outstanding unpin_work. */
1794                 flush_workqueue(dev_priv->wq);
1795
1796                 mutex_lock(&dev->struct_mutex);
1797                 i915_gem_free_all_phys_object(dev);
1798                 i915_gem_cleanup_ringbuffer(dev);
1799                 i915_gem_context_fini(dev);
1800                 mutex_unlock(&dev->struct_mutex);
1801                 i915_gem_cleanup_aliasing_ppgtt(dev);
1802 #if 0
1803                 i915_gem_cleanup_stolen(dev);
1804 #endif
1805
1806                 if (!I915_NEED_GFX_HWS(dev))
1807                         i915_free_hws(dev);
1808         }
1809
1810         list_del(&dev_priv->gtt.base.global_link);
1811         WARN_ON(!list_empty(&dev_priv->vm_list));
1812
1813         drm_vblank_cleanup(dev);
1814
1815         intel_teardown_gmbus(dev);
1816         intel_teardown_mchbar(dev);
1817
1818         bus_generic_detach(dev->dev);
1819         drm_rmmap(dev, dev_priv->mmio_map);
1820         intel_teardown_gmbus(dev);
1821
1822         destroy_workqueue(dev_priv->wq);
1823         pm_qos_remove_request(&dev_priv->pm_qos);
1824
1825         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1826
1827         intel_uncore_fini(dev);
1828 #if 0
1829         if (dev_priv->regs != NULL)
1830                 pci_iounmap(dev->pdev, dev_priv->regs);
1831 #endif
1832
1833         pci_dev_put(dev_priv->bridge_dev);
1834         kfree(dev->dev_private);
1835
1836         return 0;
1837 }
1838
1839 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1840 {
1841         struct drm_i915_file_private *file_priv;
1842
1843         DRM_DEBUG_DRIVER("\n");
1844         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
1845         if (!file_priv)
1846                 return -ENOMEM;
1847
1848         file->driver_priv = file_priv;
1849
1850         spin_init(&file_priv->mm.lock, "i915_priv");
1851         INIT_LIST_HEAD(&file_priv->mm.request_list);
1852
1853         idr_init(&file_priv->context_idr);
1854
1855         return 0;
1856 }
1857
1858 /**
1859  * i915_driver_lastclose - clean up after all DRM clients have exited
1860  * @dev: DRM device
1861  *
1862  * Take care of cleaning up after all DRM clients have exited.  In the
1863  * mode setting case, we want to restore the kernel's initial mode (just
1864  * in case the last client left us in a bad state).
1865  *
1866  * Additionally, in the non-mode setting case, we'll tear down the GTT
1867  * and DMA structures, since the kernel won't be using them, and clea
1868  * up any GEM state.
1869  */
1870 void i915_driver_lastclose(struct drm_device * dev)
1871 {
1872         drm_i915_private_t *dev_priv = dev->dev_private;
1873
1874         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1875          * goes right around and calls lastclose. Check for this and don't clean
1876          * up anything. */
1877         if (!dev_priv)
1878                 return;
1879
1880         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1881 #if 0
1882                 intel_fbdev_restore_mode(dev);
1883                 vga_switcheroo_process_delayed_switch();
1884 #endif
1885                 return;
1886         }
1887
1888         i915_gem_lastclose(dev);
1889
1890         i915_dma_cleanup(dev);
1891 }
1892
1893 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1894 {
1895         mutex_lock(&dev->struct_mutex);
1896         i915_gem_context_close(dev, file_priv);
1897         i915_gem_release(dev, file_priv);
1898         mutex_unlock(&dev->struct_mutex);
1899 }
1900
1901 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1902 {
1903         struct drm_i915_file_private *file_priv = file->driver_priv;
1904
1905         kfree(file_priv);
1906 }
1907
1908 struct drm_ioctl_desc i915_ioctls[] = {
1909         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1910         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1911         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1912         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1913         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1914         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1915         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1916         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1917         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1918         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1919         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1920         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1921         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1922         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1923         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1924         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1925         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1926         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1927         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1928         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1929         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1930         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1931         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1932         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1933         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1934         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1935         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1936         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1937         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1938         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1939         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1940         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1941         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1942         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1943         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1944         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1945         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1946         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1947         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1948         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1949         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1950         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1951         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1952         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1953         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1954         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1955         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1956         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1957 };
1958
1959 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1960
1961 /*
1962  * This is really ugly: Because old userspace abused the linux agp interface to
1963  * manage the gtt, we need to claim that all intel devices are agp.  For
1964  * otherwise the drm core refuses to initialize the agp support code.
1965  */
1966 int i915_driver_device_is_agp(struct drm_device * dev)
1967 {
1968         return 1;
1969 }