sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 /*
  37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  38  *
  39  * Written by Bill Paul <wpaul@windriver.com>
  40  * Senior Engineer, Wind River Systems
  41  */
  42
  43 /*
  44  * The Broadcom BCM5700 is based on technology originally developed by
  45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  49  * frames, highly configurable RX filtering, and 16 RX and TX queues
  50  * (which, along with RX filter rules, can be used for QOS applications).
  51  * Other features, such as TCP segmentation, may be available as part
  52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  53  * firmware images can be stored in hardware and need not be compiled
  54  * into the driver.
  55  *
  56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  58  *
  59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  61  * does not support external SSRAM.
  62  *
  63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  64  * brand name, which is functionally similar but lacks PCI-X support.
  65  *
  66  * Without external SSRAM, you can only have at most 4 TX rings,
  67  * and the use of the mini RX ring is disabled. This seems to imply
  68  * that these features are simply not available on the BCM5701. As a
  69  * result, this driver does not implement any support for the mini RX
  70  * ring.
  71  */
  72
  73 #include "opt_polling.h"
  74
  75 #include <sys/param.h>
  76 #include <sys/bus.h>
  77 #include <sys/endian.h>
  78 #include <sys/kernel.h>
  79 #include <sys/ktr.h>
  80 #include <sys/interrupt.h>
  81 #include <sys/mbuf.h>
  82 #include <sys/malloc.h>
  83 #include <sys/queue.h>
  84 #include <sys/rman.h>
  85 #include <sys/serialize.h>
  86 #include <sys/socket.h>
  87 #include <sys/sockio.h>
  88 #include <sys/sysctl.h>
  89
  90 #include <net/bpf.h>
  91 #include <net/ethernet.h>
  92 #include <net/if.h>
  93 #include <net/if_arp.h>
  94 #include <net/if_dl.h>
  95 #include <net/if_media.h>
  96 #include <net/if_types.h>
  97 #include <net/ifq_var.h>
  98 #include <net/vlan/if_vlan_var.h>
  99 #include <net/vlan/if_vlan_ether.h>
 100
 101 #include <dev/netif/mii_layer/mii.h>
 102 #include <dev/netif/mii_layer/miivar.h>
 103 #include <dev/netif/mii_layer/brgphyreg.h>
 104
 105 #include <bus/pci/pcidevs.h>
 106 #include <bus/pci/pcireg.h>
 107 #include <bus/pci/pcivar.h>
 108
 109 #include <dev/netif/bge/if_bgereg.h>
 110
 111 /* "device miibus" required.  See GENERIC if you get errors here. */
 112 #include "miibus_if.h"
 113
 114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
 115 #define BGE_MIN_FRAME           60
 116
 117 static const struct bge_type bge_devs[] = {
 118         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 119                 "3COM 3C996 Gigabit Ethernet" },
 120
 121         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 122                 "Alteon BCM5700 Gigabit Ethernet" },
 123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 124                 "Alteon BCM5701 Gigabit Ethernet" },
 125
 126         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 127                 "Altima AC1000 Gigabit Ethernet" },
 128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 129                 "Altima AC1002 Gigabit Ethernet" },
 130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 131                 "Altima AC9100 Gigabit Ethernet" },
 132
 133         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 134                 "Apple BCM5701 Gigabit Ethernet" },
 135
 136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 137                 "Broadcom BCM5700 Gigabit Ethernet" },
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 139                 "Broadcom BCM5701 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 141                 "Broadcom BCM5702 Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 143                 "Broadcom BCM5702X Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 145                 "Broadcom BCM5702 Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 147                 "Broadcom BCM5703 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 149                 "Broadcom BCM5703X Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 151                 "Broadcom BCM5703 Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 153                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 155                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 159                 "Broadcom BCM5705 Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 161                 "Broadcom BCM5705F Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 163                 "Broadcom BCM5705K Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 165                 "Broadcom BCM5705M Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 167                 "Broadcom BCM5705M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 169                 "Broadcom BCM5714C Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 171                 "Broadcom BCM5714S Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 173                 "Broadcom BCM5715 Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 175                 "Broadcom BCM5715S Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 177                 "Broadcom BCM5720 Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 179                 "Broadcom BCM5721 Gigabit Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 181                 "Broadcom BCM5722 Gigabit Ethernet" },
 182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
 183                 "Broadcom BCM5723 Gigabit Ethernet" },
 184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 185                 "Broadcom BCM5750 Gigabit Ethernet" },
 186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 187                 "Broadcom BCM5750M Gigabit Ethernet" },
 188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 189                 "Broadcom BCM5751 Gigabit Ethernet" },
 190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 191                 "Broadcom BCM5751F Gigabit Ethernet" },
 192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 193                 "Broadcom BCM5751M Gigabit Ethernet" },
 194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 195                 "Broadcom BCM5752 Gigabit Ethernet" },
 196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 197                 "Broadcom BCM5752M Gigabit Ethernet" },
 198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 199                 "Broadcom BCM5753 Gigabit Ethernet" },
 200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 201                 "Broadcom BCM5753F Gigabit Ethernet" },
 202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 203                 "Broadcom BCM5753M Gigabit Ethernet" },
 204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 205                 "Broadcom BCM5754 Gigabit Ethernet" },
 206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 207                 "Broadcom BCM5754M Gigabit Ethernet" },
 208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 209                 "Broadcom BCM5755 Gigabit Ethernet" },
 210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 211                 "Broadcom BCM5755M Gigabit Ethernet" },
 212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 213                 "Broadcom BCM5756 Gigabit Ethernet" },
 214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
 215                 "Broadcom BCM5761 Gigabit Ethernet" },
 216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
 217                 "Broadcom BCM5761E Gigabit Ethernet" },
 218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
 219                 "Broadcom BCM5761S Gigabit Ethernet" },
 220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
 221                 "Broadcom BCM5761SE Gigabit Ethernet" },
 222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
 223                 "Broadcom BCM5764 Gigabit Ethernet" },
 224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 225                 "Broadcom BCM5780 Gigabit Ethernet" },
 226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 227                 "Broadcom BCM5780S Gigabit Ethernet" },
 228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 229                 "Broadcom BCM5781 Gigabit Ethernet" },
 230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 231                 "Broadcom BCM5782 Gigabit Ethernet" },
 232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
 233                 "Broadcom BCM5784 Gigabit Ethernet" },
 234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
 235                 "Broadcom BCM5785F Gigabit Ethernet" },
 236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
 237                 "Broadcom BCM5785G Gigabit Ethernet" },
 238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 239                 "Broadcom BCM5786 Gigabit Ethernet" },
 240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 241                 "Broadcom BCM5787 Gigabit Ethernet" },
 242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 243                 "Broadcom BCM5787F Gigabit Ethernet" },
 244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 245                 "Broadcom BCM5787M Gigabit Ethernet" },
 246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 247                 "Broadcom BCM5788 Gigabit Ethernet" },
 248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 249                 "Broadcom BCM5789 Gigabit Ethernet" },
 250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 251                 "Broadcom BCM5901 Fast Ethernet" },
 252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 253                 "Broadcom BCM5901A2 Fast Ethernet" },
 254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 255                 "Broadcom BCM5903M Fast Ethernet" },
 256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
 257                 "Broadcom BCM5906 Fast Ethernet"},
 258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
 259                 "Broadcom BCM5906M Fast Ethernet"},
 260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
 261                 "Broadcom BCM57760 Gigabit Ethernet"},
 262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
 263                 "Broadcom BCM57780 Gigabit Ethernet"},
 264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
 265                 "Broadcom BCM57788 Gigabit Ethernet"},
 266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
 267                 "Broadcom BCM57790 Gigabit Ethernet"},
 268         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 269                 "SysKonnect Gigabit Ethernet" },
 270
 271         { 0, 0, NULL }
 272 };
 273
 274 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 275 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 276 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 277 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 278 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 279 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 280 #define BGE_IS_5788(sc)                 ((sc)->bge_flags & BGE_FLAG_5788)
 281
 282 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 283
 284 static int      bge_probe(device_t);
 285 static int      bge_attach(device_t);
 286 static int      bge_detach(device_t);
 287 static void     bge_txeof(struct bge_softc *);
 288 static void     bge_rxeof(struct bge_softc *);
 289
 290 static void     bge_tick(void *);
 291 static void     bge_stats_update(struct bge_softc *);
 292 static void     bge_stats_update_regs(struct bge_softc *);
 293 static struct mbuf *
 294                 bge_defrag_shortdma(struct mbuf *);
 295 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 296
 297 #ifdef DEVICE_POLLING
 298 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 299 #endif
 300 static void     bge_intr(void *);
 301 static void     bge_enable_intr(struct bge_softc *);
 302 static void     bge_disable_intr(struct bge_softc *);
 303 static void     bge_start(struct ifnet *);
 304 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 305 static void     bge_init(void *);
 306 static void     bge_stop(struct bge_softc *);
 307 static void     bge_watchdog(struct ifnet *);
 308 static void     bge_shutdown(device_t);
 309 static int      bge_suspend(device_t);
 310 static int      bge_resume(device_t);
 311 static int      bge_ifmedia_upd(struct ifnet *);
 312 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 313
 314 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 315 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 316
 317 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 318 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 319
 320 static void     bge_setmulti(struct bge_softc *);
 321 static void     bge_setpromisc(struct bge_softc *);
 322
 323 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 324 static void     bge_free_jumbo_mem(struct bge_softc *);
 325 static struct bge_jslot
 326                 *bge_jalloc(struct bge_softc *);
 327 static void     bge_jfree(void *);
 328 static void     bge_jref(void *);
 329 static int      bge_newbuf_std(struct bge_softc *, int, int);
 330 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
 331 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
 332 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
 333 static int      bge_init_rx_ring_std(struct bge_softc *);
 334 static void     bge_free_rx_ring_std(struct bge_softc *);
 335 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 336 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 337 static void     bge_free_tx_ring(struct bge_softc *);
 338 static int      bge_init_tx_ring(struct bge_softc *);
 339
 340 static int      bge_chipinit(struct bge_softc *);
 341 static int      bge_blockinit(struct bge_softc *);
 342
 343 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 344 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 345 #ifdef notdef
 346 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 347 #endif
 348 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 349 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 350 static void     bge_writembx(struct bge_softc *, int, int);
 351
 352 static int      bge_miibus_readreg(device_t, int, int);
 353 static int      bge_miibus_writereg(device_t, int, int, int);
 354 static void     bge_miibus_statchg(device_t);
 355 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 356 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 357 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 358 static void     bge_autopoll_link_upd(struct bge_softc *, uint32_t);
 359
 360 static void     bge_reset(struct bge_softc *);
 361
 362 static int      bge_dma_alloc(struct bge_softc *);
 363 static void     bge_dma_free(struct bge_softc *);
 364 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 365                                     bus_dma_tag_t *, bus_dmamap_t *,
 366                                     void **, bus_addr_t *);
 367 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 368
 369 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 370 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 371 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 372 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
 373
 374 static void     bge_coal_change(struct bge_softc *);
 375 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 376 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 377 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 378 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 379 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 380
 381 /*
 382  * Set following tunable to 1 for some IBM blade servers with the DNLK
 383  * switch module. Auto negotiation is broken for those configurations.
 384  */
 385 static int      bge_fake_autoneg = 0;
 386 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 387
 388 /* Interrupt moderation control variables. */
 389 static int      bge_rx_coal_ticks = 100;        /* usec */
 390 static int      bge_tx_coal_ticks = 1023;       /* usec */
 391 static int      bge_rx_max_coal_bds = 80;
 392 static int      bge_tx_max_coal_bds = 128;
 393
 394 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 395 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 396 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 397 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 398
 399 #if !defined(KTR_IF_BGE)
 400 #define KTR_IF_BGE      KTR_ALL
 401 #endif
 402 KTR_INFO_MASTER(if_bge);
 403 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
 404 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
 405 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
 406 #define logif(name)     KTR_LOG(if_bge_ ## name)
 407
 408 static device_method_t bge_methods[] = {
 409         /* Device interface */
 410         DEVMETHOD(device_probe,         bge_probe),
 411         DEVMETHOD(device_attach,        bge_attach),
 412         DEVMETHOD(device_detach,        bge_detach),
 413         DEVMETHOD(device_shutdown,      bge_shutdown),
 414         DEVMETHOD(device_suspend,       bge_suspend),
 415         DEVMETHOD(device_resume,        bge_resume),
 416
 417         /* bus interface */
 418         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 419         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 420
 421         /* MII interface */
 422         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 423         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 424         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 425
 426         { 0, 0 }
 427 };
 428
 429 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 430 static devclass_t bge_devclass;
 431
 432 DECLARE_DUMMY_MODULE(if_bge);
 433 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
 434 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
 435
 436 static uint32_t
 437 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 438 {
 439         device_t dev = sc->bge_dev;
 440         uint32_t val;
 441
 442         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 443             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 444                 return 0;
 445
 446         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 447         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 448         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 449         return (val);
 450 }
 451
 452 static void
 453 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 454 {
 455         device_t dev = sc->bge_dev;
 456
 457         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 458             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 459                 return;
 460
 461         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 462         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 463         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 464 }
 465
 466 #ifdef notdef
 467 static uint32_t
 468 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 469 {
 470         device_t dev = sc->bge_dev;
 471
 472         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 473         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 474 }
 475 #endif
 476
 477 static void
 478 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 479 {
 480         device_t dev = sc->bge_dev;
 481
 482         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 483         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 484 }
 485
 486 static void
 487 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 488 {
 489         CSR_WRITE_4(sc, off, val);
 490 }
 491
 492 static void
 493 bge_writembx(struct bge_softc *sc, int off, int val)
 494 {
 495         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 496                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 497
 498         CSR_WRITE_4(sc, off, val);
 499 }
 500
 501 static uint8_t
 502 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 503 {
 504         uint32_t access, byte = 0;
 505         int i;
 506
 507         /* Lock. */
 508         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 509         for (i = 0; i < 8000; i++) {
 510                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 511                         break;
 512                 DELAY(20);
 513         }
 514         if (i == 8000)
 515                 return (1);
 516
 517         /* Enable access. */
 518         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 519         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 520
 521         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 522         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 523         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 524                 DELAY(10);
 525                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 526                         DELAY(10);
 527                         break;
 528                 }
 529         }
 530
 531         if (i == BGE_TIMEOUT * 10) {
 532                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 533                 return (1);
 534         }
 535
 536         /* Get result. */
 537         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 538
 539         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 540
 541         /* Disable access. */
 542         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 543
 544         /* Unlock. */
 545         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 546         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 547
 548         return (0);
 549 }
 550
 551 /*
 552  * Read a sequence of bytes from NVRAM.
 553  */
 554 static int
 555 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 556 {
 557         int err = 0, i;
 558         uint8_t byte = 0;
 559
 560         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 561                 return (1);
 562
 563         for (i = 0; i < cnt; i++) {
 564                 err = bge_nvram_getbyte(sc, off + i, &byte);
 565                 if (err)
 566                         break;
 567                 *(dest + i) = byte;
 568         }
 569
 570         return (err ? 1 : 0);
 571 }
 572
 573 /*
 574  * Read a byte of data stored in the EEPROM at address 'addr.' The
 575  * BCM570x supports both the traditional bitbang interface and an
 576  * auto access interface for reading the EEPROM. We use the auto
 577  * access method.
 578  */
 579 static uint8_t
 580 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 581 {
 582         int i;
 583         uint32_t byte = 0;
 584
 585         /*
 586          * Enable use of auto EEPROM access so we can avoid
 587          * having to use the bitbang method.
 588          */
 589         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 590
 591         /* Reset the EEPROM, load the clock period. */
 592         CSR_WRITE_4(sc, BGE_EE_ADDR,
 593             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 594         DELAY(20);
 595
 596         /* Issue the read EEPROM command. */
 597         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 598
 599         /* Wait for completion */
 600         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 601                 DELAY(10);
 602                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 603                         break;
 604         }
 605
 606         if (i == BGE_TIMEOUT) {
 607                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 608                 return(1);
 609         }
 610
 611         /* Get result. */
 612         byte = CSR_READ_4(sc, BGE_EE_DATA);
 613
 614         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 615
 616         return(0);
 617 }
 618
 619 /*
 620  * Read a sequence of bytes from the EEPROM.
 621  */
 622 static int
 623 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 624 {
 625         size_t i;
 626         int err;
 627         uint8_t byte;
 628
 629         for (byte = 0, err = 0, i = 0; i < len; i++) {
 630                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 631                 if (err)
 632                         break;
 633                 *(dest + i) = byte;
 634         }
 635
 636         return(err ? 1 : 0);
 637 }
 638
 639 static int
 640 bge_miibus_readreg(device_t dev, int phy, int reg)
 641 {
 642         struct bge_softc *sc = device_get_softc(dev);
 643         uint32_t val;
 644         int i;
 645
 646         KASSERT(phy == sc->bge_phyno,
 647             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
 648
 649         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 650         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 651                 CSR_WRITE_4(sc, BGE_MI_MODE,
 652                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 653                 DELAY(80);
 654         }
 655
 656         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 657             BGE_MIPHY(phy) | BGE_MIREG(reg));
 658
 659         /* Poll for the PHY register access to complete. */
 660         for (i = 0; i < BGE_TIMEOUT; i++) {
 661                 DELAY(10);
 662                 val = CSR_READ_4(sc, BGE_MI_COMM);
 663                 if ((val & BGE_MICOMM_BUSY) == 0) {
 664                         DELAY(5);
 665                         val = CSR_READ_4(sc, BGE_MI_COMM);
 666                         break;
 667                 }
 668         }
 669         if (i == BGE_TIMEOUT) {
 670                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 671                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 672                 val = 0;
 673         }
 674
 675         /* Restore the autopoll bit if necessary. */
 676         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 677                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 678                 DELAY(80);
 679         }
 680
 681         if (val & BGE_MICOMM_READFAIL)
 682                 return 0;
 683
 684         return (val & 0xFFFF);
 685 }
 686
 687 static int
 688 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 689 {
 690         struct bge_softc *sc = device_get_softc(dev);
 691         int i;
 692
 693         KASSERT(phy == sc->bge_phyno,
 694             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
 695
 696         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 697             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 698                return 0;
 699
 700         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 701         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 702                 CSR_WRITE_4(sc, BGE_MI_MODE,
 703                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 704                 DELAY(80);
 705         }
 706
 707         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 708             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 709
 710         for (i = 0; i < BGE_TIMEOUT; i++) {
 711                 DELAY(10);
 712                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 713                         DELAY(5);
 714                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 715                         break;
 716                 }
 717         }
 718         if (i == BGE_TIMEOUT) {
 719                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 720                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 721         }
 722
 723         /* Restore the autopoll bit if necessary. */
 724         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 725                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 726                 DELAY(80);
 727         }
 728
 729         return 0;
 730 }
 731
 732 static void
 733 bge_miibus_statchg(device_t dev)
 734 {
 735         struct bge_softc *sc;
 736         struct mii_data *mii;
 737
 738         sc = device_get_softc(dev);
 739         mii = device_get_softc(sc->bge_miibus);
 740
 741         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 742             (IFM_ACTIVE | IFM_AVALID)) {
 743                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 744                 case IFM_10_T:
 745                 case IFM_100_TX:
 746                         sc->bge_link = 1;
 747                         break;
 748                 case IFM_1000_T:
 749                 case IFM_1000_SX:
 750                 case IFM_2500_SX:
 751                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 752                                 sc->bge_link = 1;
 753                         else
 754                                 sc->bge_link = 0;
 755                         break;
 756                 default:
 757                         sc->bge_link = 0;
 758                         break;
 759                 }
 760         } else {
 761                 sc->bge_link = 0;
 762         }
 763         if (sc->bge_link == 0)
 764                 return;
 765
 766         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 767         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 768             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 769                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 770         } else {
 771                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 772         }
 773
 774         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 775                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 776         } else {
 777                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 778         }
 779 }
 780
 781 /*
 782  * Memory management for jumbo frames.
 783  */
 784 static int
 785 bge_alloc_jumbo_mem(struct bge_softc *sc)
 786 {
 787         struct ifnet *ifp = &sc->arpcom.ac_if;
 788         struct bge_jslot *entry;
 789         uint8_t *ptr;
 790         bus_addr_t paddr;
 791         int i, error;
 792
 793         /*
 794          * Create tag for jumbo mbufs.
 795          * This is really a bit of a kludge. We allocate a special
 796          * jumbo buffer pool which (thanks to the way our DMA
 797          * memory allocation works) will consist of contiguous
 798          * pages. This means that even though a jumbo buffer might
 799          * be larger than a page size, we don't really need to
 800          * map it into more than one DMA segment. However, the
 801          * default mbuf tag will result in multi-segment mappings,
 802          * so we have to create a special jumbo mbuf tag that
 803          * lets us get away with mapping the jumbo buffers as
 804          * a single segment. I think eventually the driver should
 805          * be changed so that it uses ordinary mbufs and cluster
 806          * buffers, i.e. jumbo frames can span multiple DMA
 807          * descriptors. But that's a project for another day.
 808          */
 809
 810         /*
 811          * Create DMA stuffs for jumbo RX ring.
 812          */
 813         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 814                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 815                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 816                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
 817                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 818         if (error) {
 819                 if_printf(ifp, "could not create jumbo RX ring\n");
 820                 return error;
 821         }
 822
 823         /*
 824          * Create DMA stuffs for jumbo buffer block.
 825          */
 826         error = bge_dma_block_alloc(sc, BGE_JMEM,
 827                                     &sc->bge_cdata.bge_jumbo_tag,
 828                                     &sc->bge_cdata.bge_jumbo_map,
 829                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 830                                     &paddr);
 831         if (error) {
 832                 if_printf(ifp, "could not create jumbo buffer\n");
 833                 return error;
 834         }
 835
 836         SLIST_INIT(&sc->bge_jfree_listhead);
 837
 838         /*
 839          * Now divide it up into 9K pieces and save the addresses
 840          * in an array. Note that we play an evil trick here by using
 841          * the first few bytes in the buffer to hold the the address
 842          * of the softc structure for this interface. This is because
 843          * bge_jfree() needs it, but it is called by the mbuf management
 844          * code which will not pass it to us explicitly.
 845          */
 846         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 847                 entry = &sc->bge_cdata.bge_jslots[i];
 848                 entry->bge_sc = sc;
 849                 entry->bge_buf = ptr;
 850                 entry->bge_paddr = paddr;
 851                 entry->bge_inuse = 0;
 852                 entry->bge_slot = i;
 853                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 854
 855                 ptr += BGE_JLEN;
 856                 paddr += BGE_JLEN;
 857         }
 858         return 0;
 859 }
 860
 861 static void
 862 bge_free_jumbo_mem(struct bge_softc *sc)
 863 {
 864         /* Destroy jumbo RX ring. */
 865         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 866                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 867                            sc->bge_ldata.bge_rx_jumbo_ring);
 868
 869         /* Destroy jumbo buffer block. */
 870         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 871                            sc->bge_cdata.bge_jumbo_map,
 872                            sc->bge_ldata.bge_jumbo_buf);
 873 }
 874
 875 /*
 876  * Allocate a jumbo buffer.
 877  */
 878 static struct bge_jslot *
 879 bge_jalloc(struct bge_softc *sc)
 880 {
 881         struct bge_jslot *entry;
 882
 883         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 884         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 885         if (entry) {
 886                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 887                 entry->bge_inuse = 1;
 888         } else {
 889                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 890         }
 891         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 892         return(entry);
 893 }
 894
 895 /*
 896  * Adjust usage count on a jumbo buffer.
 897  */
 898 static void
 899 bge_jref(void *arg)
 900 {
 901         struct bge_jslot *entry = (struct bge_jslot *)arg;
 902         struct bge_softc *sc = entry->bge_sc;
 903
 904         if (sc == NULL)
 905                 panic("bge_jref: can't find softc pointer!");
 906
 907         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 908                 panic("bge_jref: asked to reference buffer "
 909                     "that we don't manage!");
 910         } else if (entry->bge_inuse == 0) {
 911                 panic("bge_jref: buffer already free!");
 912         } else {
 913                 atomic_add_int(&entry->bge_inuse, 1);
 914         }
 915 }
 916
 917 /*
 918  * Release a jumbo buffer.
 919  */
 920 static void
 921 bge_jfree(void *arg)
 922 {
 923         struct bge_jslot *entry = (struct bge_jslot *)arg;
 924         struct bge_softc *sc = entry->bge_sc;
 925
 926         if (sc == NULL)
 927                 panic("bge_jfree: can't find softc pointer!");
 928
 929         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 930                 panic("bge_jfree: asked to free buffer that we don't manage!");
 931         } else if (entry->bge_inuse == 0) {
 932                 panic("bge_jfree: buffer already free!");
 933         } else {
 934                 /*
 935                  * Possible MP race to 0, use the serializer.  The atomic insn
 936                  * is still needed for races against bge_jref().
 937                  */
 938                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 939                 atomic_subtract_int(&entry->bge_inuse, 1);
 940                 if (entry->bge_inuse == 0) {
 941                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 942                                           entry, jslot_link);
 943                 }
 944                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 945         }
 946 }
 947
 948
 949 /*
 950  * Intialize a standard receive ring descriptor.
 951  */
 952 static int
 953 bge_newbuf_std(struct bge_softc *sc, int i, int init)
 954 {
 955         struct mbuf *m_new = NULL;
 956         bus_dma_segment_t seg;
 957         bus_dmamap_t map;
 958         int error, nsegs;
 959
 960         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 961         if (m_new == NULL)
 962                 return ENOBUFS;
 963         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 964
 965         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 966                 m_adj(m_new, ETHER_ALIGN);
 967
 968         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
 969                         sc->bge_cdata.bge_rx_tmpmap, m_new,
 970                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 971         if (error) {
 972                 m_freem(m_new);
 973                 return error;
 974         }
 975
 976         if (!init) {
 977                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 978                                 sc->bge_cdata.bge_rx_std_dmamap[i],
 979                                 BUS_DMASYNC_POSTREAD);
 980                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 981                         sc->bge_cdata.bge_rx_std_dmamap[i]);
 982         }
 983
 984         map = sc->bge_cdata.bge_rx_tmpmap;
 985         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
 986         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
 987
 988         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
 989         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
 990
 991         bge_setup_rxdesc_std(sc, i);
 992         return 0;
 993 }
 994
 995 static void
 996 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
 997 {
 998         struct bge_rxchain *rc;
 999         struct bge_rx_bd *r;
1000
1001         rc = &sc->bge_cdata.bge_rx_std_chain[i];
1002         r = &sc->bge_ldata.bge_rx_std_ring[i];
1003
1004         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1005         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1006         r->bge_len = rc->bge_mbuf->m_len;
1007         r->bge_idx = i;
1008         r->bge_flags = BGE_RXBDFLAG_END;
1009 }
1010
1011 /*
1012  * Initialize a jumbo receive ring descriptor. This allocates
1013  * a jumbo buffer from the pool managed internally by the driver.
1014  */
1015 static int
1016 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
1017 {
1018         struct mbuf *m_new = NULL;
1019         struct bge_jslot *buf;
1020         bus_addr_t paddr;
1021
1022         /* Allocate the mbuf. */
1023         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1024         if (m_new == NULL)
1025                 return ENOBUFS;
1026
1027         /* Allocate the jumbo buffer */
1028         buf = bge_jalloc(sc);
1029         if (buf == NULL) {
1030                 m_freem(m_new);
1031                 return ENOBUFS;
1032         }
1033
1034         /* Attach the buffer to the mbuf. */
1035         m_new->m_ext.ext_arg = buf;
1036         m_new->m_ext.ext_buf = buf->bge_buf;
1037         m_new->m_ext.ext_free = bge_jfree;
1038         m_new->m_ext.ext_ref = bge_jref;
1039         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1040
1041         m_new->m_flags |= M_EXT;
1042
1043         m_new->m_data = m_new->m_ext.ext_buf;
1044         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1045
1046         paddr = buf->bge_paddr;
1047         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1048                 m_adj(m_new, ETHER_ALIGN);
1049                 paddr += ETHER_ALIGN;
1050         }
1051
1052         /* Save necessary information */
1053         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1054         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1055
1056         /* Set up the descriptor. */
1057         bge_setup_rxdesc_jumbo(sc, i);
1058         return 0;
1059 }
1060
1061 static void
1062 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1063 {
1064         struct bge_rx_bd *r;
1065         struct bge_rxchain *rc;
1066
1067         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1068         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1069
1070         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1071         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1072         r->bge_len = rc->bge_mbuf->m_len;
1073         r->bge_idx = i;
1074         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1075 }
1076
1077 static int
1078 bge_init_rx_ring_std(struct bge_softc *sc)
1079 {
1080         int i, error;
1081
1082         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1083                 error = bge_newbuf_std(sc, i, 1);
1084                 if (error)
1085                         return error;
1086         };
1087
1088         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1089         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1090
1091         return(0);
1092 }
1093
1094 static void
1095 bge_free_rx_ring_std(struct bge_softc *sc)
1096 {
1097         int i;
1098
1099         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1100                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1101
1102                 if (rc->bge_mbuf != NULL) {
1103                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1104                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1105                         m_freem(rc->bge_mbuf);
1106                         rc->bge_mbuf = NULL;
1107                 }
1108                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1109                     sizeof(struct bge_rx_bd));
1110         }
1111 }
1112
1113 static int
1114 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1115 {
1116         struct bge_rcb *rcb;
1117         int i, error;
1118
1119         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1120                 error = bge_newbuf_jumbo(sc, i, 1);
1121                 if (error)
1122                         return error;
1123         };
1124
1125         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1126
1127         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1128         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1129         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1130
1131         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1132
1133         return(0);
1134 }
1135
1136 static void
1137 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1138 {
1139         int i;
1140
1141         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1142                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1143
1144                 if (rc->bge_mbuf != NULL) {
1145                         m_freem(rc->bge_mbuf);
1146                         rc->bge_mbuf = NULL;
1147                 }
1148                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1149                     sizeof(struct bge_rx_bd));
1150         }
1151 }
1152
1153 static void
1154 bge_free_tx_ring(struct bge_softc *sc)
1155 {
1156         int i;
1157
1158         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1159                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1160                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1161                                           sc->bge_cdata.bge_tx_dmamap[i]);
1162                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1163                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1164                 }
1165                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1166                     sizeof(struct bge_tx_bd));
1167         }
1168 }
1169
1170 static int
1171 bge_init_tx_ring(struct bge_softc *sc)
1172 {
1173         sc->bge_txcnt = 0;
1174         sc->bge_tx_saved_considx = 0;
1175         sc->bge_tx_prodidx = 0;
1176
1177         /* Initialize transmit producer index for host-memory send ring. */
1178         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1179
1180         /* 5700 b2 errata */
1181         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1182                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1183
1184         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1185         /* 5700 b2 errata */
1186         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1187                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1188
1189         return(0);
1190 }
1191
1192 static void
1193 bge_setmulti(struct bge_softc *sc)
1194 {
1195         struct ifnet *ifp;
1196         struct ifmultiaddr *ifma;
1197         uint32_t hashes[4] = { 0, 0, 0, 0 };
1198         int h, i;
1199
1200         ifp = &sc->arpcom.ac_if;
1201
1202         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1203                 for (i = 0; i < 4; i++)
1204                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1205                 return;
1206         }
1207
1208         /* First, zot all the existing filters. */
1209         for (i = 0; i < 4; i++)
1210                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1211
1212         /* Now program new ones. */
1213         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1214                 if (ifma->ifma_addr->sa_family != AF_LINK)
1215                         continue;
1216                 h = ether_crc32_le(
1217                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1218                     ETHER_ADDR_LEN) & 0x7f;
1219                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1220         }
1221
1222         for (i = 0; i < 4; i++)
1223                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1224 }
1225
1226 /*
1227  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1228  * self-test results.
1229  */
1230 static int
1231 bge_chipinit(struct bge_softc *sc)
1232 {
1233         int i;
1234         uint32_t dma_rw_ctl;
1235         uint16_t val;
1236
1237         /* Set endian type before we access any non-PCI registers. */
1238         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1239
1240         /* Clear the MAC control register */
1241         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1242
1243         /*
1244          * Clear the MAC statistics block in the NIC's
1245          * internal memory.
1246          */
1247         for (i = BGE_STATS_BLOCK;
1248             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1249                 BGE_MEMWIN_WRITE(sc, i, 0);
1250
1251         for (i = BGE_STATUS_BLOCK;
1252             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1253                 BGE_MEMWIN_WRITE(sc, i, 0);
1254
1255         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1256                 /*
1257                  * Fix data corruption caused by non-qword write with WB.
1258                  * Fix master abort in PCI mode.
1259                  * Fix PCI latency timer.
1260                  */
1261                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1262                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1263                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1264         }
1265
1266         /* Set up the PCI DMA control register. */
1267         if (sc->bge_flags & BGE_FLAG_PCIE) {
1268                 /* PCI Express */
1269                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1270                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1271                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1272         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1273                 /* PCI-X bus */
1274                 if (BGE_IS_5714_FAMILY(sc)) {
1275                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1276                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1277                         /* XXX magic values, Broadcom-supplied Linux driver */
1278                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1279                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1280                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1281                         } else {
1282                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1283                         }
1284                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1285                         /*
1286                          * In the BCM5703, the DMA read watermark should
1287                          * be set to less than or equal to the maximum
1288                          * memory read byte count of the PCI-X command
1289                          * register.
1290                          */
1291                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1292                             (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1293                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1294                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1295                         /*
1296                          * The 5704 uses a different encoding of read/write
1297                          * watermarks.
1298                          */
1299                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1300                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1301                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1302                 } else {
1303                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1304                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1305                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1306                             (0x0F);
1307                 }
1308
1309                 /*
1310                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1311                  * for hardware bugs.
1312                  */
1313                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1314                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1315                         uint32_t tmp;
1316
1317                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1318                         if (tmp == 0x6 || tmp == 0x7)
1319                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1320                 }
1321         } else {
1322                 /* Conventional PCI bus */
1323                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1324                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1325                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1326                     (0x0F);
1327         }
1328
1329         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1330             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1331             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1332                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1333         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1334
1335         /*
1336          * Set up general mode register.
1337          */
1338         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1339             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1340             BGE_MODECTL_TX_NO_PHDR_CSUM);
1341
1342         /*
1343          * BCM5701 B5 have a bug causing data corruption when using
1344          * 64-bit DMA reads, which can be terminated early and then
1345          * completed later as 32-bit accesses, in combination with
1346          * certain bridges.
1347          */
1348         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1349             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1350                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1351
1352         /*
1353          * Disable memory write invalidate.  Apparently it is not supported
1354          * properly by these devices.
1355          */
1356         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1357
1358         /* Set the timer prescaler (always 66Mhz) */
1359         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1360
1361         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1362                 DELAY(40);      /* XXX */
1363
1364                 /* Put PHY into ready state */
1365                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1366                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1367                 DELAY(40);
1368         }
1369
1370         return(0);
1371 }
1372
1373 static int
1374 bge_blockinit(struct bge_softc *sc)
1375 {
1376         struct bge_rcb *rcb;
1377         bus_size_t vrcb;
1378         bge_hostaddr taddr;
1379         uint32_t val;
1380         int i, limit;
1381
1382         /*
1383          * Initialize the memory window pointer register so that
1384          * we can access the first 32K of internal NIC RAM. This will
1385          * allow us to set up the TX send ring RCBs and the RX return
1386          * ring RCBs, plus other things which live in NIC memory.
1387          */
1388         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1389
1390         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1391
1392         if (!BGE_IS_5705_PLUS(sc)) {
1393                 /* Configure mbuf memory pool */
1394                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1395                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1396                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1397                 else
1398                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1399
1400                 /* Configure DMA resource pool */
1401                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1402                     BGE_DMA_DESCRIPTORS);
1403                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1404         }
1405
1406         /* Configure mbuf pool watermarks */
1407         if (!BGE_IS_5705_PLUS(sc)) {
1408                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1409                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1410                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1411         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1412                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1413                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1414                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1415         } else {
1416                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1417                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1418                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1419         }
1420
1421         /* Configure DMA resource watermarks */
1422         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1423         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1424
1425         /* Enable buffer manager */
1426         if (!BGE_IS_5705_PLUS(sc)) {
1427                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1428                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1429
1430                 /* Poll for buffer manager start indication */
1431                 for (i = 0; i < BGE_TIMEOUT; i++) {
1432                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1433                                 break;
1434                         DELAY(10);
1435                 }
1436
1437                 if (i == BGE_TIMEOUT) {
1438                         if_printf(&sc->arpcom.ac_if,
1439                                   "buffer manager failed to start\n");
1440                         return(ENXIO);
1441                 }
1442         }
1443
1444         /* Enable flow-through queues */
1445         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1446         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1447
1448         /* Wait until queue initialization is complete */
1449         for (i = 0; i < BGE_TIMEOUT; i++) {
1450                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1451                         break;
1452                 DELAY(10);
1453         }
1454
1455         if (i == BGE_TIMEOUT) {
1456                 if_printf(&sc->arpcom.ac_if,
1457                           "flow-through queue init failed\n");
1458                 return(ENXIO);
1459         }
1460
1461         /*
1462          * Summary of rings supported by the controller:
1463          *
1464          * Standard Receive Producer Ring
1465          * - This ring is used to feed receive buffers for "standard"
1466          *   sized frames (typically 1536 bytes) to the controller.
1467          *
1468          * Jumbo Receive Producer Ring
1469          * - This ring is used to feed receive buffers for jumbo sized
1470          *   frames (i.e. anything bigger than the "standard" frames)
1471          *   to the controller.
1472          *
1473          * Mini Receive Producer Ring
1474          * - This ring is used to feed receive buffers for "mini"
1475          *   sized frames to the controller.
1476          * - This feature required external memory for the controller
1477          *   but was never used in a production system.  Should always
1478          *   be disabled.
1479          *
1480          * Receive Return Ring
1481          * - After the controller has placed an incoming frame into a
1482          *   receive buffer that buffer is moved into a receive return
1483          *   ring.  The driver is then responsible to passing the
1484          *   buffer up to the stack.  Many versions of the controller
1485          *   support multiple RR rings.
1486          *
1487          * Send Ring
1488          * - This ring is used for outgoing frames.  Many versions of
1489          *   the controller support multiple send rings.
1490          */
1491
1492         /* Initialize the standard receive producer ring control block. */
1493         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1494         rcb->bge_hostaddr.bge_addr_lo =
1495             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1496         rcb->bge_hostaddr.bge_addr_hi =
1497             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1498         if (BGE_IS_5705_PLUS(sc)) {
1499                 /*
1500                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1501                  * Bits 15-2 : Reserved (should be 0)
1502                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1503                  * Bit 0     : Reserved
1504                  */
1505                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1506         } else {
1507                 /*
1508                  * Ring size is always XXX entries
1509                  * Bits 31-16: Maximum RX frame size
1510                  * Bits 15-2 : Reserved (should be 0)
1511                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1512                  * Bit 0     : Reserved
1513                  */
1514                 rcb->bge_maxlen_flags =
1515                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1516         }
1517         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1518         /* Write the standard receive producer ring control block. */
1519         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1520         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1521         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1522         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1523         /* Reset the standard receive producer ring producer index. */
1524         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1525
1526         /*
1527          * Initialize the jumbo RX producer ring control
1528          * block.  We set the 'ring disabled' bit in the
1529          * flags field until we're actually ready to start
1530          * using this ring (i.e. once we set the MTU
1531          * high enough to require it).
1532          */
1533         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1534                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1535                 /* Get the jumbo receive producer ring RCB parameters. */
1536                 rcb->bge_hostaddr.bge_addr_lo =
1537                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1538                 rcb->bge_hostaddr.bge_addr_hi =
1539                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1540                 rcb->bge_maxlen_flags =
1541                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1542                     BGE_RCB_FLAG_RING_DISABLED);
1543                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1544                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1545                     rcb->bge_hostaddr.bge_addr_hi);
1546                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1547                     rcb->bge_hostaddr.bge_addr_lo);
1548                 /* Program the jumbo receive producer ring RCB parameters. */
1549                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1550                     rcb->bge_maxlen_flags);
1551                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1552                 /* Reset the jumbo receive producer ring producer index. */
1553                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1554         }
1555
1556         /* Disable the mini receive producer ring RCB. */
1557         if (BGE_IS_5700_FAMILY(sc)) {
1558                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1559                 rcb->bge_maxlen_flags =
1560                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1561                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1562                     rcb->bge_maxlen_flags);
1563                 /* Reset the mini receive producer ring producer index. */
1564                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1565         }
1566
1567         /*
1568          * The BD ring replenish thresholds control how often the
1569          * hardware fetches new BD's from the producer rings in host
1570          * memory.  Setting the value too low on a busy system can
1571          * starve the hardware and recue the throughpout.
1572          *
1573          * Set the BD ring replentish thresholds. The recommended
1574          * values are 1/8th the number of descriptors allocated to
1575          * each ring.
1576          */
1577         if (BGE_IS_5705_PLUS(sc))
1578                 val = 8;
1579         else
1580                 val = BGE_STD_RX_RING_CNT / 8;
1581         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1582         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1583                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1584                     BGE_JUMBO_RX_RING_CNT/8);
1585         }
1586
1587         /*
1588          * Disable all send rings by setting the 'ring disabled' bit
1589          * in the flags field of all the TX send ring control blocks,
1590          * located in NIC memory.
1591          */
1592         if (!BGE_IS_5705_PLUS(sc)) {
1593                 /* 5700 to 5704 had 16 send rings. */
1594                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1595         } else {
1596                 limit = 1;
1597         }
1598         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1599         for (i = 0; i < limit; i++) {
1600                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1601                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1602                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1603                 vrcb += sizeof(struct bge_rcb);
1604         }
1605
1606         /* Configure send ring RCB 0 (we use only the first ring) */
1607         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1608         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1609         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1610         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1611         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1612             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1613         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1614             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1615
1616         /*
1617          * Disable all receive return rings by setting the
1618          * 'ring diabled' bit in the flags field of all the receive
1619          * return ring control blocks, located in NIC memory.
1620          */
1621         if (!BGE_IS_5705_PLUS(sc))
1622                 limit = BGE_RX_RINGS_MAX;
1623         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1624                 limit = 4;
1625         else
1626                 limit = 1;
1627         /* Disable all receive return rings. */
1628         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1629         for (i = 0; i < limit; i++) {
1630                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1631                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1632                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1633                     BGE_RCB_FLAG_RING_DISABLED);
1634                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1635                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1636                     (i * (sizeof(uint64_t))), 0);
1637                 vrcb += sizeof(struct bge_rcb);
1638         }
1639
1640         /*
1641          * Set up receive return ring 0.  Note that the NIC address
1642          * for RX return rings is 0x0.  The return rings live entirely
1643          * within the host, so the nicaddr field in the RCB isn't used.
1644          */
1645         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1646         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1647         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1648         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1649         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1650         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1651             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1652
1653         /* Set random backoff seed for TX */
1654         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1655             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1656             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1657             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1658             BGE_TX_BACKOFF_SEED_MASK);
1659
1660         /* Set inter-packet gap */
1661         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1662
1663         /*
1664          * Specify which ring to use for packets that don't match
1665          * any RX rules.
1666          */
1667         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1668
1669         /*
1670          * Configure number of RX lists. One interrupt distribution
1671          * list, sixteen active lists, one bad frames class.
1672          */
1673         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1674
1675         /* Inialize RX list placement stats mask. */
1676         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1677         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1678
1679         /* Disable host coalescing until we get it set up */
1680         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1681
1682         /* Poll to make sure it's shut down. */
1683         for (i = 0; i < BGE_TIMEOUT; i++) {
1684                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1685                         break;
1686                 DELAY(10);
1687         }
1688
1689         if (i == BGE_TIMEOUT) {
1690                 if_printf(&sc->arpcom.ac_if,
1691                           "host coalescing engine failed to idle\n");
1692                 return(ENXIO);
1693         }
1694
1695         /* Set up host coalescing defaults */
1696         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1697         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1698         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1699         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1700         if (!BGE_IS_5705_PLUS(sc)) {
1701                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1702                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1703         }
1704         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1705         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1706
1707         /* Set up address of statistics block */
1708         if (!BGE_IS_5705_PLUS(sc)) {
1709                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1710                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1711                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1712                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1713
1714                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1715                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1716                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1717         }
1718
1719         /* Set up address of status block */
1720         bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1721         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1722             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1723         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1724             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1725
1726         /*
1727          * Set up status block partail update size.
1728          *
1729          * Because only single TX ring, RX produce ring and Rx return ring
1730          * are used, ask device to update only minimum part of status block
1731          * except for BCM5700 AX/BX, whose status block partial update size
1732          * can't be configured.
1733          */
1734         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1735             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1736                 /* XXX Actually reserved on BCM5700 AX/BX */
1737                 val = BGE_STATBLKSZ_FULL;
1738         } else {
1739                 val = BGE_STATBLKSZ_32BYTE;
1740         }
1741
1742         /* Turn on host coalescing state machine */
1743         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1744
1745         /* Turn on RX BD completion state machine and enable attentions */
1746         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1747             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1748
1749         /* Turn on RX list placement state machine */
1750         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1751
1752         /* Turn on RX list selector state machine. */
1753         if (!BGE_IS_5705_PLUS(sc))
1754                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1755
1756         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1757             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1758             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1759             BGE_MACMODE_FRMHDR_DMA_ENB;
1760
1761         if (sc->bge_flags & BGE_FLAG_TBI)
1762                 val |= BGE_PORTMODE_TBI;
1763         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1764                 val |= BGE_PORTMODE_GMII;
1765         else
1766                 val |= BGE_PORTMODE_MII;
1767
1768         /* Turn on DMA, clear stats */
1769         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1770
1771         /* Set misc. local control, enable interrupts on attentions */
1772         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1773
1774 #ifdef notdef
1775         /* Assert GPIO pins for PHY reset */
1776         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1777             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1778         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1779             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1780 #endif
1781
1782         /* Turn on DMA completion state machine */
1783         if (!BGE_IS_5705_PLUS(sc))
1784                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1785
1786         /* Turn on write DMA state machine */
1787         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1788         if (BGE_IS_5755_PLUS(sc)) {
1789                 /* Enable host coalescing bug fix. */
1790                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1791         }
1792         if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1793                 /* Request larger DMA burst size to get better performance. */
1794                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1795         }
1796         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1797         DELAY(40);
1798
1799         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1800             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1801             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1802             sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1803                 /*
1804                  * Enable fix for read DMA FIFO overruns.
1805                  * The fix is to limit the number of RX BDs
1806                  * the hardware would fetch at a fime.
1807                  */
1808                 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1809                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1810                     val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1811         }
1812
1813         /* Turn on read DMA state machine */
1814         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1815         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1816             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1817             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1818                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1819                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1820                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1821         if (sc->bge_flags & BGE_FLAG_PCIE)
1822                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1823         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1824         DELAY(40);
1825
1826         /* Turn on RX data completion state machine */
1827         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1828
1829         /* Turn on RX BD initiator state machine */
1830         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1831
1832         /* Turn on RX data and RX BD initiator state machine */
1833         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1834
1835         /* Turn on Mbuf cluster free state machine */
1836         if (!BGE_IS_5705_PLUS(sc))
1837                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1838
1839         /* Turn on send BD completion state machine */
1840         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1841
1842         /* Turn on send data completion state machine */
1843         val = BGE_SDCMODE_ENABLE;
1844         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1845                 val |= BGE_SDCMODE_CDELAY;
1846         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1847
1848         /* Turn on send data initiator state machine */
1849         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1850
1851         /* Turn on send BD initiator state machine */
1852         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1853
1854         /* Turn on send BD selector state machine */
1855         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1856
1857         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1858         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1859             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1860
1861         /* ack/clear link change events */
1862         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1863             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1864             BGE_MACSTAT_LINK_CHANGED);
1865         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1866
1867         /*
1868          * Enable attention when the link has changed state for
1869          * devices that use auto polling.
1870          */
1871         if (sc->bge_flags & BGE_FLAG_TBI) {
1872                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1873         } else {
1874                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1875                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1876                         DELAY(80);
1877                 }
1878                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1879                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1880                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1881                             BGE_EVTENB_MI_INTERRUPT);
1882                 }
1883         }
1884
1885         /*
1886          * Clear any pending link state attention.
1887          * Otherwise some link state change events may be lost until attention
1888          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1889          * It's not necessary on newer BCM chips - perhaps enabling link
1890          * state change attentions implies clearing pending attention.
1891          */
1892         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1893             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1894             BGE_MACSTAT_LINK_CHANGED);
1895
1896         /* Enable link state change attentions. */
1897         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1898
1899         return(0);
1900 }
1901
1902 /*
1903  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1904  * against our list and return its name if we find a match. Note
1905  * that since the Broadcom controller contains VPD support, we
1906  * can get the device name string from the controller itself instead
1907  * of the compiled-in string. This is a little slow, but it guarantees
1908  * we'll always announce the right product name.
1909  */
1910 static int
1911 bge_probe(device_t dev)
1912 {
1913         const struct bge_type *t;
1914         uint16_t product, vendor;
1915
1916         product = pci_get_device(dev);
1917         vendor = pci_get_vendor(dev);
1918
1919         for (t = bge_devs; t->bge_name != NULL; t++) {
1920                 if (vendor == t->bge_vid && product == t->bge_did)
1921                         break;
1922         }
1923         if (t->bge_name == NULL)
1924                 return(ENXIO);
1925
1926         device_set_desc(dev, t->bge_name);
1927         return(0);
1928 }
1929
1930 static int
1931 bge_attach(device_t dev)
1932 {
1933         struct ifnet *ifp;
1934         struct bge_softc *sc;
1935         uint32_t hwcfg = 0, misccfg;
1936         int error = 0, rid, capmask;
1937         uint8_t ether_addr[ETHER_ADDR_LEN];
1938         uint16_t product, vendor;
1939
1940         sc = device_get_softc(dev);
1941         sc->bge_dev = dev;
1942         callout_init(&sc->bge_stat_timer);
1943         lwkt_serialize_init(&sc->bge_jslot_serializer);
1944
1945 #ifndef BURN_BRIDGES
1946         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1947                 uint32_t irq, mem;
1948
1949                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1950                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1951
1952                 device_printf(dev, "chip is in D%d power mode "
1953                     "-- setting to D0\n", pci_get_powerstate(dev));
1954
1955                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1956
1957                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1958                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1959         }
1960 #endif  /* !BURN_BRIDGE */
1961
1962         /*
1963          * Map control/status registers.
1964          */
1965         pci_enable_busmaster(dev);
1966
1967         rid = BGE_PCI_BAR0;
1968         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1969             RF_ACTIVE);
1970
1971         if (sc->bge_res == NULL) {
1972                 device_printf(dev, "couldn't map memory\n");
1973                 return ENXIO;
1974         }
1975
1976         sc->bge_btag = rman_get_bustag(sc->bge_res);
1977         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1978
1979         /* Save various chip information */
1980         sc->bge_chipid =
1981             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1982             BGE_PCIMISCCTL_ASICREV_SHIFT;
1983         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1984                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
1985         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1986         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1987
1988         /* Save chipset family. */
1989         switch (sc->bge_asicrev) {
1990         case BGE_ASICREV_BCM5755:
1991         case BGE_ASICREV_BCM5761:
1992         case BGE_ASICREV_BCM5784:
1993         case BGE_ASICREV_BCM5785:
1994         case BGE_ASICREV_BCM5787:
1995         case BGE_ASICREV_BCM57780:
1996             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
1997                 BGE_FLAG_5705_PLUS;
1998             break;
1999
2000         case BGE_ASICREV_BCM5700:
2001         case BGE_ASICREV_BCM5701:
2002         case BGE_ASICREV_BCM5703:
2003         case BGE_ASICREV_BCM5704:
2004                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2005                 break;
2006
2007         case BGE_ASICREV_BCM5714_A0:
2008         case BGE_ASICREV_BCM5780:
2009         case BGE_ASICREV_BCM5714:
2010                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2011                 /* Fall through */
2012
2013         case BGE_ASICREV_BCM5750:
2014         case BGE_ASICREV_BCM5752:
2015         case BGE_ASICREV_BCM5906:
2016                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2017                 /* Fall through */
2018
2019         case BGE_ASICREV_BCM5705:
2020                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2021                 break;
2022         }
2023
2024         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2025                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2026
2027         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2028         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2029             (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2030              misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2031                 sc->bge_flags |= BGE_FLAG_5788;
2032
2033         /* BCM5755 or higher and BCM5906 have short DMA bug. */
2034         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2035                 sc->bge_flags |= BGE_FLAG_SHORTDMA;
2036
2037         /*
2038          * Set various quirk flags.
2039          */
2040
2041         product = pci_get_device(dev);
2042         vendor = pci_get_vendor(dev);
2043
2044         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2045              sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2046             pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2047                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2048
2049         capmask = MII_CAPMASK_DEFAULT;
2050         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2051              (misccfg == 0x4000 || misccfg == 0x8000)) ||
2052             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2053              vendor == PCI_VENDOR_BROADCOM &&
2054              (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2055               product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2056               product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2057             (vendor == PCI_VENDOR_BROADCOM &&
2058              (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2059               product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2060               product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2061             product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2062             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2063                 /* 10/100 only */
2064                 capmask &= ~BMSR_EXTSTAT;
2065         }
2066
2067         sc->bge_phy_flags |= BGE_PHY_WIRESPEED;
2068         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2069             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2070              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2071               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2072             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2073                 sc->bge_phy_flags &= ~BGE_PHY_WIRESPEED;
2074
2075         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2076             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2077                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
2078
2079         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2080             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2081                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
2082
2083         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2084                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
2085
2086         if (BGE_IS_5705_PLUS(sc) &&
2087             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2088             /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2089             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2090             /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2091             sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2092                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2093                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2094                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2095                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2096                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2097                             product != PCI_PRODUCT_BROADCOM_BCM5756)
2098                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
2099                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
2100                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
2101                 } else {
2102                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
2103                 }
2104         }
2105
2106         /* Identify the chips that use an CPMU. */
2107         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2108             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2109             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2110             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2111                 sc->bge_flags |= BGE_FLAG_CPMU;
2112         if (sc->bge_flags & BGE_FLAG_CPMU)
2113                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2114         else
2115                 sc->bge_mi_mode = BGE_MIMODE_BASE;
2116
2117         /* Enable auto polling for BCM570[0-5]. */
2118         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
2119                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2120
2121         /* Allocate interrupt */
2122         rid = 0;
2123
2124         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2125             RF_SHAREABLE | RF_ACTIVE);
2126
2127         if (sc->bge_irq == NULL) {
2128                 device_printf(dev, "couldn't map interrupt\n");
2129                 error = ENXIO;
2130                 goto fail;
2131         }
2132
2133         /*
2134          * Check if this is a PCI-X or PCI Express device.
2135          */
2136         if (BGE_IS_5705_PLUS(sc)) {
2137                 if (pci_is_pcie(dev)) {
2138                         sc->bge_flags |= BGE_FLAG_PCIE;
2139                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2140                 }
2141         } else {
2142                 /*
2143                  * Check if the device is in PCI-X Mode.
2144                  * (This bit is not valid on PCI Express controllers.)
2145                  */
2146                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2147                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
2148                         sc->bge_flags |= BGE_FLAG_PCIX;
2149                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2150                 }
2151         }
2152
2153         device_printf(dev, "CHIP ID 0x%08x; "
2154                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2155                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2156                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2157                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2158                         "PCI-E" : "PCI"));
2159
2160         /*
2161          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2162          * not actually a MAC controller bug but an issue with the embedded
2163          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2164          */
2165         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2166                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2167
2168         ifp = &sc->arpcom.ac_if;
2169         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2170
2171         /* Try to reset the chip. */
2172         bge_reset(sc);
2173
2174         if (bge_chipinit(sc)) {
2175                 device_printf(dev, "chip initialization failed\n");
2176                 error = ENXIO;
2177                 goto fail;
2178         }
2179
2180         /*
2181          * Get station address
2182          */
2183         error = bge_get_eaddr(sc, ether_addr);
2184         if (error) {
2185                 device_printf(dev, "failed to read station address\n");
2186                 goto fail;
2187         }
2188
2189         /* 5705/5750 limits RX return ring to 512 entries. */
2190         if (BGE_IS_5705_PLUS(sc))
2191                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2192         else
2193                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2194
2195         error = bge_dma_alloc(sc);
2196         if (error)
2197                 goto fail;
2198
2199         /* Set default tuneable values. */
2200         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2201         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
2202         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
2203         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
2204         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
2205
2206         /* Set up ifnet structure */
2207         ifp->if_softc = sc;
2208         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2209         ifp->if_ioctl = bge_ioctl;
2210         ifp->if_start = bge_start;
2211 #ifdef DEVICE_POLLING
2212         ifp->if_poll = bge_poll;
2213 #endif
2214         ifp->if_watchdog = bge_watchdog;
2215         ifp->if_init = bge_init;
2216         ifp->if_mtu = ETHERMTU;
2217         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2218         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2219         ifq_set_ready(&ifp->if_snd);
2220
2221         /*
2222          * 5700 B0 chips do not support checksumming correctly due
2223          * to hardware bugs.
2224          */
2225         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2226                 ifp->if_capabilities |= IFCAP_HWCSUM;
2227                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2228         }
2229         ifp->if_capenable = ifp->if_capabilities;
2230
2231         /*
2232          * Figure out what sort of media we have by checking the
2233          * hardware config word in the first 32k of NIC internal memory,
2234          * or fall back to examining the EEPROM if necessary.
2235          * Note: on some BCM5700 cards, this value appears to be unset.
2236          * If that's the case, we have to rely on identifying the NIC
2237          * by its PCI subsystem ID, as we do below for the SysKonnect
2238          * SK-9D41.
2239          */
2240         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2241                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2242         else {
2243                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2244                                     sizeof(hwcfg))) {
2245                         device_printf(dev, "failed to read EEPROM\n");
2246                         error = ENXIO;
2247                         goto fail;
2248                 }
2249                 hwcfg = ntohl(hwcfg);
2250         }
2251
2252         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2253         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2254             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2255                 if (BGE_IS_5714_FAMILY(sc))
2256                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2257                 else
2258                         sc->bge_flags |= BGE_FLAG_TBI;
2259         }
2260
2261         /*
2262          * Broadcom's own driver always assumes the internal
2263          * PHY is at GMII address 1.  On some chips, the PHY responds
2264          * to accesses at all addresses, which could cause us to
2265          * bogusly attach the PHY 32 times at probe type.  Always
2266          * restricting the lookup to address 1 is simpler than
2267          * trying to figure out which chips revisions should be
2268          * special-cased.
2269          */
2270         sc->bge_phyno = 1;
2271
2272         if (sc->bge_flags & BGE_FLAG_TBI) {
2273                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2274                     bge_ifmedia_upd, bge_ifmedia_sts);
2275                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2276                 ifmedia_add(&sc->bge_ifmedia,
2277                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2278                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2279                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2280                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2281         } else {
2282                 struct mii_probe_args mii_args;
2283
2284                 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2285                 mii_args.mii_probemask = 1 << sc->bge_phyno;
2286                 mii_args.mii_capmask = capmask;
2287
2288                 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2289                 if (error) {
2290                         device_printf(dev, "MII without any PHY!\n");
2291                         goto fail;
2292                 }
2293         }
2294
2295         /*
2296          * When using the BCM5701 in PCI-X mode, data corruption has
2297          * been observed in the first few bytes of some received packets.
2298          * Aligning the packet buffer in memory eliminates the corruption.
2299          * Unfortunately, this misaligns the packet payloads.  On platforms
2300          * which do not support unaligned accesses, we will realign the
2301          * payloads by copying the received packets.
2302          */
2303         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2304             (sc->bge_flags & BGE_FLAG_PCIX))
2305                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2306
2307         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2308             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2309                 sc->bge_link_upd = bge_bcm5700_link_upd;
2310                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2311         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2312                 sc->bge_link_upd = bge_tbi_link_upd;
2313                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2314         } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2315                 sc->bge_link_upd = bge_autopoll_link_upd;
2316                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2317         } else {
2318                 sc->bge_link_upd = bge_copper_link_upd;
2319                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2320         }
2321
2322         /*
2323          * Create sysctl nodes.
2324          */
2325         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2326         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2327                                               SYSCTL_STATIC_CHILDREN(_hw),
2328                                               OID_AUTO,
2329                                               device_get_nameunit(dev),
2330                                               CTLFLAG_RD, 0, "");
2331         if (sc->bge_sysctl_tree == NULL) {
2332                 device_printf(dev, "can't add sysctl node\n");
2333                 error = ENXIO;
2334                 goto fail;
2335         }
2336
2337         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2338                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2339                         OID_AUTO, "rx_coal_ticks",
2340                         CTLTYPE_INT | CTLFLAG_RW,
2341                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2342                         "Receive coalescing ticks (usec).");
2343         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2344                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2345                         OID_AUTO, "tx_coal_ticks",
2346                         CTLTYPE_INT | CTLFLAG_RW,
2347                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2348                         "Transmit coalescing ticks (usec).");
2349         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2350                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2351                         OID_AUTO, "rx_max_coal_bds",
2352                         CTLTYPE_INT | CTLFLAG_RW,
2353                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2354                         "Receive max coalesced BD count.");
2355         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2356                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2357                         OID_AUTO, "tx_max_coal_bds",
2358                         CTLTYPE_INT | CTLFLAG_RW,
2359                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2360                         "Transmit max coalesced BD count.");
2361
2362         if (sc->bge_flags & BGE_FLAG_PCIE) {
2363                 /*
2364                  * A common design characteristic for many Broadcom
2365                  * client controllers is that they only support a
2366                  * single outstanding DMA read operation on the PCIe
2367                  * bus. This means that it will take twice as long to
2368                  * fetch a TX frame that is split into header and
2369                  * payload buffers as it does to fetch a single,
2370                  * contiguous TX frame (2 reads vs. 1 read). For these
2371                  * controllers, coalescing buffers to reduce the number
2372                  * of memory reads is effective way to get maximum
2373                  * performance(about 940Mbps).  Without collapsing TX
2374                  * buffers the maximum TCP bulk transfer performance
2375                  * is about 850Mbps. However forcing coalescing mbufs
2376                  * consumes a lot of CPU cycles, so leave it off by
2377                  * default.
2378                  */
2379                 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2380                                SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2381                                OID_AUTO, "force_defrag", CTLFLAG_RW,
2382                                &sc->bge_force_defrag, 0,
2383                                "Force defragment on TX path");
2384         }
2385
2386         /*
2387          * Call MI attach routine.
2388          */
2389         ether_ifattach(ifp, ether_addr, NULL);
2390
2391         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2392                                bge_intr, sc, &sc->bge_intrhand,
2393                                ifp->if_serializer);
2394         if (error) {
2395                 ether_ifdetach(ifp);
2396                 device_printf(dev, "couldn't set up irq\n");
2397                 goto fail;
2398         }
2399
2400         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2401         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2402
2403         return(0);
2404 fail:
2405         bge_detach(dev);
2406         return(error);
2407 }
2408
2409 static int
2410 bge_detach(device_t dev)
2411 {
2412         struct bge_softc *sc = device_get_softc(dev);
2413
2414         if (device_is_attached(dev)) {
2415                 struct ifnet *ifp = &sc->arpcom.ac_if;
2416
2417                 lwkt_serialize_enter(ifp->if_serializer);
2418                 bge_stop(sc);
2419                 bge_reset(sc);
2420                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2421                 lwkt_serialize_exit(ifp->if_serializer);
2422
2423                 ether_ifdetach(ifp);
2424         }
2425
2426         if (sc->bge_flags & BGE_FLAG_TBI)
2427                 ifmedia_removeall(&sc->bge_ifmedia);
2428         if (sc->bge_miibus)
2429                 device_delete_child(dev, sc->bge_miibus);
2430         bus_generic_detach(dev);
2431
2432         if (sc->bge_irq != NULL)
2433                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2434
2435         if (sc->bge_res != NULL)
2436                 bus_release_resource(dev, SYS_RES_MEMORY,
2437                     BGE_PCI_BAR0, sc->bge_res);
2438
2439         if (sc->bge_sysctl_tree != NULL)
2440                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2441
2442         bge_dma_free(sc);
2443
2444         return 0;
2445 }
2446
2447 static void
2448 bge_reset(struct bge_softc *sc)
2449 {
2450         device_t dev;
2451         uint32_t cachesize, command, pcistate, reset;
2452         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2453         int i, val = 0;
2454
2455         dev = sc->bge_dev;
2456
2457         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2458             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2459                 if (sc->bge_flags & BGE_FLAG_PCIE)
2460                         write_op = bge_writemem_direct;
2461                 else
2462                         write_op = bge_writemem_ind;
2463         } else {
2464                 write_op = bge_writereg_ind;
2465         }
2466
2467         /* Save some important PCI state. */
2468         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2469         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2470         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2471
2472         pci_write_config(dev, BGE_PCI_MISC_CTL,
2473             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2474             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2475
2476         /* Disable fastboot on controllers that support it. */
2477         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2478             BGE_IS_5755_PLUS(sc)) {
2479                 if (bootverbose)
2480                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2481                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2482         }
2483
2484         /*
2485          * Write the magic number to SRAM at offset 0xB50.
2486          * When firmware finishes its initialization it will
2487          * write ~BGE_MAGIC_NUMBER to the same location.
2488          */
2489         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2490
2491         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2492
2493         /* XXX: Broadcom Linux driver. */
2494         if (sc->bge_flags & BGE_FLAG_PCIE) {
2495                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2496                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2497                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2498                         /* Prevent PCIE link training during global reset */
2499                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2500                         reset |= (1<<29);
2501                 }
2502         }
2503
2504         /*
2505          * Set GPHY Power Down Override to leave GPHY
2506          * powered up in D0 uninitialized.
2507          */
2508         if (BGE_IS_5705_PLUS(sc))
2509                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2510
2511         /* Issue global reset */
2512         write_op(sc, BGE_MISC_CFG, reset);
2513
2514         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2515                 uint32_t status, ctrl;
2516
2517                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2518                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2519                     status | BGE_VCPU_STATUS_DRV_RESET);
2520                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2521                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2522                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2523         }
2524
2525         DELAY(1000);
2526
2527         /* XXX: Broadcom Linux driver. */
2528         if (sc->bge_flags & BGE_FLAG_PCIE) {
2529                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2530                         uint32_t v;
2531
2532                         DELAY(500000); /* wait for link training to complete */
2533                         v = pci_read_config(dev, 0xc4, 4);
2534                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2535                 }
2536                 /*
2537                  * Set PCIE max payload size to 128 bytes and
2538                  * clear error status.
2539                  */
2540                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2541         }
2542
2543         /* Reset some of the PCI state that got zapped by reset */
2544         pci_write_config(dev, BGE_PCI_MISC_CTL,
2545             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2546             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2547         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2548         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2549         write_op(sc, BGE_MISC_CFG, (65 << 1));
2550
2551         /*
2552          * Disable PCI-X relaxed ordering to ensure status block update
2553          * comes first then packet buffer DMA. Otherwise driver may
2554          * read stale status block.
2555          */
2556         if (sc->bge_flags & BGE_FLAG_PCIX) {
2557                 uint16_t devctl;
2558
2559                 devctl = pci_read_config(dev,
2560                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
2561                 devctl &= ~PCIXM_COMMAND_ERO;
2562                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2563                         devctl &= ~PCIXM_COMMAND_MAX_READ;
2564                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2565                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2566                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2567                             PCIXM_COMMAND_MAX_READ);
2568                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2569                 }
2570                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2571                     devctl, 2);
2572         }
2573
2574         /* Enable memory arbiter. */
2575         if (BGE_IS_5714_FAMILY(sc)) {
2576                 uint32_t val;
2577
2578                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2579                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2580         } else {
2581                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2582         }
2583
2584         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2585                 for (i = 0; i < BGE_TIMEOUT; i++) {
2586                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2587                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2588                                 break;
2589                         DELAY(100);
2590                 }
2591                 if (i == BGE_TIMEOUT) {
2592                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2593                         return;
2594                 }
2595         } else {
2596                 /*
2597                  * Poll until we see the 1's complement of the magic number.
2598                  * This indicates that the firmware initialization
2599                  * is complete.
2600                  */
2601                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2602                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2603                         if (val == ~BGE_MAGIC_NUMBER)
2604                                 break;
2605                         DELAY(10);
2606                 }
2607                 if (i == BGE_FIRMWARE_TIMEOUT) {
2608                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2609                                   "timed out, found 0x%08x\n", val);
2610                         return;
2611                 }
2612         }
2613
2614         /*
2615          * XXX Wait for the value of the PCISTATE register to
2616          * return to its original pre-reset state. This is a
2617          * fairly good indicator of reset completion. If we don't
2618          * wait for the reset to fully complete, trying to read
2619          * from the device's non-PCI registers may yield garbage
2620          * results.
2621          */
2622         for (i = 0; i < BGE_TIMEOUT; i++) {
2623                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2624                         break;
2625                 DELAY(10);
2626         }
2627
2628         /* Fix up byte swapping */
2629         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2630             BGE_MODECTL_BYTESWAP_DATA);
2631
2632         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2633
2634         /*
2635          * The 5704 in TBI mode apparently needs some special
2636          * adjustment to insure the SERDES drive level is set
2637          * to 1.2V.
2638          */
2639         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2640             (sc->bge_flags & BGE_FLAG_TBI)) {
2641                 uint32_t serdescfg;
2642
2643                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2644                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2645                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2646         }
2647
2648         /* XXX: Broadcom Linux driver. */
2649         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2650             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2651             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
2652                 uint32_t v;
2653
2654                 /* Enable Data FIFO protection. */
2655                 v = CSR_READ_4(sc, 0x7c00);
2656                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2657         }
2658
2659         DELAY(10000);
2660 }
2661
2662 /*
2663  * Frame reception handling. This is called if there's a frame
2664  * on the receive return list.
2665  *
2666  * Note: we have to be able to handle two possibilities here:
2667  * 1) the frame is from the jumbo recieve ring
2668  * 2) the frame is from the standard receive ring
2669  */
2670
2671 static void
2672 bge_rxeof(struct bge_softc *sc)
2673 {
2674         struct ifnet *ifp;
2675         int stdcnt = 0, jumbocnt = 0;
2676
2677         if (sc->bge_rx_saved_considx ==
2678             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2679                 return;
2680
2681         ifp = &sc->arpcom.ac_if;
2682
2683         while (sc->bge_rx_saved_considx !=
2684                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2685                 struct bge_rx_bd        *cur_rx;
2686                 uint32_t                rxidx;
2687                 struct mbuf             *m = NULL;
2688                 uint16_t                vlan_tag = 0;
2689                 int                     have_tag = 0;
2690
2691                 cur_rx =
2692             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2693
2694                 rxidx = cur_rx->bge_idx;
2695                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2696                 logif(rx_pkt);
2697
2698                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2699                         have_tag = 1;
2700                         vlan_tag = cur_rx->bge_vlan_tag;
2701                 }
2702
2703                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2704                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2705                         jumbocnt++;
2706
2707                         if (rxidx != sc->bge_jumbo) {
2708                                 ifp->if_ierrors++;
2709                                 if_printf(ifp, "sw jumbo index(%d) "
2710                                     "and hw jumbo index(%d) mismatch, drop!\n",
2711                                     sc->bge_jumbo, rxidx);
2712                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2713                                 continue;
2714                         }
2715
2716                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2717                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2718                                 ifp->if_ierrors++;
2719                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2720                                 continue;
2721                         }
2722                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2723                                 ifp->if_ierrors++;
2724                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2725                                 continue;
2726                         }
2727                 } else {
2728                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2729                         stdcnt++;
2730
2731                         if (rxidx != sc->bge_std) {
2732                                 ifp->if_ierrors++;
2733                                 if_printf(ifp, "sw std index(%d) "
2734                                     "and hw std index(%d) mismatch, drop!\n",
2735                                     sc->bge_std, rxidx);
2736                                 bge_setup_rxdesc_std(sc, rxidx);
2737                                 continue;
2738                         }
2739
2740                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2741                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2742                                 ifp->if_ierrors++;
2743                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2744                                 continue;
2745                         }
2746                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2747                                 ifp->if_ierrors++;
2748                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2749                                 continue;
2750                         }
2751                 }
2752
2753                 ifp->if_ipackets++;
2754 #if !defined(__i386__) && !defined(__x86_64__)
2755                 /*
2756                  * The x86 allows unaligned accesses, but for other
2757                  * platforms we must make sure the payload is aligned.
2758                  */
2759                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2760                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2761                             cur_rx->bge_len);
2762                         m->m_data += ETHER_ALIGN;
2763                 }
2764 #endif
2765                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2766                 m->m_pkthdr.rcvif = ifp;
2767
2768                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2769                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2770                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2771                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2772                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2773                         }
2774                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2775                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2776                                 m->m_pkthdr.csum_data =
2777                                         cur_rx->bge_tcp_udp_csum;
2778                                 m->m_pkthdr.csum_flags |=
2779                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2780                         }
2781                 }
2782
2783                 /*
2784                  * If we received a packet with a vlan tag, pass it
2785                  * to vlan_input() instead of ether_input().
2786                  */
2787                 if (have_tag) {
2788                         m->m_flags |= M_VLANTAG;
2789                         m->m_pkthdr.ether_vlantag = vlan_tag;
2790                         have_tag = vlan_tag = 0;
2791                 }
2792                 ifp->if_input(ifp, m);
2793         }
2794
2795         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2796         if (stdcnt)
2797                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2798         if (jumbocnt)
2799                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2800 }
2801
2802 static void
2803 bge_txeof(struct bge_softc *sc)
2804 {
2805         struct bge_tx_bd *cur_tx = NULL;
2806         struct ifnet *ifp;
2807
2808         if (sc->bge_tx_saved_considx ==
2809             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2810                 return;
2811
2812         ifp = &sc->arpcom.ac_if;
2813
2814         /*
2815          * Go through our tx ring and free mbufs for those
2816          * frames that have been sent.
2817          */
2818         while (sc->bge_tx_saved_considx !=
2819                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2820                 uint32_t idx = 0;
2821
2822                 idx = sc->bge_tx_saved_considx;
2823                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2824                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2825                         ifp->if_opackets++;
2826                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2827                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2828                             sc->bge_cdata.bge_tx_dmamap[idx]);
2829                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2830                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2831                 }
2832                 sc->bge_txcnt--;
2833                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2834                 logif(tx_pkt);
2835         }
2836
2837         if (cur_tx != NULL &&
2838             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2839             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2840                 ifp->if_flags &= ~IFF_OACTIVE;
2841
2842         if (sc->bge_txcnt == 0)
2843                 ifp->if_timer = 0;
2844
2845         if (!ifq_is_empty(&ifp->if_snd))
2846                 if_devstart(ifp);
2847 }
2848
2849 #ifdef DEVICE_POLLING
2850
2851 static void
2852 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2853 {
2854         struct bge_softc *sc = ifp->if_softc;
2855         uint32_t status;
2856
2857         switch(cmd) {
2858         case POLL_REGISTER:
2859                 bge_disable_intr(sc);
2860                 break;
2861         case POLL_DEREGISTER:
2862                 bge_enable_intr(sc);
2863                 break;
2864         case POLL_AND_CHECK_STATUS:
2865                 /*
2866                  * Process link state changes.
2867                  */
2868                 status = CSR_READ_4(sc, BGE_MAC_STS);
2869                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2870                         sc->bge_link_evt = 0;
2871                         sc->bge_link_upd(sc, status);
2872                 }
2873                 /* fall through */
2874         case POLL_ONLY:
2875                 if (ifp->if_flags & IFF_RUNNING) {
2876                         bge_rxeof(sc);
2877                         bge_txeof(sc);
2878                 }
2879                 break;
2880         }
2881 }
2882
2883 #endif
2884
2885 static void
2886 bge_intr(void *xsc)
2887 {
2888         struct bge_softc *sc = xsc;
2889         struct ifnet *ifp = &sc->arpcom.ac_if;
2890         uint32_t status;
2891
2892         logif(intr);
2893
2894         /*
2895          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2896          * disable interrupts by writing nonzero like we used to, since with
2897          * our current organization this just gives complications and
2898          * pessimizations for re-enabling interrupts.  We used to have races
2899          * instead of the necessary complications.  Disabling interrupts
2900          * would just reduce the chance of a status update while we are
2901          * running (by switching to the interrupt-mode coalescence
2902          * parameters), but this chance is already very low so it is more
2903          * efficient to get another interrupt than prevent it.
2904          *
2905          * We do the ack first to ensure another interrupt if there is a
2906          * status update after the ack.  We don't check for the status
2907          * changing later because it is more efficient to get another
2908          * interrupt than prevent it, not quite as above (not checking is
2909          * a smaller optimization than not toggling the interrupt enable,
2910          * since checking doesn't involve PCI accesses and toggling require
2911          * the status check).  So toggling would probably be a pessimization
2912          * even with MSI.  It would only be needed for using a task queue.
2913          */
2914         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2915
2916         /*
2917          * Process link state changes.
2918          */
2919         status = CSR_READ_4(sc, BGE_MAC_STS);
2920         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2921                 sc->bge_link_evt = 0;
2922                 sc->bge_link_upd(sc, status);
2923         }
2924
2925         if (ifp->if_flags & IFF_RUNNING) {
2926                 /* Check RX return ring producer/consumer */
2927                 bge_rxeof(sc);
2928
2929                 /* Check TX ring producer/consumer */
2930                 bge_txeof(sc);
2931         }
2932
2933         if (sc->bge_coal_chg)
2934                 bge_coal_change(sc);
2935 }
2936
2937 static void
2938 bge_tick(void *xsc)
2939 {
2940         struct bge_softc *sc = xsc;
2941         struct ifnet *ifp = &sc->arpcom.ac_if;
2942
2943         lwkt_serialize_enter(ifp->if_serializer);
2944
2945         if (BGE_IS_5705_PLUS(sc))
2946                 bge_stats_update_regs(sc);
2947         else
2948                 bge_stats_update(sc);
2949
2950         if (sc->bge_flags & BGE_FLAG_TBI) {
2951                 /*
2952                  * Since in TBI mode auto-polling can't be used we should poll
2953                  * link status manually. Here we register pending link event
2954                  * and trigger interrupt.
2955                  */
2956                 sc->bge_link_evt++;
2957                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2958                     BGE_IS_5788(sc))
2959                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2960                 else
2961                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2962         } else if (!sc->bge_link) {
2963                 mii_tick(device_get_softc(sc->bge_miibus));
2964         }
2965
2966         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2967
2968         lwkt_serialize_exit(ifp->if_serializer);
2969 }
2970
2971 static void
2972 bge_stats_update_regs(struct bge_softc *sc)
2973 {
2974         struct ifnet *ifp = &sc->arpcom.ac_if;
2975         struct bge_mac_stats_regs stats;
2976         uint32_t *s;
2977         int i;
2978
2979         s = (uint32_t *)&stats;
2980         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2981                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2982                 s++;
2983         }
2984
2985         ifp->if_collisions +=
2986            (stats.dot3StatsSingleCollisionFrames +
2987            stats.dot3StatsMultipleCollisionFrames +
2988            stats.dot3StatsExcessiveCollisions +
2989            stats.dot3StatsLateCollisions) -
2990            ifp->if_collisions;
2991 }
2992
2993 static void
2994 bge_stats_update(struct bge_softc *sc)
2995 {
2996         struct ifnet *ifp = &sc->arpcom.ac_if;
2997         bus_size_t stats;
2998
2999         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3000
3001 #define READ_STAT(sc, stats, stat)      \
3002         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3003
3004         ifp->if_collisions +=
3005            (READ_STAT(sc, stats,
3006                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3007             READ_STAT(sc, stats,
3008                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3009             READ_STAT(sc, stats,
3010                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3011             READ_STAT(sc, stats,
3012                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
3013            ifp->if_collisions;
3014
3015 #undef READ_STAT
3016
3017 #ifdef notdef
3018         ifp->if_collisions +=
3019            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3020            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3021            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3022            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
3023            ifp->if_collisions;
3024 #endif
3025 }
3026
3027 /*
3028  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3029  * pointers to descriptors.
3030  */
3031 static int
3032 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
3033 {
3034         struct bge_tx_bd *d = NULL;
3035         uint16_t csum_flags = 0;
3036         bus_dma_segment_t segs[BGE_NSEG_NEW];
3037         bus_dmamap_t map;
3038         int error, maxsegs, nsegs, idx, i;
3039         struct mbuf *m_head = *m_head0, *m_new;
3040
3041         if (m_head->m_pkthdr.csum_flags) {
3042                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3043                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3044                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3045                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3046                 if (m_head->m_flags & M_LASTFRAG)
3047                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3048                 else if (m_head->m_flags & M_FRAG)
3049                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3050         }
3051
3052         idx = *txidx;
3053         map = sc->bge_cdata.bge_tx_dmamap[idx];
3054
3055         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
3056         KASSERT(maxsegs >= BGE_NSEG_SPARE,
3057                 ("not enough segments %d", maxsegs));
3058
3059         if (maxsegs > BGE_NSEG_NEW)
3060                 maxsegs = BGE_NSEG_NEW;
3061
3062         /*
3063          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
3064          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
3065          * but when such padded frames employ the bge IP/TCP checksum
3066          * offload, the hardware checksum assist gives incorrect results
3067          * (possibly from incorporating its own padding into the UDP/TCP
3068          * checksum; who knows).  If we pad such runts with zeros, the
3069          * onboard checksum comes out correct.
3070          */
3071         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3072             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
3073                 error = m_devpad(m_head, BGE_MIN_FRAME);
3074                 if (error)
3075                         goto back;
3076         }
3077
3078         if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
3079                 m_new = bge_defrag_shortdma(m_head);
3080                 if (m_new == NULL) {
3081                         error = ENOBUFS;
3082                         goto back;
3083                 }
3084                 *m_head0 = m_head = m_new;
3085         }
3086         if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3087             m_head->m_next != NULL) {
3088                 /*
3089                  * Forcefully defragment mbuf chain to overcome hardware
3090                  * limitation which only support a single outstanding
3091                  * DMA read operation.  If it fails, keep moving on using
3092                  * the original mbuf chain.
3093                  */
3094                 m_new = m_defrag(m_head, MB_DONTWAIT);
3095                 if (m_new != NULL)
3096                         *m_head0 = m_head = m_new;
3097         }
3098
3099         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3100                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3101         if (error)
3102                 goto back;
3103
3104         m_head = *m_head0;
3105         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3106
3107         for (i = 0; ; i++) {
3108                 d = &sc->bge_ldata.bge_tx_ring[idx];
3109
3110                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3111                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3112                 d->bge_len = segs[i].ds_len;
3113                 d->bge_flags = csum_flags;
3114
3115                 if (i == nsegs - 1)
3116                         break;
3117                 BGE_INC(idx, BGE_TX_RING_CNT);
3118         }
3119         /* Mark the last segment as end of packet... */
3120         d->bge_flags |= BGE_TXBDFLAG_END;
3121
3122         /* Set vlan tag to the first segment of the packet. */
3123         d = &sc->bge_ldata.bge_tx_ring[*txidx];
3124         if (m_head->m_flags & M_VLANTAG) {
3125                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3126                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
3127         } else {
3128                 d->bge_vlan_tag = 0;
3129         }
3130
3131         /*
3132          * Insure that the map for this transmission is placed at
3133          * the array index of the last descriptor in this chain.
3134          */
3135         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3136         sc->bge_cdata.bge_tx_dmamap[idx] = map;
3137         sc->bge_cdata.bge_tx_chain[idx] = m_head;
3138         sc->bge_txcnt += nsegs;
3139
3140         BGE_INC(idx, BGE_TX_RING_CNT);
3141         *txidx = idx;
3142 back:
3143         if (error) {
3144                 m_freem(*m_head0);
3145                 *m_head0 = NULL;
3146         }
3147         return error;
3148 }
3149
3150 /*
3151  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3152  * to the mbuf data regions directly in the transmit descriptors.
3153  */
3154 static void
3155 bge_start(struct ifnet *ifp)
3156 {
3157         struct bge_softc *sc = ifp->if_softc;
3158         struct mbuf *m_head = NULL;
3159         uint32_t prodidx;
3160         int need_trans;
3161
3162         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3163                 return;
3164
3165         prodidx = sc->bge_tx_prodidx;
3166
3167         need_trans = 0;
3168         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3169                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3170                 if (m_head == NULL)
3171                         break;
3172
3173                 /*
3174                  * XXX
3175                  * The code inside the if() block is never reached since we
3176                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3177                  * requests to checksum TCP/UDP in a fragmented packet.
3178                  *
3179                  * XXX
3180                  * safety overkill.  If this is a fragmented packet chain
3181                  * with delayed TCP/UDP checksums, then only encapsulate
3182                  * it if we have enough descriptors to handle the entire
3183                  * chain at once.
3184                  * (paranoia -- may not actually be needed)
3185                  */
3186                 if ((m_head->m_flags & M_FIRSTFRAG) &&
3187                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3188                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3189                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
3190                                 ifp->if_flags |= IFF_OACTIVE;
3191                                 ifq_prepend(&ifp->if_snd, m_head);
3192                                 break;
3193                         }
3194                 }
3195
3196                 /*
3197                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3198                  * descriptors of the end of the ring.  Also make
3199                  * sure there are BGE_NSEG_SPARE descriptors for
3200                  * jumbo buffers' defragmentation.
3201                  */
3202                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3203                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
3204                         ifp->if_flags |= IFF_OACTIVE;
3205                         ifq_prepend(&ifp->if_snd, m_head);
3206                         break;
3207                 }
3208
3209                 /*
3210                  * Pack the data into the transmit ring. If we
3211                  * don't have room, set the OACTIVE flag and wait
3212                  * for the NIC to drain the ring.
3213                  */
3214                 if (bge_encap(sc, &m_head, &prodidx)) {
3215                         ifp->if_flags |= IFF_OACTIVE;
3216                         ifp->if_oerrors++;
3217                         break;
3218                 }
3219                 need_trans = 1;
3220
3221                 ETHER_BPF_MTAP(ifp, m_head);
3222         }
3223
3224         if (!need_trans)
3225                 return;
3226
3227         /* Transmit */
3228         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3229         /* 5700 b2 errata */
3230         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3231                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3232
3233         sc->bge_tx_prodidx = prodidx;
3234
3235         /*
3236          * Set a timeout in case the chip goes out to lunch.
3237          */
3238         ifp->if_timer = 5;
3239 }
3240
3241 static void
3242 bge_init(void *xsc)
3243 {
3244         struct bge_softc *sc = xsc;
3245         struct ifnet *ifp = &sc->arpcom.ac_if;
3246         uint16_t *m;
3247         uint32_t mode;
3248
3249         ASSERT_SERIALIZED(ifp->if_serializer);
3250
3251         /* Cancel pending I/O and flush buffers. */
3252         bge_stop(sc);
3253         bge_reset(sc);
3254         bge_chipinit(sc);
3255
3256         /*
3257          * Init the various state machines, ring
3258          * control blocks and firmware.
3259          */
3260         if (bge_blockinit(sc)) {
3261                 if_printf(ifp, "initialization failure\n");
3262                 bge_stop(sc);
3263                 return;
3264         }
3265
3266         /* Specify MTU. */
3267         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3268             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3269
3270         /* Load our MAC address. */
3271         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3272         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3273         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3274
3275         /* Enable or disable promiscuous mode as needed. */
3276         bge_setpromisc(sc);
3277
3278         /* Program multicast filter. */
3279         bge_setmulti(sc);
3280
3281         /* Init RX ring. */
3282         if (bge_init_rx_ring_std(sc)) {
3283                 if_printf(ifp, "RX ring initialization failed\n");
3284                 bge_stop(sc);
3285                 return;
3286         }
3287
3288         /*
3289          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3290          * memory to insure that the chip has in fact read the first
3291          * entry of the ring.
3292          */
3293         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3294                 uint32_t                v, i;
3295                 for (i = 0; i < 10; i++) {
3296                         DELAY(20);
3297                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3298                         if (v == (MCLBYTES - ETHER_ALIGN))
3299                                 break;
3300                 }
3301                 if (i == 10)
3302                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3303         }
3304
3305         /* Init jumbo RX ring. */
3306         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3307                 if (bge_init_rx_ring_jumbo(sc)) {
3308                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3309                         bge_stop(sc);
3310                         return;
3311                 }
3312         }
3313
3314         /* Init our RX return ring index */
3315         sc->bge_rx_saved_considx = 0;
3316
3317         /* Init TX ring. */
3318         bge_init_tx_ring(sc);
3319
3320         /* Enable TX MAC state machine lockup fix. */
3321         mode = CSR_READ_4(sc, BGE_TX_MODE);
3322         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3323                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3324         /* Turn on transmitter */
3325         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3326
3327         /* Turn on receiver */
3328         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3329
3330         /*
3331          * Set the number of good frames to receive after RX MBUF
3332          * Low Watermark has been reached.  After the RX MAC receives
3333          * this number of frames, it will drop subsequent incoming
3334          * frames until the MBUF High Watermark is reached.
3335          */
3336         CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3337
3338         /* Tell firmware we're alive. */
3339         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3340
3341         /* Enable host interrupts if polling(4) is not enabled. */
3342         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3343 #ifdef DEVICE_POLLING
3344         if (ifp->if_flags & IFF_POLLING)
3345                 bge_disable_intr(sc);
3346         else
3347 #endif
3348         bge_enable_intr(sc);
3349
3350         bge_ifmedia_upd(ifp);
3351
3352         ifp->if_flags |= IFF_RUNNING;
3353         ifp->if_flags &= ~IFF_OACTIVE;
3354
3355         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3356 }
3357
3358 /*
3359  * Set media options.
3360  */
3361 static int
3362 bge_ifmedia_upd(struct ifnet *ifp)
3363 {
3364         struct bge_softc *sc = ifp->if_softc;
3365
3366         /* If this is a 1000baseX NIC, enable the TBI port. */
3367         if (sc->bge_flags & BGE_FLAG_TBI) {
3368                 struct ifmedia *ifm = &sc->bge_ifmedia;
3369
3370                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3371                         return(EINVAL);
3372
3373                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3374                 case IFM_AUTO:
3375                         /*
3376                          * The BCM5704 ASIC appears to have a special
3377                          * mechanism for programming the autoneg
3378                          * advertisement registers in TBI mode.
3379                          */
3380                         if (!bge_fake_autoneg &&
3381                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3382                                 uint32_t sgdig;
3383
3384                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3385                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3386                                 sgdig |= BGE_SGDIGCFG_AUTO |
3387                                          BGE_SGDIGCFG_PAUSE_CAP |
3388                                          BGE_SGDIGCFG_ASYM_PAUSE;
3389                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3390                                             sgdig | BGE_SGDIGCFG_SEND);
3391                                 DELAY(5);
3392                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3393                         }
3394                         break;
3395                 case IFM_1000_SX:
3396                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3397                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3398                                     BGE_MACMODE_HALF_DUPLEX);
3399                         } else {
3400                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3401                                     BGE_MACMODE_HALF_DUPLEX);
3402                         }
3403                         break;
3404                 default:
3405                         return(EINVAL);
3406                 }
3407         } else {
3408                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3409
3410                 sc->bge_link_evt++;
3411                 sc->bge_link = 0;
3412                 if (mii->mii_instance) {
3413                         struct mii_softc *miisc;
3414
3415                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3416                                 mii_phy_reset(miisc);
3417                 }
3418                 mii_mediachg(mii);
3419
3420                 /*
3421                  * Force an interrupt so that we will call bge_link_upd
3422                  * if needed and clear any pending link state attention.
3423                  * Without this we are not getting any further interrupts
3424                  * for link state changes and thus will not UP the link and
3425                  * not be able to send in bge_start.  The only way to get
3426                  * things working was to receive a packet and get an RX
3427                  * intr.
3428                  *
3429                  * bge_tick should help for fiber cards and we might not
3430                  * need to do this here if BGE_FLAG_TBI is set but as
3431                  * we poll for fiber anyway it should not harm.
3432                  */
3433                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3434                     BGE_IS_5788(sc))
3435                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3436                 else
3437                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3438         }
3439         return(0);
3440 }
3441
3442 /*
3443  * Report current media status.
3444  */
3445 static void
3446 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3447 {
3448         struct bge_softc *sc = ifp->if_softc;
3449
3450         if (sc->bge_flags & BGE_FLAG_TBI) {
3451                 ifmr->ifm_status = IFM_AVALID;
3452                 ifmr->ifm_active = IFM_ETHER;
3453                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3454                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3455                         ifmr->ifm_status |= IFM_ACTIVE;
3456                 } else {
3457                         ifmr->ifm_active |= IFM_NONE;
3458                         return;
3459                 }
3460
3461                 ifmr->ifm_active |= IFM_1000_SX;
3462                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3463                         ifmr->ifm_active |= IFM_HDX;
3464                 else
3465                         ifmr->ifm_active |= IFM_FDX;
3466         } else {
3467                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3468
3469                 mii_pollstat(mii);
3470                 ifmr->ifm_active = mii->mii_media_active;
3471                 ifmr->ifm_status = mii->mii_media_status;
3472         }
3473 }
3474
3475 static int
3476 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3477 {
3478         struct bge_softc *sc = ifp->if_softc;
3479         struct ifreq *ifr = (struct ifreq *)data;
3480         int mask, error = 0;
3481
3482         ASSERT_SERIALIZED(ifp->if_serializer);
3483
3484         switch (command) {
3485         case SIOCSIFMTU:
3486                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3487                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3488                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3489                         error = EINVAL;
3490                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3491                         ifp->if_mtu = ifr->ifr_mtu;
3492                         if (ifp->if_flags & IFF_RUNNING)
3493                                 bge_init(sc);
3494                 }
3495                 break;
3496         case SIOCSIFFLAGS:
3497                 if (ifp->if_flags & IFF_UP) {
3498                         if (ifp->if_flags & IFF_RUNNING) {
3499                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3500
3501                                 /*
3502                                  * If only the state of the PROMISC flag
3503                                  * changed, then just use the 'set promisc
3504                                  * mode' command instead of reinitializing
3505                                  * the entire NIC. Doing a full re-init
3506                                  * means reloading the firmware and waiting
3507                                  * for it to start up, which may take a
3508                                  * second or two.  Similarly for ALLMULTI.
3509                                  */
3510                                 if (mask & IFF_PROMISC)
3511                                         bge_setpromisc(sc);
3512                                 if (mask & IFF_ALLMULTI)
3513                                         bge_setmulti(sc);
3514                         } else {
3515                                 bge_init(sc);
3516                         }
3517                 } else if (ifp->if_flags & IFF_RUNNING) {
3518                         bge_stop(sc);
3519                 }
3520                 sc->bge_if_flags = ifp->if_flags;
3521                 break;
3522         case SIOCADDMULTI:
3523         case SIOCDELMULTI:
3524                 if (ifp->if_flags & IFF_RUNNING)
3525                         bge_setmulti(sc);
3526                 break;
3527         case SIOCSIFMEDIA:
3528         case SIOCGIFMEDIA:
3529                 if (sc->bge_flags & BGE_FLAG_TBI) {
3530                         error = ifmedia_ioctl(ifp, ifr,
3531                             &sc->bge_ifmedia, command);
3532                 } else {
3533                         struct mii_data *mii;
3534
3535                         mii = device_get_softc(sc->bge_miibus);
3536                         error = ifmedia_ioctl(ifp, ifr,
3537                                               &mii->mii_media, command);
3538                 }
3539                 break;
3540         case SIOCSIFCAP:
3541                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3542                 if (mask & IFCAP_HWCSUM) {
3543                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3544                         if (IFCAP_HWCSUM & ifp->if_capenable)
3545                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3546                         else
3547                                 ifp->if_hwassist = 0;
3548                 }
3549                 break;
3550         default:
3551                 error = ether_ioctl(ifp, command, data);
3552                 break;
3553         }
3554         return error;
3555 }
3556
3557 static void
3558 bge_watchdog(struct ifnet *ifp)
3559 {
3560         struct bge_softc *sc = ifp->if_softc;
3561
3562         if_printf(ifp, "watchdog timeout -- resetting\n");
3563
3564         bge_init(sc);
3565
3566         ifp->if_oerrors++;
3567
3568         if (!ifq_is_empty(&ifp->if_snd))
3569                 if_devstart(ifp);
3570 }
3571
3572 /*
3573  * Stop the adapter and free any mbufs allocated to the
3574  * RX and TX lists.
3575  */
3576 static void
3577 bge_stop(struct bge_softc *sc)
3578 {
3579         struct ifnet *ifp = &sc->arpcom.ac_if;
3580
3581         ASSERT_SERIALIZED(ifp->if_serializer);
3582
3583         callout_stop(&sc->bge_stat_timer);
3584
3585         /*
3586          * Disable all of the receiver blocks
3587          */
3588         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3589         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3590         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3591         if (!BGE_IS_5705_PLUS(sc))
3592                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3593         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3594         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3595         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3596
3597         /*
3598          * Disable all of the transmit blocks
3599          */
3600         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3601         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3602         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3603         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3604         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3605         if (!BGE_IS_5705_PLUS(sc))
3606                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3607         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3608
3609         /*
3610          * Shut down all of the memory managers and related
3611          * state machines.
3612          */
3613         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3614         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3615         if (!BGE_IS_5705_PLUS(sc))
3616                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3617         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3618         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3619         if (!BGE_IS_5705_PLUS(sc)) {
3620                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3621                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3622         }
3623
3624         /* Disable host interrupts. */
3625         bge_disable_intr(sc);
3626
3627         /*
3628          * Tell firmware we're shutting down.
3629          */
3630         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3631
3632         /* Free the RX lists. */
3633         bge_free_rx_ring_std(sc);
3634
3635         /* Free jumbo RX list. */
3636         if (BGE_IS_JUMBO_CAPABLE(sc))
3637                 bge_free_rx_ring_jumbo(sc);
3638
3639         /* Free TX buffers. */
3640         bge_free_tx_ring(sc);
3641
3642         sc->bge_link = 0;
3643         sc->bge_coal_chg = 0;
3644
3645         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3646
3647         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3648         ifp->if_timer = 0;
3649 }
3650
3651 /*
3652  * Stop all chip I/O so that the kernel's probe routines don't
3653  * get confused by errant DMAs when rebooting.
3654  */
3655 static void
3656 bge_shutdown(device_t dev)
3657 {
3658         struct bge_softc *sc = device_get_softc(dev);
3659         struct ifnet *ifp = &sc->arpcom.ac_if;
3660
3661         lwkt_serialize_enter(ifp->if_serializer);
3662         bge_stop(sc);
3663         bge_reset(sc);
3664         lwkt_serialize_exit(ifp->if_serializer);
3665 }
3666
3667 static int
3668 bge_suspend(device_t dev)
3669 {
3670         struct bge_softc *sc = device_get_softc(dev);
3671         struct ifnet *ifp = &sc->arpcom.ac_if;
3672
3673         lwkt_serialize_enter(ifp->if_serializer);
3674         bge_stop(sc);
3675         lwkt_serialize_exit(ifp->if_serializer);
3676
3677         return 0;
3678 }
3679
3680 static int
3681 bge_resume(device_t dev)
3682 {
3683         struct bge_softc *sc = device_get_softc(dev);
3684         struct ifnet *ifp = &sc->arpcom.ac_if;
3685
3686         lwkt_serialize_enter(ifp->if_serializer);
3687
3688         if (ifp->if_flags & IFF_UP) {
3689                 bge_init(sc);
3690
3691                 if (!ifq_is_empty(&ifp->if_snd))
3692                         if_devstart(ifp);
3693         }
3694
3695         lwkt_serialize_exit(ifp->if_serializer);
3696
3697         return 0;
3698 }
3699
3700 static void
3701 bge_setpromisc(struct bge_softc *sc)
3702 {
3703         struct ifnet *ifp = &sc->arpcom.ac_if;
3704
3705         if (ifp->if_flags & IFF_PROMISC)
3706                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3707         else
3708                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3709 }
3710
3711 static void
3712 bge_dma_free(struct bge_softc *sc)
3713 {
3714         int i;
3715
3716         /* Destroy RX mbuf DMA stuffs. */
3717         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3718                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3719                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3720                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3721                 }
3722                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3723                                    sc->bge_cdata.bge_rx_tmpmap);
3724                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3725         }
3726
3727         /* Destroy TX mbuf DMA stuffs. */
3728         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3729                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3730                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3731                             sc->bge_cdata.bge_tx_dmamap[i]);
3732                 }
3733                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3734         }
3735
3736         /* Destroy standard RX ring */
3737         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3738                            sc->bge_cdata.bge_rx_std_ring_map,
3739                            sc->bge_ldata.bge_rx_std_ring);
3740
3741         if (BGE_IS_JUMBO_CAPABLE(sc))
3742                 bge_free_jumbo_mem(sc);
3743
3744         /* Destroy RX return ring */
3745         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3746                            sc->bge_cdata.bge_rx_return_ring_map,
3747                            sc->bge_ldata.bge_rx_return_ring);
3748
3749         /* Destroy TX ring */
3750         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3751                            sc->bge_cdata.bge_tx_ring_map,
3752                            sc->bge_ldata.bge_tx_ring);
3753
3754         /* Destroy status block */
3755         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3756                            sc->bge_cdata.bge_status_map,
3757                            sc->bge_ldata.bge_status_block);
3758
3759         /* Destroy statistics block */
3760         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3761                            sc->bge_cdata.bge_stats_map,
3762                            sc->bge_ldata.bge_stats);
3763
3764         /* Destroy the parent tag */
3765         if (sc->bge_cdata.bge_parent_tag != NULL)
3766                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3767 }
3768
3769 static int
3770 bge_dma_alloc(struct bge_softc *sc)
3771 {
3772         struct ifnet *ifp = &sc->arpcom.ac_if;
3773         int i, error;
3774         bus_addr_t lowaddr;
3775
3776         lowaddr = BUS_SPACE_MAXADDR;
3777         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3778                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3779
3780         /*
3781          * Allocate the parent bus DMA tag appropriate for PCI.
3782          *
3783          * All of the NetExtreme/NetLink controllers have 4GB boundary
3784          * DMA bug.
3785          * Whenever an address crosses a multiple of the 4GB boundary
3786          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3787          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3788          * state machine will lockup and cause the device to hang.
3789          */
3790         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3791                                    lowaddr, BUS_SPACE_MAXADDR,
3792                                    NULL, NULL,
3793                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3794                                    BUS_SPACE_MAXSIZE_32BIT,
3795                                    0, &sc->bge_cdata.bge_parent_tag);
3796         if (error) {
3797                 if_printf(ifp, "could not allocate parent dma tag\n");
3798                 return error;
3799         }
3800
3801         /*
3802          * Create DMA tag and maps for RX mbufs.
3803          */
3804         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3805                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3806                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3807                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3808                                    &sc->bge_cdata.bge_rx_mtag);
3809         if (error) {
3810                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3811                 return error;
3812         }
3813
3814         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3815                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
3816         if (error) {
3817                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3818                 sc->bge_cdata.bge_rx_mtag = NULL;
3819                 return error;
3820         }
3821
3822         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3823                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3824                                           BUS_DMA_WAITOK,
3825                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3826                 if (error) {
3827                         int j;
3828
3829                         for (j = 0; j < i; ++j) {
3830                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3831                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3832                         }
3833                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3834                         sc->bge_cdata.bge_rx_mtag = NULL;
3835
3836                         if_printf(ifp, "could not create DMA map for RX\n");
3837                         return error;
3838                 }
3839         }
3840
3841         /*
3842          * Create DMA tag and maps for TX mbufs.
3843          */
3844         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3845                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3846                                    NULL, NULL,
3847                                    BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
3848                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3849                                    BUS_DMA_ONEBPAGE,
3850                                    &sc->bge_cdata.bge_tx_mtag);
3851         if (error) {
3852                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3853                 return error;
3854         }
3855
3856         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3857                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
3858                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3859                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3860                 if (error) {
3861                         int j;
3862
3863                         for (j = 0; j < i; ++j) {
3864                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3865                                         sc->bge_cdata.bge_tx_dmamap[j]);
3866                         }
3867                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3868                         sc->bge_cdata.bge_tx_mtag = NULL;
3869
3870                         if_printf(ifp, "could not create DMA map for TX\n");
3871                         return error;
3872                 }
3873         }
3874
3875         /*
3876          * Create DMA stuffs for standard RX ring.
3877          */
3878         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3879                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3880                                     &sc->bge_cdata.bge_rx_std_ring_map,
3881                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
3882                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3883         if (error) {
3884                 if_printf(ifp, "could not create std RX ring\n");
3885                 return error;
3886         }
3887
3888         /*
3889          * Create jumbo buffer pool.
3890          */
3891         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3892                 error = bge_alloc_jumbo_mem(sc);
3893                 if (error) {
3894                         if_printf(ifp, "could not create jumbo buffer pool\n");
3895                         return error;
3896                 }
3897         }
3898
3899         /*
3900          * Create DMA stuffs for RX return ring.
3901          */
3902         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3903                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3904                                     &sc->bge_cdata.bge_rx_return_ring_map,
3905                                     (void *)&sc->bge_ldata.bge_rx_return_ring,
3906                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3907         if (error) {
3908                 if_printf(ifp, "could not create RX ret ring\n");
3909                 return error;
3910         }
3911
3912         /*
3913          * Create DMA stuffs for TX ring.
3914          */
3915         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3916                                     &sc->bge_cdata.bge_tx_ring_tag,
3917                                     &sc->bge_cdata.bge_tx_ring_map,
3918                                     (void *)&sc->bge_ldata.bge_tx_ring,
3919                                     &sc->bge_ldata.bge_tx_ring_paddr);
3920         if (error) {
3921                 if_printf(ifp, "could not create TX ring\n");
3922                 return error;
3923         }
3924
3925         /*
3926          * Create DMA stuffs for status block.
3927          */
3928         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3929                                     &sc->bge_cdata.bge_status_tag,
3930                                     &sc->bge_cdata.bge_status_map,
3931                                     (void *)&sc->bge_ldata.bge_status_block,
3932                                     &sc->bge_ldata.bge_status_block_paddr);
3933         if (error) {
3934                 if_printf(ifp, "could not create status block\n");
3935                 return error;
3936         }
3937
3938         /*
3939          * Create DMA stuffs for statistics block.
3940          */
3941         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3942                                     &sc->bge_cdata.bge_stats_tag,
3943                                     &sc->bge_cdata.bge_stats_map,
3944                                     (void *)&sc->bge_ldata.bge_stats,
3945                                     &sc->bge_ldata.bge_stats_paddr);
3946         if (error) {
3947                 if_printf(ifp, "could not create stats block\n");
3948                 return error;
3949         }
3950         return 0;
3951 }
3952
3953 static int
3954 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3955                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3956 {
3957         bus_dmamem_t dmem;
3958         int error;
3959
3960         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3961                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3962                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3963         if (error)
3964                 return error;
3965
3966         *tag = dmem.dmem_tag;
3967         *map = dmem.dmem_map;
3968         *addr = dmem.dmem_addr;
3969         *paddr = dmem.dmem_busaddr;
3970
3971         return 0;
3972 }
3973
3974 static void
3975 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3976 {
3977         if (tag != NULL) {
3978                 bus_dmamap_unload(tag, map);
3979                 bus_dmamem_free(tag, addr, map);
3980                 bus_dma_tag_destroy(tag);
3981         }
3982 }
3983
3984 /*
3985  * Grrr. The link status word in the status block does
3986  * not work correctly on the BCM5700 rev AX and BX chips,
3987  * according to all available information. Hence, we have
3988  * to enable MII interrupts in order to properly obtain
3989  * async link changes. Unfortunately, this also means that
3990  * we have to read the MAC status register to detect link
3991  * changes, thereby adding an additional register access to
3992  * the interrupt handler.
3993  *
3994  * XXX: perhaps link state detection procedure used for
3995  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3996  */
3997 static void
3998 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3999 {
4000         struct ifnet *ifp = &sc->arpcom.ac_if;
4001         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4002
4003         mii_pollstat(mii);
4004
4005         if (!sc->bge_link &&
4006             (mii->mii_media_status & IFM_ACTIVE) &&
4007             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4008                 sc->bge_link++;
4009                 if (bootverbose)
4010                         if_printf(ifp, "link UP\n");
4011         } else if (sc->bge_link &&
4012             (!(mii->mii_media_status & IFM_ACTIVE) ||
4013             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4014                 sc->bge_link = 0;
4015                 if (bootverbose)
4016                         if_printf(ifp, "link DOWN\n");
4017         }
4018
4019         /* Clear the interrupt. */
4020         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
4021         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4022         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
4023 }
4024
4025 static void
4026 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
4027 {
4028         struct ifnet *ifp = &sc->arpcom.ac_if;
4029
4030 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
4031
4032         /*
4033          * Sometimes PCS encoding errors are detected in
4034          * TBI mode (on fiber NICs), and for some reason
4035          * the chip will signal them as link changes.
4036          * If we get a link change event, but the 'PCS
4037          * encoding error' bit in the MAC status register
4038          * is set, don't bother doing a link check.
4039          * This avoids spurious "gigabit link up" messages
4040          * that sometimes appear on fiber NICs during
4041          * periods of heavy traffic.
4042          */
4043         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4044                 if (!sc->bge_link) {
4045                         sc->bge_link++;
4046                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4047                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4048                                     BGE_MACMODE_TBI_SEND_CFGS);
4049                         }
4050                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4051
4052                         if (bootverbose)
4053                                 if_printf(ifp, "link UP\n");
4054
4055                         ifp->if_link_state = LINK_STATE_UP;
4056                         if_link_state_change(ifp);
4057                 }
4058         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
4059                 if (sc->bge_link) {
4060                         sc->bge_link = 0;
4061
4062                         if (bootverbose)
4063                                 if_printf(ifp, "link DOWN\n");
4064
4065                         ifp->if_link_state = LINK_STATE_DOWN;
4066                         if_link_state_change(ifp);
4067                 }
4068         }
4069
4070 #undef PCS_ENCODE_ERR
4071
4072         /* Clear the attention. */
4073         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4074             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4075             BGE_MACSTAT_LINK_CHANGED);
4076 }
4077
4078 static void
4079 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
4080 {
4081         struct ifnet *ifp = &sc->arpcom.ac_if;
4082         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4083
4084         mii_pollstat(mii);
4085         bge_miibus_statchg(sc->bge_dev);
4086
4087         if (bootverbose) {
4088                 if (sc->bge_link)
4089                         if_printf(ifp, "link UP\n");
4090                 else
4091                         if_printf(ifp, "link DOWN\n");
4092         }
4093
4094         /* Clear the attention. */
4095         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4096             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4097             BGE_MACSTAT_LINK_CHANGED);
4098 }
4099
4100 static void
4101 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused)
4102 {
4103         struct ifnet *ifp = &sc->arpcom.ac_if;
4104         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4105
4106         mii_pollstat(mii);
4107
4108         if (!sc->bge_link &&
4109             (mii->mii_media_status & IFM_ACTIVE) &&
4110             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4111                 sc->bge_link++;
4112                 if (bootverbose)
4113                         if_printf(ifp, "link UP\n");
4114         } else if (sc->bge_link &&
4115             (!(mii->mii_media_status & IFM_ACTIVE) ||
4116             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4117                 sc->bge_link = 0;
4118                 if (bootverbose)
4119                         if_printf(ifp, "link DOWN\n");
4120         }
4121
4122         /* Clear the attention. */
4123         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4124             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4125             BGE_MACSTAT_LINK_CHANGED);
4126 }
4127
4128 static int
4129 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
4130 {
4131         struct bge_softc *sc = arg1;
4132
4133         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4134                                    &sc->bge_rx_coal_ticks,
4135                                    BGE_RX_COAL_TICKS_CHG);
4136 }
4137
4138 static int
4139 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
4140 {
4141         struct bge_softc *sc = arg1;
4142
4143         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4144                                    &sc->bge_tx_coal_ticks,
4145                                    BGE_TX_COAL_TICKS_CHG);
4146 }
4147
4148 static int
4149 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
4150 {
4151         struct bge_softc *sc = arg1;
4152
4153         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4154                                    &sc->bge_rx_max_coal_bds,
4155                                    BGE_RX_MAX_COAL_BDS_CHG);
4156 }
4157
4158 static int
4159 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
4160 {
4161         struct bge_softc *sc = arg1;
4162
4163         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4164                                    &sc->bge_tx_max_coal_bds,
4165                                    BGE_TX_MAX_COAL_BDS_CHG);
4166 }
4167
4168 static int
4169 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
4170                     uint32_t coal_chg_mask)
4171 {
4172         struct bge_softc *sc = arg1;
4173         struct ifnet *ifp = &sc->arpcom.ac_if;
4174         int error = 0, v;
4175
4176         lwkt_serialize_enter(ifp->if_serializer);
4177
4178         v = *coal;
4179         error = sysctl_handle_int(oidp, &v, 0, req);
4180         if (!error && req->newptr != NULL) {
4181                 if (v < 0) {
4182                         error = EINVAL;
4183                 } else {
4184                         *coal = v;
4185                         sc->bge_coal_chg |= coal_chg_mask;
4186                 }
4187         }
4188
4189         lwkt_serialize_exit(ifp->if_serializer);
4190         return error;
4191 }
4192
4193 static void
4194 bge_coal_change(struct bge_softc *sc)
4195 {
4196         struct ifnet *ifp = &sc->arpcom.ac_if;
4197         uint32_t val;
4198
4199         ASSERT_SERIALIZED(ifp->if_serializer);
4200
4201         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
4202                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
4203                             sc->bge_rx_coal_ticks);
4204                 DELAY(10);
4205                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
4206
4207                 if (bootverbose) {
4208                         if_printf(ifp, "rx_coal_ticks -> %u\n",
4209                                   sc->bge_rx_coal_ticks);
4210                 }
4211         }
4212
4213         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
4214                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4215                             sc->bge_tx_coal_ticks);
4216                 DELAY(10);
4217                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
4218
4219                 if (bootverbose) {
4220                         if_printf(ifp, "tx_coal_ticks -> %u\n",
4221                                   sc->bge_tx_coal_ticks);
4222                 }
4223         }
4224
4225         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
4226                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4227                             sc->bge_rx_max_coal_bds);
4228                 DELAY(10);
4229                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4230
4231                 if (bootverbose) {
4232                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
4233                                   sc->bge_rx_max_coal_bds);
4234                 }
4235         }
4236
4237         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
4238                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4239                             sc->bge_tx_max_coal_bds);
4240                 DELAY(10);
4241                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
4242
4243                 if (bootverbose) {
4244                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
4245                                   sc->bge_tx_max_coal_bds);
4246                 }
4247         }
4248
4249         sc->bge_coal_chg = 0;
4250 }
4251
4252 static void
4253 bge_enable_intr(struct bge_softc *sc)
4254 {
4255         struct ifnet *ifp = &sc->arpcom.ac_if;
4256
4257         lwkt_serialize_handler_enable(ifp->if_serializer);
4258
4259         /*
4260          * Enable interrupt.
4261          */
4262         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4263
4264         /*
4265          * Unmask the interrupt when we stop polling.
4266          */
4267         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4268
4269         /*
4270          * Trigger another interrupt, since above writing
4271          * to interrupt mailbox0 may acknowledge pending
4272          * interrupt.
4273          */
4274         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4275 }
4276
4277 static void
4278 bge_disable_intr(struct bge_softc *sc)
4279 {
4280         struct ifnet *ifp = &sc->arpcom.ac_if;
4281
4282         /*
4283          * Mask the interrupt when we start polling.
4284          */
4285         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4286
4287         /*
4288          * Acknowledge possible asserted interrupt.
4289          */
4290         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4291
4292         lwkt_serialize_handler_disable(ifp->if_serializer);
4293 }
4294
4295 static int
4296 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4297 {
4298         uint32_t mac_addr;
4299         int ret = 1;
4300
4301         mac_addr = bge_readmem_ind(sc, 0x0c14);
4302         if ((mac_addr >> 16) == 0x484b) {
4303                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4304                 ether_addr[1] = (uint8_t)mac_addr;
4305                 mac_addr = bge_readmem_ind(sc, 0x0c18);
4306                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4307                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4308                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4309                 ether_addr[5] = (uint8_t)mac_addr;
4310                 ret = 0;
4311         }
4312         return ret;
4313 }
4314
4315 static int
4316 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4317 {
4318         int mac_offset = BGE_EE_MAC_OFFSET;
4319
4320         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4321                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4322
4323         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4324 }
4325
4326 static int
4327 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4328 {
4329         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4330                 return 1;
4331
4332         return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4333                                ETHER_ADDR_LEN);
4334 }
4335
4336 static int
4337 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4338 {
4339         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4340                 /* NOTE: Order is critical */
4341                 bge_get_eaddr_mem,
4342                 bge_get_eaddr_nvram,
4343                 bge_get_eaddr_eeprom,
4344                 NULL
4345         };
4346         const bge_eaddr_fcn_t *func;
4347
4348         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4349                 if ((*func)(sc, eaddr) == 0)
4350                         break;
4351         }
4352         return (*func == NULL ? ENXIO : 0);
4353 }
4354
4355 /*
4356  * NOTE: 'm' is not freed upon failure
4357  */
4358 struct mbuf *
4359 bge_defrag_shortdma(struct mbuf *m)
4360 {
4361         struct mbuf *n;
4362         int found;
4363
4364         /*
4365          * If device receive two back-to-back send BDs with less than
4366          * or equal to 8 total bytes then the device may hang.  The two
4367          * back-to-back send BDs must in the same frame for this failure
4368          * to occur.  Scan mbuf chains and see whether two back-to-back
4369          * send BDs are there.  If this is the case, allocate new mbuf
4370          * and copy the frame to workaround the silicon bug.
4371          */
4372         for (n = m, found = 0; n != NULL; n = n->m_next) {
4373                 if (n->m_len < 8) {
4374                         found++;
4375                         if (found > 1)
4376                                 break;
4377                         continue;
4378                 }
4379                 found = 0;
4380         }
4381
4382         if (found > 1)
4383                 n = m_defrag(m, MB_DONTWAIT);
4384         else
4385                 n = m;
4386         return n;
4387 }