2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 #include <machine/md_var.h>
58 #include <drm/drm_vma_manager.h>
59 #include <drm/i915_drm.h>
61 #include "i915_trace.h"
62 #include "intel_drv.h"
63 #include <linux/shmem_fs.h>
64 #include <linux/slab.h>
65 #include <linux/swap.h>
66 #include <linux/pci.h>
68 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
69 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
71 static __must_check int
72 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
74 static __must_check int
75 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
76 struct i915_address_space *vm,
78 bool map_and_fenceable,
80 static int i915_gem_phys_pwrite(struct drm_device *dev,
81 struct drm_i915_gem_object *obj,
82 struct drm_i915_gem_pwrite *args,
83 struct drm_file *file);
85 static void i915_gem_write_fence(struct drm_device *dev, int reg,
86 struct drm_i915_gem_object *obj);
87 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
88 struct drm_i915_fence_reg *fence,
91 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
92 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
93 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
95 static bool cpu_cache_is_coherent(struct drm_device *dev,
96 enum i915_cache_level level)
98 return HAS_LLC(dev) || level != I915_CACHE_NONE;
101 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
103 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
106 return obj->pin_display;
109 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
111 if (obj->tiling_mode)
112 i915_gem_release_mmap(obj);
114 /* As we do not have an associated fence register, we will force
115 * a tiling change if we ever need to acquire one.
117 obj->fence_dirty = false;
118 obj->fence_reg = I915_FENCE_REG_NONE;
121 /* some bookkeeping */
122 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
125 spin_lock(&dev_priv->mm.object_stat_lock);
126 dev_priv->mm.object_count++;
127 dev_priv->mm.object_memory += size;
128 spin_unlock(&dev_priv->mm.object_stat_lock);
131 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
134 spin_lock(&dev_priv->mm.object_stat_lock);
135 dev_priv->mm.object_count--;
136 dev_priv->mm.object_memory -= size;
137 spin_unlock(&dev_priv->mm.object_stat_lock);
141 i915_gem_wait_for_error(struct i915_gpu_error *error)
145 #define EXIT_COND (!i915_reset_in_progress(error) || \
146 i915_terminally_wedged(error))
151 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
152 * userspace. If it takes that long something really bad is going on and
153 * we should simply try to bail out and fail as gracefully as possible.
155 ret = wait_event_interruptible_timeout(error->reset_queue,
159 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
161 } else if (ret < 0) {
169 int i915_mutex_lock_interruptible(struct drm_device *dev)
171 struct drm_i915_private *dev_priv = dev->dev_private;
174 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
178 ret = lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_SLEEPFAIL);
182 WARN_ON(i915_verify_lists(dev));
187 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
189 return i915_gem_obj_bound_any(obj) && !obj->active;
193 i915_gem_init_ioctl(struct drm_device *dev, void *data,
194 struct drm_file *file)
196 struct drm_i915_private *dev_priv = dev->dev_private;
197 struct drm_i915_gem_init *args = data;
199 if (drm_core_check_feature(dev, DRIVER_MODESET))
202 if (args->gtt_start >= args->gtt_end ||
203 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
206 /* GEM with user mode setting was never supported on ilk and later. */
207 if (INTEL_INFO(dev)->gen >= 5)
210 mutex_lock(&dev->struct_mutex);
211 dev_priv->gtt.mappable_end = args->gtt_end;
212 kprintf("INITGLOBALGTT GTT_START %016jx\n", (uintmax_t)args->gtt_start);
213 i915_gem_init_global_gtt(dev);
215 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
218 mutex_unlock(&dev->struct_mutex);
224 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
225 struct drm_file *file)
227 struct drm_i915_private *dev_priv = dev->dev_private;
228 struct drm_i915_gem_get_aperture *args = data;
229 struct drm_i915_gem_object *obj;
233 mutex_lock(&dev->struct_mutex);
234 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
236 pinned += i915_gem_obj_ggtt_size(obj);
237 mutex_unlock(&dev->struct_mutex);
239 args->aper_size = dev_priv->gtt.base.total;
240 args->aper_available_size = args->aper_size - pinned;
245 void *i915_gem_object_alloc(struct drm_device *dev)
247 return kmalloc(sizeof(struct drm_i915_gem_object),
248 M_DRM, M_WAITOK | M_ZERO);
251 void i915_gem_object_free(struct drm_i915_gem_object *obj)
257 i915_gem_create(struct drm_file *file,
258 struct drm_device *dev,
262 struct drm_i915_gem_object *obj;
266 size = roundup(size, PAGE_SIZE);
270 /* Allocate the new object */
271 obj = i915_gem_alloc_object(dev, size);
275 ret = drm_gem_handle_create(file, &obj->base, &handle);
276 /* drop reference from allocate - handle holds it now */
277 drm_gem_object_unreference_unlocked(&obj->base);
286 i915_gem_dumb_create(struct drm_file *file,
287 struct drm_device *dev,
288 struct drm_mode_create_dumb *args)
290 /* have to work out size/pitch and return them */
291 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
292 args->size = args->pitch * args->height;
293 return i915_gem_create(file, dev,
294 args->size, &args->handle);
298 * Creates a new mm object and returns a handle to it.
301 i915_gem_create_ioctl(struct drm_device *dev, void *data,
302 struct drm_file *file)
304 struct drm_i915_gem_create *args = data;
306 return i915_gem_create(file, dev,
307 args->size, &args->handle);
311 __copy_to_user_swizzled(char __user *cpu_vaddr,
312 const char *gpu_vaddr, int gpu_offset,
315 int ret, cpu_offset = 0;
318 int cacheline_end = ALIGN(gpu_offset + 1, 64);
319 int this_length = min(cacheline_end - gpu_offset, length);
320 int swizzled_gpu_offset = gpu_offset ^ 64;
322 ret = __copy_to_user(cpu_vaddr + cpu_offset,
323 gpu_vaddr + swizzled_gpu_offset,
328 cpu_offset += this_length;
329 gpu_offset += this_length;
330 length -= this_length;
337 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
338 const char __user *cpu_vaddr,
341 int ret, cpu_offset = 0;
344 int cacheline_end = ALIGN(gpu_offset + 1, 64);
345 int this_length = min(cacheline_end - gpu_offset, length);
346 int swizzled_gpu_offset = gpu_offset ^ 64;
348 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
349 cpu_vaddr + cpu_offset,
354 cpu_offset += this_length;
355 gpu_offset += this_length;
356 length -= this_length;
362 /* Per-page copy function for the shmem pread fastpath.
363 * Flushes invalid cachelines before reading the target if
364 * needs_clflush is set. */
366 shmem_pread_fast(struct vm_page *page, int shmem_page_offset, int page_length,
367 char __user *user_data,
368 bool page_do_bit17_swizzling, bool needs_clflush)
373 if (unlikely(page_do_bit17_swizzling))
376 vaddr = kmap_atomic(page);
378 drm_clflush_virt_range(vaddr + shmem_page_offset,
380 ret = __copy_to_user_inatomic(user_data,
381 vaddr + shmem_page_offset,
383 kunmap_atomic(vaddr);
385 return ret ? -EFAULT : 0;
389 shmem_clflush_swizzled_range(char *addr, unsigned long length,
392 if (unlikely(swizzled)) {
393 unsigned long start = (unsigned long) addr;
394 unsigned long end = (unsigned long) addr + length;
396 /* For swizzling simply ensure that we always flush both
397 * channels. Lame, but simple and it works. Swizzled
398 * pwrite/pread is far from a hotpath - current userspace
399 * doesn't use it at all. */
400 start = round_down(start, 128);
401 end = round_up(end, 128);
403 drm_clflush_virt_range((void *)start, end - start);
405 drm_clflush_virt_range(addr, length);
410 /* Only difference to the fast-path function is that this can handle bit17
411 * and uses non-atomic copy and kmap functions. */
413 shmem_pread_slow(struct vm_page *page, int shmem_page_offset, int page_length,
414 char __user *user_data,
415 bool page_do_bit17_swizzling, bool needs_clflush)
422 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
424 page_do_bit17_swizzling);
426 if (page_do_bit17_swizzling)
427 ret = __copy_to_user_swizzled(user_data,
428 vaddr, shmem_page_offset,
431 ret = __copy_to_user(user_data,
432 vaddr + shmem_page_offset,
436 return ret ? - EFAULT : 0;
440 i915_gem_shmem_pread(struct drm_device *dev,
441 struct drm_i915_gem_object *obj,
442 struct drm_i915_gem_pread *args,
443 struct drm_file *file)
445 char __user *user_data;
448 int shmem_page_offset, page_length, ret = 0;
449 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
451 int needs_clflush = 0;
454 user_data = to_user_ptr(args->data_ptr);
457 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
459 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
460 /* If we're not in the cpu read domain, set ourself into the gtt
461 * read domain and manually flush cachelines (if required). This
462 * optimizes for the case when the gpu will dirty the data
463 * anyway again before the next pread happens. */
464 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
465 ret = i915_gem_object_wait_rendering(obj, true);
470 ret = i915_gem_object_get_pages(obj);
474 i915_gem_object_pin_pages(obj);
476 offset = args->offset;
478 for (i = 0; i < (obj->base.size >> PAGE_SHIFT); i++) {
479 struct vm_page *page = obj->pages[i];
484 /* Operation in this page
486 * shmem_page_offset = offset within page in shmem file
487 * page_length = bytes to copy for this page
489 shmem_page_offset = offset_in_page(offset);
490 page_length = remain;
491 if ((shmem_page_offset + page_length) > PAGE_SIZE)
492 page_length = PAGE_SIZE - shmem_page_offset;
494 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
495 (page_to_phys(page) & (1 << 17)) != 0;
497 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
498 user_data, page_do_bit17_swizzling,
503 mutex_unlock(&dev->struct_mutex);
505 if (likely(!i915_prefault_disable) && !prefaulted) {
506 ret = fault_in_multipages_writeable(user_data, remain);
507 /* Userspace is tricking us, but we've already clobbered
508 * its pages with the prefault and promised to write the
509 * data up to the first fault. Hence ignore any errors
510 * and just continue. */
515 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
516 user_data, page_do_bit17_swizzling,
519 mutex_lock(&dev->struct_mutex);
522 mark_page_accessed(page);
527 remain -= page_length;
528 user_data += page_length;
529 offset += page_length;
533 i915_gem_object_unpin_pages(obj);
539 * Reads data from the object referenced by handle.
541 * On error, the contents of *data are undefined.
544 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
545 struct drm_file *file)
547 struct drm_i915_gem_pread *args = data;
548 struct drm_i915_gem_object *obj;
554 ret = i915_mutex_lock_interruptible(dev);
558 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
559 if (&obj->base == NULL) {
564 /* Bounds check source. */
565 if (args->offset > obj->base.size ||
566 args->size > obj->base.size - args->offset) {
571 trace_i915_gem_object_pread(obj, args->offset, args->size);
573 ret = i915_gem_shmem_pread(dev, obj, args, file);
576 drm_gem_object_unreference(&obj->base);
578 mutex_unlock(&dev->struct_mutex);
582 /* This is the fast write path which cannot handle
583 * page faults in the source data
586 #if 0 /* XXX: buggy on core2 machines */
588 fast_user_write(struct io_mapping *mapping,
589 loff_t page_base, int page_offset,
590 char __user *user_data,
593 void __iomem *vaddr_atomic;
595 unsigned long unwritten;
597 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
598 /* We can use the cpu mem copy function because this is X86. */
599 vaddr = (char __force*)vaddr_atomic + page_offset;
600 unwritten = __copy_from_user_inatomic_nocache(vaddr,
602 io_mapping_unmap_atomic(vaddr_atomic);
608 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
609 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
615 * Pass the unaligned physical address and size to pmap_mapdev_attr()
616 * so it can properly calculate whether an extra page needs to be
617 * mapped or not to cover the requested range. The function will
618 * add the page offset into the returned mkva for us.
620 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base +
621 i915_gem_obj_ggtt_offset(obj) + offset, size, PAT_WRITE_COMBINING);
622 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
623 pmap_unmapdev(mkva, size);
628 * This is the fast pwrite path, where we copy the data directly from the
629 * user into the GTT, uncached.
632 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
633 struct drm_i915_gem_object *obj,
634 struct drm_i915_gem_pwrite *args,
635 struct drm_file *file)
638 loff_t offset, page_base;
639 char __user *user_data;
640 int page_offset, page_length, ret;
642 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
646 ret = i915_gem_object_set_to_gtt_domain(obj, true);
650 ret = i915_gem_object_put_fence(obj);
654 user_data = to_user_ptr(args->data_ptr);
657 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
660 /* Operation in this page
662 * page_base = page offset within aperture
663 * page_offset = offset within page
664 * page_length = bytes to copy for this page
666 page_base = offset & ~PAGE_MASK;
667 page_offset = offset_in_page(offset);
668 page_length = remain;
669 if ((page_offset + remain) > PAGE_SIZE)
670 page_length = PAGE_SIZE - page_offset;
672 /* If we get a fault while copying data, then (presumably) our
673 * source page isn't available. Return the error and we'll
674 * retry in the slow path.
677 if (fast_user_write(dev_priv->gtt.mappable, page_base,
678 page_offset, user_data, page_length)) {
680 if (i915_gem_gtt_write(dev, obj, args->data_ptr, args->size, args->offset, file)) {
686 remain -= page_length;
687 user_data += page_length;
688 offset += page_length;
692 i915_gem_object_unpin(obj);
697 /* Per-page copy function for the shmem pwrite fastpath.
698 * Flushes invalid cachelines before writing to the target if
699 * needs_clflush_before is set and flushes out any written cachelines after
700 * writing if needs_clflush is set. */
702 shmem_pwrite_fast(struct vm_page *page, int shmem_page_offset, int page_length,
703 char __user *user_data,
704 bool page_do_bit17_swizzling,
705 bool needs_clflush_before,
706 bool needs_clflush_after)
711 if (unlikely(page_do_bit17_swizzling))
714 vaddr = kmap_atomic(page);
715 if (needs_clflush_before)
716 drm_clflush_virt_range(vaddr + shmem_page_offset,
718 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
721 if (needs_clflush_after)
722 drm_clflush_virt_range(vaddr + shmem_page_offset,
724 kunmap_atomic(vaddr);
726 return ret ? -EFAULT : 0;
729 /* Only difference to the fast-path function is that this can handle bit17
730 * and uses non-atomic copy and kmap functions. */
732 shmem_pwrite_slow(struct vm_page *page, int shmem_page_offset, int page_length,
733 char __user *user_data,
734 bool page_do_bit17_swizzling,
735 bool needs_clflush_before,
736 bool needs_clflush_after)
742 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
743 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
745 page_do_bit17_swizzling);
746 if (page_do_bit17_swizzling)
747 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
751 ret = __copy_from_user(vaddr + shmem_page_offset,
754 if (needs_clflush_after)
755 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
757 page_do_bit17_swizzling);
760 return ret ? -EFAULT : 0;
764 i915_gem_shmem_pwrite(struct drm_device *dev,
765 struct drm_i915_gem_object *obj,
766 struct drm_i915_gem_pwrite *args,
767 struct drm_file *file)
771 char __user *user_data;
772 int shmem_page_offset, page_length, ret = 0;
773 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
774 int hit_slowpath = 0;
775 int needs_clflush_after = 0;
776 int needs_clflush_before = 0;
779 user_data = to_user_ptr(args->data_ptr);
782 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
784 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
785 /* If we're not in the cpu write domain, set ourself into the gtt
786 * write domain and manually flush cachelines (if required). This
787 * optimizes for the case when the gpu will use the data
788 * right away and we therefore have to clflush anyway. */
789 needs_clflush_after = cpu_write_needs_clflush(obj);
790 ret = i915_gem_object_wait_rendering(obj, false);
794 /* Same trick applies to invalidate partially written cachelines read
796 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
797 needs_clflush_before =
798 !cpu_cache_is_coherent(dev, obj->cache_level);
800 ret = i915_gem_object_get_pages(obj);
804 i915_gem_object_pin_pages(obj);
806 offset = args->offset;
809 VM_OBJECT_LOCK(obj->base.vm_obj);
810 vm_object_pip_add(obj->base.vm_obj, 1);
811 for (i = 0; i < (obj->base.size >> PAGE_SHIFT); i++) {
812 struct vm_page *page = obj->pages[i];
813 int partial_cacheline_write;
815 if (i < offset >> PAGE_SHIFT)
821 /* Operation in this page
823 * shmem_page_offset = offset within page in shmem file
824 * page_length = bytes to copy for this page
826 shmem_page_offset = offset_in_page(offset);
828 page_length = remain;
829 if ((shmem_page_offset + page_length) > PAGE_SIZE)
830 page_length = PAGE_SIZE - shmem_page_offset;
832 /* If we don't overwrite a cacheline completely we need to be
833 * careful to have up-to-date data by first clflushing. Don't
834 * overcomplicate things and flush the entire patch. */
835 partial_cacheline_write = needs_clflush_before &&
836 ((shmem_page_offset | page_length)
837 & (cpu_clflush_line_size - 1));
839 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
840 (page_to_phys(page) & (1 << 17)) != 0;
842 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
843 user_data, page_do_bit17_swizzling,
844 partial_cacheline_write,
845 needs_clflush_after);
850 mutex_unlock(&dev->struct_mutex);
851 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
852 user_data, page_do_bit17_swizzling,
853 partial_cacheline_write,
854 needs_clflush_after);
856 mutex_lock(&dev->struct_mutex);
859 set_page_dirty(page);
860 mark_page_accessed(page);
865 remain -= page_length;
866 user_data += page_length;
867 offset += page_length;
869 vm_object_pip_wakeup(obj->base.vm_obj);
870 VM_OBJECT_UNLOCK(obj->base.vm_obj);
873 i915_gem_object_unpin_pages(obj);
877 * Fixup: Flush cpu caches in case we didn't flush the dirty
878 * cachelines in-line while writing and the object moved
879 * out of the cpu write domain while we've dropped the lock.
881 if (!needs_clflush_after &&
882 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
883 if (i915_gem_clflush_object(obj, obj->pin_display))
884 i915_gem_chipset_flush(dev);
888 if (needs_clflush_after)
889 i915_gem_chipset_flush(dev);
895 * Writes data to the object referenced by handle.
897 * On error, the contents of the buffer that were to be modified are undefined.
900 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
901 struct drm_file *file)
903 struct drm_i915_gem_pwrite *args = data;
904 struct drm_i915_gem_object *obj;
910 if (likely(!i915_prefault_disable)) {
911 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
917 ret = i915_mutex_lock_interruptible(dev);
921 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
922 if (&obj->base == NULL) {
927 /* Bounds check destination. */
928 if (args->offset > obj->base.size ||
929 args->size > obj->base.size - args->offset) {
934 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
937 /* We can only do the GTT pwrite on untiled buffers, as otherwise
938 * it would end up going through the fenced access, and we'll get
939 * different detiling behavior between reading and writing.
940 * pread/pwrite currently are reading and writing from the CPU
941 * perspective, requiring manual detiling by the client.
944 ret = i915_gem_phys_pwrite(dev, obj, args, file);
948 if (obj->tiling_mode == I915_TILING_NONE &&
949 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
950 cpu_write_needs_clflush(obj)) {
951 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
952 /* Note that the gtt paths might fail with non-page-backed user
953 * pointers (e.g. gtt mappings when moving data between
954 * textures). Fallback to the shmem path in that case. */
957 if (ret == -EFAULT || ret == -ENOSPC)
958 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
961 drm_gem_object_unreference(&obj->base);
963 mutex_unlock(&dev->struct_mutex);
968 i915_gem_check_wedge(struct i915_gpu_error *error,
971 if (i915_reset_in_progress(error)) {
972 /* Non-interruptible callers can't handle -EAGAIN, hence return
973 * -EIO unconditionally for these. */
977 /* Recovery complete, but the reset failed ... */
978 if (i915_terminally_wedged(error))
988 * Compare seqno against outstanding lazy request. Emit a request if they are
992 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
996 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
999 if (seqno == ring->outstanding_lazy_seqno)
1000 ret = i915_add_request(ring, NULL);
1006 static void fake_irq(unsigned long data)
1008 wake_up_process((struct task_struct *)data);
1011 static bool missed_irq(struct drm_i915_private *dev_priv,
1012 struct intel_ring_buffer *ring)
1014 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1017 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1019 if (file_priv == NULL)
1022 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1027 * __wait_seqno - wait until execution of seqno has finished
1028 * @ring: the ring expected to report seqno
1030 * @reset_counter: reset sequence associated with the given seqno
1031 * @interruptible: do an interruptible wait (normally yes)
1032 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1034 * Note: It is of utmost importance that the passed in seqno and reset_counter
1035 * values have been read by the caller in an smp safe manner. Where read-side
1036 * locks are involved, it is sufficient to read the reset_counter before
1037 * unlocking the lock that protects the seqno. For lockless tricks, the
1038 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1041 * Returns 0 if the seqno was found within the alloted time. Else returns the
1042 * errno with remaining time filled in timeout argument.
1044 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1045 unsigned reset_counter,
1046 bool interruptible, struct timespec *timeout)
1048 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1049 struct timespec before, now, wait_time={1,0};
1050 unsigned long timeout_jiffies;
1052 bool wait_forever = true;
1055 WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
1057 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1060 trace_i915_gem_request_wait_begin(ring, seqno);
1062 if (timeout != NULL) {
1063 wait_time = *timeout;
1064 wait_forever = false;
1067 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1069 if (WARN_ON(!ring->irq_get(ring)))
1072 /* Record current time in case interrupted by signal, or wedged * */
1073 getrawmonotonic(&before);
1076 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1077 i915_reset_in_progress(&dev_priv->gpu_error) || \
1078 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1081 end = wait_event_interruptible_timeout(ring->irq_queue,
1085 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1088 /* We need to check whether any gpu reset happened in between
1089 * the caller grabbing the seqno and now ... */
1090 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1093 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1095 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1098 } while (end == 0 && wait_forever);
1100 getrawmonotonic(&now);
1102 ring->irq_put(ring);
1103 trace_i915_gem_request_wait_end(ring, seqno);
1107 struct timespec sleep_time = timespec_sub(now, before);
1108 *timeout = timespec_sub(*timeout, sleep_time);
1109 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1110 set_normalized_timespec(timeout, 0, 0);
1115 case -EAGAIN: /* Wedged */
1116 case -ERESTARTSYS: /* Signal */
1118 case 0: /* Timeout */
1119 return -ETIMEDOUT; /* -ETIME on Linux */
1120 default: /* Completed */
1121 WARN_ON(end < 0); /* We're not aware of other errors */
1127 * Waits for a sequence number to be signaled, and cleans up the
1128 * request and object lists appropriately for that event.
1131 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1133 struct drm_device *dev = ring->dev;
1134 struct drm_i915_private *dev_priv = dev->dev_private;
1135 bool interruptible = dev_priv->mm.interruptible;
1138 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1141 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1145 ret = i915_gem_check_olr(ring, seqno);
1149 return __wait_seqno(ring, seqno,
1150 atomic_read(&dev_priv->gpu_error.reset_counter),
1151 interruptible, NULL);
1155 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1156 struct intel_ring_buffer *ring)
1158 i915_gem_retire_requests_ring(ring);
1160 /* Manually manage the write flush as we may have not yet
1161 * retired the buffer.
1163 * Note that the last_write_seqno is always the earlier of
1164 * the two (read/write) seqno, so if we haved successfully waited,
1165 * we know we have passed the last write.
1167 obj->last_write_seqno = 0;
1168 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1174 * Ensures that all rendering to the object has completed and the object is
1175 * safe to unbind from the GTT or access from the CPU.
1177 static __must_check int
1178 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1181 struct intel_ring_buffer *ring = obj->ring;
1185 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1189 ret = i915_wait_seqno(ring, seqno);
1193 return i915_gem_object_wait_rendering__tail(obj, ring);
1196 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1197 * as the object state may change during this call.
1199 static __must_check int
1200 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1203 struct drm_device *dev = obj->base.dev;
1204 struct drm_i915_private *dev_priv = dev->dev_private;
1205 struct intel_ring_buffer *ring = obj->ring;
1206 unsigned reset_counter;
1210 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1211 BUG_ON(!dev_priv->mm.interruptible);
1213 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1217 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1221 ret = i915_gem_check_olr(ring, seqno);
1225 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1226 mutex_unlock(&dev->struct_mutex);
1227 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1228 mutex_lock(&dev->struct_mutex);
1232 return i915_gem_object_wait_rendering__tail(obj, ring);
1236 * Called when user space prepares to use an object with the CPU, either
1237 * through the mmap ioctl's mapping or a GTT mapping.
1240 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1241 struct drm_file *file)
1243 struct drm_i915_gem_set_domain *args = data;
1244 struct drm_i915_gem_object *obj;
1245 uint32_t read_domains = args->read_domains;
1246 uint32_t write_domain = args->write_domain;
1249 /* Only handle setting domains to types used by the CPU. */
1250 if (write_domain & I915_GEM_GPU_DOMAINS)
1253 if (read_domains & I915_GEM_GPU_DOMAINS)
1256 /* Having something in the write domain implies it's in the read
1257 * domain, and only that read domain. Enforce that in the request.
1259 if (write_domain != 0 && read_domains != write_domain)
1262 ret = i915_mutex_lock_interruptible(dev);
1266 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1267 if (&obj->base == NULL) {
1272 /* Try to flush the object off the GPU without holding the lock.
1273 * We will repeat the flush holding the lock in the normal manner
1274 * to catch cases where we are gazumped.
1276 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1280 if (read_domains & I915_GEM_DOMAIN_GTT) {
1281 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1283 /* Silently promote "you're not bound, there was nothing to do"
1284 * to success, since the client was just asking us to
1285 * make sure everything was done.
1290 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1294 drm_gem_object_unreference(&obj->base);
1296 mutex_unlock(&dev->struct_mutex);
1301 * Called when user space has done writes to this buffer
1304 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1305 struct drm_file *file)
1307 struct drm_i915_gem_sw_finish *args = data;
1308 struct drm_i915_gem_object *obj;
1311 ret = i915_mutex_lock_interruptible(dev);
1315 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1316 if (&obj->base == NULL) {
1321 /* Pinned buffers may be scanout, so flush the cache */
1322 if (obj->pin_display)
1323 i915_gem_object_flush_cpu_write_domain(obj, true);
1325 drm_gem_object_unreference(&obj->base);
1327 mutex_unlock(&dev->struct_mutex);
1332 * Maps the contents of an object, returning the address it is mapped
1335 * While the mapping holds a reference on the contents of the object, it doesn't
1336 * imply a ref on the object itself.
1339 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1340 struct drm_file *file)
1342 struct drm_i915_gem_mmap *args = data;
1343 struct drm_gem_object *obj;
1345 struct proc *p = curproc;
1346 vm_map_t map = &p->p_vmspace->vm_map;
1350 obj = drm_gem_object_lookup(dev, file, args->handle);
1354 if (args->size == 0)
1357 size = round_page(args->size);
1358 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1364 vm_object_hold(obj->vm_obj);
1365 vm_object_reference_locked(obj->vm_obj);
1366 vm_object_drop(obj->vm_obj);
1367 rv = vm_map_find(map, obj->vm_obj, NULL,
1368 args->offset, &addr, args->size,
1369 PAGE_SIZE, /* align */
1371 VM_MAPTYPE_NORMAL, /* maptype */
1372 VM_PROT_READ | VM_PROT_WRITE, /* prot */
1373 VM_PROT_READ | VM_PROT_WRITE, /* max */
1374 MAP_SHARED /* cow */);
1375 if (rv != KERN_SUCCESS) {
1376 vm_object_deallocate(obj->vm_obj);
1377 error = -vm_mmap_to_errno(rv);
1379 args->addr_ptr = (uint64_t)addr;
1382 drm_gem_object_unreference(obj);
1387 * i915_gem_fault - fault a page into the GTT
1388 * vma: VMA in question
1391 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1392 * from userspace. The fault handler takes care of binding the object to
1393 * the GTT (if needed), allocating and programming a fence register (again,
1394 * only if needed based on whether the old reg is still valid or the object
1395 * is tiled) and inserting a new PTE into the faulting process.
1397 * Note that the faulting process may involve evicting existing objects
1398 * from the GTT and/or fence registers to make room. So performance may
1399 * suffer if the GTT working set is large or there are few fence registers
1402 int i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, vm_page_t *mres)
1404 struct drm_i915_gem_object *obj = to_intel_bo(vm_obj->handle);
1405 struct drm_device *dev = obj->base.dev;
1406 drm_i915_private_t *dev_priv = dev->dev_private;
1407 unsigned long page_offset;
1408 vm_page_t m, oldm = NULL;
1410 bool write = !!(prot & VM_PROT_WRITE);
1412 intel_runtime_pm_get(dev_priv);
1414 /* We don't use vmf->pgoff since that has the fake offset */
1415 page_offset = (unsigned long)offset;
1417 /* Magic FreeBSD VM stuff */
1418 vm_object_pip_add(vm_obj, 1);
1421 * Remove the placeholder page inserted by vm_fault() from the
1422 * object before dropping the object lock. If
1423 * i915_gem_release_mmap() is active in parallel on this gem
1424 * object, then it owns the drm device sx and might find the
1425 * placeholder already. Then, since the page is busy,
1426 * i915_gem_release_mmap() sleeps waiting for the busy state
1427 * of the page cleared. We will be not able to acquire drm
1428 * device lock until i915_gem_release_mmap() is able to make a
1431 if (*mres != NULL) {
1433 vm_page_remove(oldm);
1438 VM_OBJECT_UNLOCK(vm_obj);
1443 mutex_lock(&dev->struct_mutex);
1446 * Since the object lock was dropped, other thread might have
1447 * faulted on the same GTT address and instantiated the
1448 * mapping for the page. Recheck.
1450 VM_OBJECT_LOCK(vm_obj);
1451 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1453 if ((m->flags & PG_BUSY) != 0) {
1454 mutex_unlock(&dev->struct_mutex);
1459 VM_OBJECT_UNLOCK(vm_obj);
1460 /* End magic VM stuff */
1462 trace_i915_gem_object_fault(obj, page_offset, true, write);
1464 /* Access to snoopable pages through the GTT is incoherent. */
1465 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1470 /* Now bind it into the GTT if needed */
1471 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1475 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1479 ret = i915_gem_object_get_fence(obj);
1483 obj->fault_mappable = true;
1485 VM_OBJECT_LOCK(vm_obj);
1486 m = vm_phys_fictitious_to_vm_page(dev->agp->base +
1487 i915_gem_obj_ggtt_offset(obj) + offset);
1492 KASSERT((m->flags & PG_FICTITIOUS) != 0,
1493 ("not fictitious %p", m));
1494 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1496 if ((m->flags & PG_BUSY) != 0) {
1497 i915_gem_object_unpin(obj);
1498 mutex_unlock(&dev->struct_mutex);
1501 m->valid = VM_PAGE_BITS_ALL;
1503 /* Finally, remap it using the new GTT offset */
1504 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1507 vm_page_busy_try(m, false);
1509 i915_gem_object_unpin(obj);
1510 mutex_unlock(&dev->struct_mutex);
1514 vm_object_pip_wakeup(vm_obj);
1515 return (VM_PAGER_OK);
1518 i915_gem_object_unpin(obj);
1520 mutex_unlock(&dev->struct_mutex);
1522 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1527 goto unlocked_vmobj;
1529 VM_OBJECT_LOCK(vm_obj);
1530 vm_object_pip_wakeup(vm_obj);
1531 ret = VM_PAGER_ERROR;
1534 intel_runtime_pm_put(dev_priv);
1538 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1540 struct i915_vma *vma;
1543 * Only the global gtt is relevant for gtt memory mappings, so restrict
1544 * list traversal to objects bound into the global address space. Note
1545 * that the active list should be empty, but better safe than sorry.
1547 WARN_ON(!list_empty(&dev_priv->gtt.base.active_list));
1548 list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list)
1549 i915_gem_release_mmap(vma->obj);
1550 list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list)
1551 i915_gem_release_mmap(vma->obj);
1555 * i915_gem_release_mmap - remove physical page mappings
1556 * @obj: obj in question
1558 * Preserve the reservation of the mmapping with the DRM core code, but
1559 * relinquish ownership of the pages back to the system.
1561 * It is vital that we remove the page mapping if we have mapped a tiled
1562 * object through the GTT and then lose the fence register due to
1563 * resource pressure. Similarly if the object has been moved out of the
1564 * aperture, than pages mapped into userspace must be revoked. Removing the
1565 * mapping will then trigger a page fault on the next user access, allowing
1566 * fixup by i915_gem_fault().
1569 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1575 if (!obj->fault_mappable)
1578 devobj = cdev_pager_lookup(obj);
1579 if (devobj != NULL) {
1580 page_count = OFF_TO_IDX(obj->base.size);
1582 VM_OBJECT_LOCK(devobj);
1583 for (i = 0; i < page_count; i++) {
1584 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
1587 cdev_pager_free_page(devobj, m);
1589 VM_OBJECT_UNLOCK(devobj);
1590 vm_object_deallocate(devobj);
1593 obj->fault_mappable = false;
1597 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1601 if (INTEL_INFO(dev)->gen >= 4 ||
1602 tiling_mode == I915_TILING_NONE)
1605 /* Previous chips need a power-of-two fence region when tiling */
1606 if (INTEL_INFO(dev)->gen == 3)
1607 gtt_size = 1024*1024;
1609 gtt_size = 512*1024;
1611 while (gtt_size < size)
1618 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1619 * @obj: object to check
1621 * Return the required GTT alignment for an object, taking into account
1622 * potential fence register mapping.
1625 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1626 int tiling_mode, bool fenced)
1629 * Minimum alignment is 4k (GTT page size), but might be greater
1630 * if a fence register is needed for the object.
1632 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1633 tiling_mode == I915_TILING_NONE)
1637 * Previous chips need to be aligned to the size of the smallest
1638 * fence register that can contain the object.
1640 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1643 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1645 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1649 if (drm_vma_node_has_offset(&obj->base.vma_node))
1653 dev_priv->mm.shrinker_no_lock_stealing = true;
1655 ret = drm_gem_create_mmap_offset(&obj->base);
1659 /* Badly fragmented mmap space? The only way we can recover
1660 * space is by destroying unwanted objects. We can't randomly release
1661 * mmap_offsets as userspace expects them to be persistent for the
1662 * lifetime of the objects. The closest we can is to release the
1663 * offsets on purgeable objects by truncating it and marking it purged,
1664 * which prevents userspace from ever using that object again.
1666 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1667 ret = drm_gem_create_mmap_offset(&obj->base);
1671 i915_gem_shrink_all(dev_priv);
1672 ret = drm_gem_create_mmap_offset(&obj->base);
1674 dev_priv->mm.shrinker_no_lock_stealing = false;
1679 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1681 drm_gem_free_mmap_offset(&obj->base);
1685 i915_gem_mmap_gtt(struct drm_file *file,
1686 struct drm_device *dev,
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 struct drm_i915_gem_object *obj;
1694 ret = i915_mutex_lock_interruptible(dev);
1698 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1699 if (&obj->base == NULL) {
1704 if (obj->base.size > dev_priv->gtt.mappable_end) {
1709 if (obj->madv != I915_MADV_WILLNEED) {
1710 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1715 ret = i915_gem_object_create_mmap_offset(obj);
1719 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1720 DRM_GEM_MAPPING_KEY;
1723 drm_gem_object_unreference(&obj->base);
1725 mutex_unlock(&dev->struct_mutex);
1730 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1732 * @data: GTT mapping ioctl data
1733 * @file: GEM object info
1735 * Simply returns the fake offset to userspace so it can mmap it.
1736 * The mmap call will end up in drm_gem_mmap(), which will set things
1737 * up so we can get faults in the handler above.
1739 * The fault handler will take care of binding the object into the GTT
1740 * (since it may have been evicted to make room for something), allocating
1741 * a fence register, and mapping the appropriate aperture address into
1745 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1746 struct drm_file *file)
1748 struct drm_i915_gem_mmap_gtt *args = data;
1750 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1753 /* Immediately discard the backing storage */
1755 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1759 vm_obj = obj->base.vm_obj;
1760 VM_OBJECT_LOCK(vm_obj);
1761 vm_object_page_remove(vm_obj, 0, 0, false);
1762 VM_OBJECT_UNLOCK(vm_obj);
1764 obj->madv = __I915_MADV_PURGED;
1768 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1770 return obj->madv == I915_MADV_DONTNEED;
1774 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1776 int page_count = obj->base.size / PAGE_SIZE;
1782 BUG_ON(obj->madv == __I915_MADV_PURGED);
1784 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1786 /* In the event of a disaster, abandon all caches and
1787 * hope for the best.
1789 WARN_ON(ret != -EIO);
1790 i915_gem_clflush_object(obj, true);
1791 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1794 if (i915_gem_object_needs_bit17_swizzle(obj))
1795 i915_gem_object_save_bit_17_swizzle(obj);
1797 if (obj->madv == I915_MADV_DONTNEED)
1800 for (i = 0; i < page_count; i++) {
1801 struct vm_page *page = obj->pages[i];
1804 set_page_dirty(page);
1806 if (obj->madv == I915_MADV_WILLNEED)
1807 mark_page_accessed(page);
1809 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
1810 vm_page_unwire(obj->pages[i], 1);
1811 vm_page_wakeup(obj->pages[i]);
1820 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1822 const struct drm_i915_gem_object_ops *ops = obj->ops;
1824 if (obj->pages == NULL)
1827 if (obj->pages_pin_count)
1830 BUG_ON(i915_gem_obj_bound_any(obj));
1832 /* ->put_pages might need to allocate memory for the bit17 swizzle
1833 * array, hence protect them from being reaped by removing them from gtt
1835 list_del(&obj->global_list);
1837 ops->put_pages(obj);
1840 if (i915_gem_object_is_purgeable(obj))
1841 i915_gem_object_truncate(obj);
1846 static unsigned long
1847 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1848 bool purgeable_only)
1850 struct drm_i915_gem_object *obj, *next;
1851 unsigned long count = 0;
1853 list_for_each_entry_safe(obj, next,
1854 &dev_priv->mm.unbound_list,
1856 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1857 i915_gem_object_put_pages(obj) == 0) {
1858 count += obj->base.size >> PAGE_SHIFT;
1859 if (count >= target)
1864 list_for_each_entry_safe(obj, next, &dev_priv->mm.bound_list,
1866 struct i915_vma *vma, *v;
1868 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1871 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1872 if (i915_vma_unbind(vma))
1875 if (!i915_gem_object_put_pages(obj)) {
1876 count += obj->base.size >> PAGE_SHIFT;
1877 if (count >= target)
1885 static unsigned long
1886 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1888 return __i915_gem_shrink(dev_priv, target, true);
1891 static unsigned long
1892 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1894 struct drm_i915_gem_object *obj, *next;
1897 i915_gem_evict_everything(dev_priv->dev);
1899 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1901 if (i915_gem_object_put_pages(obj) == 0)
1902 freed += obj->base.size >> PAGE_SHIFT;
1908 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1910 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1911 int page_count, i, j;
1913 struct vm_page *page;
1915 /* Assert that the object is not currently in any GPU domain. As it
1916 * wasn't in the GTT, there shouldn't be any way it could have been in
1919 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1920 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1922 page_count = obj->base.size / PAGE_SIZE;
1923 obj->pages = kmalloc(page_count * sizeof(vm_page_t), M_DRM,
1926 /* Get the list of pages out of our struct file. They'll be pinned
1927 * at this point until we release them.
1929 * Fail silently without starting the shrinker
1931 vm_obj = obj->base.vm_obj;
1932 VM_OBJECT_LOCK(vm_obj);
1933 for (i = 0; i < page_count; i++) {
1934 page = shmem_read_mapping_page(vm_obj, i);
1936 i915_gem_purge(dev_priv, page_count);
1937 page = shmem_read_mapping_page(vm_obj, i);
1940 /* We've tried hard to allocate the memory by reaping
1941 * our own buffer, now let the real VM do its job and
1942 * go down in flames if truly OOM.
1945 i915_gem_shrink_all(dev_priv);
1946 page = shmem_read_mapping_page(vm_obj, i);
1950 #ifdef CONFIG_SWIOTLB
1951 if (swiotlb_nr_tbl()) {
1953 sg_set_page(sg, page, PAGE_SIZE, 0);
1958 obj->pages[i] = page;
1960 #ifdef CONFIG_SWIOTLB
1961 if (!swiotlb_nr_tbl())
1963 VM_OBJECT_UNLOCK(vm_obj);
1965 if (i915_gem_object_needs_bit17_swizzle(obj))
1966 i915_gem_object_do_bit_17_swizzle(obj);
1971 for (j = 0; j < i; j++) {
1972 page = obj->pages[j];
1973 vm_page_busy_wait(page, FALSE, "i915gem");
1974 vm_page_unwire(page, 0);
1975 vm_page_wakeup(page);
1977 VM_OBJECT_UNLOCK(vm_obj);
1983 /* Ensure that the associated pages are gathered from the backing storage
1984 * and pinned into our object. i915_gem_object_get_pages() may be called
1985 * multiple times before they are released by a single call to
1986 * i915_gem_object_put_pages() - once the pages are no longer referenced
1987 * either as a result of memory pressure (reaping pages under the shrinker)
1988 * or as the object is itself released.
1991 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1993 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1994 const struct drm_i915_gem_object_ops *ops = obj->ops;
2000 if (obj->madv != I915_MADV_WILLNEED) {
2001 DRM_ERROR("Attempting to obtain a purgeable object\n");
2005 BUG_ON(obj->pages_pin_count);
2007 ret = ops->get_pages(obj);
2011 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2016 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2017 struct intel_ring_buffer *ring)
2019 struct drm_device *dev = obj->base.dev;
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 u32 seqno = intel_ring_get_seqno(ring);
2023 BUG_ON(ring == NULL);
2024 if (obj->ring != ring && obj->last_write_seqno) {
2025 /* Keep the seqno relative to the current ring */
2026 obj->last_write_seqno = seqno;
2030 /* Add a reference if we're newly entering the active list. */
2032 drm_gem_object_reference(&obj->base);
2036 list_move_tail(&obj->ring_list, &ring->active_list);
2038 obj->last_read_seqno = seqno;
2040 if (obj->fenced_gpu_access) {
2041 obj->last_fenced_seqno = seqno;
2043 /* Bump MRU to take account of the delayed flush */
2044 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2045 struct drm_i915_fence_reg *reg;
2047 reg = &dev_priv->fence_regs[obj->fence_reg];
2048 list_move_tail(®->lru_list,
2049 &dev_priv->mm.fence_list);
2054 void i915_vma_move_to_active(struct i915_vma *vma,
2055 struct intel_ring_buffer *ring)
2057 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2058 return i915_gem_object_move_to_active(vma->obj, ring);
2062 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2064 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2065 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2066 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2068 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2069 BUG_ON(!obj->active);
2071 list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
2073 list_del_init(&obj->ring_list);
2076 obj->last_read_seqno = 0;
2077 obj->last_write_seqno = 0;
2078 obj->base.write_domain = 0;
2080 obj->last_fenced_seqno = 0;
2081 obj->fenced_gpu_access = false;
2084 drm_gem_object_unreference(&obj->base);
2086 WARN_ON(i915_verify_lists(dev));
2090 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2092 struct drm_i915_private *dev_priv = dev->dev_private;
2093 struct intel_ring_buffer *ring;
2096 /* Carefully retire all requests without writing to the rings */
2097 for_each_ring(ring, dev_priv, i) {
2098 ret = intel_ring_idle(ring);
2102 i915_gem_retire_requests(dev);
2104 /* Finally reset hw state */
2105 for_each_ring(ring, dev_priv, i) {
2106 intel_ring_init_seqno(ring, seqno);
2108 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2109 ring->sync_seqno[j] = 0;
2115 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2123 /* HWS page needs to be set less than what we
2124 * will inject to ring
2126 ret = i915_gem_init_seqno(dev, seqno - 1);
2130 /* Carefully set the last_seqno value so that wrap
2131 * detection still works
2133 dev_priv->next_seqno = seqno;
2134 dev_priv->last_seqno = seqno - 1;
2135 if (dev_priv->last_seqno == 0)
2136 dev_priv->last_seqno--;
2142 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2144 struct drm_i915_private *dev_priv = dev->dev_private;
2146 /* reserve 0 for non-seqno */
2147 if (dev_priv->next_seqno == 0) {
2148 int ret = i915_gem_init_seqno(dev, 0);
2152 dev_priv->next_seqno = 1;
2155 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2159 int __i915_add_request(struct intel_ring_buffer *ring,
2160 struct drm_file *file,
2161 struct drm_i915_gem_object *obj,
2164 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2165 struct drm_i915_gem_request *request;
2166 u32 request_ring_position, request_start;
2170 request_start = intel_ring_get_tail(ring);
2172 * Emit any outstanding flushes - execbuf can fail to emit the flush
2173 * after having emitted the batchbuffer command. Hence we need to fix
2174 * things up similar to emitting the lazy request. The difference here
2175 * is that the flush _must_ happen before the next request, no matter
2178 ret = intel_ring_flush_all_caches(ring);
2182 request = ring->preallocated_lazy_request;
2183 if (WARN_ON(request == NULL))
2186 /* Record the position of the start of the request so that
2187 * should we detect the updated seqno part-way through the
2188 * GPU processing the request, we never over-estimate the
2189 * position of the head.
2191 request_ring_position = intel_ring_get_tail(ring);
2193 ret = ring->add_request(ring);
2197 request->seqno = intel_ring_get_seqno(ring);
2198 request->ring = ring;
2199 request->head = request_start;
2200 request->tail = request_ring_position;
2202 /* Whilst this request exists, batch_obj will be on the
2203 * active_list, and so will hold the active reference. Only when this
2204 * request is retired will the the batch_obj be moved onto the
2205 * inactive_list and lose its active reference. Hence we do not need
2206 * to explicitly hold another reference here.
2208 request->batch_obj = obj;
2210 /* Hold a reference to the current context so that we can inspect
2211 * it later in case a hangcheck error event fires.
2213 request->ctx = ring->last_context;
2215 i915_gem_context_reference(request->ctx);
2217 request->emitted_jiffies = jiffies;
2218 was_empty = list_empty(&ring->request_list);
2219 list_add_tail(&request->list, &ring->request_list);
2220 request->file_priv = NULL;
2223 struct drm_i915_file_private *file_priv = file->driver_priv;
2225 spin_lock(&file_priv->mm.lock);
2226 request->file_priv = file_priv;
2227 list_add_tail(&request->client_list,
2228 &file_priv->mm.request_list);
2229 spin_unlock(&file_priv->mm.lock);
2232 trace_i915_gem_request_add(ring, request->seqno);
2233 ring->outstanding_lazy_seqno = 0;
2234 ring->preallocated_lazy_request = NULL;
2236 if (!dev_priv->ums.mm_suspended) {
2237 i915_queue_hangcheck(ring->dev);
2240 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2241 queue_delayed_work(dev_priv->wq,
2242 &dev_priv->mm.retire_work,
2243 round_jiffies_up_relative(HZ));
2244 intel_mark_busy(dev_priv->dev);
2249 *out_seqno = request->seqno;
2254 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2256 struct drm_i915_file_private *file_priv = request->file_priv;
2261 spin_lock(&file_priv->mm.lock);
2262 if (request->file_priv) {
2263 list_del(&request->client_list);
2264 request->file_priv = NULL;
2266 spin_unlock(&file_priv->mm.lock);
2269 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
2270 struct i915_address_space *vm)
2272 if (acthd >= i915_gem_obj_offset(obj, vm) &&
2273 acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2279 static bool i915_head_inside_request(const u32 acthd_unmasked,
2280 const u32 request_start,
2281 const u32 request_end)
2283 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2285 if (request_start < request_end) {
2286 if (acthd >= request_start && acthd < request_end)
2288 } else if (request_start > request_end) {
2289 if (acthd >= request_start || acthd < request_end)
2296 static struct i915_address_space *
2297 request_to_vm(struct drm_i915_gem_request *request)
2299 struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
2300 struct i915_address_space *vm;
2302 vm = &dev_priv->gtt.base;
2307 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2308 const u32 acthd, bool *inside)
2310 /* There is a possibility that unmasked head address
2311 * pointing inside the ring, matches the batch_obj address range.
2312 * However this is extremely unlikely.
2314 if (request->batch_obj) {
2315 if (i915_head_inside_object(acthd, request->batch_obj,
2316 request_to_vm(request))) {
2322 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2330 static bool i915_context_is_banned(const struct i915_ctx_hang_stats *hs)
2332 const unsigned long elapsed = get_seconds() - hs->guilty_ts;
2337 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2338 DRM_ERROR("context hanging too fast, declaring banned!\n");
2345 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2346 struct drm_i915_gem_request *request,
2349 struct i915_ctx_hang_stats *hs = NULL;
2350 bool inside, guilty;
2351 unsigned long offset = 0;
2353 /* Innocent until proven guilty */
2356 if (request->batch_obj)
2357 offset = i915_gem_obj_offset(request->batch_obj,
2358 request_to_vm(request));
2360 if (ring->hangcheck.action != HANGCHECK_WAIT &&
2361 i915_request_guilty(request, acthd, &inside)) {
2362 DRM_DEBUG("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2364 inside ? "inside" : "flushing",
2366 request->ctx ? request->ctx->id : 0,
2372 /* If contexts are disabled or this is the default context, use
2373 * file_priv->reset_state
2375 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2376 hs = &request->ctx->hang_stats;
2377 else if (request->file_priv)
2378 hs = &request->file_priv->hang_stats;
2382 hs->banned = i915_context_is_banned(hs);
2384 hs->guilty_ts = get_seconds();
2386 hs->batch_pending++;
2391 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2393 list_del(&request->list);
2394 i915_gem_request_remove_from_client(request);
2397 i915_gem_context_unreference(request->ctx);
2402 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2403 struct intel_ring_buffer *ring)
2405 u32 completed_seqno = ring->get_seqno(ring, false);
2406 u32 acthd = intel_ring_get_active_head(ring);
2407 struct drm_i915_gem_request *request;
2409 list_for_each_entry(request, &ring->request_list, list) {
2410 if (i915_seqno_passed(completed_seqno, request->seqno))
2413 i915_set_reset_status(ring, request, acthd);
2417 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2418 struct intel_ring_buffer *ring)
2420 while (!list_empty(&ring->active_list)) {
2421 struct drm_i915_gem_object *obj;
2423 obj = list_first_entry(&ring->active_list,
2424 struct drm_i915_gem_object,
2427 i915_gem_object_move_to_inactive(obj);
2431 * We must free the requests after all the corresponding objects have
2432 * been moved off active lists. Which is the same order as the normal
2433 * retire_requests function does. This is important if object hold
2434 * implicit references on things like e.g. ppgtt address spaces through
2437 while (!list_empty(&ring->request_list)) {
2438 struct drm_i915_gem_request *request;
2440 request = list_first_entry(&ring->request_list,
2441 struct drm_i915_gem_request,
2444 i915_gem_free_request(request);
2448 void i915_gem_restore_fences(struct drm_device *dev)
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2453 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2454 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2457 * Commit delayed tiling changes if we have an object still
2458 * attached to the fence, otherwise just clear the fence.
2461 i915_gem_object_update_fence(reg->obj, reg,
2462 reg->obj->tiling_mode);
2464 i915_gem_write_fence(dev, i, NULL);
2469 void i915_gem_reset(struct drm_device *dev)
2471 struct drm_i915_private *dev_priv = dev->dev_private;
2472 struct intel_ring_buffer *ring;
2476 * Before we free the objects from the requests, we need to inspect
2477 * them for finding the guilty party. As the requests only borrow
2478 * their reference to the objects, the inspection must be done first.
2480 for_each_ring(ring, dev_priv, i)
2481 i915_gem_reset_ring_status(dev_priv, ring);
2483 for_each_ring(ring, dev_priv, i)
2484 i915_gem_reset_ring_cleanup(dev_priv, ring);
2486 i915_gem_cleanup_ringbuffer(dev);
2488 i915_gem_restore_fences(dev);
2492 * This function clears the request list as sequence numbers are passed.
2495 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2499 if (list_empty(&ring->request_list))
2502 WARN_ON(i915_verify_lists(ring->dev));
2504 seqno = ring->get_seqno(ring, true);
2506 while (!list_empty(&ring->request_list)) {
2507 struct drm_i915_gem_request *request;
2509 request = list_first_entry(&ring->request_list,
2510 struct drm_i915_gem_request,
2513 if (!i915_seqno_passed(seqno, request->seqno))
2516 trace_i915_gem_request_retire(ring, request->seqno);
2517 /* We know the GPU must have read the request to have
2518 * sent us the seqno + interrupt, so use the position
2519 * of tail of the request to update the last known position
2522 ring->last_retired_head = request->tail;
2524 i915_gem_free_request(request);
2527 /* Move any buffers on the active list that are no longer referenced
2528 * by the ringbuffer to the flushing/inactive lists as appropriate.
2530 while (!list_empty(&ring->active_list)) {
2531 struct drm_i915_gem_object *obj;
2533 obj = list_first_entry(&ring->active_list,
2534 struct drm_i915_gem_object,
2537 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2540 i915_gem_object_move_to_inactive(obj);
2543 if (unlikely(ring->trace_irq_seqno &&
2544 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2545 ring->irq_put(ring);
2546 ring->trace_irq_seqno = 0;
2549 WARN_ON(i915_verify_lists(ring->dev));
2553 i915_gem_retire_requests(struct drm_device *dev)
2555 drm_i915_private_t *dev_priv = dev->dev_private;
2556 struct intel_ring_buffer *ring;
2560 for_each_ring(ring, dev_priv, i) {
2561 i915_gem_retire_requests_ring(ring);
2562 idle &= list_empty(&ring->request_list);
2569 i915_gem_retire_work_handler(struct work_struct *work)
2571 drm_i915_private_t *dev_priv;
2572 struct drm_device *dev;
2573 struct intel_ring_buffer *ring;
2577 dev_priv = container_of(work, drm_i915_private_t,
2578 mm.retire_work.work);
2579 dev = dev_priv->dev;
2581 /* Come back later if the device is busy... */
2582 if (lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_NOWAIT)) {
2583 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2584 round_jiffies_up_relative(HZ));
2588 i915_gem_retire_requests(dev);
2590 /* Send a periodic flush down the ring so we don't hold onto GEM
2591 * objects indefinitely.
2594 for_each_ring(ring, dev_priv, i) {
2595 if (ring->gpu_caches_dirty)
2596 i915_add_request(ring, NULL);
2598 idle &= list_empty(&ring->request_list);
2601 if (!dev_priv->ums.mm_suspended && !idle)
2602 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2603 round_jiffies_up_relative(HZ));
2605 intel_mark_idle(dev);
2607 mutex_unlock(&dev->struct_mutex);
2611 i915_gem_idle_work_handler(struct work_struct *work)
2613 struct drm_i915_private *dev_priv =
2614 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2616 intel_mark_idle(dev_priv->dev);
2620 * Ensures that an object will eventually get non-busy by flushing any required
2621 * write domains, emitting any outstanding lazy request and retiring and
2622 * completed requests.
2625 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2630 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2634 i915_gem_retire_requests_ring(obj->ring);
2641 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2642 * @DRM_IOCTL_ARGS: standard ioctl arguments
2644 * Returns 0 if successful, else an error is returned with the remaining time in
2645 * the timeout parameter.
2646 * -ETIME: object is still busy after timeout
2647 * -ERESTARTSYS: signal interrupted the wait
2648 * -ENONENT: object doesn't exist
2649 * Also possible, but rare:
2650 * -EAGAIN: GPU wedged
2652 * -ENODEV: Internal IRQ fail
2653 * -E?: The add request failed
2655 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2656 * non-zero timeout parameter the wait ioctl will wait for the given number of
2657 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2658 * without holding struct_mutex the object may become re-busied before this
2659 * function completes. A similar but shorter * race condition exists in the busy
2663 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2665 drm_i915_private_t *dev_priv = dev->dev_private;
2666 struct drm_i915_gem_wait *args = data;
2667 struct drm_i915_gem_object *obj;
2668 struct intel_ring_buffer *ring = NULL;
2669 struct timespec timeout_stack, *timeout = NULL;
2670 unsigned reset_counter;
2674 if (args->timeout_ns >= 0) {
2675 timeout_stack = ns_to_timespec(args->timeout_ns);
2676 timeout = &timeout_stack;
2679 ret = i915_mutex_lock_interruptible(dev);
2683 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2684 if (&obj->base == NULL) {
2685 mutex_unlock(&dev->struct_mutex);
2689 /* Need to make sure the object gets inactive eventually. */
2690 ret = i915_gem_object_flush_active(obj);
2695 seqno = obj->last_read_seqno;
2702 /* Do this after OLR check to make sure we make forward progress polling
2703 * on this IOCTL with a 0 timeout (like busy ioctl)
2705 if (!args->timeout_ns) {
2710 drm_gem_object_unreference(&obj->base);
2711 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2712 mutex_unlock(&dev->struct_mutex);
2714 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2716 args->timeout_ns = timespec_to_ns(timeout);
2720 drm_gem_object_unreference(&obj->base);
2721 mutex_unlock(&dev->struct_mutex);
2726 * i915_gem_object_sync - sync an object to a ring.
2728 * @obj: object which may be in use on another ring.
2729 * @to: ring we wish to use the object on. May be NULL.
2731 * This code is meant to abstract object synchronization with the GPU.
2732 * Calling with NULL implies synchronizing the object with the CPU
2733 * rather than a particular GPU ring.
2735 * Returns 0 if successful, else propagates up the lower layer error.
2738 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2739 struct intel_ring_buffer *to)
2741 struct intel_ring_buffer *from = obj->ring;
2745 if (from == NULL || to == from)
2748 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2749 return i915_gem_object_wait_rendering(obj, false);
2751 idx = intel_ring_sync_index(from, to);
2753 seqno = obj->last_read_seqno;
2754 if (seqno <= from->sync_seqno[idx])
2757 ret = i915_gem_check_olr(obj->ring, seqno);
2761 trace_i915_gem_ring_sync_to(from, to, seqno);
2762 ret = to->sync_to(to, from, seqno);
2764 /* We use last_read_seqno because sync_to()
2765 * might have just caused seqno wrap under
2768 from->sync_seqno[idx] = obj->last_read_seqno;
2773 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2775 u32 old_write_domain, old_read_domains;
2777 /* Force a pagefault for domain tracking on next user access */
2778 i915_gem_release_mmap(obj);
2780 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2783 /* Wait for any direct GTT access to complete */
2786 old_read_domains = obj->base.read_domains;
2787 old_write_domain = obj->base.write_domain;
2789 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2790 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2792 trace_i915_gem_object_change_domain(obj,
2797 int i915_vma_unbind(struct i915_vma *vma)
2799 struct drm_i915_gem_object *obj = vma->obj;
2800 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2803 /* For now we only ever use 1 vma per object */
2805 WARN_ON(!list_is_singular(&obj->vma_list));
2808 if (list_empty(&vma->vma_link))
2811 if (!drm_mm_node_allocated(&vma->node)) {
2812 i915_gem_vma_destroy(vma);
2820 BUG_ON(obj->pages == NULL);
2822 ret = i915_gem_object_finish_gpu(obj);
2825 /* Continue on if we fail due to EIO, the GPU is hung so we
2826 * should be safe and we need to cleanup or else we might
2827 * cause memory corruption through use-after-free.
2830 i915_gem_object_finish_gtt(obj);
2832 /* release the fence reg _after_ flushing */
2833 ret = i915_gem_object_put_fence(obj);
2837 trace_i915_vma_unbind(vma);
2839 if (obj->has_global_gtt_mapping)
2840 i915_gem_gtt_unbind_object(obj);
2841 if (obj->has_aliasing_ppgtt_mapping) {
2842 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2843 obj->has_aliasing_ppgtt_mapping = 0;
2845 i915_gem_gtt_finish_object(obj);
2847 list_del(&vma->mm_list);
2848 /* Avoid an unnecessary call to unbind on rebind. */
2849 if (i915_is_ggtt(vma->vm))
2850 obj->map_and_fenceable = true;
2852 drm_mm_remove_node(&vma->node);
2853 i915_gem_vma_destroy(vma);
2855 /* Since the unbound list is global, only move to that list if
2856 * no more VMAs exist. */
2857 if (list_empty(&obj->vma_list))
2858 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2860 /* And finally now the object is completely decoupled from this vma,
2861 * we can drop its hold on the backing storage and allow it to be
2862 * reaped by the shrinker.
2864 i915_gem_object_unpin_pages(obj);
2870 * Unbinds an object from the global GTT aperture.
2873 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2875 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2876 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2878 if (!i915_gem_obj_ggtt_bound(obj))
2884 BUG_ON(obj->pages == NULL);
2886 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2889 int i915_gpu_idle(struct drm_device *dev)
2891 drm_i915_private_t *dev_priv = dev->dev_private;
2892 struct intel_ring_buffer *ring;
2895 /* Flush everything onto the inactive list. */
2896 for_each_ring(ring, dev_priv, i) {
2897 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2901 ret = intel_ring_idle(ring);
2909 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2910 struct drm_i915_gem_object *obj)
2912 drm_i915_private_t *dev_priv = dev->dev_private;
2914 int fence_pitch_shift;
2916 if (INTEL_INFO(dev)->gen >= 6) {
2917 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2918 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2920 fence_reg = FENCE_REG_965_0;
2921 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2924 fence_reg += reg * 8;
2926 /* To w/a incoherency with non-atomic 64-bit register updates,
2927 * we split the 64-bit update into two 32-bit writes. In order
2928 * for a partial fence not to be evaluated between writes, we
2929 * precede the update with write to turn off the fence register,
2930 * and only enable the fence as the last step.
2932 * For extra levels of paranoia, we make sure each step lands
2933 * before applying the next step.
2935 I915_WRITE(fence_reg, 0);
2936 POSTING_READ(fence_reg);
2939 u32 size = i915_gem_obj_ggtt_size(obj);
2942 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2944 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2945 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2946 if (obj->tiling_mode == I915_TILING_Y)
2947 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2948 val |= I965_FENCE_REG_VALID;
2950 I915_WRITE(fence_reg + 4, val >> 32);
2951 POSTING_READ(fence_reg + 4);
2953 I915_WRITE(fence_reg + 0, val);
2954 POSTING_READ(fence_reg);
2956 I915_WRITE(fence_reg + 4, 0);
2957 POSTING_READ(fence_reg + 4);
2961 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2962 struct drm_i915_gem_object *obj)
2964 drm_i915_private_t *dev_priv = dev->dev_private;
2968 u32 size = i915_gem_obj_ggtt_size(obj);
2972 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2973 (size & -size) != size ||
2974 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2975 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2976 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2978 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2983 /* Note: pitch better be a power of two tile widths */
2984 pitch_val = obj->stride / tile_width;
2985 pitch_val = ffs(pitch_val) - 1;
2987 val = i915_gem_obj_ggtt_offset(obj);
2988 if (obj->tiling_mode == I915_TILING_Y)
2989 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2990 val |= I915_FENCE_SIZE_BITS(size);
2991 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2992 val |= I830_FENCE_REG_VALID;
2997 reg = FENCE_REG_830_0 + reg * 4;
2999 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3001 I915_WRITE(reg, val);
3005 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3006 struct drm_i915_gem_object *obj)
3008 drm_i915_private_t *dev_priv = dev->dev_private;
3012 u32 size = i915_gem_obj_ggtt_size(obj);
3015 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3016 (size & -size) != size ||
3017 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3018 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3019 i915_gem_obj_ggtt_offset(obj), size);
3021 pitch_val = obj->stride / 128;
3022 pitch_val = ffs(pitch_val) - 1;
3024 val = i915_gem_obj_ggtt_offset(obj);
3025 if (obj->tiling_mode == I915_TILING_Y)
3026 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3027 val |= I830_FENCE_SIZE_BITS(size);
3028 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3029 val |= I830_FENCE_REG_VALID;
3033 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3034 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3037 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3039 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3042 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3043 struct drm_i915_gem_object *obj)
3045 struct drm_i915_private *dev_priv = dev->dev_private;
3047 /* Ensure that all CPU reads are completed before installing a fence
3048 * and all writes before removing the fence.
3050 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3053 WARN(obj && (!obj->stride || !obj->tiling_mode),
3054 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3055 obj->stride, obj->tiling_mode);
3057 switch (INTEL_INFO(dev)->gen) {
3062 case 4: i965_write_fence_reg(dev, reg, obj); break;
3063 case 3: i915_write_fence_reg(dev, reg, obj); break;
3064 case 2: i830_write_fence_reg(dev, reg, obj); break;
3068 /* And similarly be paranoid that no direct access to this region
3069 * is reordered to before the fence is installed.
3071 if (i915_gem_object_needs_mb(obj))
3075 static inline int fence_number(struct drm_i915_private *dev_priv,
3076 struct drm_i915_fence_reg *fence)
3078 return fence - dev_priv->fence_regs;
3081 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3082 struct drm_i915_fence_reg *fence,
3085 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3086 int reg = fence_number(dev_priv, fence);
3088 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3091 obj->fence_reg = reg;
3093 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3095 obj->fence_reg = I915_FENCE_REG_NONE;
3097 list_del_init(&fence->lru_list);
3099 obj->fence_dirty = false;
3103 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3105 if (obj->last_fenced_seqno) {
3106 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3110 obj->last_fenced_seqno = 0;
3113 obj->fenced_gpu_access = false;
3118 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3120 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3121 struct drm_i915_fence_reg *fence;
3124 ret = i915_gem_object_wait_fence(obj);
3128 if (obj->fence_reg == I915_FENCE_REG_NONE)
3131 fence = &dev_priv->fence_regs[obj->fence_reg];
3133 i915_gem_object_fence_lost(obj);
3134 i915_gem_object_update_fence(obj, fence, false);
3139 static struct drm_i915_fence_reg *
3140 i915_find_fence_reg(struct drm_device *dev)
3142 struct drm_i915_private *dev_priv = dev->dev_private;
3143 struct drm_i915_fence_reg *reg, *avail;
3146 /* First try to find a free reg */
3148 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3149 reg = &dev_priv->fence_regs[i];
3153 if (!reg->pin_count)
3160 /* None available, try to steal one or wait for a user to finish */
3161 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3169 /* Wait for completion of pending flips which consume fences */
3170 if (intel_has_pending_fb_unpin(dev))
3171 return ERR_PTR(-EAGAIN);
3173 return ERR_PTR(-EDEADLK);
3177 * i915_gem_object_get_fence - set up fencing for an object
3178 * @obj: object to map through a fence reg
3180 * When mapping objects through the GTT, userspace wants to be able to write
3181 * to them without having to worry about swizzling if the object is tiled.
3182 * This function walks the fence regs looking for a free one for @obj,
3183 * stealing one if it can't find any.
3185 * It then sets up the reg based on the object's properties: address, pitch
3186 * and tiling format.
3188 * For an untiled surface, this removes any existing fence.
3191 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3193 struct drm_device *dev = obj->base.dev;
3194 struct drm_i915_private *dev_priv = dev->dev_private;
3195 bool enable = obj->tiling_mode != I915_TILING_NONE;
3196 struct drm_i915_fence_reg *reg;
3199 /* Have we updated the tiling parameters upon the object and so
3200 * will need to serialise the write to the associated fence register?
3202 if (obj->fence_dirty) {
3203 ret = i915_gem_object_wait_fence(obj);
3208 /* Just update our place in the LRU if our fence is getting reused. */
3209 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3210 reg = &dev_priv->fence_regs[obj->fence_reg];
3211 if (!obj->fence_dirty) {
3212 list_move_tail(®->lru_list,
3213 &dev_priv->mm.fence_list);
3216 } else if (enable) {
3217 reg = i915_find_fence_reg(dev);
3219 return PTR_ERR(reg);
3222 struct drm_i915_gem_object *old = reg->obj;
3224 ret = i915_gem_object_wait_fence(old);
3228 i915_gem_object_fence_lost(old);
3233 i915_gem_object_update_fence(obj, reg, enable);
3238 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3239 struct drm_mm_node *gtt_space,
3240 unsigned long cache_level)
3242 struct drm_mm_node *other;
3244 /* On non-LLC machines we have to be careful when putting differing
3245 * types of snoopable memory together to avoid the prefetcher
3246 * crossing memory domains and dying.
3251 if (!drm_mm_node_allocated(gtt_space))
3254 if (list_empty(>t_space->node_list))
3257 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3258 if (other->allocated && !other->hole_follows && other->color != cache_level)
3261 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3262 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3268 static void i915_gem_verify_gtt(struct drm_device *dev)
3271 struct drm_i915_private *dev_priv = dev->dev_private;
3272 struct drm_i915_gem_object *obj;
3275 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3276 if (obj->gtt_space == NULL) {
3277 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3282 if (obj->cache_level != obj->gtt_space->color) {
3283 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3284 i915_gem_obj_ggtt_offset(obj),
3285 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3287 obj->gtt_space->color);
3292 if (!i915_gem_valid_gtt_space(dev,
3294 obj->cache_level)) {
3295 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3296 i915_gem_obj_ggtt_offset(obj),
3297 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3309 * Finds free space in the GTT aperture and binds the object there.
3312 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3313 struct i915_address_space *vm,
3315 bool map_and_fenceable,
3318 struct drm_device *dev = obj->base.dev;
3319 drm_i915_private_t *dev_priv = dev->dev_private;
3320 u32 size, fence_size, fence_alignment, unfenced_alignment;
3322 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3323 struct i915_vma *vma;
3326 fence_size = i915_gem_get_gtt_size(dev,
3329 fence_alignment = i915_gem_get_gtt_alignment(dev,
3331 obj->tiling_mode, true);
3332 unfenced_alignment =
3333 i915_gem_get_gtt_alignment(dev,
3335 obj->tiling_mode, false);
3338 alignment = map_and_fenceable ? fence_alignment :
3340 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3341 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3345 size = map_and_fenceable ? fence_size : obj->base.size;
3347 /* If the object is bigger than the entire aperture, reject it early
3348 * before evicting everything in a vain attempt to find space.
3350 if (obj->base.size > gtt_max) {
3351 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3353 map_and_fenceable ? "mappable" : "total",
3358 ret = i915_gem_object_get_pages(obj);
3362 i915_gem_object_pin_pages(obj);
3364 BUG_ON(!i915_is_ggtt(vm));
3366 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3372 /* For now we only ever use 1 vma per object */
3374 WARN_ON(!list_is_singular(&obj->vma_list));
3378 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3380 obj->cache_level, 0, gtt_max,
3381 DRM_MM_SEARCH_DEFAULT);
3383 ret = i915_gem_evict_something(dev, vm, size, alignment,
3392 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3393 obj->cache_level))) {
3395 goto err_remove_node;
3398 ret = i915_gem_gtt_prepare_object(obj);
3400 goto err_remove_node;
3402 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3403 list_add_tail(&vma->mm_list, &vm->inactive_list);
3405 if (i915_is_ggtt(vm)) {
3406 bool mappable, fenceable;
3408 fenceable = (vma->node.size == fence_size &&
3409 (vma->node.start & (fence_alignment - 1)) == 0);
3411 mappable = (vma->node.start + obj->base.size <=
3412 dev_priv->gtt.mappable_end);
3414 obj->map_and_fenceable = mappable && fenceable;
3417 WARN_ON(map_and_fenceable && !obj->map_and_fenceable);
3419 trace_i915_vma_bind(vma, map_and_fenceable);
3420 i915_gem_verify_gtt(dev);
3424 drm_mm_remove_node(&vma->node);
3426 i915_gem_vma_destroy(vma);
3428 i915_gem_object_unpin_pages(obj);
3433 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3436 /* If we don't have a page list set up, then we're not pinned
3437 * to GPU, and we can ignore the cache flush because it'll happen
3438 * again at bind time.
3440 if (obj->pages == NULL)
3444 * Stolen memory is always coherent with the GPU as it is explicitly
3445 * marked as wc by the system, or the system is cache-coherent.
3450 /* If the GPU is snooping the contents of the CPU cache,
3451 * we do not need to manually clear the CPU cache lines. However,
3452 * the caches are only snooped when the render cache is
3453 * flushed/invalidated. As we always have to emit invalidations
3454 * and flushes when moving into and out of the RENDER domain, correct
3455 * snooping behaviour occurs naturally as the result of our domain
3458 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3461 trace_i915_gem_object_clflush(obj);
3462 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
3467 /** Flushes the GTT write domain for the object if it's dirty. */
3469 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3471 uint32_t old_write_domain;
3473 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3476 /* No actual flushing is required for the GTT write domain. Writes
3477 * to it immediately go to main memory as far as we know, so there's
3478 * no chipset flush. It also doesn't land in render cache.
3480 * However, we do have to enforce the order so that all writes through
3481 * the GTT land before any writes to the device, such as updates to
3486 old_write_domain = obj->base.write_domain;
3487 obj->base.write_domain = 0;
3489 trace_i915_gem_object_change_domain(obj,
3490 obj->base.read_domains,
3494 /** Flushes the CPU write domain for the object if it's dirty. */
3496 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3499 uint32_t old_write_domain;
3501 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3504 if (i915_gem_clflush_object(obj, force))
3505 i915_gem_chipset_flush(obj->base.dev);
3507 old_write_domain = obj->base.write_domain;
3508 obj->base.write_domain = 0;
3510 trace_i915_gem_object_change_domain(obj,
3511 obj->base.read_domains,
3516 * Moves a single object to the GTT read, and possibly write domain.
3518 * This function returns when the move is complete, including waiting on
3522 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3524 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3525 uint32_t old_write_domain, old_read_domains;
3528 /* Not valid to be called on unbound objects. */
3529 if (!i915_gem_obj_bound_any(obj))
3532 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3535 ret = i915_gem_object_wait_rendering(obj, !write);
3539 i915_gem_object_flush_cpu_write_domain(obj, false);
3541 /* Serialise direct access to this object with the barriers for
3542 * coherent writes from the GPU, by effectively invalidating the
3543 * GTT domain upon first access.
3545 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3548 old_write_domain = obj->base.write_domain;
3549 old_read_domains = obj->base.read_domains;
3551 /* It should now be out of any other write domains, and we can update
3552 * the domain values for our changes.
3554 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3555 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3557 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3558 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3562 trace_i915_gem_object_change_domain(obj,
3566 /* And bump the LRU for this access */
3567 if (i915_gem_object_is_inactive(obj)) {
3568 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3570 list_move_tail(&vma->mm_list,
3571 &dev_priv->gtt.base.inactive_list);
3578 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3579 enum i915_cache_level cache_level)
3581 struct drm_device *dev = obj->base.dev;
3582 drm_i915_private_t *dev_priv = dev->dev_private;
3583 struct i915_vma *vma;
3586 if (obj->cache_level == cache_level)
3589 if (obj->pin_count) {
3590 DRM_DEBUG("can not change the cache level of pinned objects\n");
3594 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3595 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3596 ret = i915_vma_unbind(vma);
3604 if (i915_gem_obj_bound_any(obj)) {
3605 ret = i915_gem_object_finish_gpu(obj);
3609 i915_gem_object_finish_gtt(obj);
3611 /* Before SandyBridge, you could not use tiling or fence
3612 * registers with snooped memory, so relinquish any fences
3613 * currently pointing to our region in the aperture.
3615 if (INTEL_INFO(dev)->gen < 6) {
3616 ret = i915_gem_object_put_fence(obj);
3621 if (obj->has_global_gtt_mapping)
3622 i915_gem_gtt_bind_object(obj, cache_level);
3623 if (obj->has_aliasing_ppgtt_mapping)
3624 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3628 list_for_each_entry(vma, &obj->vma_list, vma_link)
3629 vma->node.color = cache_level;
3630 obj->cache_level = cache_level;
3632 if (cpu_write_needs_clflush(obj)) {
3633 u32 old_read_domains, old_write_domain;
3635 /* If we're coming from LLC cached, then we haven't
3636 * actually been tracking whether the data is in the
3637 * CPU cache or not, since we only allow one bit set
3638 * in obj->write_domain and have been skipping the clflushes.
3639 * Just set it to the CPU cache for now.
3641 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3643 old_read_domains = obj->base.read_domains;
3644 old_write_domain = obj->base.write_domain;
3646 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3647 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3649 trace_i915_gem_object_change_domain(obj,
3654 i915_gem_verify_gtt(dev);
3658 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3659 struct drm_file *file)
3661 struct drm_i915_gem_caching *args = data;
3662 struct drm_i915_gem_object *obj;
3665 ret = i915_mutex_lock_interruptible(dev);
3669 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3670 if (&obj->base == NULL) {
3675 switch (obj->cache_level) {
3676 case I915_CACHE_LLC:
3677 case I915_CACHE_L3_LLC:
3678 args->caching = I915_CACHING_CACHED;
3682 args->caching = I915_CACHING_DISPLAY;
3686 args->caching = I915_CACHING_NONE;
3690 drm_gem_object_unreference(&obj->base);
3692 mutex_unlock(&dev->struct_mutex);
3696 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3697 struct drm_file *file)
3699 struct drm_i915_gem_caching *args = data;
3700 struct drm_i915_gem_object *obj;
3701 enum i915_cache_level level;
3704 switch (args->caching) {
3705 case I915_CACHING_NONE:
3706 level = I915_CACHE_NONE;
3708 case I915_CACHING_CACHED:
3709 level = I915_CACHE_LLC;
3711 case I915_CACHING_DISPLAY:
3712 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3718 ret = i915_mutex_lock_interruptible(dev);
3722 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3723 if (&obj->base == NULL) {
3728 ret = i915_gem_object_set_cache_level(obj, level);
3730 drm_gem_object_unreference(&obj->base);
3732 mutex_unlock(&dev->struct_mutex);
3736 static bool is_pin_display(struct drm_i915_gem_object *obj)
3738 /* There are 3 sources that pin objects:
3739 * 1. The display engine (scanouts, sprites, cursors);
3740 * 2. Reservations for execbuffer;
3743 * We can ignore reservations as we hold the struct_mutex and
3744 * are only called outside of the reservation path. The user
3745 * can only increment pin_count once, and so if after
3746 * subtracting the potential reference by the user, any pin_count
3747 * remains, it must be due to another use by the display engine.
3749 return obj->pin_count - !!obj->user_pin_count;
3753 * Prepare buffer for display plane (scanout, cursors, etc).
3754 * Can be called from an uninterruptible phase (modesetting) and allows
3755 * any flushes to be pipelined (for pageflips).
3758 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3760 struct intel_ring_buffer *pipelined)
3762 u32 old_read_domains, old_write_domain;
3765 if (pipelined != obj->ring) {
3766 ret = i915_gem_object_sync(obj, pipelined);
3771 /* Mark the pin_display early so that we account for the
3772 * display coherency whilst setting up the cache domains.
3774 obj->pin_display = true;
3776 /* The display engine is not coherent with the LLC cache on gen6. As
3777 * a result, we make sure that the pinning that is about to occur is
3778 * done with uncached PTEs. This is lowest common denominator for all
3781 * However for gen6+, we could do better by using the GFDT bit instead
3782 * of uncaching, which would allow us to flush all the LLC-cached data
3783 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3785 ret = i915_gem_object_set_cache_level(obj,
3786 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3788 goto err_unpin_display;
3790 /* As the user may map the buffer once pinned in the display plane
3791 * (e.g. libkms for the bootup splash), we have to ensure that we
3792 * always use map_and_fenceable for all scanout buffers.
3794 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3796 goto err_unpin_display;
3798 i915_gem_object_flush_cpu_write_domain(obj, true);
3800 old_write_domain = obj->base.write_domain;
3801 old_read_domains = obj->base.read_domains;
3803 /* It should now be out of any other write domains, and we can update
3804 * the domain values for our changes.
3806 obj->base.write_domain = 0;
3807 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3809 trace_i915_gem_object_change_domain(obj,
3816 obj->pin_display = is_pin_display(obj);
3821 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3823 i915_gem_object_unpin(obj);
3824 obj->pin_display = is_pin_display(obj);
3828 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3832 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3835 ret = i915_gem_object_wait_rendering(obj, false);
3839 /* Ensure that we invalidate the GPU's caches and TLBs. */
3840 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3845 * Moves a single object to the CPU read, and possibly write domain.
3847 * This function returns when the move is complete, including waiting on
3851 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3853 uint32_t old_write_domain, old_read_domains;
3856 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3859 ret = i915_gem_object_wait_rendering(obj, !write);
3863 i915_gem_object_flush_gtt_write_domain(obj);
3865 old_write_domain = obj->base.write_domain;
3866 old_read_domains = obj->base.read_domains;
3868 /* Flush the CPU cache if it's still invalid. */
3869 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3870 i915_gem_clflush_object(obj, false);
3872 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3875 /* It should now be out of any other write domains, and we can update
3876 * the domain values for our changes.
3878 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3880 /* If we're writing through the CPU, then the GPU read domains will
3881 * need to be invalidated at next use.
3884 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3885 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3888 trace_i915_gem_object_change_domain(obj,
3895 /* Throttle our rendering by waiting until the ring has completed our requests
3896 * emitted over 20 msec ago.
3898 * Note that if we were to use the current jiffies each time around the loop,
3899 * we wouldn't escape the function with any frames outstanding if the time to
3900 * render a frame was over 20ms.
3902 * This should get us reasonable parallelism between CPU and GPU but also
3903 * relatively low latency when blocking on a particular request to finish.
3906 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3908 struct drm_i915_private *dev_priv = dev->dev_private;
3909 struct drm_i915_file_private *file_priv = file->driver_priv;
3910 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3911 struct drm_i915_gem_request *request;
3912 struct intel_ring_buffer *ring = NULL;
3913 unsigned reset_counter;
3917 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3921 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3925 spin_lock(&file_priv->mm.lock);
3926 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3927 if (time_after_eq(request->emitted_jiffies, recent_enough))
3930 ring = request->ring;
3931 seqno = request->seqno;
3933 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3934 spin_unlock(&file_priv->mm.lock);
3939 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3941 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3947 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3948 struct i915_address_space *vm,
3950 bool map_and_fenceable,
3953 struct i915_vma *vma;
3956 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3959 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3961 vma = i915_gem_obj_to_vma(obj, vm);
3965 vma->node.start & (alignment - 1)) ||
3966 (map_and_fenceable && !obj->map_and_fenceable)) {
3967 WARN(obj->pin_count,
3968 "bo is already pinned with incorrect alignment:"
3969 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3970 " obj->map_and_fenceable=%d\n",
3971 i915_gem_obj_offset(obj, vm), alignment,
3973 obj->map_and_fenceable);
3974 ret = i915_vma_unbind(vma);
3980 if (!i915_gem_obj_bound(obj, vm)) {
3981 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3983 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3989 if (!dev_priv->mm.aliasing_ppgtt)
3990 i915_gem_gtt_bind_object(obj, obj->cache_level);
3993 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3994 i915_gem_gtt_bind_object(obj, obj->cache_level);
3997 obj->pin_mappable |= map_and_fenceable;
4003 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
4005 BUG_ON(obj->pin_count == 0);
4006 BUG_ON(!i915_gem_obj_bound_any(obj));
4008 if (--obj->pin_count == 0)
4009 obj->pin_mappable = false;
4013 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4014 struct drm_file *file)
4016 struct drm_i915_gem_pin *args = data;
4017 struct drm_i915_gem_object *obj;
4020 ret = i915_mutex_lock_interruptible(dev);
4024 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4025 if (&obj->base == NULL) {
4030 if (obj->madv != I915_MADV_WILLNEED) {
4031 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4036 if (obj->pin_filp != NULL && obj->pin_filp != file) {
4037 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4043 if (obj->user_pin_count == ULONG_MAX) {
4048 if (obj->user_pin_count == 0) {
4049 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
4054 obj->user_pin_count++;
4055 obj->pin_filp = file;
4057 args->offset = i915_gem_obj_ggtt_offset(obj);
4059 drm_gem_object_unreference(&obj->base);
4061 mutex_unlock(&dev->struct_mutex);
4066 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4067 struct drm_file *file)
4069 struct drm_i915_gem_pin *args = data;
4070 struct drm_i915_gem_object *obj;
4073 ret = i915_mutex_lock_interruptible(dev);
4077 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4078 if (&obj->base == NULL) {
4083 if (obj->pin_filp != file) {
4084 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4089 obj->user_pin_count--;
4090 if (obj->user_pin_count == 0) {
4091 obj->pin_filp = NULL;
4092 i915_gem_object_unpin(obj);
4096 drm_gem_object_unreference(&obj->base);
4098 mutex_unlock(&dev->struct_mutex);
4103 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4104 struct drm_file *file)
4106 struct drm_i915_gem_busy *args = data;
4107 struct drm_i915_gem_object *obj;
4110 ret = i915_mutex_lock_interruptible(dev);
4114 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4115 if (&obj->base == NULL) {
4120 /* Count all active objects as busy, even if they are currently not used
4121 * by the gpu. Users of this interface expect objects to eventually
4122 * become non-busy without any further actions, therefore emit any
4123 * necessary flushes here.
4125 ret = i915_gem_object_flush_active(obj);
4127 args->busy = obj->active;
4129 args->busy |= intel_ring_flag(obj->ring) << 16;
4132 drm_gem_object_unreference(&obj->base);
4134 mutex_unlock(&dev->struct_mutex);
4139 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4140 struct drm_file *file_priv)
4142 return i915_gem_ring_throttle(dev, file_priv);
4146 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4147 struct drm_file *file_priv)
4149 struct drm_i915_gem_madvise *args = data;
4150 struct drm_i915_gem_object *obj;
4153 switch (args->madv) {
4154 case I915_MADV_DONTNEED:
4155 case I915_MADV_WILLNEED:
4161 ret = i915_mutex_lock_interruptible(dev);
4165 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4166 if (&obj->base == NULL) {
4171 if (obj->pin_count) {
4176 if (obj->madv != __I915_MADV_PURGED)
4177 obj->madv = args->madv;
4179 /* if the object is no longer attached, discard its backing storage */
4180 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4181 i915_gem_object_truncate(obj);
4183 args->retained = obj->madv != __I915_MADV_PURGED;
4186 drm_gem_object_unreference(&obj->base);
4188 mutex_unlock(&dev->struct_mutex);
4192 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4193 const struct drm_i915_gem_object_ops *ops)
4195 INIT_LIST_HEAD(&obj->global_list);
4196 INIT_LIST_HEAD(&obj->ring_list);
4197 INIT_LIST_HEAD(&obj->obj_exec_link);
4198 INIT_LIST_HEAD(&obj->vma_list);
4202 obj->fence_reg = I915_FENCE_REG_NONE;
4203 obj->madv = I915_MADV_WILLNEED;
4204 /* Avoid an unnecessary call to unbind on the first bind. */
4205 obj->map_and_fenceable = true;
4207 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4210 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4211 .get_pages = i915_gem_object_get_pages_gtt,
4212 .put_pages = i915_gem_object_put_pages_gtt,
4215 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4218 struct drm_i915_gem_object *obj;
4220 struct address_space *mapping;
4224 obj = i915_gem_object_alloc(dev);
4228 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4229 i915_gem_object_free(obj);
4234 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4235 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4236 /* 965gm cannot relocate objects above 4GiB. */
4237 mask &= ~__GFP_HIGHMEM;
4238 mask |= __GFP_DMA32;
4241 mapping = file_inode(obj->base.filp)->i_mapping;
4242 mapping_set_gfp_mask(mapping, mask);
4245 i915_gem_object_init(obj, &i915_gem_object_ops);
4247 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4248 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4251 /* On some devices, we can have the GPU use the LLC (the CPU
4252 * cache) for about a 10% performance improvement
4253 * compared to uncached. Graphics requests other than
4254 * display scanout are coherent with the CPU in
4255 * accessing this cache. This means in this mode we
4256 * don't need to clflush on the CPU side, and on the
4257 * GPU side we only need to flush internal caches to
4258 * get data visible to the CPU.
4260 * However, we maintain the display planes as UC, and so
4261 * need to rebind when first used as such.
4263 obj->cache_level = I915_CACHE_LLC;
4265 obj->cache_level = I915_CACHE_NONE;
4267 trace_i915_gem_object_create(obj);
4272 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4274 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4275 struct drm_device *dev = obj->base.dev;
4276 drm_i915_private_t *dev_priv = dev->dev_private;
4277 struct i915_vma *vma, *next;
4279 intel_runtime_pm_get(dev_priv);
4281 trace_i915_gem_object_destroy(obj);
4284 i915_gem_detach_phys_object(dev, obj);
4287 /* NB: 0 or 1 elements */
4289 WARN_ON(!list_empty(&obj->vma_list) &&
4290 !list_is_singular(&obj->vma_list));
4292 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4293 int ret = i915_vma_unbind(vma);
4294 if (WARN_ON(ret == -ERESTARTSYS)) {
4295 bool was_interruptible;
4297 was_interruptible = dev_priv->mm.interruptible;
4298 dev_priv->mm.interruptible = false;
4300 WARN_ON(i915_vma_unbind(vma));
4302 dev_priv->mm.interruptible = was_interruptible;
4306 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4307 * before progressing. */
4309 i915_gem_object_unpin_pages(obj);
4311 if (WARN_ON(obj->pages_pin_count))
4312 obj->pages_pin_count = 0;
4313 i915_gem_object_put_pages(obj);
4314 i915_gem_object_free_mmap_offset(obj);
4319 if (obj->base.import_attach)
4320 drm_prime_gem_destroy(&obj->base, NULL);
4323 drm_gem_object_release(&obj->base);
4324 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4327 i915_gem_object_free(obj);
4329 intel_runtime_pm_put(dev_priv);
4332 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4333 struct i915_address_space *vm)
4335 struct i915_vma *vma;
4336 list_for_each_entry(vma, &obj->vma_list, vma_link)
4343 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
4344 struct i915_address_space *vm)
4346 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4348 return ERR_PTR(-ENOMEM);
4350 INIT_LIST_HEAD(&vma->vma_link);
4351 INIT_LIST_HEAD(&vma->mm_list);
4352 INIT_LIST_HEAD(&vma->exec_list);
4356 /* Keep GGTT vmas first to make debug easier */
4357 if (i915_is_ggtt(vm))
4358 list_add(&vma->vma_link, &obj->vma_list);
4360 list_add_tail(&vma->vma_link, &obj->vma_list);
4366 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
4367 struct i915_address_space *vm)
4369 struct i915_vma *vma;
4371 vma = i915_gem_obj_to_vma(obj, vm);
4373 vma = __i915_gem_vma_create(obj, vm);
4378 void i915_gem_vma_destroy(struct i915_vma *vma)
4380 WARN_ON(vma->node.allocated);
4382 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4383 if (!list_empty(&vma->exec_list))
4386 list_del(&vma->vma_link);
4392 i915_gem_suspend(struct drm_device *dev)
4394 drm_i915_private_t *dev_priv = dev->dev_private;
4397 mutex_lock(&dev->struct_mutex);
4398 if (dev_priv->ums.mm_suspended)
4401 ret = i915_gpu_idle(dev);
4405 i915_gem_retire_requests(dev);
4407 /* Under UMS, be paranoid and evict. */
4408 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4409 i915_gem_evict_everything(dev);
4411 i915_kernel_lost_context(dev);
4412 i915_gem_cleanup_ringbuffer(dev);
4414 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4415 * We need to replace this with a semaphore, or something.
4416 * And not confound ums.mm_suspended!
4418 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4420 mutex_unlock(&dev->struct_mutex);
4422 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4423 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4424 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4429 mutex_unlock(&dev->struct_mutex);
4433 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice)
4435 struct drm_device *dev = ring->dev;
4436 drm_i915_private_t *dev_priv = dev->dev_private;
4437 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4438 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4441 if (!HAS_L3_DPF(dev) || !remap_info)
4444 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4449 * Note: We do not worry about the concurrent register cacheline hang
4450 * here because no other code should access these registers other than
4451 * at initialization time.
4453 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4454 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4455 intel_ring_emit(ring, reg_base + i);
4456 intel_ring_emit(ring, remap_info[i/4]);
4459 intel_ring_advance(ring);
4464 void i915_gem_init_swizzling(struct drm_device *dev)
4466 drm_i915_private_t *dev_priv = dev->dev_private;
4468 if (INTEL_INFO(dev)->gen < 5 ||
4469 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4472 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4473 DISP_TILE_SURFACE_SWIZZLING);
4478 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4480 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4481 else if (IS_GEN7(dev))
4482 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4483 else if (IS_GEN8(dev))
4484 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4490 intel_enable_blt(struct drm_device *dev)
4497 /* The blitter was dysfunctional on early prototypes */
4498 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
4499 if (IS_GEN6(dev) && revision < 8) {
4500 DRM_INFO("BLT not supported on this pre-production hardware;"
4501 " graphics performance will be degraded.\n");
4508 static int i915_gem_init_rings(struct drm_device *dev)
4510 struct drm_i915_private *dev_priv = dev->dev_private;
4513 ret = intel_init_render_ring_buffer(dev);
4518 ret = intel_init_bsd_ring_buffer(dev);
4520 goto cleanup_render_ring;
4523 if (intel_enable_blt(dev)) {
4524 ret = intel_init_blt_ring_buffer(dev);
4526 goto cleanup_bsd_ring;
4529 if (HAS_VEBOX(dev)) {
4530 ret = intel_init_vebox_ring_buffer(dev);
4532 goto cleanup_blt_ring;
4536 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4538 goto cleanup_vebox_ring;
4543 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4545 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4547 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4548 cleanup_render_ring:
4549 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4555 i915_gem_init_hw(struct drm_device *dev)
4557 drm_i915_private_t *dev_priv = dev->dev_private;
4561 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4565 if (dev_priv->ellc_size)
4566 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4568 if (IS_HASWELL(dev))
4569 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4570 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4572 if (HAS_PCH_NOP(dev)) {
4573 u32 temp = I915_READ(GEN7_MSG_CTL);
4574 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4575 I915_WRITE(GEN7_MSG_CTL, temp);
4578 i915_gem_init_swizzling(dev);
4580 ret = i915_gem_init_rings(dev);
4584 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4585 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4588 * XXX: There was some w/a described somewhere suggesting loading
4589 * contexts before PPGTT.
4591 ret = i915_gem_context_init(dev);
4593 i915_gem_cleanup_ringbuffer(dev);
4594 DRM_ERROR("Context initialization failed %d\n", ret);
4598 if (dev_priv->mm.aliasing_ppgtt) {
4599 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4601 i915_gem_cleanup_aliasing_ppgtt(dev);
4602 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4609 int i915_gem_init(struct drm_device *dev)
4611 struct drm_i915_private *dev_priv = dev->dev_private;
4614 mutex_lock(&dev->struct_mutex);
4616 if (IS_VALLEYVIEW(dev)) {
4617 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4618 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4619 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4620 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4623 i915_gem_init_global_gtt(dev);
4625 ret = i915_gem_init_hw(dev);
4626 mutex_unlock(&dev->struct_mutex);
4628 i915_gem_cleanup_aliasing_ppgtt(dev);
4632 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4633 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4634 dev_priv->dri1.allow_batchbuffer = 1;
4639 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4641 drm_i915_private_t *dev_priv = dev->dev_private;
4642 struct intel_ring_buffer *ring;
4645 for_each_ring(ring, dev_priv, i)
4646 intel_cleanup_ring_buffer(ring);
4650 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4651 struct drm_file *file_priv)
4653 struct drm_i915_private *dev_priv = dev->dev_private;
4656 if (drm_core_check_feature(dev, DRIVER_MODESET))
4659 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4660 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4661 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4664 mutex_lock(&dev->struct_mutex);
4665 dev_priv->ums.mm_suspended = 0;
4667 ret = i915_gem_init_hw(dev);
4669 mutex_unlock(&dev->struct_mutex);
4673 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4674 mutex_unlock(&dev->struct_mutex);
4676 ret = drm_irq_install(dev);
4678 goto cleanup_ringbuffer;
4683 mutex_lock(&dev->struct_mutex);
4684 i915_gem_cleanup_ringbuffer(dev);
4685 dev_priv->ums.mm_suspended = 1;
4686 mutex_unlock(&dev->struct_mutex);
4692 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4693 struct drm_file *file_priv)
4695 if (drm_core_check_feature(dev, DRIVER_MODESET))
4698 drm_irq_uninstall(dev);
4700 return i915_gem_suspend(dev);
4704 i915_gem_lastclose(struct drm_device *dev)
4708 if (drm_core_check_feature(dev, DRIVER_MODESET))
4711 ret = i915_gem_suspend(dev);
4713 DRM_ERROR("failed to idle hardware: %d\n", ret);
4717 init_ring_lists(struct intel_ring_buffer *ring)
4719 INIT_LIST_HEAD(&ring->active_list);
4720 INIT_LIST_HEAD(&ring->request_list);
4723 static void i915_init_vm(struct drm_i915_private *dev_priv,
4724 struct i915_address_space *vm)
4726 vm->dev = dev_priv->dev;
4727 INIT_LIST_HEAD(&vm->active_list);
4728 INIT_LIST_HEAD(&vm->inactive_list);
4729 INIT_LIST_HEAD(&vm->global_link);
4730 list_add(&vm->global_link, &dev_priv->vm_list);
4734 i915_gem_load(struct drm_device *dev)
4736 drm_i915_private_t *dev_priv = dev->dev_private;
4739 INIT_LIST_HEAD(&dev_priv->vm_list);
4740 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4742 INIT_LIST_HEAD(&dev_priv->context_list);
4743 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4744 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4745 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4746 for (i = 0; i < I915_NUM_RINGS; i++)
4747 init_ring_lists(&dev_priv->ring[i]);
4748 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4749 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4750 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4751 i915_gem_retire_work_handler);
4752 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4753 i915_gem_idle_work_handler);
4754 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4756 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4758 I915_WRITE(MI_ARB_STATE,
4759 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4762 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4764 /* Old X drivers will take 0-2 for front, back, depth buffers */
4765 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4766 dev_priv->fence_reg_start = 3;
4768 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4769 dev_priv->num_fence_regs = 32;
4770 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4771 dev_priv->num_fence_regs = 16;
4773 dev_priv->num_fence_regs = 8;
4775 /* Initialize fence registers to zero */
4776 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4777 i915_gem_restore_fences(dev);
4779 i915_gem_detect_bit_6_swizzle(dev);
4780 init_waitqueue_head(&dev_priv->pending_flip_queue);
4782 dev_priv->mm.interruptible = true;
4785 dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan;
4786 dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count;
4787 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4788 register_shrinker(&dev_priv->mm.inactive_shrinker);
4789 /* Old FreeBSD code */
4790 dev_priv->mm.inactive_shrinker = EVENTHANDLER_REGISTER(vm_lowmem,
4791 i915_gem_inactive_shrink, dev, EVENTHANDLER_PRI_ANY);
4796 * Create a physically contiguous memory object for this object
4797 * e.g. for cursor + overlay regs
4799 static int i915_gem_init_phys_object(struct drm_device *dev,
4800 int id, int size, int align)
4802 drm_i915_private_t *dev_priv = dev->dev_private;
4803 struct drm_i915_gem_phys_object *phys_obj;
4806 if (dev_priv->mm.phys_objs[id - 1] || !size)
4809 phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL);
4815 phys_obj->handle = drm_pci_alloc(dev, size, align);
4816 if (!phys_obj->handle) {
4821 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4823 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
4824 size / PAGE_SIZE, PAT_WRITE_COMBINING);
4826 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4834 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4836 drm_i915_private_t *dev_priv = dev->dev_private;
4837 struct drm_i915_gem_phys_object *phys_obj;
4839 if (!dev_priv->mm.phys_objs[id - 1])
4842 phys_obj = dev_priv->mm.phys_objs[id - 1];
4843 if (phys_obj->cur_obj) {
4844 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4848 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4850 drm_pci_free(dev, phys_obj->handle);
4852 dev_priv->mm.phys_objs[id - 1] = NULL;
4855 void i915_gem_free_all_phys_object(struct drm_device *dev)
4859 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4860 i915_gem_free_phys_object(dev, i);
4863 void i915_gem_detach_phys_object(struct drm_device *dev,
4864 struct drm_i915_gem_object *obj)
4866 struct vm_object *mapping = obj->base.vm_obj;
4873 vaddr = obj->phys_obj->handle->vaddr;
4875 page_count = obj->base.size / PAGE_SIZE;
4876 for (i = 0; i < page_count; i++) {
4877 struct vm_page *page = shmem_read_mapping_page(mapping, i);
4878 if (!IS_ERR(page)) {
4879 char *dst = kmap_atomic(page);
4880 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4883 drm_clflush_pages(&page, 1);
4885 set_page_dirty(page);
4886 mark_page_accessed(page);
4888 page_cache_release(page);
4890 vm_page_busy_wait(page, FALSE, "i915gem");
4891 vm_page_unwire(page, 0);
4892 vm_page_wakeup(page);
4895 i915_gem_chipset_flush(dev);
4897 obj->phys_obj->cur_obj = NULL;
4898 obj->phys_obj = NULL;
4902 i915_gem_attach_phys_object(struct drm_device *dev,
4903 struct drm_i915_gem_object *obj,
4907 struct vm_object *mapping = obj->base.vm_obj;
4908 drm_i915_private_t *dev_priv = dev->dev_private;
4913 if (id > I915_MAX_PHYS_OBJECT)
4916 if (obj->phys_obj) {
4917 if (obj->phys_obj->id == id)
4919 i915_gem_detach_phys_object(dev, obj);
4922 /* create a new object */
4923 if (!dev_priv->mm.phys_objs[id - 1]) {
4924 ret = i915_gem_init_phys_object(dev, id,
4925 obj->base.size, align);
4927 DRM_ERROR("failed to init phys object %d size: %zu\n",
4928 id, obj->base.size);
4933 /* bind to the object */
4934 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4935 obj->phys_obj->cur_obj = obj;
4937 page_count = obj->base.size / PAGE_SIZE;
4939 for (i = 0; i < page_count; i++) {
4940 struct vm_page *page;
4943 page = shmem_read_mapping_page(mapping, i);
4945 return PTR_ERR(page);
4947 src = kmap_atomic(page);
4948 dst = (char*)obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4949 memcpy(dst, src, PAGE_SIZE);
4952 mark_page_accessed(page);
4954 page_cache_release(page);
4956 vm_page_busy_wait(page, FALSE, "i915gem");
4957 vm_page_unwire(page, 0);
4958 vm_page_wakeup(page);
4965 i915_gem_phys_pwrite(struct drm_device *dev,
4966 struct drm_i915_gem_object *obj,
4967 struct drm_i915_gem_pwrite *args,
4968 struct drm_file *file_priv)
4970 void *vaddr = (char *)obj->phys_obj->handle->vaddr + args->offset;
4971 char __user *user_data = to_user_ptr(args->data_ptr);
4973 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4974 unsigned long unwritten;
4976 /* The physical object once assigned is fixed for the lifetime
4977 * of the obj, so we can safely drop the lock and continue
4980 mutex_unlock(&dev->struct_mutex);
4981 unwritten = copy_from_user(vaddr, user_data, args->size);
4982 mutex_lock(&dev->struct_mutex);
4987 i915_gem_chipset_flush(dev);
4991 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4993 struct drm_i915_file_private *file_priv = file->driver_priv;
4995 /* Clean up our request list when the client is going away, so that
4996 * later retire_requests won't dereference our soon-to-be-gone
4999 spin_lock(&file_priv->mm.lock);
5000 while (!list_empty(&file_priv->mm.request_list)) {
5001 struct drm_i915_gem_request *request;
5003 request = list_first_entry(&file_priv->mm.request_list,
5004 struct drm_i915_gem_request,
5006 list_del(&request->client_list);
5007 request->file_priv = NULL;
5009 spin_unlock(&file_priv->mm.lock);
5013 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
5014 vm_ooffset_t foff, struct ucred *cred, u_short *color)
5016 *color = 0; /* XXXKIB */
5021 i915_gem_pager_dtor(void *handle)
5023 struct drm_gem_object *obj;
5024 struct drm_device *dev;
5029 mutex_lock(&dev->struct_mutex);
5030 drm_gem_free_mmap_offset(obj);
5031 i915_gem_release_mmap(to_intel_bo(obj));
5032 drm_gem_object_unreference(obj);
5033 mutex_unlock(&dev->struct_mutex);
5037 i915_gem_file_idle_work_handler(struct work_struct *work)
5039 struct drm_i915_file_private *file_priv =
5040 container_of(work, typeof(*file_priv), mm.idle_work.work);
5042 atomic_set(&file_priv->rps_wait_boost, false);
5045 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5047 struct drm_i915_file_private *file_priv;
5049 DRM_DEBUG_DRIVER("\n");
5051 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5055 file->driver_priv = file_priv;
5056 file_priv->dev_priv = dev->dev_private;
5058 spin_init(&file_priv->mm.lock, "i915_priv");
5059 INIT_LIST_HEAD(&file_priv->mm.request_list);
5060 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5061 i915_gem_file_idle_work_handler);
5063 idr_init(&file_priv->context_idr);
5069 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5071 if (!mutex_is_locked(mutex))
5074 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5075 return mutex->owner == task;
5077 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5084 static unsigned long
5085 i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc)
5087 struct drm_i915_private *dev_priv =
5088 container_of(shrinker,
5089 struct drm_i915_private,
5090 mm.inactive_shrinker);
5091 struct drm_device *dev = dev_priv->dev;
5092 struct drm_i915_gem_object *obj;
5094 unsigned long count;
5096 if (!mutex_trylock(&dev->struct_mutex)) {
5097 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5100 if (dev_priv->mm.shrinker_no_lock_stealing)
5107 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5108 if (obj->pages_pin_count == 0)
5109 count += obj->base.size >> PAGE_SHIFT;
5111 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5115 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
5116 count += obj->base.size >> PAGE_SHIFT;
5120 mutex_unlock(&dev->struct_mutex);
5126 /* All the new VM stuff */
5127 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5128 struct i915_address_space *vm)
5130 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5131 struct i915_vma *vma;
5133 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
5134 vm = &dev_priv->gtt.base;
5136 BUG_ON(list_empty(&o->vma_list));
5137 list_for_each_entry(vma, &o->vma_list, vma_link) {
5139 return vma->node.start;
5145 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5146 struct i915_address_space *vm)
5148 struct i915_vma *vma;
5150 list_for_each_entry(vma, &o->vma_list, vma_link)
5151 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5157 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5159 struct i915_vma *vma;
5161 list_for_each_entry(vma, &o->vma_list, vma_link)
5162 if (drm_mm_node_allocated(&vma->node))
5168 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5169 struct i915_address_space *vm)
5171 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5172 struct i915_vma *vma;
5174 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
5175 vm = &dev_priv->gtt.base;
5177 BUG_ON(list_empty(&o->vma_list));
5179 list_for_each_entry(vma, &o->vma_list, vma_link)
5181 return vma->node.size;
5187 static unsigned long
5188 i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc)
5190 struct drm_i915_private *dev_priv =
5191 container_of(shrinker,
5192 struct drm_i915_private,
5193 mm.inactive_shrinker);
5194 struct drm_device *dev = dev_priv->dev;
5195 unsigned long freed;
5198 if (!mutex_trylock(&dev->struct_mutex)) {
5199 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5202 if (dev_priv->mm.shrinker_no_lock_stealing)
5208 freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5209 if (freed < sc->nr_to_scan)
5210 freed += __i915_gem_shrink(dev_priv,
5211 sc->nr_to_scan - freed,
5213 if (freed < sc->nr_to_scan)
5214 freed += i915_gem_shrink_all(dev_priv);
5217 mutex_unlock(&dev->struct_mutex);
5223 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5225 struct i915_vma *vma;
5227 if (WARN_ON(list_empty(&obj->vma_list)))
5230 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5231 if (WARN_ON(vma->vm != obj_to_ggtt(obj)))