sys/dev/drm/radeon/kv_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include "radeon.h"
  26 #include "radeon_asic.h"
  27 #include "cikd.h"
  28 #include "r600_dpm.h"
  29 #include "kv_dpm.h"
  30 #include "radeon_asic.h"
  31 #include <linux/seq_file.h>
  32
  33 #define KV_MAX_DEEPSLEEP_DIVIDER_ID     5
  34 #define KV_MINIMUM_ENGINE_CLOCK         800
  35 #define SMC_RAM_END                     0x40000
  36
  37 static void kv_init_graphics_levels(struct radeon_device *rdev);
  38 static int kv_calculate_ds_divider(struct radeon_device *rdev);
  39 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
  40 static int kv_calculate_dpm_settings(struct radeon_device *rdev);
  41 static void kv_enable_new_levels(struct radeon_device *rdev);
  42 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
  43                                            struct radeon_ps *new_rps);
  44 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level);
  45 static int kv_set_enabled_levels(struct radeon_device *rdev);
  46 static int kv_force_dpm_highest(struct radeon_device *rdev);
  47 static int kv_force_dpm_lowest(struct radeon_device *rdev);
  48 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
  49                                         struct radeon_ps *new_rps,
  50                                         struct radeon_ps *old_rps);
  51 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
  52                                             int min_temp, int max_temp);
  53 static int kv_init_fps_limits(struct radeon_device *rdev);
  54
  55 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate);
  56 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate);
  57 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate);
  58
  59 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
  60 {
  61         {  0,       4,        1    },
  62         {  1,       4,        1    },
  63         {  2,       5,        1    },
  64         {  3,       4,        2    },
  65         {  4,       1,        1    },
  66         {  5,       5,        2    },
  67         {  6,       6,        1    },
  68         {  7,       9,        2    },
  69         { 0xffffffff }
  70 };
  71
  72 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
  73 {
  74         {  0,       4,        1    },
  75         { 0xffffffff }
  76 };
  77
  78 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
  79 {
  80         {  0,       4,        1    },
  81         { 0xffffffff }
  82 };
  83
  84 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
  85 {
  86         {  0,       4,        1    },
  87         { 0xffffffff }
  88 };
  89
  90 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
  91 {
  92         {  0,       4,        1    },
  93         { 0xffffffff }
  94 };
  95
  96 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
  97 {
  98         {  0,       4,        1    },
  99         {  1,       4,        1    },
 100         {  2,       5,        1    },
 101         {  3,       4,        1    },
 102         {  4,       1,        1    },
 103         {  5,       5,        1    },
 104         {  6,       6,        1    },
 105         {  7,       9,        1    },
 106         {  8,       4,        1    },
 107         {  9,       2,        1    },
 108         {  10,      3,        1    },
 109         {  11,      6,        1    },
 110         {  12,      8,        2    },
 111         {  13,      1,        1    },
 112         {  14,      2,        1    },
 113         {  15,      3,        1    },
 114         {  16,      1,        1    },
 115         {  17,      4,        1    },
 116         {  18,      3,        1    },
 117         {  19,      1,        1    },
 118         {  20,      8,        1    },
 119         {  21,      5,        1    },
 120         {  22,      1,        1    },
 121         {  23,      1,        1    },
 122         {  24,      4,        1    },
 123         {  27,      6,        1    },
 124         {  28,      1,        1    },
 125         { 0xffffffff }
 126 };
 127
 128 static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
 129 {
 130         { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 131 };
 132
 133 static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
 134 {
 135         { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 136 };
 137
 138 static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
 139 {
 140         { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 141 };
 142
 143 static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
 144 {
 145         { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 146 };
 147
 148 static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
 149 {
 150         { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 151 };
 152
 153 static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
 154 {
 155         { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 156 };
 157
 158 static const struct kv_pt_config_reg didt_config_kv[] =
 159 {
 160         { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 161         { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 162         { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 163         { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 164         { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 165         { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 166         { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 167         { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 168         { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 169         { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 170         { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 171         { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 172         { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 173         { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 174         { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 175         { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 176         { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 177         { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 178         { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 179         { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 180         { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 181         { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 182         { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 183         { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 184         { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 185         { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 186         { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 187         { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 188         { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 189         { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 190         { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 191         { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 192         { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 193         { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 194         { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 195         { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 196         { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 197         { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 198         { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 199         { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 200         { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 201         { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 202         { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 203         { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 204         { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 205         { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 206         { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 207         { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 208         { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 209         { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 210         { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 211         { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 212         { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 213         { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 214         { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 215         { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 216         { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 217         { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 218         { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 219         { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 220         { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 221         { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 222         { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 223         { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 224         { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 225         { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 226         { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 227         { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 228         { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 229         { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 230         { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 231         { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 232         { 0xFFFFFFFF }
 233 };
 234
 235 static struct kv_ps *kv_get_ps(struct radeon_ps *rps)
 236 {
 237         struct kv_ps *ps = rps->ps_priv;
 238
 239         return ps;
 240 }
 241
 242 static struct kv_power_info *kv_get_pi(struct radeon_device *rdev)
 243 {
 244         struct kv_power_info *pi = rdev->pm.dpm.priv;
 245
 246         return pi;
 247 }
 248
 249 #if 0
 250 static void kv_program_local_cac_table(struct radeon_device *rdev,
 251                                        const struct kv_lcac_config_values *local_cac_table,
 252                                        const struct kv_lcac_config_reg *local_cac_reg)
 253 {
 254         u32 i, count, data;
 255         const struct kv_lcac_config_values *values = local_cac_table;
 256
 257         while (values->block_id != 0xffffffff) {
 258                 count = values->signal_id;
 259                 for (i = 0; i < count; i++) {
 260                         data = ((values->block_id << local_cac_reg->block_shift) &
 261                                 local_cac_reg->block_mask);
 262                         data |= ((i << local_cac_reg->signal_shift) &
 263                                  local_cac_reg->signal_mask);
 264                         data |= ((values->t << local_cac_reg->t_shift) &
 265                                  local_cac_reg->t_mask);
 266                         data |= ((1 << local_cac_reg->enable_shift) &
 267                                  local_cac_reg->enable_mask);
 268                         WREG32_SMC(local_cac_reg->cntl, data);
 269                 }
 270                 values++;
 271         }
 272 }
 273 #endif
 274
 275 static int kv_program_pt_config_registers(struct radeon_device *rdev,
 276                                           const struct kv_pt_config_reg *cac_config_regs)
 277 {
 278         const struct kv_pt_config_reg *config_regs = cac_config_regs;
 279         u32 data;
 280         u32 cache = 0;
 281
 282         if (config_regs == NULL)
 283                 return -EINVAL;
 284
 285         while (config_regs->offset != 0xFFFFFFFF) {
 286                 if (config_regs->type == KV_CONFIGREG_CACHE) {
 287                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 288                 } else {
 289                         switch (config_regs->type) {
 290                         case KV_CONFIGREG_SMC_IND:
 291                                 data = RREG32_SMC(config_regs->offset);
 292                                 break;
 293                         case KV_CONFIGREG_DIDT_IND:
 294                                 data = RREG32_DIDT(config_regs->offset);
 295                                 break;
 296                         default:
 297                                 data = RREG32(config_regs->offset << 2);
 298                                 break;
 299                         }
 300
 301                         data &= ~config_regs->mask;
 302                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 303                         data |= cache;
 304                         cache = 0;
 305
 306                         switch (config_regs->type) {
 307                         case KV_CONFIGREG_SMC_IND:
 308                                 WREG32_SMC(config_regs->offset, data);
 309                                 break;
 310                         case KV_CONFIGREG_DIDT_IND:
 311                                 WREG32_DIDT(config_regs->offset, data);
 312                                 break;
 313                         default:
 314                                 WREG32(config_regs->offset << 2, data);
 315                                 break;
 316                         }
 317                 }
 318                 config_regs++;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static void kv_do_enable_didt(struct radeon_device *rdev, bool enable)
 325 {
 326         struct kv_power_info *pi = kv_get_pi(rdev);
 327         u32 data;
 328
 329         if (pi->caps_sq_ramping) {
 330                 data = RREG32_DIDT(DIDT_SQ_CTRL0);
 331                 if (enable)
 332                         data |= DIDT_CTRL_EN;
 333                 else
 334                         data &= ~DIDT_CTRL_EN;
 335                 WREG32_DIDT(DIDT_SQ_CTRL0, data);
 336         }
 337
 338         if (pi->caps_db_ramping) {
 339                 data = RREG32_DIDT(DIDT_DB_CTRL0);
 340                 if (enable)
 341                         data |= DIDT_CTRL_EN;
 342                 else
 343                         data &= ~DIDT_CTRL_EN;
 344                 WREG32_DIDT(DIDT_DB_CTRL0, data);
 345         }
 346
 347         if (pi->caps_td_ramping) {
 348                 data = RREG32_DIDT(DIDT_TD_CTRL0);
 349                 if (enable)
 350                         data |= DIDT_CTRL_EN;
 351                 else
 352                         data &= ~DIDT_CTRL_EN;
 353                 WREG32_DIDT(DIDT_TD_CTRL0, data);
 354         }
 355
 356         if (pi->caps_tcp_ramping) {
 357                 data = RREG32_DIDT(DIDT_TCP_CTRL0);
 358                 if (enable)
 359                         data |= DIDT_CTRL_EN;
 360                 else
 361                         data &= ~DIDT_CTRL_EN;
 362                 WREG32_DIDT(DIDT_TCP_CTRL0, data);
 363         }
 364 }
 365
 366 static int kv_enable_didt(struct radeon_device *rdev, bool enable)
 367 {
 368         struct kv_power_info *pi = kv_get_pi(rdev);
 369         int ret;
 370
 371         if (pi->caps_sq_ramping ||
 372             pi->caps_db_ramping ||
 373             pi->caps_td_ramping ||
 374             pi->caps_tcp_ramping) {
 375                 cik_enter_rlc_safe_mode(rdev);
 376
 377                 if (enable) {
 378                         ret = kv_program_pt_config_registers(rdev, didt_config_kv);
 379                         if (ret) {
 380                                 cik_exit_rlc_safe_mode(rdev);
 381                                 return ret;
 382                         }
 383                 }
 384
 385                 kv_do_enable_didt(rdev, enable);
 386
 387                 cik_exit_rlc_safe_mode(rdev);
 388         }
 389
 390         return 0;
 391 }
 392
 393 #if 0
 394 static void kv_initialize_hardware_cac_manager(struct radeon_device *rdev)
 395 {
 396         struct kv_power_info *pi = kv_get_pi(rdev);
 397
 398         if (pi->caps_cac) {
 399                 WREG32_SMC(LCAC_SX0_OVR_SEL, 0);
 400                 WREG32_SMC(LCAC_SX0_OVR_VAL, 0);
 401                 kv_program_local_cac_table(rdev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
 402
 403                 WREG32_SMC(LCAC_MC0_OVR_SEL, 0);
 404                 WREG32_SMC(LCAC_MC0_OVR_VAL, 0);
 405                 kv_program_local_cac_table(rdev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
 406
 407                 WREG32_SMC(LCAC_MC1_OVR_SEL, 0);
 408                 WREG32_SMC(LCAC_MC1_OVR_VAL, 0);
 409                 kv_program_local_cac_table(rdev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
 410
 411                 WREG32_SMC(LCAC_MC2_OVR_SEL, 0);
 412                 WREG32_SMC(LCAC_MC2_OVR_VAL, 0);
 413                 kv_program_local_cac_table(rdev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
 414
 415                 WREG32_SMC(LCAC_MC3_OVR_SEL, 0);
 416                 WREG32_SMC(LCAC_MC3_OVR_VAL, 0);
 417                 kv_program_local_cac_table(rdev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
 418
 419                 WREG32_SMC(LCAC_CPL_OVR_SEL, 0);
 420                 WREG32_SMC(LCAC_CPL_OVR_VAL, 0);
 421                 kv_program_local_cac_table(rdev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
 422         }
 423 }
 424 #endif
 425
 426 static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable)
 427 {
 428         struct kv_power_info *pi = kv_get_pi(rdev);
 429         int ret = 0;
 430
 431         if (pi->caps_cac) {
 432                 if (enable) {
 433                         ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac);
 434                         if (ret)
 435                                 pi->cac_enabled = false;
 436                         else
 437                                 pi->cac_enabled = true;
 438                 } else if (pi->cac_enabled) {
 439                         kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac);
 440                         pi->cac_enabled = false;
 441                 }
 442         }
 443
 444         return ret;
 445 }
 446
 447 static int kv_process_firmware_header(struct radeon_device *rdev)
 448 {
 449         struct kv_power_info *pi = kv_get_pi(rdev);
 450         u32 tmp;
 451         int ret;
 452
 453         ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
 454                                      offsetof(SMU7_Firmware_Header, DpmTable),
 455                                      &tmp, pi->sram_end);
 456
 457         if (ret == 0)
 458                 pi->dpm_table_start = tmp;
 459
 460         ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
 461                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
 462                                      &tmp, pi->sram_end);
 463
 464         if (ret == 0)
 465                 pi->soft_regs_start = tmp;
 466
 467         return ret;
 468 }
 469
 470 static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev)
 471 {
 472         struct kv_power_info *pi = kv_get_pi(rdev);
 473         int ret;
 474
 475         pi->graphics_voltage_change_enable = 1;
 476
 477         ret = kv_copy_bytes_to_smc(rdev,
 478                                    pi->dpm_table_start +
 479                                    offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
 480                                    &pi->graphics_voltage_change_enable,
 481                                    sizeof(u8), pi->sram_end);
 482
 483         return ret;
 484 }
 485
 486 static int kv_set_dpm_interval(struct radeon_device *rdev)
 487 {
 488         struct kv_power_info *pi = kv_get_pi(rdev);
 489         int ret;
 490
 491         pi->graphics_interval = 1;
 492
 493         ret = kv_copy_bytes_to_smc(rdev,
 494                                    pi->dpm_table_start +
 495                                    offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
 496                                    &pi->graphics_interval,
 497                                    sizeof(u8), pi->sram_end);
 498
 499         return ret;
 500 }
 501
 502 static int kv_set_dpm_boot_state(struct radeon_device *rdev)
 503 {
 504         struct kv_power_info *pi = kv_get_pi(rdev);
 505         int ret;
 506
 507         ret = kv_copy_bytes_to_smc(rdev,
 508                                    pi->dpm_table_start +
 509                                    offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
 510                                    &pi->graphics_boot_level,
 511                                    sizeof(u8), pi->sram_end);
 512
 513         return ret;
 514 }
 515
 516 static void kv_program_vc(struct radeon_device *rdev)
 517 {
 518         WREG32_SMC(CG_FTV_0, 0x3FFFC100);
 519 }
 520
 521 static void kv_clear_vc(struct radeon_device *rdev)
 522 {
 523         WREG32_SMC(CG_FTV_0, 0);
 524 }
 525
 526 static int kv_set_divider_value(struct radeon_device *rdev,
 527                                 u32 index, u32 sclk)
 528 {
 529         struct kv_power_info *pi = kv_get_pi(rdev);
 530         struct atom_clock_dividers dividers;
 531         int ret;
 532
 533         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 534                                              sclk, false, &dividers);
 535         if (ret)
 536                 return ret;
 537
 538         pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
 539         pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
 540
 541         return 0;
 542 }
 543
 544 static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev,
 545                                             u16 voltage)
 546 {
 547         return 6200 - (voltage * 25);
 548 }
 549
 550 static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev,
 551                                             u32 vid_2bit)
 552 {
 553         struct kv_power_info *pi = kv_get_pi(rdev);
 554         u32 vid_8bit = sumo_convert_vid2_to_vid7(rdev,
 555                                                  &pi->sys_info.vid_mapping_table,
 556                                                  vid_2bit);
 557
 558         return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit);
 559 }
 560
 561
 562 static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
 563 {
 564         struct kv_power_info *pi = kv_get_pi(rdev);
 565
 566         pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
 567         pi->graphics_level[index].MinVddNb =
 568                 cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid));
 569
 570         return 0;
 571 }
 572
 573 static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at)
 574 {
 575         struct kv_power_info *pi = kv_get_pi(rdev);
 576
 577         pi->graphics_level[index].AT = cpu_to_be16((u16)at);
 578
 579         return 0;
 580 }
 581
 582 static void kv_dpm_power_level_enable(struct radeon_device *rdev,
 583                                       u32 index, bool enable)
 584 {
 585         struct kv_power_info *pi = kv_get_pi(rdev);
 586
 587         pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
 588 }
 589
 590 static void kv_start_dpm(struct radeon_device *rdev)
 591 {
 592         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
 593
 594         tmp |= GLOBAL_PWRMGT_EN;
 595         WREG32_SMC(GENERAL_PWRMGT, tmp);
 596
 597         kv_smc_dpm_enable(rdev, true);
 598 }
 599
 600 static void kv_stop_dpm(struct radeon_device *rdev)
 601 {
 602         kv_smc_dpm_enable(rdev, false);
 603 }
 604
 605 static void kv_start_am(struct radeon_device *rdev)
 606 {
 607         u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
 608
 609         sclk_pwrmgt_cntl &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
 610         sclk_pwrmgt_cntl |= DYNAMIC_PM_EN;
 611
 612         WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 613 }
 614
 615 static void kv_reset_am(struct radeon_device *rdev)
 616 {
 617         u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
 618
 619         sclk_pwrmgt_cntl |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
 620
 621         WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 622 }
 623
 624 static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze)
 625 {
 626         return kv_notify_message_to_smu(rdev, freeze ?
 627                                         PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
 628 }
 629
 630 static int kv_force_lowest_valid(struct radeon_device *rdev)
 631 {
 632         return kv_force_dpm_lowest(rdev);
 633 }
 634
 635 static int kv_unforce_levels(struct radeon_device *rdev)
 636 {
 637         if (rdev->family == CHIP_KABINI)
 638                 return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
 639         else
 640                 return kv_set_enabled_levels(rdev);
 641 }
 642
 643 static int kv_update_sclk_t(struct radeon_device *rdev)
 644 {
 645         struct kv_power_info *pi = kv_get_pi(rdev);
 646         u32 low_sclk_interrupt_t = 0;
 647         int ret = 0;
 648
 649         if (pi->caps_sclk_throttle_low_notification) {
 650                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 651
 652                 ret = kv_copy_bytes_to_smc(rdev,
 653                                            pi->dpm_table_start +
 654                                            offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
 655                                            (u8 *)&low_sclk_interrupt_t,
 656                                            sizeof(u32), pi->sram_end);
 657         }
 658         return ret;
 659 }
 660
 661 static int kv_program_bootup_state(struct radeon_device *rdev)
 662 {
 663         struct kv_power_info *pi = kv_get_pi(rdev);
 664         u32 i;
 665         struct radeon_clock_voltage_dependency_table *table =
 666                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 667
 668         if (table && table->count) {
 669                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
 670                         if (table->entries[i].clk == pi->boot_pl.sclk)
 671                                 break;
 672                 }
 673
 674                 pi->graphics_boot_level = (u8)i;
 675                 kv_dpm_power_level_enable(rdev, i, true);
 676         } else {
 677                 struct sumo_sclk_voltage_mapping_table *table =
 678                         &pi->sys_info.sclk_voltage_mapping_table;
 679
 680                 if (table->num_max_dpm_entries == 0)
 681                         return -EINVAL;
 682
 683                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
 684                         if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
 685                                 break;
 686                 }
 687
 688                 pi->graphics_boot_level = (u8)i;
 689                 kv_dpm_power_level_enable(rdev, i, true);
 690         }
 691         return 0;
 692 }
 693
 694 static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev)
 695 {
 696         struct kv_power_info *pi = kv_get_pi(rdev);
 697         int ret;
 698
 699         pi->graphics_therm_throttle_enable = 1;
 700
 701         ret = kv_copy_bytes_to_smc(rdev,
 702                                    pi->dpm_table_start +
 703                                    offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
 704                                    &pi->graphics_therm_throttle_enable,
 705                                    sizeof(u8), pi->sram_end);
 706
 707         return ret;
 708 }
 709
 710 static int kv_upload_dpm_settings(struct radeon_device *rdev)
 711 {
 712         struct kv_power_info *pi = kv_get_pi(rdev);
 713         int ret;
 714
 715         ret = kv_copy_bytes_to_smc(rdev,
 716                                    pi->dpm_table_start +
 717                                    offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
 718                                    (u8 *)&pi->graphics_level,
 719                                    sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
 720                                    pi->sram_end);
 721
 722         if (ret)
 723                 return ret;
 724
 725         ret = kv_copy_bytes_to_smc(rdev,
 726                                    pi->dpm_table_start +
 727                                    offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
 728                                    &pi->graphics_dpm_level_count,
 729                                    sizeof(u8), pi->sram_end);
 730
 731         return ret;
 732 }
 733
 734 static u32 kv_get_clock_difference(u32 a, u32 b)
 735 {
 736         return (a >= b) ? a - b : b - a;
 737 }
 738
 739 static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk)
 740 {
 741         struct kv_power_info *pi = kv_get_pi(rdev);
 742         u32 value;
 743
 744         if (pi->caps_enable_dfs_bypass) {
 745                 if (kv_get_clock_difference(clk, 40000) < 200)
 746                         value = 3;
 747                 else if (kv_get_clock_difference(clk, 30000) < 200)
 748                         value = 2;
 749                 else if (kv_get_clock_difference(clk, 20000) < 200)
 750                         value = 7;
 751                 else if (kv_get_clock_difference(clk, 15000) < 200)
 752                         value = 6;
 753                 else if (kv_get_clock_difference(clk, 10000) < 200)
 754                         value = 8;
 755                 else
 756                         value = 0;
 757         } else {
 758                 value = 0;
 759         }
 760
 761         return value;
 762 }
 763
 764 static int kv_populate_uvd_table(struct radeon_device *rdev)
 765 {
 766         struct kv_power_info *pi = kv_get_pi(rdev);
 767         struct radeon_uvd_clock_voltage_dependency_table *table =
 768                 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
 769         struct atom_clock_dividers dividers;
 770         int ret;
 771         u32 i;
 772
 773         if (table == NULL || table->count == 0)
 774                 return 0;
 775
 776         pi->uvd_level_count = 0;
 777         for (i = 0; i < table->count; i++) {
 778                 if (pi->high_voltage_t &&
 779                     (pi->high_voltage_t < table->entries[i].v))
 780                         break;
 781
 782                 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
 783                 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
 784                 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
 785
 786                 pi->uvd_level[i].VClkBypassCntl =
 787                         (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);
 788                 pi->uvd_level[i].DClkBypassCntl =
 789                         (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);
 790
 791                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 792                                                      table->entries[i].vclk, false, &dividers);
 793                 if (ret)
 794                         return ret;
 795                 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
 796
 797                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 798                                                      table->entries[i].dclk, false, &dividers);
 799                 if (ret)
 800                         return ret;
 801                 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
 802
 803                 pi->uvd_level_count++;
 804         }
 805
 806         ret = kv_copy_bytes_to_smc(rdev,
 807                                    pi->dpm_table_start +
 808                                    offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
 809                                    (u8 *)&pi->uvd_level_count,
 810                                    sizeof(u8), pi->sram_end);
 811         if (ret)
 812                 return ret;
 813
 814         pi->uvd_interval = 1;
 815
 816         ret = kv_copy_bytes_to_smc(rdev,
 817                                    pi->dpm_table_start +
 818                                    offsetof(SMU7_Fusion_DpmTable, UVDInterval),
 819                                    &pi->uvd_interval,
 820                                    sizeof(u8), pi->sram_end);
 821         if (ret)
 822                 return ret;
 823
 824         ret = kv_copy_bytes_to_smc(rdev,
 825                                    pi->dpm_table_start +
 826                                    offsetof(SMU7_Fusion_DpmTable, UvdLevel),
 827                                    (u8 *)&pi->uvd_level,
 828                                    sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
 829                                    pi->sram_end);
 830
 831         return ret;
 832
 833 }
 834
 835 static int kv_populate_vce_table(struct radeon_device *rdev)
 836 {
 837         struct kv_power_info *pi = kv_get_pi(rdev);
 838         int ret;
 839         u32 i;
 840         struct radeon_vce_clock_voltage_dependency_table *table =
 841                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
 842         struct atom_clock_dividers dividers;
 843
 844         if (table == NULL || table->count == 0)
 845                 return 0;
 846
 847         pi->vce_level_count = 0;
 848         for (i = 0; i < table->count; i++) {
 849                 if (pi->high_voltage_t &&
 850                     pi->high_voltage_t < table->entries[i].v)
 851                         break;
 852
 853                 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
 854                 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 855
 856                 pi->vce_level[i].ClkBypassCntl =
 857                         (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);
 858
 859                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 860                                                      table->entries[i].evclk, false, &dividers);
 861                 if (ret)
 862                         return ret;
 863                 pi->vce_level[i].Divider = (u8)dividers.post_div;
 864
 865                 pi->vce_level_count++;
 866         }
 867
 868         ret = kv_copy_bytes_to_smc(rdev,
 869                                    pi->dpm_table_start +
 870                                    offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
 871                                    (u8 *)&pi->vce_level_count,
 872                                    sizeof(u8),
 873                                    pi->sram_end);
 874         if (ret)
 875                 return ret;
 876
 877         pi->vce_interval = 1;
 878
 879         ret = kv_copy_bytes_to_smc(rdev,
 880                                    pi->dpm_table_start +
 881                                    offsetof(SMU7_Fusion_DpmTable, VCEInterval),
 882                                    (u8 *)&pi->vce_interval,
 883                                    sizeof(u8),
 884                                    pi->sram_end);
 885         if (ret)
 886                 return ret;
 887
 888         ret = kv_copy_bytes_to_smc(rdev,
 889                                    pi->dpm_table_start +
 890                                    offsetof(SMU7_Fusion_DpmTable, VceLevel),
 891                                    (u8 *)&pi->vce_level,
 892                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
 893                                    pi->sram_end);
 894
 895         return ret;
 896 }
 897
 898 static int kv_populate_samu_table(struct radeon_device *rdev)
 899 {
 900         struct kv_power_info *pi = kv_get_pi(rdev);
 901         struct radeon_clock_voltage_dependency_table *table =
 902                 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
 903         struct atom_clock_dividers dividers;
 904         int ret;
 905         u32 i;
 906
 907         if (table == NULL || table->count == 0)
 908                 return 0;
 909
 910         pi->samu_level_count = 0;
 911         for (i = 0; i < table->count; i++) {
 912                 if (pi->high_voltage_t &&
 913                     pi->high_voltage_t < table->entries[i].v)
 914                         break;
 915
 916                 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
 917                 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 918
 919                 pi->samu_level[i].ClkBypassCntl =
 920                         (u8)kv_get_clk_bypass(rdev, table->entries[i].clk);
 921
 922                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 923                                                      table->entries[i].clk, false, &dividers);
 924                 if (ret)
 925                         return ret;
 926                 pi->samu_level[i].Divider = (u8)dividers.post_div;
 927
 928                 pi->samu_level_count++;
 929         }
 930
 931         ret = kv_copy_bytes_to_smc(rdev,
 932                                    pi->dpm_table_start +
 933                                    offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
 934                                    (u8 *)&pi->samu_level_count,
 935                                    sizeof(u8),
 936                                    pi->sram_end);
 937         if (ret)
 938                 return ret;
 939
 940         pi->samu_interval = 1;
 941
 942         ret = kv_copy_bytes_to_smc(rdev,
 943                                    pi->dpm_table_start +
 944                                    offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
 945                                    (u8 *)&pi->samu_interval,
 946                                    sizeof(u8),
 947                                    pi->sram_end);
 948         if (ret)
 949                 return ret;
 950
 951         ret = kv_copy_bytes_to_smc(rdev,
 952                                    pi->dpm_table_start +
 953                                    offsetof(SMU7_Fusion_DpmTable, SamuLevel),
 954                                    (u8 *)&pi->samu_level,
 955                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
 956                                    pi->sram_end);
 957         if (ret)
 958                 return ret;
 959
 960         return ret;
 961 }
 962
 963
 964 static int kv_populate_acp_table(struct radeon_device *rdev)
 965 {
 966         struct kv_power_info *pi = kv_get_pi(rdev);
 967         struct radeon_clock_voltage_dependency_table *table =
 968                 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
 969         struct atom_clock_dividers dividers;
 970         int ret;
 971         u32 i;
 972
 973         if (table == NULL || table->count == 0)
 974                 return 0;
 975
 976         pi->acp_level_count = 0;
 977         for (i = 0; i < table->count; i++) {
 978                 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
 979                 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 980
 981                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 982                                                      table->entries[i].clk, false, &dividers);
 983                 if (ret)
 984                         return ret;
 985                 pi->acp_level[i].Divider = (u8)dividers.post_div;
 986
 987                 pi->acp_level_count++;
 988         }
 989
 990         ret = kv_copy_bytes_to_smc(rdev,
 991                                    pi->dpm_table_start +
 992                                    offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
 993                                    (u8 *)&pi->acp_level_count,
 994                                    sizeof(u8),
 995                                    pi->sram_end);
 996         if (ret)
 997                 return ret;
 998
 999         pi->acp_interval = 1;
1000
1001         ret = kv_copy_bytes_to_smc(rdev,
1002                                    pi->dpm_table_start +
1003                                    offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1004                                    (u8 *)&pi->acp_interval,
1005                                    sizeof(u8),
1006                                    pi->sram_end);
1007         if (ret)
1008                 return ret;
1009
1010         ret = kv_copy_bytes_to_smc(rdev,
1011                                    pi->dpm_table_start +
1012                                    offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1013                                    (u8 *)&pi->acp_level,
1014                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1015                                    pi->sram_end);
1016         if (ret)
1017                 return ret;
1018
1019         return ret;
1020 }
1021
1022 static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev)
1023 {
1024         struct kv_power_info *pi = kv_get_pi(rdev);
1025         u32 i;
1026         struct radeon_clock_voltage_dependency_table *table =
1027                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1028
1029         if (table && table->count) {
1030                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1031                         if (pi->caps_enable_dfs_bypass) {
1032                                 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1033                                         pi->graphics_level[i].ClkBypassCntl = 3;
1034                                 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1035                                         pi->graphics_level[i].ClkBypassCntl = 2;
1036                                 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1037                                         pi->graphics_level[i].ClkBypassCntl = 7;
1038                                 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1039                                         pi->graphics_level[i].ClkBypassCntl = 6;
1040                                 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1041                                         pi->graphics_level[i].ClkBypassCntl = 8;
1042                                 else
1043                                         pi->graphics_level[i].ClkBypassCntl = 0;
1044                         } else {
1045                                 pi->graphics_level[i].ClkBypassCntl = 0;
1046                         }
1047                 }
1048         } else {
1049                 struct sumo_sclk_voltage_mapping_table *table =
1050                         &pi->sys_info.sclk_voltage_mapping_table;
1051                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1052                         if (pi->caps_enable_dfs_bypass) {
1053                                 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1054                                         pi->graphics_level[i].ClkBypassCntl = 3;
1055                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1056                                         pi->graphics_level[i].ClkBypassCntl = 2;
1057                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1058                                         pi->graphics_level[i].ClkBypassCntl = 7;
1059                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1060                                         pi->graphics_level[i].ClkBypassCntl = 6;
1061                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1062                                         pi->graphics_level[i].ClkBypassCntl = 8;
1063                                 else
1064                                         pi->graphics_level[i].ClkBypassCntl = 0;
1065                         } else {
1066                                 pi->graphics_level[i].ClkBypassCntl = 0;
1067                         }
1068                 }
1069         }
1070 }
1071
1072 static int kv_enable_ulv(struct radeon_device *rdev, bool enable)
1073 {
1074         return kv_notify_message_to_smu(rdev, enable ?
1075                                         PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1076 }
1077
1078 static void kv_reset_acp_boot_level(struct radeon_device *rdev)
1079 {
1080         struct kv_power_info *pi = kv_get_pi(rdev);
1081
1082         pi->acp_boot_level = 0xff;
1083 }
1084
1085 static void kv_update_current_ps(struct radeon_device *rdev,
1086                                  struct radeon_ps *rps)
1087 {
1088         struct kv_ps *new_ps = kv_get_ps(rps);
1089         struct kv_power_info *pi = kv_get_pi(rdev);
1090
1091         pi->current_rps = *rps;
1092         pi->current_ps = *new_ps;
1093         pi->current_rps.ps_priv = &pi->current_ps;
1094 }
1095
1096 static void kv_update_requested_ps(struct radeon_device *rdev,
1097                                    struct radeon_ps *rps)
1098 {
1099         struct kv_ps *new_ps = kv_get_ps(rps);
1100         struct kv_power_info *pi = kv_get_pi(rdev);
1101
1102         pi->requested_rps = *rps;
1103         pi->requested_ps = *new_ps;
1104         pi->requested_rps.ps_priv = &pi->requested_ps;
1105 }
1106
1107 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
1108 {
1109         struct kv_power_info *pi = kv_get_pi(rdev);
1110         int ret;
1111
1112         if (pi->bapm_enable) {
1113                 ret = kv_smc_bapm_enable(rdev, enable);
1114                 if (ret)
1115                         DRM_ERROR("kv_smc_bapm_enable failed\n");
1116         }
1117 }
1118
1119 int kv_dpm_enable(struct radeon_device *rdev)
1120 {
1121         struct kv_power_info *pi = kv_get_pi(rdev);
1122         int ret;
1123
1124         cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1125                              RADEON_CG_BLOCK_SDMA |
1126                              RADEON_CG_BLOCK_BIF |
1127                              RADEON_CG_BLOCK_HDP), false);
1128
1129         ret = kv_process_firmware_header(rdev);
1130         if (ret) {
1131                 DRM_ERROR("kv_process_firmware_header failed\n");
1132                 return ret;
1133         }
1134         kv_init_fps_limits(rdev);
1135         kv_init_graphics_levels(rdev);
1136         ret = kv_program_bootup_state(rdev);
1137         if (ret) {
1138                 DRM_ERROR("kv_program_bootup_state failed\n");
1139                 return ret;
1140         }
1141         kv_calculate_dfs_bypass_settings(rdev);
1142         ret = kv_upload_dpm_settings(rdev);
1143         if (ret) {
1144                 DRM_ERROR("kv_upload_dpm_settings failed\n");
1145                 return ret;
1146         }
1147         ret = kv_populate_uvd_table(rdev);
1148         if (ret) {
1149                 DRM_ERROR("kv_populate_uvd_table failed\n");
1150                 return ret;
1151         }
1152         ret = kv_populate_vce_table(rdev);
1153         if (ret) {
1154                 DRM_ERROR("kv_populate_vce_table failed\n");
1155                 return ret;
1156         }
1157         ret = kv_populate_samu_table(rdev);
1158         if (ret) {
1159                 DRM_ERROR("kv_populate_samu_table failed\n");
1160                 return ret;
1161         }
1162         ret = kv_populate_acp_table(rdev);
1163         if (ret) {
1164                 DRM_ERROR("kv_populate_acp_table failed\n");
1165                 return ret;
1166         }
1167         kv_program_vc(rdev);
1168 #if 0
1169         kv_initialize_hardware_cac_manager(rdev);
1170 #endif
1171         kv_start_am(rdev);
1172         if (pi->enable_auto_thermal_throttling) {
1173                 ret = kv_enable_auto_thermal_throttling(rdev);
1174                 if (ret) {
1175                         DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1176                         return ret;
1177                 }
1178         }
1179         ret = kv_enable_dpm_voltage_scaling(rdev);
1180         if (ret) {
1181                 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1182                 return ret;
1183         }
1184         ret = kv_set_dpm_interval(rdev);
1185         if (ret) {
1186                 DRM_ERROR("kv_set_dpm_interval failed\n");
1187                 return ret;
1188         }
1189         ret = kv_set_dpm_boot_state(rdev);
1190         if (ret) {
1191                 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1192                 return ret;
1193         }
1194         ret = kv_enable_ulv(rdev, true);
1195         if (ret) {
1196                 DRM_ERROR("kv_enable_ulv failed\n");
1197                 return ret;
1198         }
1199         kv_start_dpm(rdev);
1200         ret = kv_enable_didt(rdev, true);
1201         if (ret) {
1202                 DRM_ERROR("kv_enable_didt failed\n");
1203                 return ret;
1204         }
1205         ret = kv_enable_smc_cac(rdev, true);
1206         if (ret) {
1207                 DRM_ERROR("kv_enable_smc_cac failed\n");
1208                 return ret;
1209         }
1210
1211         kv_reset_acp_boot_level(rdev);
1212
1213         if (rdev->irq.installed &&
1214             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1215                 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1216                 if (ret) {
1217                         DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1218                         return ret;
1219                 }
1220                 rdev->irq.dpm_thermal = true;
1221                 radeon_irq_set(rdev);
1222         }
1223
1224         ret = kv_smc_bapm_enable(rdev, false);
1225         if (ret) {
1226                 DRM_ERROR("kv_smc_bapm_enable failed\n");
1227                 return ret;
1228         }
1229
1230         /* powerdown unused blocks for now */
1231         kv_dpm_powergate_acp(rdev, true);
1232         kv_dpm_powergate_samu(rdev, true);
1233         kv_dpm_powergate_vce(rdev, true);
1234         kv_dpm_powergate_uvd(rdev, true);
1235
1236         cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1237                              RADEON_CG_BLOCK_SDMA |
1238                              RADEON_CG_BLOCK_BIF |
1239                              RADEON_CG_BLOCK_HDP), true);
1240
1241         kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1242
1243         return ret;
1244 }
1245
1246 void kv_dpm_disable(struct radeon_device *rdev)
1247 {
1248         cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1249                              RADEON_CG_BLOCK_SDMA |
1250                              RADEON_CG_BLOCK_BIF |
1251                              RADEON_CG_BLOCK_HDP), false);
1252
1253         kv_smc_bapm_enable(rdev, false);
1254
1255         /* powerup blocks */
1256         kv_dpm_powergate_acp(rdev, false);
1257         kv_dpm_powergate_samu(rdev, false);
1258         kv_dpm_powergate_vce(rdev, false);
1259         kv_dpm_powergate_uvd(rdev, false);
1260
1261         kv_enable_smc_cac(rdev, false);
1262         kv_enable_didt(rdev, false);
1263         kv_clear_vc(rdev);
1264         kv_stop_dpm(rdev);
1265         kv_enable_ulv(rdev, false);
1266         kv_reset_am(rdev);
1267
1268         kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1269 }
1270
1271 #if 0
1272 static int kv_write_smc_soft_register(struct radeon_device *rdev,
1273                                       u16 reg_offset, u32 value)
1274 {
1275         struct kv_power_info *pi = kv_get_pi(rdev);
1276
1277         return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1278                                     (u8 *)&value, sizeof(u16), pi->sram_end);
1279 }
1280
1281 static int kv_read_smc_soft_register(struct radeon_device *rdev,
1282                                      u16 reg_offset, u32 *value)
1283 {
1284         struct kv_power_info *pi = kv_get_pi(rdev);
1285
1286         return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
1287                                       value, pi->sram_end);
1288 }
1289 #endif
1290
1291 static void kv_init_sclk_t(struct radeon_device *rdev)
1292 {
1293         struct kv_power_info *pi = kv_get_pi(rdev);
1294
1295         pi->low_sclk_interrupt_t = 0;
1296 }
1297
1298 static int kv_init_fps_limits(struct radeon_device *rdev)
1299 {
1300         struct kv_power_info *pi = kv_get_pi(rdev);
1301         int ret = 0;
1302
1303         if (pi->caps_fps) {
1304                 u16 tmp;
1305
1306                 tmp = 45;
1307                 pi->fps_high_t = cpu_to_be16(tmp);
1308                 ret = kv_copy_bytes_to_smc(rdev,
1309                                            pi->dpm_table_start +
1310                                            offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1311                                            (u8 *)&pi->fps_high_t,
1312                                            sizeof(u16), pi->sram_end);
1313
1314                 tmp = 30;
1315                 pi->fps_low_t = cpu_to_be16(tmp);
1316
1317                 ret = kv_copy_bytes_to_smc(rdev,
1318                                            pi->dpm_table_start +
1319                                            offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1320                                            (u8 *)&pi->fps_low_t,
1321                                            sizeof(u16), pi->sram_end);
1322
1323         }
1324         return ret;
1325 }
1326
1327 static void kv_init_powergate_state(struct radeon_device *rdev)
1328 {
1329         struct kv_power_info *pi = kv_get_pi(rdev);
1330
1331         pi->uvd_power_gated = false;
1332         pi->vce_power_gated = false;
1333         pi->samu_power_gated = false;
1334         pi->acp_power_gated = false;
1335
1336 }
1337
1338 static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
1339 {
1340         return kv_notify_message_to_smu(rdev, enable ?
1341                                         PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1342 }
1343
1344 #if 0
1345 static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable)
1346 {
1347         return kv_notify_message_to_smu(rdev, enable ?
1348                                         PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1349 }
1350 #endif
1351
1352 static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable)
1353 {
1354         return kv_notify_message_to_smu(rdev, enable ?
1355                                         PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1356 }
1357
1358 static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable)
1359 {
1360         return kv_notify_message_to_smu(rdev, enable ?
1361                                         PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1362 }
1363
1364 static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
1365 {
1366         struct kv_power_info *pi = kv_get_pi(rdev);
1367         struct radeon_uvd_clock_voltage_dependency_table *table =
1368                 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1369         int ret;
1370
1371         if (!gate) {
1372                 if (!pi->caps_uvd_dpm || table->count || pi->caps_stable_p_state)
1373                         pi->uvd_boot_level = table->count - 1;
1374                 else
1375                         pi->uvd_boot_level = 0;
1376
1377                 ret = kv_copy_bytes_to_smc(rdev,
1378                                            pi->dpm_table_start +
1379                                            offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1380                                            (uint8_t *)&pi->uvd_boot_level,
1381                                            sizeof(u8), pi->sram_end);
1382                 if (ret)
1383                         return ret;
1384
1385                 if (!pi->caps_uvd_dpm ||
1386                     pi->caps_stable_p_state)
1387                         kv_send_msg_to_smc_with_parameter(rdev,
1388                                                           PPSMC_MSG_UVDDPM_SetEnabledMask,
1389                                                           (1 << pi->uvd_boot_level));
1390         }
1391
1392         return kv_enable_uvd_dpm(rdev, !gate);
1393 }
1394
1395 #if 0
1396 static u8 kv_get_vce_boot_level(struct radeon_device *rdev)
1397 {
1398         u8 i;
1399         struct radeon_vce_clock_voltage_dependency_table *table =
1400                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1401
1402         for (i = 0; i < table->count; i++) {
1403                 if (table->entries[i].evclk >= 0) /* XXX */
1404                         break;
1405         }
1406
1407         return i;
1408 }
1409
1410 static int kv_update_vce_dpm(struct radeon_device *rdev,
1411                              struct radeon_ps *radeon_new_state,
1412                              struct radeon_ps *radeon_current_state)
1413 {
1414         struct kv_power_info *pi = kv_get_pi(rdev);
1415         struct radeon_vce_clock_voltage_dependency_table *table =
1416                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1417         int ret;
1418
1419         if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) {
1420                 if (pi->caps_stable_p_state)
1421                         pi->vce_boot_level = table->count - 1;
1422                 else
1423                         pi->vce_boot_level = kv_get_vce_boot_level(rdev);
1424
1425                 ret = kv_copy_bytes_to_smc(rdev,
1426                                            pi->dpm_table_start +
1427                                            offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1428                                            (u8 *)&pi->vce_boot_level,
1429                                            sizeof(u8),
1430                                            pi->sram_end);
1431                 if (ret)
1432                         return ret;
1433
1434                 if (pi->caps_stable_p_state)
1435                         kv_send_msg_to_smc_with_parameter(rdev,
1436                                                           PPSMC_MSG_VCEDPM_SetEnabledMask,
1437                                                           (1 << pi->vce_boot_level));
1438
1439                 kv_enable_vce_dpm(rdev, true);
1440         } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) {
1441                 kv_enable_vce_dpm(rdev, false);
1442         }
1443
1444         return 0;
1445 }
1446 #endif
1447
1448 static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate)
1449 {
1450         struct kv_power_info *pi = kv_get_pi(rdev);
1451         struct radeon_clock_voltage_dependency_table *table =
1452                 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1453         int ret;
1454
1455         if (!gate) {
1456                 if (pi->caps_stable_p_state)
1457                         pi->samu_boot_level = table->count - 1;
1458                 else
1459                         pi->samu_boot_level = 0;
1460
1461                 ret = kv_copy_bytes_to_smc(rdev,
1462                                            pi->dpm_table_start +
1463                                            offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1464                                            (u8 *)&pi->samu_boot_level,
1465                                            sizeof(u8),
1466                                            pi->sram_end);
1467                 if (ret)
1468                         return ret;
1469
1470                 if (pi->caps_stable_p_state)
1471                         kv_send_msg_to_smc_with_parameter(rdev,
1472                                                           PPSMC_MSG_SAMUDPM_SetEnabledMask,
1473                                                           (1 << pi->samu_boot_level));
1474         }
1475
1476         return kv_enable_samu_dpm(rdev, !gate);
1477 }
1478
1479 static u8 kv_get_acp_boot_level(struct radeon_device *rdev)
1480 {
1481         u8 i;
1482         struct radeon_clock_voltage_dependency_table *table =
1483                 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1484
1485         for (i = 0; i < table->count; i++) {
1486                 if (table->entries[i].clk >= 0) /* XXX */
1487                         break;
1488         }
1489
1490         if (i >= table->count)
1491                 i = table->count - 1;
1492
1493         return i;
1494 }
1495
1496 static void kv_update_acp_boot_level(struct radeon_device *rdev)
1497 {
1498         struct kv_power_info *pi = kv_get_pi(rdev);
1499         u8 acp_boot_level;
1500
1501         if (!pi->caps_stable_p_state) {
1502                 acp_boot_level = kv_get_acp_boot_level(rdev);
1503                 if (acp_boot_level != pi->acp_boot_level) {
1504                         pi->acp_boot_level = acp_boot_level;
1505                         kv_send_msg_to_smc_with_parameter(rdev,
1506                                                           PPSMC_MSG_ACPDPM_SetEnabledMask,
1507                                                           (1 << pi->acp_boot_level));
1508                 }
1509         }
1510 }
1511
1512 static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
1513 {
1514         struct kv_power_info *pi = kv_get_pi(rdev);
1515         struct radeon_clock_voltage_dependency_table *table =
1516                 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1517         int ret;
1518
1519         if (!gate) {
1520                 if (pi->caps_stable_p_state)
1521                         pi->acp_boot_level = table->count - 1;
1522                 else
1523                         pi->acp_boot_level = kv_get_acp_boot_level(rdev);
1524
1525                 ret = kv_copy_bytes_to_smc(rdev,
1526                                            pi->dpm_table_start +
1527                                            offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1528                                            (u8 *)&pi->acp_boot_level,
1529                                            sizeof(u8),
1530                                            pi->sram_end);
1531                 if (ret)
1532                         return ret;
1533
1534                 if (pi->caps_stable_p_state)
1535                         kv_send_msg_to_smc_with_parameter(rdev,
1536                                                           PPSMC_MSG_ACPDPM_SetEnabledMask,
1537                                                           (1 << pi->acp_boot_level));
1538         }
1539
1540         return kv_enable_acp_dpm(rdev, !gate);
1541 }
1542
1543 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
1544 {
1545         struct kv_power_info *pi = kv_get_pi(rdev);
1546
1547         if (pi->uvd_power_gated == gate)
1548                 return;
1549
1550         pi->uvd_power_gated = gate;
1551
1552         if (gate) {
1553                 if (pi->caps_uvd_pg) {
1554                         uvd_v1_0_stop(rdev);
1555                         cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
1556                 }
1557                 kv_update_uvd_dpm(rdev, gate);
1558                 if (pi->caps_uvd_pg)
1559                         kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF);
1560         } else {
1561                 if (pi->caps_uvd_pg) {
1562                         kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON);
1563                         uvd_v4_2_resume(rdev);
1564                         uvd_v1_0_start(rdev);
1565                         cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
1566                 }
1567                 kv_update_uvd_dpm(rdev, gate);
1568         }
1569 }
1570
1571 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate)
1572 {
1573         struct kv_power_info *pi = kv_get_pi(rdev);
1574
1575         if (pi->vce_power_gated == gate)
1576                 return;
1577
1578         pi->vce_power_gated = gate;
1579
1580         if (gate) {
1581                 if (pi->caps_vce_pg)
1582                         kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF);
1583         } else {
1584                 if (pi->caps_vce_pg)
1585                         kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON);
1586         }
1587 }
1588
1589 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate)
1590 {
1591         struct kv_power_info *pi = kv_get_pi(rdev);
1592
1593         if (pi->samu_power_gated == gate)
1594                 return;
1595
1596         pi->samu_power_gated = gate;
1597
1598         if (gate) {
1599                 kv_update_samu_dpm(rdev, true);
1600                 if (pi->caps_samu_pg)
1601                         kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF);
1602         } else {
1603                 if (pi->caps_samu_pg)
1604                         kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON);
1605                 kv_update_samu_dpm(rdev, false);
1606         }
1607 }
1608
1609 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate)
1610 {
1611         struct kv_power_info *pi = kv_get_pi(rdev);
1612
1613         if (pi->acp_power_gated == gate)
1614                 return;
1615
1616         if (rdev->family == CHIP_KABINI)
1617                 return;
1618
1619         pi->acp_power_gated = gate;
1620
1621         if (gate) {
1622                 kv_update_acp_dpm(rdev, true);
1623                 if (pi->caps_acp_pg)
1624                         kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF);
1625         } else {
1626                 if (pi->caps_acp_pg)
1627                         kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON);
1628                 kv_update_acp_dpm(rdev, false);
1629         }
1630 }
1631
1632 static void kv_set_valid_clock_range(struct radeon_device *rdev,
1633                                      struct radeon_ps *new_rps)
1634 {
1635         struct kv_ps *new_ps = kv_get_ps(new_rps);
1636         struct kv_power_info *pi = kv_get_pi(rdev);
1637         u32 i;
1638         struct radeon_clock_voltage_dependency_table *table =
1639                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1640
1641         if (table && table->count) {
1642                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1643                         if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1644                             (i == (pi->graphics_dpm_level_count - 1))) {
1645                                 pi->lowest_valid = i;
1646                                 break;
1647                         }
1648                 }
1649
1650                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1651                         if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1652                                 break;
1653                 }
1654                 pi->highest_valid = i;
1655
1656                 if (pi->lowest_valid > pi->highest_valid) {
1657                         if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1658                             (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1659                                 pi->highest_valid = pi->lowest_valid;
1660                         else
1661                                 pi->lowest_valid =  pi->highest_valid;
1662                 }
1663         } else {
1664                 struct sumo_sclk_voltage_mapping_table *table =
1665                         &pi->sys_info.sclk_voltage_mapping_table;
1666
1667                 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1668                         if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1669                             i == (int)(pi->graphics_dpm_level_count - 1)) {
1670                                 pi->lowest_valid = i;
1671                                 break;
1672                         }
1673                 }
1674
1675                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1676                         if (table->entries[i].sclk_frequency <=
1677                             new_ps->levels[new_ps->num_levels - 1].sclk)
1678                                 break;
1679                 }
1680                 pi->highest_valid = i;
1681
1682                 if (pi->lowest_valid > pi->highest_valid) {
1683                         if ((new_ps->levels[0].sclk -
1684                              table->entries[pi->highest_valid].sclk_frequency) >
1685                             (table->entries[pi->lowest_valid].sclk_frequency -
1686                              new_ps->levels[new_ps->num_levels -1].sclk))
1687                                 pi->highest_valid = pi->lowest_valid;
1688                         else
1689                                 pi->lowest_valid =  pi->highest_valid;
1690                 }
1691         }
1692 }
1693
1694 static int kv_update_dfs_bypass_settings(struct radeon_device *rdev,
1695                                          struct radeon_ps *new_rps)
1696 {
1697         struct kv_ps *new_ps = kv_get_ps(new_rps);
1698         struct kv_power_info *pi = kv_get_pi(rdev);
1699         int ret = 0;
1700         u8 clk_bypass_cntl;
1701
1702         if (pi->caps_enable_dfs_bypass) {
1703                 clk_bypass_cntl = new_ps->need_dfs_bypass ?
1704                         pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1705                 ret = kv_copy_bytes_to_smc(rdev,
1706                                            (pi->dpm_table_start +
1707                                             offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
1708                                             (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1709                                             offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
1710                                            &clk_bypass_cntl,
1711                                            sizeof(u8), pi->sram_end);
1712         }
1713
1714         return ret;
1715 }
1716
1717 static int kv_enable_nb_dpm(struct radeon_device *rdev)
1718 {
1719         struct kv_power_info *pi = kv_get_pi(rdev);
1720         int ret = 0;
1721
1722         if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1723                 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1724                 if (ret == 0)
1725                         pi->nb_dpm_enabled = true;
1726         }
1727
1728         return ret;
1729 }
1730
1731 int kv_dpm_force_performance_level(struct radeon_device *rdev,
1732                                    enum radeon_dpm_forced_level level)
1733 {
1734         int ret;
1735
1736         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1737                 ret = kv_force_dpm_highest(rdev);
1738                 if (ret)
1739                         return ret;
1740         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1741                 ret = kv_force_dpm_lowest(rdev);
1742                 if (ret)
1743                         return ret;
1744         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
1745                 ret = kv_unforce_levels(rdev);
1746                 if (ret)
1747                         return ret;
1748         }
1749
1750         rdev->pm.dpm.forced_level = level;
1751
1752         return 0;
1753 }
1754
1755 int kv_dpm_pre_set_power_state(struct radeon_device *rdev)
1756 {
1757         struct kv_power_info *pi = kv_get_pi(rdev);
1758         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1759         struct radeon_ps *new_ps = &requested_ps;
1760
1761         kv_update_requested_ps(rdev, new_ps);
1762
1763         kv_apply_state_adjust_rules(rdev,
1764                                     &pi->requested_rps,
1765                                     &pi->current_rps);
1766
1767         return 0;
1768 }
1769
1770 int kv_dpm_set_power_state(struct radeon_device *rdev)
1771 {
1772         struct kv_power_info *pi = kv_get_pi(rdev);
1773         struct radeon_ps *new_ps = &pi->requested_rps;
1774         /*struct radeon_ps *old_ps = &pi->current_rps;*/
1775         int ret;
1776
1777         cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1778                              RADEON_CG_BLOCK_SDMA |
1779                              RADEON_CG_BLOCK_BIF |
1780                              RADEON_CG_BLOCK_HDP), false);
1781
1782         if (pi->bapm_enable) {
1783                 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power);
1784                 if (ret) {
1785                         DRM_ERROR("kv_smc_bapm_enable failed\n");
1786                         return ret;
1787                 }
1788         }
1789
1790         if (rdev->family == CHIP_KABINI) {
1791                 if (pi->enable_dpm) {
1792                         kv_set_valid_clock_range(rdev, new_ps);
1793                         kv_update_dfs_bypass_settings(rdev, new_ps);
1794                         ret = kv_calculate_ds_divider(rdev);
1795                         if (ret) {
1796                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1797                                 return ret;
1798                         }
1799                         kv_calculate_nbps_level_settings(rdev);
1800                         kv_calculate_dpm_settings(rdev);
1801                         kv_force_lowest_valid(rdev);
1802                         kv_enable_new_levels(rdev);
1803                         kv_upload_dpm_settings(rdev);
1804                         kv_program_nbps_index_settings(rdev, new_ps);
1805                         kv_unforce_levels(rdev);
1806                         kv_set_enabled_levels(rdev);
1807                         kv_force_lowest_valid(rdev);
1808                         kv_unforce_levels(rdev);
1809 #if 0
1810                         ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1811                         if (ret) {
1812                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1813                                 return ret;
1814                         }
1815 #endif
1816                         kv_update_sclk_t(rdev);
1817                 }
1818         } else {
1819                 if (pi->enable_dpm) {
1820                         kv_set_valid_clock_range(rdev, new_ps);
1821                         kv_update_dfs_bypass_settings(rdev, new_ps);
1822                         ret = kv_calculate_ds_divider(rdev);
1823                         if (ret) {
1824                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1825                                 return ret;
1826                         }
1827                         kv_calculate_nbps_level_settings(rdev);
1828                         kv_calculate_dpm_settings(rdev);
1829                         kv_freeze_sclk_dpm(rdev, true);
1830                         kv_upload_dpm_settings(rdev);
1831                         kv_program_nbps_index_settings(rdev, new_ps);
1832                         kv_freeze_sclk_dpm(rdev, false);
1833                         kv_set_enabled_levels(rdev);
1834 #if 0
1835                         ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1836                         if (ret) {
1837                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1838                                 return ret;
1839                         }
1840 #endif
1841                         kv_update_acp_boot_level(rdev);
1842                         kv_update_sclk_t(rdev);
1843                         kv_enable_nb_dpm(rdev);
1844                 }
1845         }
1846
1847         cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1848                              RADEON_CG_BLOCK_SDMA |
1849                              RADEON_CG_BLOCK_BIF |
1850                              RADEON_CG_BLOCK_HDP), true);
1851
1852         return 0;
1853 }
1854
1855 void kv_dpm_post_set_power_state(struct radeon_device *rdev)
1856 {
1857         struct kv_power_info *pi = kv_get_pi(rdev);
1858         struct radeon_ps *new_ps = &pi->requested_rps;
1859
1860         kv_update_current_ps(rdev, new_ps);
1861 }
1862
1863 void kv_dpm_setup_asic(struct radeon_device *rdev)
1864 {
1865         sumo_take_smu_control(rdev, true);
1866         kv_init_powergate_state(rdev);
1867         kv_init_sclk_t(rdev);
1868 }
1869
1870 void kv_dpm_reset_asic(struct radeon_device *rdev)
1871 {
1872         struct kv_power_info *pi = kv_get_pi(rdev);
1873
1874         if (rdev->family == CHIP_KABINI) {
1875                 kv_force_lowest_valid(rdev);
1876                 kv_init_graphics_levels(rdev);
1877                 kv_program_bootup_state(rdev);
1878                 kv_upload_dpm_settings(rdev);
1879                 kv_force_lowest_valid(rdev);
1880                 kv_unforce_levels(rdev);
1881         } else {
1882                 kv_init_graphics_levels(rdev);
1883                 kv_program_bootup_state(rdev);
1884                 kv_freeze_sclk_dpm(rdev, true);
1885                 kv_upload_dpm_settings(rdev);
1886                 kv_freeze_sclk_dpm(rdev, false);
1887                 kv_set_enabled_level(rdev, pi->graphics_boot_level);
1888         }
1889 }
1890
1891 //XXX use sumo_dpm_display_configuration_changed
1892
1893 static void kv_construct_max_power_limits_table(struct radeon_device *rdev,
1894                                                 struct radeon_clock_and_voltage_limits *table)
1895 {
1896         struct kv_power_info *pi = kv_get_pi(rdev);
1897
1898         if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
1899                 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
1900                 table->sclk =
1901                         pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
1902                 table->vddc =
1903                         kv_convert_2bit_index_to_voltage(rdev,
1904                                                          pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
1905         }
1906
1907         table->mclk = pi->sys_info.nbp_memory_clock[0];
1908 }
1909
1910 static void kv_patch_voltage_values(struct radeon_device *rdev)
1911 {
1912         int i;
1913         struct radeon_uvd_clock_voltage_dependency_table *table =
1914                 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1915
1916         if (table->count) {
1917                 for (i = 0; i < table->count; i++)
1918                         table->entries[i].v =
1919                                 kv_convert_8bit_index_to_voltage(rdev,
1920                                                                  table->entries[i].v);
1921         }
1922
1923 }
1924
1925 static void kv_construct_boot_state(struct radeon_device *rdev)
1926 {
1927         struct kv_power_info *pi = kv_get_pi(rdev);
1928
1929         pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1930         pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1931         pi->boot_pl.ds_divider_index = 0;
1932         pi->boot_pl.ss_divider_index = 0;
1933         pi->boot_pl.allow_gnb_slow = 1;
1934         pi->boot_pl.force_nbp_state = 0;
1935         pi->boot_pl.display_wm = 0;
1936         pi->boot_pl.vce_wm = 0;
1937 }
1938
1939 static int kv_force_dpm_highest(struct radeon_device *rdev)
1940 {
1941         int ret;
1942         u32 enable_mask, i;
1943
1944         ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1945         if (ret)
1946                 return ret;
1947
1948         for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
1949                 if (enable_mask & (1 << i))
1950                         break;
1951         }
1952
1953         if (rdev->family == CHIP_KABINI)
1954                 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1955         else
1956                 return kv_set_enabled_level(rdev, i);
1957 }
1958
1959 static int kv_force_dpm_lowest(struct radeon_device *rdev)
1960 {
1961         int ret;
1962         u32 enable_mask, i;
1963
1964         ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1965         if (ret)
1966                 return ret;
1967
1968         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
1969                 if (enable_mask & (1 << i))
1970                         break;
1971         }
1972
1973         if (rdev->family == CHIP_KABINI)
1974                 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1975         else
1976                 return kv_set_enabled_level(rdev, i);
1977 }
1978
1979 static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1980                                              u32 sclk, u32 min_sclk_in_sr)
1981 {
1982         struct kv_power_info *pi = kv_get_pi(rdev);
1983         u32 i;
1984         u32 temp;
1985         u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ?
1986                 min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK;
1987
1988         if (sclk < min)
1989                 return 0;
1990
1991         if (!pi->caps_sclk_ds)
1992                 return 0;
1993
1994         for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
1995                 temp = sclk / sumo_get_sleep_divider_from_id(i);
1996                 if (temp >= min)
1997                         break;
1998         }
1999
2000         return (u8)i;
2001 }
2002
2003 static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit)
2004 {
2005         struct kv_power_info *pi = kv_get_pi(rdev);
2006         struct radeon_clock_voltage_dependency_table *table =
2007                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2008         int i;
2009
2010         if (table && table->count) {
2011                 for (i = table->count - 1; i >= 0; i--) {
2012                         if (pi->high_voltage_t &&
2013                             (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=
2014                              pi->high_voltage_t)) {
2015                                 *limit = i;
2016                                 return 0;
2017                         }
2018                 }
2019         } else {
2020                 struct sumo_sclk_voltage_mapping_table *table =
2021                         &pi->sys_info.sclk_voltage_mapping_table;
2022
2023                 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
2024                         if (pi->high_voltage_t &&
2025                             (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <=
2026                              pi->high_voltage_t)) {
2027                                 *limit = i;
2028                                 return 0;
2029                         }
2030                 }
2031         }
2032
2033         *limit = 0;
2034         return 0;
2035 }
2036
2037 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
2038                                         struct radeon_ps *new_rps,
2039                                         struct radeon_ps *old_rps)
2040 {
2041         struct kv_ps *ps = kv_get_ps(new_rps);
2042         struct kv_power_info *pi = kv_get_pi(rdev);
2043         u32 min_sclk = 10000; /* ??? */
2044         u32 sclk, mclk = 0;
2045         int i, limit;
2046         bool force_high;
2047         struct radeon_clock_voltage_dependency_table *table =
2048                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2049         u32 stable_p_state_sclk = 0;
2050         struct radeon_clock_and_voltage_limits *max_limits =
2051                 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2052
2053         mclk = max_limits->mclk;
2054         sclk = min_sclk;
2055
2056         if (pi->caps_stable_p_state) {
2057                 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
2058
2059                 for (i = table->count - 1; i >= 0; i++) {
2060                         if (stable_p_state_sclk >= table->entries[i].clk) {
2061                                 stable_p_state_sclk = table->entries[i].clk;
2062                                 break;
2063                         }
2064                 }
2065
2066                 if (i > 0)
2067                         stable_p_state_sclk = table->entries[0].clk;
2068
2069                 sclk = stable_p_state_sclk;
2070         }
2071
2072         ps->need_dfs_bypass = true;
2073
2074         for (i = 0; i < ps->num_levels; i++) {
2075                 if (ps->levels[i].sclk < sclk)
2076                         ps->levels[i].sclk = sclk;
2077         }
2078
2079         if (table && table->count) {
2080                 for (i = 0; i < ps->num_levels; i++) {
2081                         if (pi->high_voltage_t &&
2082                             (pi->high_voltage_t <
2083                              kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2084                                 kv_get_high_voltage_limit(rdev, &limit);
2085                                 ps->levels[i].sclk = table->entries[limit].clk;
2086                         }
2087                 }
2088         } else {
2089                 struct sumo_sclk_voltage_mapping_table *table =
2090                         &pi->sys_info.sclk_voltage_mapping_table;
2091
2092                 for (i = 0; i < ps->num_levels; i++) {
2093                         if (pi->high_voltage_t &&
2094                             (pi->high_voltage_t <
2095                              kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2096                                 kv_get_high_voltage_limit(rdev, &limit);
2097                                 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
2098                         }
2099                 }
2100         }
2101
2102         if (pi->caps_stable_p_state) {
2103                 for (i = 0; i < ps->num_levels; i++) {
2104                         ps->levels[i].sclk = stable_p_state_sclk;
2105                 }
2106         }
2107
2108         pi->video_start = new_rps->dclk || new_rps->vclk;
2109
2110         if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
2111             ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
2112                 pi->battery_state = true;
2113         else
2114                 pi->battery_state = false;
2115
2116         if (rdev->family == CHIP_KABINI) {
2117                 ps->dpm0_pg_nb_ps_lo = 0x1;
2118                 ps->dpm0_pg_nb_ps_hi = 0x0;
2119                 ps->dpmx_nb_ps_lo = 0x1;
2120                 ps->dpmx_nb_ps_hi = 0x0;
2121         } else {
2122                 ps->dpm0_pg_nb_ps_lo = 0x3;
2123                 ps->dpm0_pg_nb_ps_hi = 0x0;
2124                 ps->dpmx_nb_ps_lo = 0x3;
2125                 ps->dpmx_nb_ps_hi = 0x0;
2126
2127                 if (pi->sys_info.nb_dpm_enable) {
2128                         force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2129                                 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
2130                                 pi->disable_nb_ps3_in_battery;
2131                         ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
2132                         ps->dpm0_pg_nb_ps_hi = 0x2;
2133                         ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
2134                         ps->dpmx_nb_ps_hi = 0x2;
2135                 }
2136         }
2137 }
2138
2139 static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev,
2140                                                     u32 index, bool enable)
2141 {
2142         struct kv_power_info *pi = kv_get_pi(rdev);
2143
2144         pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2145 }
2146
2147 static int kv_calculate_ds_divider(struct radeon_device *rdev)
2148 {
2149         struct kv_power_info *pi = kv_get_pi(rdev);
2150         u32 sclk_in_sr = 10000; /* ??? */
2151         u32 i;
2152
2153         if (pi->lowest_valid > pi->highest_valid)
2154                 return -EINVAL;
2155
2156         for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2157                 pi->graphics_level[i].DeepSleepDivId =
2158                         kv_get_sleep_divider_id_from_clock(rdev,
2159                                                            be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2160                                                            sclk_in_sr);
2161         }
2162         return 0;
2163 }
2164
2165 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev)
2166 {
2167         struct kv_power_info *pi = kv_get_pi(rdev);
2168         u32 i;
2169         bool force_high;
2170         struct radeon_clock_and_voltage_limits *max_limits =
2171                 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2172         u32 mclk = max_limits->mclk;
2173
2174         if (pi->lowest_valid > pi->highest_valid)
2175                 return -EINVAL;
2176
2177         if (rdev->family == CHIP_KABINI) {
2178                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2179                         pi->graphics_level[i].GnbSlow = 1;
2180                         pi->graphics_level[i].ForceNbPs1 = 0;
2181                         pi->graphics_level[i].UpH = 0;
2182                 }
2183
2184                 if (!pi->sys_info.nb_dpm_enable)
2185                         return 0;
2186
2187                 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2188                               (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2189
2190                 if (force_high) {
2191                         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2192                                 pi->graphics_level[i].GnbSlow = 0;
2193                 } else {
2194                         if (pi->battery_state)
2195                                 pi->graphics_level[0].ForceNbPs1 = 1;
2196
2197                         pi->graphics_level[1].GnbSlow = 0;
2198                         pi->graphics_level[2].GnbSlow = 0;
2199                         pi->graphics_level[3].GnbSlow = 0;
2200                         pi->graphics_level[4].GnbSlow = 0;
2201                 }
2202         } else {
2203                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2204                         pi->graphics_level[i].GnbSlow = 1;
2205                         pi->graphics_level[i].ForceNbPs1 = 0;
2206                         pi->graphics_level[i].UpH = 0;
2207                 }
2208
2209                 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2210                         pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2211                         pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2212                         if (pi->lowest_valid != pi->highest_valid)
2213                                 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2214                 }
2215         }
2216         return 0;
2217 }
2218
2219 static int kv_calculate_dpm_settings(struct radeon_device *rdev)
2220 {
2221         struct kv_power_info *pi = kv_get_pi(rdev);
2222         u32 i;
2223
2224         if (pi->lowest_valid > pi->highest_valid)
2225                 return -EINVAL;
2226
2227         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2228                 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2229
2230         return 0;
2231 }
2232
2233 static void kv_init_graphics_levels(struct radeon_device *rdev)
2234 {
2235         struct kv_power_info *pi = kv_get_pi(rdev);
2236         u32 i;
2237         struct radeon_clock_voltage_dependency_table *table =
2238                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2239
2240         if (table && table->count) {
2241                 u32 vid_2bit;
2242
2243                 pi->graphics_dpm_level_count = 0;
2244                 for (i = 0; i < table->count; i++) {
2245                         if (pi->high_voltage_t &&
2246                             (pi->high_voltage_t <
2247                              kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))
2248                                 break;
2249
2250                         kv_set_divider_value(rdev, i, table->entries[i].clk);
2251                         vid_2bit = sumo_convert_vid7_to_vid2(rdev,
2252                                                              &pi->sys_info.vid_mapping_table,
2253                                                              table->entries[i].v);
2254                         kv_set_vid(rdev, i, vid_2bit);
2255                         kv_set_at(rdev, i, pi->at[i]);
2256                         kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2257                         pi->graphics_dpm_level_count++;
2258                 }
2259         } else {
2260                 struct sumo_sclk_voltage_mapping_table *table =
2261                         &pi->sys_info.sclk_voltage_mapping_table;
2262
2263                 pi->graphics_dpm_level_count = 0;
2264                 for (i = 0; i < table->num_max_dpm_entries; i++) {
2265                         if (pi->high_voltage_t &&
2266                             pi->high_voltage_t <
2267                             kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit))
2268                                 break;
2269
2270                         kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency);
2271                         kv_set_vid(rdev, i, table->entries[i].vid_2bit);
2272                         kv_set_at(rdev, i, pi->at[i]);
2273                         kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2274                         pi->graphics_dpm_level_count++;
2275                 }
2276         }
2277
2278         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
2279                 kv_dpm_power_level_enable(rdev, i, false);
2280 }
2281
2282 static void kv_enable_new_levels(struct radeon_device *rdev)
2283 {
2284         struct kv_power_info *pi = kv_get_pi(rdev);
2285         u32 i;
2286
2287         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2288                 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2289                         kv_dpm_power_level_enable(rdev, i, true);
2290         }
2291 }
2292
2293 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level)
2294 {
2295         u32 new_mask = (1 << level);
2296
2297         return kv_send_msg_to_smc_with_parameter(rdev,
2298                                                  PPSMC_MSG_SCLKDPM_SetEnabledMask,
2299                                                  new_mask);
2300 }
2301
2302 static int kv_set_enabled_levels(struct radeon_device *rdev)
2303 {
2304         struct kv_power_info *pi = kv_get_pi(rdev);
2305         u32 i, new_mask = 0;
2306
2307         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2308                 new_mask |= (1 << i);
2309
2310         return kv_send_msg_to_smc_with_parameter(rdev,
2311                                                  PPSMC_MSG_SCLKDPM_SetEnabledMask,
2312                                                  new_mask);
2313 }
2314
2315 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
2316                                            struct radeon_ps *new_rps)
2317 {
2318         struct kv_ps *new_ps = kv_get_ps(new_rps);
2319         struct kv_power_info *pi = kv_get_pi(rdev);
2320         u32 nbdpmconfig1;
2321
2322         if (rdev->family == CHIP_KABINI)
2323                 return;
2324
2325         if (pi->sys_info.nb_dpm_enable) {
2326                 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1);
2327                 nbdpmconfig1 &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK |
2328                                   DpmXNbPsLo_MASK | DpmXNbPsHi_MASK);
2329                 nbdpmconfig1 |= (Dpm0PgNbPsLo(new_ps->dpm0_pg_nb_ps_lo) |
2330                                  Dpm0PgNbPsHi(new_ps->dpm0_pg_nb_ps_hi) |
2331                                  DpmXNbPsLo(new_ps->dpmx_nb_ps_lo) |
2332                                  DpmXNbPsHi(new_ps->dpmx_nb_ps_hi));
2333                 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1);
2334         }
2335 }
2336
2337 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
2338                                             int min_temp, int max_temp)
2339 {
2340         int low_temp = 0 * 1000;
2341         int high_temp = 255 * 1000;
2342         u32 tmp;
2343
2344         if (low_temp < min_temp)
2345                 low_temp = min_temp;
2346         if (high_temp > max_temp)
2347                 high_temp = max_temp;
2348         if (high_temp < low_temp) {
2349                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
2350                 return -EINVAL;
2351         }
2352
2353         tmp = RREG32_SMC(CG_THERMAL_INT_CTRL);
2354         tmp &= ~(DIG_THERM_INTH_MASK | DIG_THERM_INTL_MASK);
2355         tmp |= (DIG_THERM_INTH(49 + (high_temp / 1000)) |
2356                 DIG_THERM_INTL(49 + (low_temp / 1000)));
2357         WREG32_SMC(CG_THERMAL_INT_CTRL, tmp);
2358
2359         rdev->pm.dpm.thermal.min_temp = low_temp;
2360         rdev->pm.dpm.thermal.max_temp = high_temp;
2361
2362         return 0;
2363 }
2364
2365 union igp_info {
2366         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
2367         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2368         struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
2369         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
2370         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
2371         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
2372 };
2373
2374 static int kv_parse_sys_info_table(struct radeon_device *rdev)
2375 {
2376         struct kv_power_info *pi = kv_get_pi(rdev);
2377         struct radeon_mode_info *mode_info = &rdev->mode_info;
2378         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
2379         union igp_info *igp_info;
2380         u8 frev, crev;
2381         u16 data_offset;
2382         int i;
2383
2384         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2385                                    &frev, &crev, &data_offset)) {
2386                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
2387                                               data_offset);
2388
2389                 if (crev != 8) {
2390                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
2391                         return -EINVAL;
2392                 }
2393                 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2394                 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2395                 pi->sys_info.bootup_nb_voltage_index =
2396                         le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
2397                 if (igp_info->info_8.ucHtcTmpLmt == 0)
2398                         pi->sys_info.htc_tmp_lmt = 203;
2399                 else
2400                         pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2401                 if (igp_info->info_8.ucHtcHystLmt == 0)
2402                         pi->sys_info.htc_hyst_lmt = 5;
2403                 else
2404                         pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2405                 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2406                         DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2407                 }
2408
2409                 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
2410                         pi->sys_info.nb_dpm_enable = true;
2411                 else
2412                         pi->sys_info.nb_dpm_enable = false;
2413
2414                 for (i = 0; i < KV_NUM_NBPSTATES; i++) {
2415                         pi->sys_info.nbp_memory_clock[i] =
2416                                 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
2417                         pi->sys_info.nbp_n_clock[i] =
2418                                 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
2419                 }
2420                 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
2421                     SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
2422                         pi->caps_enable_dfs_bypass = true;
2423
2424                 sumo_construct_sclk_voltage_mapping_table(rdev,
2425                                                           &pi->sys_info.sclk_voltage_mapping_table,
2426                                                           igp_info->info_8.sAvail_SCLK);
2427
2428                 sumo_construct_vid_mapping_table(rdev,
2429                                                  &pi->sys_info.vid_mapping_table,
2430                                                  igp_info->info_8.sAvail_SCLK);
2431
2432                 kv_construct_max_power_limits_table(rdev,
2433                                                     &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2434         }
2435         return 0;
2436 }
2437
2438 union power_info {
2439         struct _ATOM_POWERPLAY_INFO info;
2440         struct _ATOM_POWERPLAY_INFO_V2 info_2;
2441         struct _ATOM_POWERPLAY_INFO_V3 info_3;
2442         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2443         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2444         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2445 };
2446
2447 union pplib_clock_info {
2448         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2449         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2450         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2451         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2452 };
2453
2454 union pplib_power_state {
2455         struct _ATOM_PPLIB_STATE v1;
2456         struct _ATOM_PPLIB_STATE_V2 v2;
2457 };
2458
2459 static void kv_patch_boot_state(struct radeon_device *rdev,
2460                                 struct kv_ps *ps)
2461 {
2462         struct kv_power_info *pi = kv_get_pi(rdev);
2463
2464         ps->num_levels = 1;
2465         ps->levels[0] = pi->boot_pl;
2466 }
2467
2468 static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev,
2469                                           struct radeon_ps *rps,
2470                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2471                                           u8 table_rev)
2472 {
2473         struct kv_ps *ps = kv_get_ps(rps);
2474
2475         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2476         rps->class = le16_to_cpu(non_clock_info->usClassification);
2477         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2478
2479         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2480                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2481                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2482         } else {
2483                 rps->vclk = 0;
2484                 rps->dclk = 0;
2485         }
2486
2487         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2488                 rdev->pm.dpm.boot_ps = rps;
2489                 kv_patch_boot_state(rdev, ps);
2490         }
2491         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2492                 rdev->pm.dpm.uvd_ps = rps;
2493 }
2494
2495 static void kv_parse_pplib_clock_info(struct radeon_device *rdev,
2496                                       struct radeon_ps *rps, int index,
2497                                         union pplib_clock_info *clock_info)
2498 {
2499         struct kv_power_info *pi = kv_get_pi(rdev);
2500         struct kv_ps *ps = kv_get_ps(rps);
2501         struct kv_pl *pl = &ps->levels[index];
2502         u32 sclk;
2503
2504         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2505         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2506         pl->sclk = sclk;
2507         pl->vddc_index = clock_info->sumo.vddcIndex;
2508
2509         ps->num_levels = index + 1;
2510
2511         if (pi->caps_sclk_ds) {
2512                 pl->ds_divider_index = 5;
2513                 pl->ss_divider_index = 5;
2514         }
2515 }
2516
2517 static int kv_parse_power_table(struct radeon_device *rdev)
2518 {
2519         struct radeon_mode_info *mode_info = &rdev->mode_info;
2520         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2521         union pplib_power_state *power_state;
2522         int i, j, k, non_clock_array_index, clock_array_index;
2523         union pplib_clock_info *clock_info;
2524         struct _StateArray *state_array;
2525         struct _ClockInfoArray *clock_info_array;
2526         struct _NonClockInfoArray *non_clock_info_array;
2527         union power_info *power_info;
2528         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2529         u16 data_offset;
2530         u8 frev, crev;
2531         u8 *power_state_offset;
2532         struct kv_ps *ps;
2533
2534         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2535                                    &frev, &crev, &data_offset))
2536                 return -EINVAL;
2537         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2538
2539         state_array = (struct _StateArray *)
2540                 (mode_info->atom_context->bios + data_offset +
2541                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2542         clock_info_array = (struct _ClockInfoArray *)
2543                 (mode_info->atom_context->bios + data_offset +
2544                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2545         non_clock_info_array = (struct _NonClockInfoArray *)
2546                 (mode_info->atom_context->bios + data_offset +
2547                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2548
2549         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
2550                                   state_array->ucNumEntries, GFP_KERNEL);
2551         if (!rdev->pm.dpm.ps)
2552                 return -ENOMEM;
2553         power_state_offset = (u8 *)state_array->states;
2554         rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
2555         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
2556         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
2557         for (i = 0; i < state_array->ucNumEntries; i++) {
2558                 u8 *idx;
2559                 power_state = (union pplib_power_state *)power_state_offset;
2560                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2561                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2562                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2563                 if (!rdev->pm.power_state[i].clock_info)
2564                         return -EINVAL;
2565                 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
2566                 if (ps == NULL) {
2567                         kfree(rdev->pm.dpm.ps);
2568                         return -ENOMEM;
2569                 }
2570                 rdev->pm.dpm.ps[i].ps_priv = ps;
2571                 k = 0;
2572                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
2573                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2574                         clock_array_index = idx[j];
2575                         if (clock_array_index >= clock_info_array->ucNumEntries)
2576                                 continue;
2577                         if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
2578                                 break;
2579                         clock_info = (union pplib_clock_info *)
2580                                 ((u8 *)&clock_info_array->clockInfo[0] +
2581                                  (clock_array_index * clock_info_array->ucEntrySize));
2582                         kv_parse_pplib_clock_info(rdev,
2583                                                   &rdev->pm.dpm.ps[i], k,
2584                                                   clock_info);
2585                         k++;
2586                 }
2587                 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
2588                                               non_clock_info,
2589                                               non_clock_info_array->ucEntrySize);
2590                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2591         }
2592         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
2593         return 0;
2594 }
2595
2596 int kv_dpm_init(struct radeon_device *rdev)
2597 {
2598         struct kv_power_info *pi;
2599         int ret, i;
2600
2601         pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2602         if (pi == NULL)
2603                 return -ENOMEM;
2604         rdev->pm.dpm.priv = pi;
2605
2606         ret = r600_parse_extended_power_table(rdev);
2607         if (ret)
2608                 return ret;
2609
2610         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
2611                 pi->at[i] = TRINITY_AT_DFLT;
2612
2613         pi->sram_end = SMC_RAM_END;
2614
2615         if (rdev->family == CHIP_KABINI)
2616                 pi->high_voltage_t = 4001;
2617
2618         pi->enable_nb_dpm = true;
2619
2620         pi->caps_power_containment = true;
2621         pi->caps_cac = true;
2622         pi->enable_didt = false;
2623         if (pi->enable_didt) {
2624                 pi->caps_sq_ramping = true;
2625                 pi->caps_db_ramping = true;
2626                 pi->caps_td_ramping = true;
2627                 pi->caps_tcp_ramping = true;
2628         }
2629
2630         pi->caps_sclk_ds = true;
2631         pi->enable_auto_thermal_throttling = true;
2632         pi->disable_nb_ps3_in_battery = false;
2633         pi->bapm_enable = false;
2634         pi->voltage_drop_t = 0;
2635         pi->caps_sclk_throttle_low_notification = false;
2636         pi->caps_fps = false; /* true? */
2637         pi->caps_uvd_pg = true;
2638         pi->caps_uvd_dpm = true;
2639         pi->caps_vce_pg = false;
2640         pi->caps_samu_pg = false;
2641         pi->caps_acp_pg = false;
2642         pi->caps_stable_p_state = false;
2643
2644         ret = kv_parse_sys_info_table(rdev);
2645         if (ret)
2646                 return ret;
2647
2648         kv_patch_voltage_values(rdev);
2649         kv_construct_boot_state(rdev);
2650
2651         ret = kv_parse_power_table(rdev);
2652         if (ret)
2653                 return ret;
2654
2655         pi->enable_dpm = true;
2656
2657         return 0;
2658 }
2659
2660 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2661                                                     struct seq_file *m)
2662 {
2663         struct kv_power_info *pi = kv_get_pi(rdev);
2664         u32 current_index =
2665                 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>
2666                 CURR_SCLK_INDEX_SHIFT;
2667         u32 sclk, tmp;
2668         u16 vddc;
2669
2670         if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2671                 seq_printf(m, "invalid dpm profile %d\n", current_index);
2672         } else {
2673                 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2674                 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2675                         SMU_VOLTAGE_CURRENT_LEVEL_SHIFT;
2676                 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
2677                 seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
2678                            current_index, sclk, vddc);
2679         }
2680 }
2681
2682 void kv_dpm_print_power_state(struct radeon_device *rdev,
2683                               struct radeon_ps *rps)
2684 {
2685         int i;
2686         struct kv_ps *ps = kv_get_ps(rps);
2687
2688         r600_dpm_print_class_info(rps->class, rps->class2);
2689         r600_dpm_print_cap_info(rps->caps);
2690         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2691         for (i = 0; i < ps->num_levels; i++) {
2692                 struct kv_pl *pl = &ps->levels[i];
2693                 printk("\t\tpower level %d    sclk: %u vddc: %u\n",
2694                        i, pl->sclk,
2695                        kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index));
2696         }
2697         r600_dpm_print_ps_status(rdev, rps);
2698 }
2699
2700 void kv_dpm_fini(struct radeon_device *rdev)
2701 {
2702         int i;
2703
2704         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2705                 kfree(rdev->pm.dpm.ps[i].ps_priv);
2706         }
2707         kfree(rdev->pm.dpm.ps);
2708         kfree(rdev->pm.dpm.priv);
2709         r600_free_extended_power_table(rdev);
2710 }
2711
2712 void kv_dpm_display_configuration_changed(struct radeon_device *rdev)
2713 {
2714
2715 }
2716
2717 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low)
2718 {
2719         struct kv_power_info *pi = kv_get_pi(rdev);
2720         struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2721
2722         if (low)
2723                 return requested_state->levels[0].sclk;
2724         else
2725                 return requested_state->levels[requested_state->num_levels - 1].sclk;
2726 }
2727
2728 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low)
2729 {
2730         struct kv_power_info *pi = kv_get_pi(rdev);
2731
2732         return pi->sys_info.bootup_uma_clk;
2733 }