2 * Copyright (c) 2004 David O'Brien <obrien@FreeBSD.org>
3 * Copyright (c) 2003 Orlando Bassotto <orlando.bassotto@ieo-research.it>
4 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifdef HAVE_KERNEL_OPTION_HEADERS
33 #include <dev/sound/pcm/sound.h>
34 #include <dev/sound/pcm/ac97.h>
35 #include <dev/sound/pci/emuxkireg.h>
37 #include <dev/pci/pcireg.h>
38 #include <dev/pci/pcivar.h>
39 #include <sys/queue.h>
41 SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/emu10k1.c 267581 2014-06-17 16:07:57Z jhb $");
43 /* -------------------------------------------------------------------- */
45 #define NUM_G 64 /* use all channels */
46 #define WAVEOUT_MAXBUFSIZE 32768
47 #define EMUPAGESIZE 4096 /* don't change */
48 #define EMUMAXPAGES (WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE)
49 #define EMU10K1_PCI_ID 0x00021102 /* 1102 => Creative Labs Vendor ID */
50 #define EMU10K2_PCI_ID 0x00041102
51 #define EMU10K3_PCI_ID 0x00081102
52 #define EMU_DEFAULT_BUFSZ 4096
53 #define EMU_MAX_CHANS 8
56 #define MAXREQVOICES 8
61 #define TMEMSIZE 256*1024
64 #define ENABLE 0xffffffff
65 #define DISABLE 0x00000000
66 #define ENV_ON EMU_CHAN_DCYSUSV_CHANNELENABLE_MASK
67 #define ENV_OFF 0x00 /* XXX: should this be 1? */
69 #define EMU_A_IOCFG_GPOUT_A 0x40
70 #define EMU_A_IOCFG_GPOUT_D 0x04
71 #define EMU_A_IOCFG_GPOUT_AD (EMU_A_IOCFG_GPOUT_A|EMU_A_IOCFG_GPOUT_D) /* EMU_A_IOCFG_GPOUT0 */
73 #define EMU_HCFG_GPOUT1 0x00000800
80 #define C_00000000 0x40
81 #define C_00000001 0x41
82 #define C_00000004 0x44
83 #define C_40000000 0x4d
84 /* Audigy constants */
85 #define A_C_00000000 0xc0
86 #define A_C_40000000 0xcd
89 #define FXBUS(x) (0x00 + (x))
90 #define EXTIN(x) (0x10 + (x))
91 #define EXTOUT(x) (0x20 + (x))
93 #define GPR(x) (EMU_FXGPREGBASE + (x))
94 #define A_EXTIN(x) (0x40 + (x))
95 #define A_FXBUS(x) (0x00 + (x))
96 #define A_EXTOUT(x) (0x60 + (x))
97 #define A_GPR(x) (EMU_A_FXGPREGBASE + (x))
100 #define FXBUS_PCM_LEFT 0x00
101 #define FXBUS_PCM_RIGHT 0x01
102 #define FXBUS_MIDI_LEFT 0x04
103 #define FXBUS_MIDI_RIGHT 0x05
104 #define FXBUS_MIDI_REVERB 0x0c
105 #define FXBUS_MIDI_CHORUS 0x0d
108 #define EXTIN_AC97_L 0x00
109 #define EXTIN_AC97_R 0x01
110 #define EXTIN_SPDIF_CD_L 0x02
111 #define EXTIN_SPDIF_CD_R 0x03
112 #define EXTIN_TOSLINK_L 0x06
113 #define EXTIN_TOSLINK_R 0x07
114 #define EXTIN_COAX_SPDIF_L 0x0a
115 #define EXTIN_COAX_SPDIF_R 0x0b
117 #define A_EXTIN_AC97_L 0x00
118 #define A_EXTIN_AC97_R 0x01
121 #define EXTOUT_AC97_L 0x00
122 #define EXTOUT_AC97_R 0x01
123 #define EXTOUT_TOSLINK_L 0x02
124 #define EXTOUT_TOSLINK_R 0x03
125 #define EXTOUT_AC97_CENTER 0x04
126 #define EXTOUT_AC97_LFE 0x05
127 #define EXTOUT_HEADPHONE_L 0x06
128 #define EXTOUT_HEADPHONE_R 0x07
129 #define EXTOUT_REAR_L 0x08
130 #define EXTOUT_REAR_R 0x09
131 #define EXTOUT_ADC_CAP_L 0x0a
132 #define EXTOUT_ADC_CAP_R 0x0b
133 #define EXTOUT_ACENTER 0x11
134 #define EXTOUT_ALFE 0x12
136 #define A_EXTOUT_FRONT_L 0x00
137 #define A_EXTOUT_FRONT_R 0x01
138 #define A_EXTOUT_CENTER 0x02
139 #define A_EXTOUT_LFE 0x03
140 #define A_EXTOUT_HEADPHONE_L 0x04
141 #define A_EXTOUT_HEADPHONE_R 0x05
142 #define A_EXTOUT_REAR_L 0x06
143 #define A_EXTOUT_REAR_R 0x07
144 #define A_EXTOUT_AFRONT_L 0x08
145 #define A_EXTOUT_AFRONT_R 0x09
146 #define A_EXTOUT_ACENTER 0x0a
147 #define A_EXTOUT_ALFE 0x0b
148 #define A_EXTOUT_AREAR_L 0x0e
149 #define A_EXTOUT_AREAR_R 0x0f
150 #define A_EXTOUT_AC97_L 0x10
151 #define A_EXTOUT_AC97_R 0x11
152 #define A_EXTOUT_ADC_CAP_L 0x16
153 #define A_EXTOUT_ADC_CAP_R 0x17
156 SLIST_ENTRY(emu_memblk) link;
159 u_int32_t pte_start, pte_size;
160 bus_dmamap_t buf_map;
164 u_int8_t bmap[EMUMAXPAGES / 8];
165 u_int32_t *ptb_pages;
167 bus_addr_t silent_page_addr;
168 bus_addr_t ptb_pages_addr;
169 bus_dmamap_t ptb_map;
170 bus_dmamap_t silent_map;
171 SLIST_HEAD(, emu_memblk) blocks;
176 unsigned int b16:1, stereo:1, busy:1, running:1, ismaster:1;
179 int fxrt1; /* FX routing */
180 int fxrt2; /* FX routing (only for audigy) */
182 struct emu_voice *slave;
183 struct pcm_channel *channel;
188 /* channel registers */
190 int spd, fmt, blksz, run;
191 struct emu_voice *master, *slave;
192 struct snd_dbuf *buffer;
193 struct pcm_channel *channel;
194 struct sc_info *parent;
198 int spd, fmt, run, blksz, num;
199 u_int32_t idxreg, basereg, sizereg, setupreg, irqmask;
200 struct snd_dbuf *buffer;
201 struct pcm_channel *channel;
202 struct sc_info *parent;
205 /* device private data */
209 u_int32_t tos_link:1, APS:1, audigy:1, audigy2:1;
210 u_int32_t addrmask; /* wider if audigy */
213 bus_space_handle_t sh;
214 bus_dma_tag_t parent_dmat;
216 struct resource *reg, *irq;
221 int timer, timerinterval;
225 struct emu_voice voice[64];
226 struct sc_pchinfo pch[EMU_MAX_CHANS];
227 struct sc_rchinfo rch[3];
230 /* -------------------------------------------------------------------- */
237 static int emu_init(struct sc_info *);
238 static void emu_intr(void *);
239 static void *emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr, bus_dmamap_t *map);
240 static void *emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr);
241 static int emu_memfree(struct sc_info *sc, void *buf);
242 static int emu_memstart(struct sc_info *sc, void *buf);
244 static void emu_vdump(struct sc_info *sc, struct emu_voice *v);
247 /* talk to the card */
248 static u_int32_t emu_rd(struct sc_info *, int, int);
249 static void emu_wr(struct sc_info *, int, u_int32_t, int);
251 /* -------------------------------------------------------------------- */
253 static u_int32_t emu_rfmt_ac97[] = {
254 SND_FORMAT(AFMT_S16_LE, 1, 0),
255 SND_FORMAT(AFMT_S16_LE, 2, 0),
259 static u_int32_t emu_rfmt_mic[] = {
260 SND_FORMAT(AFMT_U8, 1, 0),
264 static u_int32_t emu_rfmt_efx[] = {
265 SND_FORMAT(AFMT_S16_LE, 2, 0),
269 static struct pcmchan_caps emu_reccaps[3] = {
270 {8000, 48000, emu_rfmt_ac97, 0},
271 {8000, 8000, emu_rfmt_mic, 0},
272 {48000, 48000, emu_rfmt_efx, 0},
275 static u_int32_t emu_pfmt[] = {
276 SND_FORMAT(AFMT_U8, 1, 0),
277 SND_FORMAT(AFMT_U8, 2, 0),
278 SND_FORMAT(AFMT_S16_LE, 1, 0),
279 SND_FORMAT(AFMT_S16_LE, 2, 0),
283 static struct pcmchan_caps emu_playcaps = {4000, 48000, emu_pfmt, 0};
285 static int adcspeed[8] = {48000, 44100, 32000, 24000, 22050, 16000, 11025, 8000};
286 /* audigy supports 12kHz. */
287 static int audigy_adcspeed[9] = {
288 48000, 44100, 32000, 24000, 22050, 16000, 12000, 11025, 8000
291 /* -------------------------------------------------------------------- */
294 emu_rd(struct sc_info *sc, int regno, int size)
298 return bus_space_read_1(sc->st, sc->sh, regno);
300 return bus_space_read_2(sc->st, sc->sh, regno);
302 return bus_space_read_4(sc->st, sc->sh, regno);
309 emu_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
313 bus_space_write_1(sc->st, sc->sh, regno, data);
316 bus_space_write_2(sc->st, sc->sh, regno, data);
319 bus_space_write_4(sc->st, sc->sh, regno, data);
325 emu_rdptr(struct sc_info *sc, int chn, int reg)
327 u_int32_t ptr, val, mask, size, offset;
329 ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK);
330 emu_wr(sc, EMU_PTR, ptr, 4);
331 val = emu_rd(sc, EMU_DATA, 4);
332 if (reg & 0xff000000) {
333 size = (reg >> 24) & 0x3f;
334 offset = (reg >> 16) & 0x1f;
335 mask = ((1 << size) - 1) << offset;
343 emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data)
345 u_int32_t ptr, mask, size, offset;
347 ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK);
348 emu_wr(sc, EMU_PTR, ptr, 4);
349 if (reg & 0xff000000) {
350 size = (reg >> 24) & 0x3f;
351 offset = (reg >> 16) & 0x1f;
352 mask = ((1 << size) - 1) << offset;
355 data |= emu_rd(sc, EMU_DATA, 4) & ~mask;
357 emu_wr(sc, EMU_DATA, data, 4);
361 emu_wrefx(struct sc_info *sc, unsigned int pc, unsigned int data)
363 pc += sc->audigy ? EMU_A_MICROCODEBASE : EMU_MICROCODEBASE;
364 emu_wrptr(sc, 0, pc, data);
367 /* -------------------------------------------------------------------- */
369 /* no locking needed */
372 emu_rdcd(kobj_t obj, void *devinfo, int regno)
374 struct sc_info *sc = (struct sc_info *)devinfo;
376 emu_wr(sc, EMU_AC97ADDR, regno, 1);
377 return emu_rd(sc, EMU_AC97DATA, 2);
381 emu_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
383 struct sc_info *sc = (struct sc_info *)devinfo;
385 emu_wr(sc, EMU_AC97ADDR, regno, 1);
386 emu_wr(sc, EMU_AC97DATA, data, 2);
390 static kobj_method_t emu_ac97_methods[] = {
391 KOBJMETHOD(ac97_read, emu_rdcd),
392 KOBJMETHOD(ac97_write, emu_wrcd),
395 AC97_DECLARE(emu_ac97);
397 /* -------------------------------------------------------------------- */
400 emu_settimer(struct sc_info *sc)
402 struct sc_pchinfo *pch;
403 struct sc_rchinfo *rch;
407 for (i = 0; i < sc->nchans; i++) {
410 tmp = (pch->spd * sndbuf_getalign(pch->buffer))
417 for (i = 0; i < 3; i++) {
420 tmp = (rch->spd * sndbuf_getalign(rch->buffer))
426 RANGE(rate, 48, 9600);
427 sc->timerinterval = 48000 / rate;
428 emu_wr(sc, EMU_TIMER, sc->timerinterval & 0x03ff, 2);
430 return sc->timerinterval;
434 emu_enatimer(struct sc_info *sc, int go)
438 if (sc->timer++ == 0) {
439 x = emu_rd(sc, EMU_INTE, 4);
440 x |= EMU_INTE_INTERTIMERENB;
441 emu_wr(sc, EMU_INTE, x, 4);
445 x = emu_rd(sc, EMU_INTE, 4);
446 x &= ~EMU_INTE_INTERTIMERENB;
447 emu_wr(sc, EMU_INTE, x, 4);
453 emu_enastop(struct sc_info *sc, char channel, int enable)
455 int reg = (channel & 0x20) ? EMU_SOLEH : EMU_SOLEL;
458 reg |= channel << 16;
459 emu_wrptr(sc, 0, reg, enable);
463 emu_recval(int speed) {
467 while (val < 7 && speed < adcspeed[val])
473 audigy_recval(int speed) {
477 while (val < 8 && speed < audigy_adcspeed[val])
483 emu_rate_to_pitch(u_int32_t rate)
485 static u_int32_t logMagTable[128] = {
486 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2,
487 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5,
488 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081,
489 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191,
490 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7,
491 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829,
492 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e,
493 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26,
494 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d,
495 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885,
496 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899,
497 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c,
498 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3,
499 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3,
500 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83,
501 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df
503 static char logSlopeTable[128] = {
504 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58,
505 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53,
506 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f,
507 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b,
508 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47,
509 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44,
510 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41,
511 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e,
512 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c,
513 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39,
514 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37,
515 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35,
516 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34,
517 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32,
518 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30,
519 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f
524 return 0; /* Bail out if no leading "1" */
525 rate *= 11185; /* Scale 48000 to 0x20002380 */
526 for (i = 31; i > 0; i--) {
527 if (rate & 0x80000000) { /* Detect leading "1" */
528 return (((u_int32_t) (i - 15) << 20) +
529 logMagTable[0x7f & (rate >> 24)] +
530 (0x7f & (rate >> 17)) *
531 logSlopeTable[0x7f & (rate >> 24)]);
536 return 0; /* Should never reach this point */
540 emu_rate_to_linearpitch(u_int32_t rate)
542 rate = (rate << 8) / 375;
543 return (rate >> 1) + (rate & 1);
546 static struct emu_voice *
547 emu_valloc(struct sc_info *sc)
553 for (i = 0; i < 64 && sc->voice[i].busy; i++);
562 emu_vinit(struct sc_info *sc, struct emu_voice *m, struct emu_voice *s,
563 u_int32_t sz, struct snd_dbuf *b)
568 buf = emu_memalloc(sc, sz, &tmp_addr);
572 sndbuf_setup(b, buf, sz);
573 m->start = emu_memstart(sc, buf) * EMUPAGESIZE;
574 m->end = m->start + sz;
585 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 8 |
586 FXBUS_PCM_LEFT << 16 | FXBUS_MIDI_REVERB << 24;
587 m->fxrt2 = 0x3f3f3f3f; /* No effects on second route */
589 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 4 |
590 FXBUS_PCM_LEFT << 8 | FXBUS_MIDI_REVERB << 12;
613 emu_vsetup(struct sc_pchinfo *ch)
615 struct emu_voice *v = ch->master;
618 v->b16 = (ch->fmt & AFMT_16BIT) ? 1 : 0;
619 v->stereo = (AFMT_CHANNEL(ch->fmt) > 1) ? 1 : 0;
620 if (v->slave != NULL) {
621 v->slave->b16 = v->b16;
622 v->slave->stereo = v->stereo;
627 if (v->slave != NULL)
628 v->slave->speed = v->speed;
633 emu_vwrite(struct sc_info *sc, struct emu_voice *v)
637 u_int32_t sa, ea, start, val, silent_page;
639 s = (v->stereo ? 1 : 0) + (v->b16 ? 1 : 0);
644 l = r = x = y = v->vol;
646 l = v->ismaster ? l : 0;
647 r = v->ismaster ? 0 : r;
650 emu_wrptr(sc, v->vnum, EMU_CHAN_CPF, v->stereo ? EMU_CHAN_CPF_STEREO_MASK : 0);
651 val = v->stereo ? 28 : 30;
652 val *= v->b16 ? 1 : 2;
656 emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT1, v->fxrt1);
657 emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT2, v->fxrt2);
658 emu_wrptr(sc, v->vnum, EMU_A_CHAN_SENDAMOUNTS, 0);
661 emu_wrptr(sc, v->vnum, EMU_CHAN_FXRT, v->fxrt1 << 16);
663 emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX, (x << 8) | r);
664 emu_wrptr(sc, v->vnum, EMU_CHAN_DSL, ea | (y << 24));
665 emu_wrptr(sc, v->vnum, EMU_CHAN_PSST, sa | (l << 24));
666 emu_wrptr(sc, v->vnum, EMU_CHAN_CCCA, start | (v->b16 ? 0 : EMU_CHAN_CCCA_8BITSELECT));
668 emu_wrptr(sc, v->vnum, EMU_CHAN_Z1, 0);
669 emu_wrptr(sc, v->vnum, EMU_CHAN_Z2, 0);
671 silent_page = ((u_int32_t)(sc->mem.silent_page_addr) << 1)
672 | EMU_CHAN_MAP_PTI_MASK;
673 emu_wrptr(sc, v->vnum, EMU_CHAN_MAPA, silent_page);
674 emu_wrptr(sc, v->vnum, EMU_CHAN_MAPB, silent_page);
676 emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, EMU_CHAN_CVCF_CURRFILTER_MASK);
677 emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, EMU_CHAN_VTFT_FILTERTARGET_MASK);
678 emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDM, 0);
679 emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSM, EMU_CHAN_DCYSUSM_DECAYTIME_MASK);
680 emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL1, 0x8000);
681 emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL2, 0x8000);
682 emu_wrptr(sc, v->vnum, EMU_CHAN_FMMOD, 0);
683 emu_wrptr(sc, v->vnum, EMU_CHAN_TREMFRQ, 0);
684 emu_wrptr(sc, v->vnum, EMU_CHAN_FM2FRQ2, 0);
685 emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVAL, 0x8000);
687 emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDV,
688 EMU_CHAN_ATKHLDV_HOLDTIME_MASK | EMU_CHAN_ATKHLDV_ATTACKTIME_MASK);
689 emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVOL, 0x8000);
691 emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_FILTERAMOUNT, 0x7f);
692 emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_PITCHAMOUNT, 0);
694 if (v->slave != NULL)
695 emu_vwrite(sc, v->slave);
699 emu_vtrigger(struct sc_info *sc, struct emu_voice *v, int go)
701 u_int32_t pitch_target, initial_pitch;
702 u_int32_t cra, cs, ccis;
707 cs = v->stereo ? 4 : 2;
708 ccis = v->stereo ? 28 : 30;
709 ccis *= v->b16 ? 1 : 2;
710 sample = v->b16 ? 0x00000000 : 0x80808080;
712 for (i = 0; i < cs; i++)
713 emu_wrptr(sc, v->vnum, EMU_CHAN_CD0 + i, sample);
714 emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, 0);
715 emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_READADDRESS, cra);
716 emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, ccis);
718 emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xff00);
719 emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0xffffffff);
720 emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0xffffffff);
721 emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSV, 0x00007f7f);
722 emu_enastop(sc, v->vnum, 0);
724 pitch_target = emu_rate_to_linearpitch(v->speed);
725 initial_pitch = emu_rate_to_pitch(v->speed) >> 8;
726 emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, pitch_target);
727 emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, pitch_target);
728 emu_wrptr(sc, v->vnum, EMU_CHAN_IP, initial_pitch);
730 emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, 0);
731 emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, 0);
732 emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xffff);
733 emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0x0000ffff);
734 emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0x0000ffff);
735 emu_wrptr(sc, v->vnum, EMU_CHAN_IP, 0);
736 emu_enastop(sc, v->vnum, 1);
738 if (v->slave != NULL)
739 emu_vtrigger(sc, v->slave, go);
743 emu_vpos(struct sc_info *sc, struct emu_voice *v)
747 s = (v->b16 ? 1 : 0) + (v->stereo ? 1 : 0);
748 ptr = (emu_rdptr(sc, v->vnum, EMU_CHAN_CCCA_CURRADDR) - (v->start >> s)) << s;
749 return ptr & ~0x0000001f;
754 emu_vdump(struct sc_info *sc, struct emu_voice *v)
757 "cpf", "ptrx", "cvcf", "vtft", "z2", "z1", "psst", "dsl",
758 "ccca", "ccr", "clp", "fxrt", "mapa", "mapb", NULL, NULL,
759 "envvol", "atkhldv", "dcysusv", "lfoval1",
760 "envval", "atkhldm", "dcysusm", "lfoval2",
761 "ip", "ifatn", "pefe", "fmmod", "tremfrq", "fmfrq2",
765 "mudata1", "mustat1", "mudata2", "mustat2",
766 "fxwc1", "fxwc2", "spdrate", NULL, NULL,
767 NULL, NULL, NULL, "fxrt2", "sndamnt", "fxrt1",
772 printf("voice number %d\n", v->vnum);
773 for (i = 0, x = 0; i <= 0x1e; i++) {
774 if (regname[i] == NULL)
776 printf("%s\t[%08x]", regname[i], emu_rdptr(sc, v->vnum, i));
777 printf("%s", (x == 2) ? "\n" : "\t");
783 /* Print out audigy extra registers */
785 for (i = 0; i <= 0xe; i++) {
786 if (regname2[i] == NULL)
788 printf("%s\t[%08x]", regname2[i],
789 emu_rdptr(sc, v->vnum, i + 0x70));
790 printf("%s", (x == 2)? "\n" : "\t");
800 /* channel interface */
802 emupchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
803 struct pcm_channel *c, int dir)
805 struct sc_info *sc = devinfo;
806 struct sc_pchinfo *ch;
809 KASSERT(dir == PCMDIR_PLAY, ("emupchan_init: bad direction"));
810 ch = &sc->pch[sc->pnum++];
814 ch->blksz = sc->bufsz / 2;
815 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
817 snd_mtxlock(sc->lock);
818 ch->master = emu_valloc(sc);
819 ch->slave = emu_valloc(sc);
820 snd_mtxunlock(sc->lock);
821 r = (emu_vinit(sc, ch->master, ch->slave, sc->bufsz, ch->buffer))
828 emupchan_free(kobj_t obj, void *data)
830 struct sc_pchinfo *ch = data;
831 struct sc_info *sc = ch->parent;
834 snd_mtxlock(sc->lock);
835 r = emu_memfree(sc, sndbuf_getbuf(ch->buffer));
836 snd_mtxunlock(sc->lock);
842 emupchan_setformat(kobj_t obj, void *data, u_int32_t format)
844 struct sc_pchinfo *ch = data;
851 emupchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
853 struct sc_pchinfo *ch = data;
860 emupchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
862 struct sc_pchinfo *ch = data;
863 struct sc_info *sc = ch->parent;
866 ch->blksz = blocksize;
867 snd_mtxlock(sc->lock);
869 irqrate = 48000 / sc->timerinterval;
870 snd_mtxunlock(sc->lock);
871 blksz = (ch->spd * sndbuf_getalign(ch->buffer)) / irqrate;
876 emupchan_trigger(kobj_t obj, void *data, int go)
878 struct sc_pchinfo *ch = data;
879 struct sc_info *sc = ch->parent;
881 if (!PCMTRIG_COMMON(go))
884 snd_mtxlock(sc->lock);
885 if (go == PCMTRIG_START) {
887 emu_vwrite(sc, ch->master);
891 printf("start [%d bit, %s, %d hz]\n",
892 ch->master->b16 ? 16 : 8,
893 ch->master->stereo ? "stereo" : "mono",
895 emu_vdump(sc, ch->master);
896 emu_vdump(sc, ch->slave);
899 ch->run = (go == PCMTRIG_START) ? 1 : 0;
900 emu_vtrigger(sc, ch->master, ch->run);
901 snd_mtxunlock(sc->lock);
906 emupchan_getptr(kobj_t obj, void *data)
908 struct sc_pchinfo *ch = data;
909 struct sc_info *sc = ch->parent;
912 snd_mtxlock(sc->lock);
913 r = emu_vpos(sc, ch->master);
914 snd_mtxunlock(sc->lock);
919 static struct pcmchan_caps *
920 emupchan_getcaps(kobj_t obj, void *data)
922 return &emu_playcaps;
925 static kobj_method_t emupchan_methods[] = {
926 KOBJMETHOD(channel_init, emupchan_init),
927 KOBJMETHOD(channel_free, emupchan_free),
928 KOBJMETHOD(channel_setformat, emupchan_setformat),
929 KOBJMETHOD(channel_setspeed, emupchan_setspeed),
930 KOBJMETHOD(channel_setblocksize, emupchan_setblocksize),
931 KOBJMETHOD(channel_trigger, emupchan_trigger),
932 KOBJMETHOD(channel_getptr, emupchan_getptr),
933 KOBJMETHOD(channel_getcaps, emupchan_getcaps),
936 CHANNEL_DECLARE(emupchan);
938 /* channel interface */
940 emurchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
941 struct pcm_channel *c, int dir)
943 struct sc_info *sc = devinfo;
944 struct sc_rchinfo *ch;
946 KASSERT(dir == PCMDIR_REC, ("emurchan_init: bad direction"));
947 ch = &sc->rch[sc->rnum];
951 ch->blksz = sc->bufsz / 2;
952 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
957 ch->idxreg = sc->audigy ? EMU_A_ADCIDX : EMU_ADCIDX;
958 ch->basereg = EMU_ADCBA;
959 ch->sizereg = EMU_ADCBS;
960 ch->setupreg = EMU_ADCCR;
961 ch->irqmask = EMU_INTE_ADCBUFENABLE;
965 ch->idxreg = EMU_FXIDX;
966 ch->basereg = EMU_FXBA;
967 ch->sizereg = EMU_FXBS;
968 ch->setupreg = EMU_FXWC;
969 ch->irqmask = EMU_INTE_EFXBUFENABLE;
973 ch->idxreg = EMU_MICIDX;
974 ch->basereg = EMU_MICBA;
975 ch->sizereg = EMU_MICBS;
977 ch->irqmask = EMU_INTE_MICBUFENABLE;
981 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0)
984 snd_mtxlock(sc->lock);
985 emu_wrptr(sc, 0, ch->basereg, sndbuf_getbufaddr(ch->buffer));
986 emu_wrptr(sc, 0, ch->sizereg, 0); /* off */
987 snd_mtxunlock(sc->lock);
993 emurchan_setformat(kobj_t obj, void *data, u_int32_t format)
995 struct sc_rchinfo *ch = data;
1002 emurchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
1004 struct sc_rchinfo *ch = data;
1007 if (ch->parent->audigy)
1008 speed = audigy_adcspeed[audigy_recval(speed)];
1010 speed = adcspeed[emu_recval(speed)];
1021 emurchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1023 struct sc_rchinfo *ch = data;
1024 struct sc_info *sc = ch->parent;
1027 ch->blksz = blocksize;
1028 snd_mtxlock(sc->lock);
1030 irqrate = 48000 / sc->timerinterval;
1031 snd_mtxunlock(sc->lock);
1032 blksz = (ch->spd * sndbuf_getalign(ch->buffer)) / irqrate;
1036 /* semantic note: must start at beginning of buffer */
1038 emurchan_trigger(kobj_t obj, void *data, int go)
1040 struct sc_rchinfo *ch = data;
1041 struct sc_info *sc = ch->parent;
1044 if (!PCMTRIG_COMMON(go))
1049 sz = EMU_RECBS_BUFSIZE_4096;
1053 sz = EMU_RECBS_BUFSIZE_8192;
1057 sz = EMU_RECBS_BUFSIZE_16384;
1061 sz = EMU_RECBS_BUFSIZE_32768;
1065 sz = EMU_RECBS_BUFSIZE_65536;
1069 sz = EMU_RECBS_BUFSIZE_4096;
1072 snd_mtxlock(sc->lock);
1076 emu_wrptr(sc, 0, ch->sizereg, sz);
1079 val = EMU_A_ADCCR_LCHANENABLE;
1080 if (AFMT_CHANNEL(ch->fmt) > 1)
1081 val |= EMU_A_ADCCR_RCHANENABLE;
1082 val |= audigy_recval(ch->spd);
1084 val = EMU_ADCCR_LCHANENABLE;
1085 if (AFMT_CHANNEL(ch->fmt) > 1)
1086 val |= EMU_ADCCR_RCHANENABLE;
1087 val |= emu_recval(ch->spd);
1090 emu_wrptr(sc, 0, ch->setupreg, 0);
1091 emu_wrptr(sc, 0, ch->setupreg, val);
1093 val = emu_rd(sc, EMU_INTE, 4);
1095 emu_wr(sc, EMU_INTE, val, 4);
1101 emu_wrptr(sc, 0, ch->sizereg, 0);
1103 emu_wrptr(sc, 0, ch->setupreg, 0);
1104 val = emu_rd(sc, EMU_INTE, 4);
1105 val &= ~ch->irqmask;
1106 emu_wr(sc, EMU_INTE, val, 4);
1109 case PCMTRIG_EMLDMAWR:
1110 case PCMTRIG_EMLDMARD:
1114 snd_mtxunlock(sc->lock);
1120 emurchan_getptr(kobj_t obj, void *data)
1122 struct sc_rchinfo *ch = data;
1123 struct sc_info *sc = ch->parent;
1126 snd_mtxlock(sc->lock);
1127 r = emu_rdptr(sc, 0, ch->idxreg) & 0x0000ffff;
1128 snd_mtxunlock(sc->lock);
1133 static struct pcmchan_caps *
1134 emurchan_getcaps(kobj_t obj, void *data)
1136 struct sc_rchinfo *ch = data;
1138 return &emu_reccaps[ch->num];
1141 static kobj_method_t emurchan_methods[] = {
1142 KOBJMETHOD(channel_init, emurchan_init),
1143 KOBJMETHOD(channel_setformat, emurchan_setformat),
1144 KOBJMETHOD(channel_setspeed, emurchan_setspeed),
1145 KOBJMETHOD(channel_setblocksize, emurchan_setblocksize),
1146 KOBJMETHOD(channel_trigger, emurchan_trigger),
1147 KOBJMETHOD(channel_getptr, emurchan_getptr),
1148 KOBJMETHOD(channel_getcaps, emurchan_getcaps),
1151 CHANNEL_DECLARE(emurchan);
1153 /* -------------------------------------------------------------------- */
1154 /* The interrupt handler */
1157 emu_intr(void *data)
1159 struct sc_info *sc = data;
1160 u_int32_t stat, ack, i, x;
1162 snd_mtxlock(sc->lock);
1164 stat = emu_rd(sc, EMU_IPR, 4);
1170 if (stat & EMU_IPR_INTERVALTIMER)
1171 ack |= EMU_IPR_INTERVALTIMER;
1173 if (stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL))
1174 ack |= stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL);
1176 if (stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL))
1177 ack |= stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL);
1179 if (stat & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL))
1180 ack |= stat & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL);
1182 if (stat & EMU_PCIERROR) {
1183 ack |= EMU_PCIERROR;
1184 device_printf(sc->dev, "pci error\n");
1185 /* we still get an nmi with ecc ram even if we ack this */
1187 if (stat & EMU_IPR_RATETRCHANGE) {
1188 ack |= EMU_IPR_RATETRCHANGE;
1190 device_printf(sc->dev,
1191 "sample rate tracker lock status change\n");
1196 device_printf(sc->dev, "dodgy irq: %x (harmless)\n",
1199 emu_wr(sc, EMU_IPR, stat, 4);
1202 snd_mtxunlock(sc->lock);
1204 if (ack & EMU_IPR_INTERVALTIMER) {
1206 for (i = 0; i < sc->nchans; i++) {
1207 if (sc->pch[i].run) {
1209 chn_intr(sc->pch[i].channel);
1213 emu_enatimer(sc, 0);
1217 if (ack & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL)) {
1218 if (sc->rch[0].channel)
1219 chn_intr(sc->rch[0].channel);
1221 if (ack & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL)) {
1222 if (sc->rch[1].channel)
1223 chn_intr(sc->rch[1].channel);
1225 if (ack & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL)) {
1226 if (sc->rch[2].channel)
1227 chn_intr(sc->rch[2].channel);
1230 snd_mtxlock(sc->lock);
1233 snd_mtxunlock(sc->lock);
1236 /* -------------------------------------------------------------------- */
1239 emu_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1241 bus_addr_t *phys = arg;
1243 *phys = error ? 0 : (bus_addr_t)segs->ds_addr;
1246 printf("emu: setmap (%lx, %lx), nseg=%d, error=%d\n",
1247 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
1253 emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr,
1259 if (bus_dmamem_alloc(sc->parent_dmat, &buf, BUS_DMA_NOWAIT, map))
1261 if (bus_dmamap_load(sc->parent_dmat, *map, buf, sz, emu_setmap, addr, 0)
1263 bus_dmamem_free(sc->parent_dmat, buf, *map);
1270 emu_free(struct sc_info *sc, void *buf, bus_dmamap_t map)
1272 bus_dmamap_unload(sc->parent_dmat, map);
1273 bus_dmamem_free(sc->parent_dmat, buf, map);
1277 emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr)
1279 u_int32_t blksz, start, idx, ofs, tmp, found;
1280 struct emu_mem *mem = &sc->mem;
1281 struct emu_memblk *blk;
1284 blksz = sz / EMUPAGESIZE;
1285 if (sz > (blksz * EMUPAGESIZE))
1287 /* find a free block in the bitmap */
1290 while (!found && start + blksz < EMUMAXPAGES) {
1292 for (idx = start; idx < start + blksz; idx++)
1293 if (mem->bmap[idx >> 3] & (1 << (idx & 7)))
1300 blk = malloc(sizeof(*blk), M_DEVBUF, M_NOWAIT);
1303 buf = emu_malloc(sc, sz, &blk->buf_addr, &blk->buf_map);
1304 *addr = blk->buf_addr;
1306 free(blk, M_DEVBUF);
1310 blk->pte_start = start;
1311 blk->pte_size = blksz;
1313 printf("buf %p, pte_start %d, pte_size %d\n", blk->buf,
1314 blk->pte_start, blk->pte_size);
1317 for (idx = start; idx < start + blksz; idx++) {
1318 mem->bmap[idx >> 3] |= 1 << (idx & 7);
1319 tmp = (uint32_t)(blk->buf_addr + ofs);
1321 printf("pte[%d] -> %x phys, %x virt\n", idx, tmp,
1322 ((u_int32_t)buf) + ofs);
1324 mem->ptb_pages[idx] = (tmp << 1) | idx;
1327 SLIST_INSERT_HEAD(&mem->blocks, blk, link);
1332 emu_memfree(struct sc_info *sc, void *buf)
1335 struct emu_mem *mem = &sc->mem;
1336 struct emu_memblk *blk, *i;
1339 SLIST_FOREACH(i, &mem->blocks, link) {
1345 SLIST_REMOVE(&mem->blocks, blk, emu_memblk, link);
1346 emu_free(sc, buf, blk->buf_map);
1347 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1;
1348 for (idx = blk->pte_start; idx < blk->pte_start + blk->pte_size; idx++) {
1349 mem->bmap[idx >> 3] &= ~(1 << (idx & 7));
1350 mem->ptb_pages[idx] = tmp | idx;
1352 free(blk, M_DEVBUF);
1357 emu_memstart(struct sc_info *sc, void *buf)
1359 struct emu_mem *mem = &sc->mem;
1360 struct emu_memblk *blk, *i;
1363 SLIST_FOREACH(i, &mem->blocks, link) {
1369 return blk->pte_start;
1373 emu_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y,
1376 emu_wrefx(sc, (*pc) * 2, (x << 10) | y);
1377 emu_wrefx(sc, (*pc) * 2 + 1, (op << 20) | (z << 10) | w);
1382 audigy_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y,
1385 emu_wrefx(sc, (*pc) * 2, (x << 12) | y);
1386 emu_wrefx(sc, (*pc) * 2 + 1, (op << 24) | (z << 12) | w);
1391 audigy_initefx(struct sc_info *sc)
1396 /* skip 0, 0, -1, 0 - NOPs */
1397 for (i = 0; i < 512; i++)
1398 audigy_addefxop(sc, 0x0f, 0x0c0, 0x0c0, 0x0cf, 0x0c0, &pc);
1400 for (i = 0; i < 512; i++)
1401 emu_wrptr(sc, 0, EMU_A_FXGPREGBASE + i, 0x0);
1405 /* stop fx processor */
1406 emu_wrptr(sc, 0, EMU_A_DBG, EMU_A_DBG_SINGLE_STEP);
1408 /* Audigy 2 (EMU10K2) DSP Registers:
1410 0x000-0x00f : 16 registers (?)
1412 0x040/0x041 : AC97 Codec (l/r)
1413 0x042/0x043 : ADC, S/PDIF (l/r)
1414 0x044/0x045 : Optical S/PDIF in (l/r)
1416 0x048/0x049 : Line/Mic 2 (l/r)
1417 0x04a/0x04b : RCA S/PDIF (l/r)
1418 0x04c/0x04d : Aux 2 (l/r)
1420 0x060/0x061 : Digital Front (l/r)
1421 0x062/0x063 : Digital Center/LFE
1422 0x064/0x065 : AudigyDrive Heaphone (l/r)
1423 0x066/0x067 : Digital Rear (l/r)
1424 0x068/0x069 : Analog Front (l/r)
1425 0x06a/0x06b : Analog Center/LFE
1427 0x06e/0x06f : Analog Rear (l/r)
1428 0x070/0x071 : AC97 Output (l/r)
1431 0x076/0x077 : ADC Recording Buffer (l/r)
1433 0x0c0 - 0x0c4 = 0 - 4
1434 0x0c5 = 0x8, 0x0c6 = 0x10, 0x0c7 = 0x20
1435 0x0c8 = 0x100, 0x0c9 = 0x10000, 0x0ca = 0x80000
1436 0x0cb = 0x10000000, 0x0cc = 0x20000000, 0x0cd = 0x40000000
1437 0x0ce = 0x80000000, 0x0cf = 0x7fffffff, 0x0d0 = 0xffffffff
1438 0x0d1 = 0xfffffffe, 0x0d2 = 0xc0000000, 0x0d3 = 0x41fbbcdc
1439 0x0d4 = 0x5a7ef9db, 0x0d5 = 0x00100000, 0x0dc = 0x00000001 (?)
1441 0x0d6 : Accumulator (?)
1442 0x0d7 : Condition Register
1443 0x0d8 : Noise source
1444 0x0d9 : Noise source
1445 Tank Memory Data Registers
1447 Tank Memory Address Registers
1449 General Purpose Registers
1453 /* AC97Output[l/r] = FXBus PCM[l/r] */
1454 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_L), A_C_00000000,
1455 A_C_00000000, A_FXBUS(FXBUS_PCM_LEFT), &pc);
1456 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_R), A_C_00000000,
1457 A_C_00000000, A_FXBUS(FXBUS_PCM_RIGHT), &pc);
1459 /* GPR[0/1] = RCA S/PDIF[l/r] -- Master volume */
1460 audigy_addefxop(sc, iACC3, A_GPR(0), A_C_00000000,
1461 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_L), &pc);
1462 audigy_addefxop(sc, iACC3, A_GPR(1), A_C_00000000,
1463 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_R), &pc);
1465 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */
1466 audigy_addefxop(sc, iINTERP, A_GPR(2), A_GPR(1),
1467 A_C_40000000, A_GPR(0), &pc);
1469 /* Headphones[l/r] = GPR[0/1] */
1470 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_L),
1471 A_C_00000000, A_C_00000000, A_GPR(0), &pc);
1472 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_R),
1473 A_C_00000000, A_C_00000000, A_GPR(1), &pc);
1475 /* Analog Front[l/r] = GPR[0/1] */
1476 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_L), A_C_00000000,
1477 A_C_00000000, A_GPR(0), &pc);
1478 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_R), A_C_00000000,
1479 A_C_00000000, A_GPR(1), &pc);
1481 /* Digital Front[l/r] = GPR[0/1] */
1482 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L), A_C_00000000,
1483 A_C_00000000, A_GPR(0), &pc);
1484 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_R), A_C_00000000,
1485 A_C_00000000, A_GPR(1), &pc);
1487 /* Center and Subwoofer configuration */
1488 /* Analog Center = GPR[0] + GPR[2] */
1489 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ACENTER), A_C_00000000,
1490 A_GPR(0), A_GPR(2), &pc);
1491 /* Analog Sub = GPR[1] + GPR[2] */
1492 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ALFE), A_C_00000000,
1493 A_GPR(1), A_GPR(2), &pc);
1495 /* Digital Center = GPR[0] + GPR[2] */
1496 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_CENTER), A_C_00000000,
1497 A_GPR(0), A_GPR(2), &pc);
1498 /* Digital Sub = GPR[1] + GPR[2] */
1499 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_LFE), A_C_00000000,
1500 A_GPR(1), A_GPR(2), &pc);
1503 /* Analog Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */
1504 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */
1505 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000,
1506 A_GPR(16), A_GPR(0), &pc);
1507 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000,
1508 A_GPR(17), A_GPR(1), &pc);
1510 /* Digital Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */
1511 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */
1512 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000,
1513 A_GPR(16), A_GPR(0), &pc);
1514 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000,
1515 A_GPR(17), A_GPR(1), &pc);
1517 /* XXX This is just a copy to the channel, since we do not have
1518 * a patch manager, it is useful for have another output enabled.
1521 /* Analog Rear[l/r] = GPR[0/1] */
1522 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000,
1523 A_C_00000000, A_GPR(0), &pc);
1524 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000,
1525 A_C_00000000, A_GPR(1), &pc);
1527 /* Digital Rear[l/r] = GPR[0/1] */
1528 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000,
1529 A_C_00000000, A_GPR(0), &pc);
1530 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000,
1531 A_C_00000000, A_GPR(1), &pc);
1534 /* ADC Recording buffer[l/r] = AC97Input[l/r] */
1535 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_L), A_C_00000000,
1536 A_C_00000000, A_EXTIN(A_EXTIN_AC97_L), &pc);
1537 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_R), A_C_00000000,
1538 A_C_00000000, A_EXTIN(A_EXTIN_AC97_R), &pc);
1540 /* resume normal operations */
1541 emu_wrptr(sc, 0, EMU_A_DBG, 0);
1545 emu_initefx(struct sc_info *sc)
1550 /* acc3 0,0,0,0 - NOPs */
1551 for (i = 0; i < 512; i++) {
1552 emu_wrefx(sc, i * 2, 0x10040);
1553 emu_wrefx(sc, i * 2 + 1, 0x610040);
1556 for (i = 0; i < 256; i++)
1557 emu_wrptr(sc, 0, EMU_FXGPREGBASE + i, 0);
1559 /* FX-8010 DSP Registers:
1561 0x000-0x00f : 16 registers
1563 0x010/0x011 : AC97 Codec (l/r)
1564 0x012/0x013 : ADC, S/PDIF (l/r)
1565 0x014/0x015 : Mic(left), Zoom (l/r)
1566 0x016/0x017 : TOS link in (l/r)
1567 0x018/0x019 : Line/Mic 1 (l/r)
1568 0x01a/0x01b : COAX S/PDIF (l/r)
1569 0x01c/0x01d : Line/Mic 2 (l/r)
1571 0x020/0x021 : AC97 Output (l/r)
1572 0x022/0x023 : TOS link out (l/r)
1573 0x024/0x025 : Center/LFE
1574 0x026/0x027 : LiveDrive Headphone (l/r)
1575 0x028/0x029 : Rear Channel (l/r)
1576 0x02a/0x02b : ADC Recording Buffer (l/r)
1577 0x02c : Mic Recording Buffer
1578 0x031/0x032 : Analog Center/LFE
1580 0x040 - 0x044 = 0 - 4
1581 0x045 = 0x8, 0x046 = 0x10, 0x047 = 0x20
1582 0x048 = 0x100, 0x049 = 0x10000, 0x04a = 0x80000
1583 0x04b = 0x10000000, 0x04c = 0x20000000, 0x04d = 0x40000000
1584 0x04e = 0x80000000, 0x04f = 0x7fffffff, 0x050 = 0xffffffff
1585 0x051 = 0xfffffffe, 0x052 = 0xc0000000, 0x053 = 0x41fbbcdc
1586 0x054 = 0x5a7ef9db, 0x055 = 0x00100000
1589 0x057 : Condition Register
1590 0x058 : Noise source
1591 0x059 : Noise source
1592 0x05a : IRQ Register
1593 0x05b : TRAM Delay Base Address Count
1594 General Purpose Registers
1596 Tank Memory Data Registers
1598 Tank Memory Address Registers
1602 /* Routing - this will be configurable in later version */
1604 /* GPR[0/1] = FX * 4 + SPDIF-in */
1605 emu_addefxop(sc, iMACINT0, GPR(0), EXTIN(EXTIN_SPDIF_CD_L),
1606 FXBUS(FXBUS_PCM_LEFT), C_00000004, &pc);
1607 emu_addefxop(sc, iMACINT0, GPR(1), EXTIN(EXTIN_SPDIF_CD_R),
1608 FXBUS(FXBUS_PCM_RIGHT), C_00000004, &pc);
1610 /* GPR[0/1] += APS-input */
1611 emu_addefxop(sc, iACC3, GPR(0), GPR(0), C_00000000,
1612 sc->APS ? EXTIN(EXTIN_TOSLINK_L) : C_00000000, &pc);
1613 emu_addefxop(sc, iACC3, GPR(1), GPR(1), C_00000000,
1614 sc->APS ? EXTIN(EXTIN_TOSLINK_R) : C_00000000, &pc);
1616 /* FrontOut (AC97) = GPR[0/1] */
1617 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_L), C_00000000,
1618 C_00000000, GPR(0), &pc);
1619 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_R), C_00000000,
1620 C_00000001, GPR(1), &pc);
1622 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */
1623 emu_addefxop(sc, iINTERP, GPR(2), GPR(1), C_40000000, GPR(0), &pc);
1626 /* RearOut = (GPR[0/1] * RearVolume) >> 31 */
1627 /* RearVolume = GPR[0x10/0x11] */
1628 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_L), C_00000000,
1629 GPR(16), GPR(0), &pc);
1630 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_R), C_00000000,
1631 GPR(17), GPR(1), &pc);
1633 /* XXX This is just a copy to the channel, since we do not have
1634 * a patch manager, it is useful for have another output enabled.
1637 /* Rear[l/r] = GPR[0/1] */
1638 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_L), C_00000000,
1639 C_00000000, GPR(0), &pc);
1640 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_R), C_00000000,
1641 C_00000000, GPR(1), &pc);
1644 /* TOS out[l/r] = GPR[0/1] */
1645 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_L), C_00000000,
1646 C_00000000, GPR(0), &pc);
1647 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_R), C_00000000,
1648 C_00000000, GPR(1), &pc);
1650 /* Center and Subwoofer configuration */
1651 /* Analog Center = GPR[0] + GPR[2] */
1652 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ACENTER), C_00000000,
1653 GPR(0), GPR(2), &pc);
1654 /* Analog Sub = GPR[1] + GPR[2] */
1655 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ALFE), C_00000000,
1656 GPR(1), GPR(2), &pc);
1657 /* Digital Center = GPR[0] + GPR[2] */
1658 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_CENTER), C_00000000,
1659 GPR(0), GPR(2), &pc);
1660 /* Digital Sub = GPR[1] + GPR[2] */
1661 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_LFE), C_00000000,
1662 GPR(1), GPR(2), &pc);
1664 /* Headphones[l/r] = GPR[0/1] */
1665 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_L), C_00000000,
1666 C_00000000, GPR(0), &pc);
1667 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_R), C_00000000,
1668 C_00000000, GPR(1), &pc);
1670 /* ADC Recording buffer[l/r] = AC97Input[l/r] */
1671 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_L), C_00000000,
1672 C_00000000, EXTIN(EXTIN_AC97_L), &pc);
1673 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_R), C_00000000,
1674 C_00000000, EXTIN(EXTIN_AC97_R), &pc);
1676 /* resume normal operations */
1677 emu_wrptr(sc, 0, EMU_DBG, 0);
1680 /* Probe and attach the card */
1682 emu_init(struct sc_info *sc)
1684 u_int32_t spcs, ch, tmp, i;
1687 /* enable additional AC97 slots */
1688 emu_wrptr(sc, 0, EMU_AC97SLOT, EMU_AC97SLOT_CENTER | EMU_AC97SLOT_LFE);
1691 /* disable audio and lock cache */
1692 emu_wr(sc, EMU_HCFG,
1693 EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE,
1696 /* reset recording buffers */
1697 emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
1698 emu_wrptr(sc, 0, EMU_MICBA, 0);
1699 emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
1700 emu_wrptr(sc, 0, EMU_FXBA, 0);
1701 emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
1702 emu_wrptr(sc, 0, EMU_ADCBA, 0);
1704 /* disable channel interrupt */
1705 emu_wr(sc, EMU_INTE,
1706 EMU_INTE_INTERTIMERENB | EMU_INTE_SAMPLERATER | EMU_INTE_PCIERRENABLE,
1708 emu_wrptr(sc, 0, EMU_CLIEL, 0);
1709 emu_wrptr(sc, 0, EMU_CLIEH, 0);
1710 emu_wrptr(sc, 0, EMU_SOLEL, 0);
1711 emu_wrptr(sc, 0, EMU_SOLEH, 0);
1713 /* wonder what these do... */
1715 emu_wrptr(sc, 0, EMU_SPBYPASS, 0xf00);
1716 emu_wrptr(sc, 0, EMU_AC97SLOT, 0x3);
1719 /* init envelope engine */
1720 for (ch = 0; ch < NUM_G; ch++) {
1721 emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, ENV_OFF);
1722 emu_wrptr(sc, ch, EMU_CHAN_IP, 0);
1723 emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0xffff);
1724 emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0xffff);
1725 emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0);
1726 emu_wrptr(sc, ch, EMU_CHAN_CPF, 0);
1727 emu_wrptr(sc, ch, EMU_CHAN_CCR, 0);
1729 emu_wrptr(sc, ch, EMU_CHAN_PSST, 0);
1730 emu_wrptr(sc, ch, EMU_CHAN_DSL, 0x10);
1731 emu_wrptr(sc, ch, EMU_CHAN_CCCA, 0);
1732 emu_wrptr(sc, ch, EMU_CHAN_Z1, 0);
1733 emu_wrptr(sc, ch, EMU_CHAN_Z2, 0);
1734 emu_wrptr(sc, ch, EMU_CHAN_FXRT, 0xd01c0000);
1736 emu_wrptr(sc, ch, EMU_CHAN_ATKHLDM, 0);
1737 emu_wrptr(sc, ch, EMU_CHAN_DCYSUSM, 0);
1738 emu_wrptr(sc, ch, EMU_CHAN_IFATN, 0xffff);
1739 emu_wrptr(sc, ch, EMU_CHAN_PEFE, 0);
1740 emu_wrptr(sc, ch, EMU_CHAN_FMMOD, 0);
1741 emu_wrptr(sc, ch, EMU_CHAN_TREMFRQ, 24); /* 1 Hz */
1742 emu_wrptr(sc, ch, EMU_CHAN_FM2FRQ2, 24); /* 1 Hz */
1743 emu_wrptr(sc, ch, EMU_CHAN_TEMPENV, 0);
1745 /*** these are last so OFF prevents writing ***/
1746 emu_wrptr(sc, ch, EMU_CHAN_LFOVAL2, 0);
1747 emu_wrptr(sc, ch, EMU_CHAN_LFOVAL1, 0);
1748 emu_wrptr(sc, ch, EMU_CHAN_ATKHLDV, 0);
1749 emu_wrptr(sc, ch, EMU_CHAN_ENVVOL, 0);
1750 emu_wrptr(sc, ch, EMU_CHAN_ENVVAL, 0);
1753 /* audigy cards need this to initialize correctly */
1754 emu_wrptr(sc, ch, 0x4c, 0);
1755 emu_wrptr(sc, ch, 0x4d, 0);
1756 emu_wrptr(sc, ch, 0x4e, 0);
1757 emu_wrptr(sc, ch, 0x4f, 0);
1758 /* set default routing */
1759 emu_wrptr(sc, ch, EMU_A_CHAN_FXRT1, 0x03020100);
1760 emu_wrptr(sc, ch, EMU_A_CHAN_FXRT2, 0x3f3f3f3f);
1761 emu_wrptr(sc, ch, EMU_A_CHAN_SENDAMOUNTS, 0);
1764 sc->voice[ch].vnum = ch;
1765 sc->voice[ch].slave = NULL;
1766 sc->voice[ch].busy = 0;
1767 sc->voice[ch].ismaster = 0;
1768 sc->voice[ch].running = 0;
1769 sc->voice[ch].b16 = 0;
1770 sc->voice[ch].stereo = 0;
1771 sc->voice[ch].speed = 0;
1772 sc->voice[ch].start = 0;
1773 sc->voice[ch].end = 0;
1774 sc->voice[ch].channel = NULL;
1776 sc->pnum = sc->rnum = 0;
1779 * Init to 0x02109204 :
1780 * Clock accuracy = 0 (1000ppm)
1781 * Sample Rate = 2 (48kHz)
1782 * Audio Channel = 1 (Left of 2)
1783 * Source Number = 0 (Unspecified)
1784 * Generation Status = 1 (Original for Cat Code 12)
1785 * Cat Code = 12 (Digital Signal Mixer)
1787 * Emphasis = 0 (None)
1788 * CP = 1 (Copyright unasserted)
1789 * AN = 0 (Audio data)
1792 spcs = EMU_SPCS_CLKACCY_1000PPM | EMU_SPCS_SAMPLERATE_48 |
1793 EMU_SPCS_CHANNELNUM_LEFT | EMU_SPCS_SOURCENUM_UNSPEC |
1794 EMU_SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 |
1795 EMU_SPCS_EMPHASIS_NONE | EMU_SPCS_COPYRIGHT;
1796 emu_wrptr(sc, 0, EMU_SPCS0, spcs);
1797 emu_wrptr(sc, 0, EMU_SPCS1, spcs);
1798 emu_wrptr(sc, 0, EMU_SPCS2, spcs);
1802 else if (sc->audigy2) { /* Audigy 2 */
1803 /* from ALSA initialization code: */
1805 /* Hack for Alice3 to work independent of haP16V driver */
1808 /* Setup SRCMulti_I2S SamplingRate */
1809 tmp = emu_rdptr(sc, 0, EMU_A_SPDIF_SAMPLERATE) & 0xfffff1ff;
1810 emu_wrptr(sc, 0, EMU_A_SPDIF_SAMPLERATE, tmp | 0x400);
1812 /* Setup SRCSel (Enable SPDIF, I2S SRCMulti) */
1813 emu_wr(sc, 0x20, 0x00600000, 4);
1814 emu_wr(sc, 0x24, 0x00000014, 4);
1816 /* Setup SRCMulti Input Audio Enable */
1817 emu_wr(sc, 0x20, 0x006e0000, 4);
1818 emu_wr(sc, 0x24, 0xff00ff00, 4);
1821 SLIST_INIT(&sc->mem.blocks);
1822 sc->mem.ptb_pages = emu_malloc(sc, EMUMAXPAGES * sizeof(u_int32_t),
1823 &sc->mem.ptb_pages_addr, &sc->mem.ptb_map);
1824 if (sc->mem.ptb_pages == NULL)
1827 sc->mem.silent_page = emu_malloc(sc, EMUPAGESIZE,
1828 &sc->mem.silent_page_addr, &sc->mem.silent_map);
1829 if (sc->mem.silent_page == NULL) {
1830 emu_free(sc, sc->mem.ptb_pages, sc->mem.ptb_map);
1833 /* Clear page with silence & setup all pointers to this page */
1834 bzero(sc->mem.silent_page, EMUPAGESIZE);
1835 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1;
1836 for (i = 0; i < EMUMAXPAGES; i++)
1837 sc->mem.ptb_pages[i] = tmp | i;
1839 emu_wrptr(sc, 0, EMU_PTB, (sc->mem.ptb_pages_addr));
1840 emu_wrptr(sc, 0, EMU_TCB, 0); /* taken from original driver */
1841 emu_wrptr(sc, 0, EMU_TCBS, 0); /* taken from original driver */
1843 for (ch = 0; ch < NUM_G; ch++) {
1844 emu_wrptr(sc, ch, EMU_CHAN_MAPA, tmp | EMU_CHAN_MAP_PTI_MASK);
1845 emu_wrptr(sc, ch, EMU_CHAN_MAPB, tmp | EMU_CHAN_MAP_PTI_MASK);
1848 /* emu_memalloc(sc, EMUPAGESIZE); */
1850 * Hokay, now enable the AUD bit
1853 * Enable Audio = 0 (enabled after fx processor initialization)
1854 * Mute Disable Audio = 0
1859 * Mute Disable Audio = 0
1861 * GP S/PDIF AC3 Enable = 1
1862 * CD S/PDIF AC3 Enable = 1
1866 * Mute Disable Audio = 0
1867 * Lock Tank Memory = 1
1868 * Lock Sound Memory = 0
1873 tmp = EMU_HCFG_AUTOMUTE | EMU_HCFG_JOYENABLE;
1874 if (sc->audigy2) /* Audigy 2 */
1875 tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_AC3ENABLE_CDSPDIF |
1876 EMU_HCFG_AC3ENABLE_GPSPDIF;
1877 emu_wr(sc, EMU_HCFG, tmp, 4);
1881 /* from ALSA initialization code: */
1883 /* enable audio and disable both audio/digital outputs */
1884 emu_wr(sc, EMU_HCFG, emu_rd(sc, EMU_HCFG, 4) | EMU_HCFG_AUDIOENABLE, 4);
1885 emu_wr(sc, EMU_A_IOCFG, emu_rd(sc, EMU_A_IOCFG, 4) & ~EMU_A_IOCFG_GPOUT_AD,
1887 if (sc->audigy2) { /* Audigy 2 */
1889 * Set GPO6 to 1 for Apollo. This has to be done after
1890 * init Alice3 I2SOut beyond 48kHz.
1891 * So, sequence is important.
1893 emu_wr(sc, EMU_A_IOCFG,
1894 emu_rd(sc, EMU_A_IOCFG, 4) | EMU_A_IOCFG_GPOUT_A, 4);
1897 /* EMU10K1 initialization code */
1898 tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_LOCKTANKCACHE_MASK
1899 | EMU_HCFG_AUTOMUTE;
1901 tmp |= EMU_HCFG_JOYENABLE;
1903 emu_wr(sc, EMU_HCFG, tmp, 4);
1905 /* TOSLink detection */
1907 tmp = emu_rd(sc, EMU_HCFG, 4);
1908 if (tmp & (EMU_HCFG_GPINPUT0 | EMU_HCFG_GPINPUT1)) {
1909 emu_wr(sc, EMU_HCFG, tmp | EMU_HCFG_GPOUT1, 4);
1911 if (tmp != (emu_rd(sc, EMU_HCFG, 4) & ~EMU_HCFG_GPOUT1)) {
1913 emu_wr(sc, EMU_HCFG, tmp, 4);
1922 emu_uninit(struct sc_info *sc)
1926 emu_wr(sc, EMU_INTE, 0, 4);
1927 for (ch = 0; ch < NUM_G; ch++)
1928 emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, ENV_OFF);
1929 for (ch = 0; ch < NUM_G; ch++) {
1930 emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0);
1931 emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0);
1932 emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0);
1933 emu_wrptr(sc, ch, EMU_CHAN_CPF, 0);
1936 if (sc->audigy) { /* stop fx processor */
1937 emu_wrptr(sc, 0, EMU_A_DBG, EMU_A_DBG_SINGLE_STEP);
1940 /* disable audio and lock cache */
1941 emu_wr(sc, EMU_HCFG,
1942 EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE,
1945 emu_wrptr(sc, 0, EMU_PTB, 0);
1946 /* reset recording buffers */
1947 emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
1948 emu_wrptr(sc, 0, EMU_MICBA, 0);
1949 emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
1950 emu_wrptr(sc, 0, EMU_FXBA, 0);
1951 emu_wrptr(sc, 0, EMU_FXWC, 0);
1952 emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
1953 emu_wrptr(sc, 0, EMU_ADCBA, 0);
1954 emu_wrptr(sc, 0, EMU_TCB, 0);
1955 emu_wrptr(sc, 0, EMU_TCBS, 0);
1957 /* disable channel interrupt */
1958 emu_wrptr(sc, 0, EMU_CLIEL, 0);
1959 emu_wrptr(sc, 0, EMU_CLIEH, 0);
1960 emu_wrptr(sc, 0, EMU_SOLEL, 0);
1961 emu_wrptr(sc, 0, EMU_SOLEH, 0);
1963 /* init envelope engine */
1964 if (!SLIST_EMPTY(&sc->mem.blocks))
1965 device_printf(sc->dev, "warning: memblock list not empty\n");
1966 emu_free(sc, sc->mem.ptb_pages, sc->mem.ptb_map);
1967 emu_free(sc, sc->mem.silent_page, sc->mem.silent_map);
1973 emu_pci_probe(device_t dev)
1977 switch (pci_get_devid(dev)) {
1978 case EMU10K1_PCI_ID:
1979 s = "Creative EMU10K1";
1982 case EMU10K2_PCI_ID:
1983 if (pci_get_revid(dev) == 0x04)
1984 s = "Creative Audigy 2 (EMU10K2)";
1986 s = "Creative Audigy (EMU10K2)";
1989 case EMU10K3_PCI_ID:
1990 s = "Creative Audigy 2 (EMU10K3)";
1997 device_set_desc(dev, s);
1998 return BUS_PROBE_LOW_PRIORITY;
2002 emu_pci_attach(device_t dev)
2004 struct ac97_info *codec = NULL;
2007 char status[SND_STATUSLEN];
2009 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
2010 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_emu10k1 softc");
2012 sc->type = pci_get_devid(dev);
2013 sc->rev = pci_get_revid(dev);
2014 sc->audigy = sc->type == EMU10K2_PCI_ID || sc->type == EMU10K3_PCI_ID;
2015 sc->audigy2 = (sc->audigy && sc->rev == 0x04);
2016 sc->nchans = sc->audigy ? 8 : 4;
2017 sc->addrmask = sc->audigy ? EMU_A_PTR_ADDR_MASK : EMU_PTR_ADDR_MASK;
2019 pci_enable_busmaster(dev);
2022 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE);
2023 if (sc->reg == NULL) {
2024 device_printf(dev, "unable to map register space\n");
2027 sc->st = rman_get_bustag(sc->reg);
2028 sc->sh = rman_get_bushandle(sc->reg);
2030 sc->bufsz = pcm_getbuffersize(dev, 4096, EMU_DEFAULT_BUFSZ, 65536);
2032 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
2034 /*lowaddr*/(1U << 31) - 1, /* can only access 0-2gb */
2035 /*highaddr*/BUS_SPACE_MAXADDR,
2036 /*filter*/NULL, /*filterarg*/NULL,
2037 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
2038 /*flags*/0, /*lockfunc*/busdma_lock_mutex,
2039 /*lockarg*/&Giant, &sc->parent_dmat) != 0) {
2040 device_printf(dev, "unable to create dma tag\n");
2044 if (emu_init(sc) == -1) {
2045 device_printf(dev, "unable to initialize the card\n");
2049 codec = AC97_CREATE(dev, sc, emu_ac97);
2050 if (codec == NULL) goto bad;
2051 gotmic = (ac97_getcaps(codec) & AC97_CAP_MICCHANNEL) ? 1 : 0;
2052 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
2055 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i,
2056 RF_ACTIVE | RF_SHAREABLE);
2058 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, emu_intr, sc, &sc->ih)) {
2059 device_printf(dev, "unable to map interrupt\n");
2063 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s",
2064 rman_get_start(sc->reg), rman_get_start(sc->irq),
2065 PCM_KLDSTRING(snd_emu10k1));
2067 if (pcm_register(dev, sc, sc->nchans, gotmic ? 3 : 2)) goto bad;
2068 for (i = 0; i < sc->nchans; i++)
2069 pcm_addchan(dev, PCMDIR_PLAY, &emupchan_class, sc);
2070 for (i = 0; i < (gotmic ? 3 : 2); i++)
2071 pcm_addchan(dev, PCMDIR_REC, &emurchan_class, sc);
2073 pcm_setstatus(dev, status);
2078 if (codec) ac97_destroy(codec);
2079 if (sc->reg) bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);
2080 if (sc->ih) bus_teardown_intr(dev, sc->irq, sc->ih);
2081 if (sc->irq) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
2082 if (sc->parent_dmat) bus_dma_tag_destroy(sc->parent_dmat);
2083 if (sc->lock) snd_mtxfree(sc->lock);
2089 emu_pci_detach(device_t dev)
2094 r = pcm_unregister(dev);
2098 sc = pcm_getdevinfo(dev);
2102 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);
2103 bus_teardown_intr(dev, sc->irq, sc->ih);
2104 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
2105 bus_dma_tag_destroy(sc->parent_dmat);
2106 snd_mtxfree(sc->lock);
2112 /* add suspend, resume */
2113 static device_method_t emu_methods[] = {
2114 /* Device interface */
2115 DEVMETHOD(device_probe, emu_pci_probe),
2116 DEVMETHOD(device_attach, emu_pci_attach),
2117 DEVMETHOD(device_detach, emu_pci_detach),
2122 static driver_t emu_driver = {
2128 DRIVER_MODULE(snd_emu10k1, pci, emu_driver, pcm_devclass, NULL, NULL);
2129 MODULE_DEPEND(snd_emu10k1, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2130 MODULE_VERSION(snd_emu10k1, 1);
2131 MODULE_DEPEND(snd_emu10k1, midi, 1, 1, 1);
2133 /* dummy driver to silence the joystick device */
2135 emujoy_pci_probe(device_t dev)
2139 switch (pci_get_devid(dev)) {
2141 s = "Creative EMU10K1 Joystick";
2145 s = "Creative EMU10K2 Joystick";
2150 if (s) device_set_desc(dev, s);
2151 return s ? -1000 : ENXIO;
2155 emujoy_pci_attach(device_t dev)
2162 emujoy_pci_detach(device_t dev)
2168 static device_method_t emujoy_methods[] = {
2169 DEVMETHOD(device_probe, emujoy_pci_probe),
2170 DEVMETHOD(device_attach, emujoy_pci_attach),
2171 DEVMETHOD(device_detach, emujoy_pci_detach),
2176 static driver_t emujoy_driver = {
2182 static devclass_t emujoy_devclass;
2184 DRIVER_MODULE(emujoy, pci, emujoy_driver, emujoy_devclass, NULL, NULL);