sys/dev/drm/i915/i915_gem.c

   1 /*-
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  * Copyright (c) 2011 The FreeBSD Foundation
  27  * All rights reserved.
  28  *
  29  * This software was developed by Konstantin Belousov under sponsorship from
  30  * the FreeBSD Foundation.
  31  *
  32  * Redistribution and use in source and binary forms, with or without
  33  * modification, are permitted provided that the following conditions
  34  * are met:
  35  * 1. Redistributions of source code must retain the above copyright
  36  *    notice, this list of conditions and the following disclaimer.
  37  * 2. Redistributions in binary form must reproduce the above copyright
  38  *    notice, this list of conditions and the following disclaimer in the
  39  *    documentation and/or other materials provided with the distribution.
  40  *
  41  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  42  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  43  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  44  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  45  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  46  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  47  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  48  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  49  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  50  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  51  * SUCH DAMAGE.
  52  *
  53  * $FreeBSD: head/sys/dev/drm2/i915/i915_gem.c 253497 2013-07-20 13:52:40Z kib $
  54  */
  55
  56 #include <sys/resourcevar.h>
  57 #include <sys/sfbuf.h>
  58
  59 #include <drm/drmP.h>
  60 #include <drm/i915_drm.h>
  61 #include "i915_drv.h"
  62 #include "intel_drv.h"
  63 #include "intel_ringbuffer.h"
  64
  65 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  66 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  67
  68 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
  69     int tiling_mode);
  70 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
  71     uint32_t size, int tiling_mode);
  72 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  73     unsigned alignment, bool map_and_fenceable);
  74 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
  75     int flags);
  76 static void i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj);
  77 static int i915_gem_object_set_cpu_read_domain_range(
  78     struct drm_i915_gem_object *obj, uint64_t offset, uint64_t size);
  79 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
  80 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  81 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
  82 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
  83 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
  84 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
  85 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
  86     uint32_t flush_domains);
  87 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  88     struct drm_i915_fence_reg *reg);
  89 static void i915_gem_reset_fences(struct drm_device *dev);
  90 static int i915_gem_phys_pwrite(struct drm_device *dev,
  91     struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
  92     uint64_t size, struct drm_file *file_priv);
  93 static void i915_gem_lowmem(void *arg);
  94
  95 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
  96 long i915_gem_wired_pages_cnt;
  97
  98 static void
  99 i915_gem_info_add_obj(struct drm_i915_private *dev_priv, size_t size)
 100 {
 101
 102         dev_priv->mm.object_count++;
 103         dev_priv->mm.object_memory += size;
 104 }
 105
 106 static void
 107 i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, size_t size)
 108 {
 109
 110         dev_priv->mm.object_count--;
 111         dev_priv->mm.object_memory -= size;
 112 }
 113
 114 static int
 115 i915_gem_wait_for_error(struct drm_device *dev)
 116 {
 117         struct drm_i915_private *dev_priv = dev->dev_private;
 118         int ret;
 119
 120         if (!atomic_read(&dev_priv->mm.wedged))
 121                 return 0;
 122
 123         lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
 124         while (dev_priv->error_completion == 0) {
 125                 ret = -lksleep(&dev_priv->error_completion,
 126                     &dev_priv->error_completion_lock, PCATCH, "915wco", 0);
 127                 if (ret != 0) {
 128                         lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 129                         return (ret);
 130                 }
 131         }
 132         lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 133
 134         if (atomic_read(&dev_priv->mm.wedged)) {
 135                 /* GPU is hung, bump the completion count to account for
 136                  * the token we just consumed so that we never hit zero and
 137                  * end up waiting upon a subsequent completion event that
 138                  * will never happen.
 139                  */
 140                 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
 141                 dev_priv->error_completion++;
 142                 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 143         }
 144         return 0;
 145 }
 146
 147 int
 148 i915_mutex_lock_interruptible(struct drm_device *dev)
 149 {
 150         struct drm_i915_private *dev_priv;
 151         int ret;
 152
 153         dev_priv = dev->dev_private;
 154         ret = i915_gem_wait_for_error(dev);
 155         if (ret != 0)
 156                 return (ret);
 157
 158         /*
 159          * interruptible shall it be. might indeed be if dev_lock is
 160          * changed to sx
 161          */
 162         ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
 163         if (ret != 0)
 164                 return (-ret);
 165
 166         return (0);
 167 }
 168
 169
 170 static void
 171 i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
 172 {
 173         struct drm_device *dev;
 174         drm_i915_private_t *dev_priv;
 175         int ret;
 176
 177         dev = obj->base.dev;
 178         dev_priv = dev->dev_private;
 179
 180         ret = i915_gem_object_unbind(obj);
 181         if (ret == -ERESTART) {
 182                 list_move(&obj->mm_list, &dev_priv->mm.deferred_free_list);
 183                 return;
 184         }
 185
 186         drm_gem_free_mmap_offset(&obj->base);
 187         drm_gem_object_release(&obj->base);
 188         i915_gem_info_remove_obj(dev_priv, obj->base.size);
 189
 190         drm_free(obj->page_cpu_valid, DRM_I915_GEM);
 191         drm_free(obj->bit_17, DRM_I915_GEM);
 192         drm_free(obj, DRM_I915_GEM);
 193 }
 194
 195 void
 196 i915_gem_free_object(struct drm_gem_object *gem_obj)
 197 {
 198         struct drm_i915_gem_object *obj;
 199         struct drm_device *dev;
 200
 201         obj = to_intel_bo(gem_obj);
 202         dev = obj->base.dev;
 203
 204         while (obj->pin_count > 0)
 205                 i915_gem_object_unpin(obj);
 206
 207         if (obj->phys_obj != NULL)
 208                 i915_gem_detach_phys_object(dev, obj);
 209
 210         i915_gem_free_object_tail(obj);
 211 }
 212
 213 int
 214 i915_gem_do_init(struct drm_device *dev, unsigned long start,
 215     unsigned long mappable_end, unsigned long end)
 216 {
 217         drm_i915_private_t *dev_priv;
 218         unsigned long mappable;
 219         int error;
 220
 221         dev_priv = dev->dev_private;
 222         mappable = min(end, mappable_end) - start;
 223
 224         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 225
 226         dev_priv->mm.gtt_start = start;
 227         dev_priv->mm.gtt_mappable_end = mappable_end;
 228         dev_priv->mm.gtt_end = end;
 229         dev_priv->mm.gtt_total = end - start;
 230         dev_priv->mm.mappable_gtt_total = mappable;
 231
 232         /* Take over this portion of the GTT */
 233         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 234         device_printf(dev->dev,
 235             "taking over the fictitious range 0x%lx-0x%lx\n",
 236             dev->agp->base + start, dev->agp->base + start + mappable);
 237         error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
 238             dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
 239         return (error);
 240 }
 241
 242 int
 243 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 244     struct drm_file *file)
 245 {
 246         struct drm_i915_gem_init *args;
 247         drm_i915_private_t *dev_priv;
 248
 249         dev_priv = dev->dev_private;
 250         args = data;
 251
 252         if (args->gtt_start >= args->gtt_end ||
 253             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 254                 return (-EINVAL);
 255
 256         /*
 257          * XXXKIB. The second-time initialization should be guarded
 258          * against.
 259          */
 260         lockmgr(&dev->dev_lock, LK_EXCLUSIVE|LK_RETRY|LK_CANRECURSE);
 261         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 262         lockmgr(&dev->dev_lock, LK_RELEASE);
 263
 264         return 0;
 265 }
 266
 267 int
 268 i915_gem_idle(struct drm_device *dev)
 269 {
 270         drm_i915_private_t *dev_priv;
 271         int ret;
 272
 273         dev_priv = dev->dev_private;
 274         if (dev_priv->mm.suspended)
 275                 return (0);
 276
 277         ret = i915_gpu_idle(dev, true);
 278         if (ret != 0)
 279                 return (ret);
 280
 281         /* Under UMS, be paranoid and evict. */
 282         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 283                 ret = i915_gem_evict_inactive(dev, false);
 284                 if (ret != 0)
 285                         return ret;
 286         }
 287
 288         i915_gem_reset_fences(dev);
 289
 290         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
 291          * We need to replace this with a semaphore, or something.
 292          * And not confound mm.suspended!
 293          */
 294         dev_priv->mm.suspended = 1;
 295         del_timer_sync(&dev_priv->hangcheck_timer);
 296
 297         i915_kernel_lost_context(dev);
 298         i915_gem_cleanup_ringbuffer(dev);
 299
 300         /* Cancel the retire work handler, which should be idle now. */
 301         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
 302
 303         return (ret);
 304 }
 305
 306 void
 307 i915_gem_init_swizzling(struct drm_device *dev)
 308 {
 309         drm_i915_private_t *dev_priv;
 310
 311         dev_priv = dev->dev_private;
 312
 313         if (INTEL_INFO(dev)->gen < 5 ||
 314             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
 315                 return;
 316
 317         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
 318                                  DISP_TILE_SURFACE_SWIZZLING);
 319
 320         if (IS_GEN5(dev))
 321                 return;
 322
 323         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
 324         if (IS_GEN6(dev))
 325                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
 326         else
 327                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
 328 }
 329
 330 int
 331 i915_gem_init_hw(struct drm_device *dev)
 332 {
 333         drm_i915_private_t *dev_priv;
 334         int ret;
 335
 336         dev_priv = dev->dev_private;
 337
 338         i915_gem_init_swizzling(dev);
 339
 340         ret = intel_init_render_ring_buffer(dev);
 341         if (ret != 0)
 342                 return (ret);
 343
 344         if (HAS_BSD(dev)) {
 345                 ret = intel_init_bsd_ring_buffer(dev);
 346                 if (ret != 0)
 347                         goto cleanup_render_ring;
 348         }
 349
 350         if (HAS_BLT(dev)) {
 351                 ret = intel_init_blt_ring_buffer(dev);
 352                 if (ret != 0)
 353                         goto cleanup_bsd_ring;
 354         }
 355
 356         dev_priv->next_seqno = 1;
 357         i915_gem_init_ppgtt(dev);
 358         return (0);
 359
 360 cleanup_bsd_ring:
 361         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
 362 cleanup_render_ring:
 363         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
 364         return (ret);
 365 }
 366
 367 int
 368 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 369     struct drm_file *file)
 370 {
 371         struct drm_i915_private *dev_priv;
 372         struct drm_i915_gem_get_aperture *args;
 373         struct drm_i915_gem_object *obj;
 374         size_t pinned;
 375
 376         dev_priv = dev->dev_private;
 377         args = data;
 378
 379         if (!(dev->driver->driver_features & DRIVER_GEM))
 380                 return (-ENODEV);
 381
 382         pinned = 0;
 383         DRM_LOCK(dev);
 384         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 385                 pinned += obj->gtt_space->size;
 386         DRM_UNLOCK(dev);
 387
 388         args->aper_size = dev_priv->mm.gtt_total;
 389         args->aper_available_size = args->aper_size - pinned;
 390
 391         return (0);
 392 }
 393
 394 int
 395 i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
 396      bool map_and_fenceable)
 397 {
 398         struct drm_device *dev;
 399         struct drm_i915_private *dev_priv;
 400         int ret;
 401
 402         dev = obj->base.dev;
 403         dev_priv = dev->dev_private;
 404
 405         KASSERT(obj->pin_count != DRM_I915_GEM_OBJECT_MAX_PIN_COUNT,
 406             ("Max pin count"));
 407
 408         if (obj->gtt_space != NULL) {
 409                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
 410                     (map_and_fenceable && !obj->map_and_fenceable)) {
 411                         DRM_DEBUG("bo is already pinned with incorrect alignment:"
 412                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
 413                              " obj->map_and_fenceable=%d\n",
 414                              obj->gtt_offset, alignment,
 415                              map_and_fenceable,
 416                              obj->map_and_fenceable);
 417                         ret = i915_gem_object_unbind(obj);
 418                         if (ret != 0)
 419                                 return (ret);
 420                 }
 421         }
 422
 423         if (obj->gtt_space == NULL) {
 424                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
 425                     map_and_fenceable);
 426                 if (ret)
 427                         return (ret);
 428         }
 429
 430         if (obj->pin_count++ == 0 && !obj->active)
 431                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
 432         obj->pin_mappable |= map_and_fenceable;
 433
 434 #if 1
 435         KIB_NOTYET();
 436 #else
 437         WARN_ON(i915_verify_lists(dev));
 438 #endif
 439         return (0);
 440 }
 441
 442 void
 443 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
 444 {
 445         struct drm_device *dev;
 446         drm_i915_private_t *dev_priv;
 447
 448         dev = obj->base.dev;
 449         dev_priv = dev->dev_private;
 450
 451 #if 1
 452         KIB_NOTYET();
 453 #else
 454         WARN_ON(i915_verify_lists(dev));
 455 #endif
 456
 457         KASSERT(obj->pin_count != 0, ("zero pin count"));
 458         KASSERT(obj->gtt_space != NULL, ("No gtt mapping"));
 459
 460         if (--obj->pin_count == 0) {
 461                 if (!obj->active)
 462                         list_move_tail(&obj->mm_list,
 463                             &dev_priv->mm.inactive_list);
 464                 obj->pin_mappable = false;
 465         }
 466 #if 1
 467         KIB_NOTYET();
 468 #else
 469         WARN_ON(i915_verify_lists(dev));
 470 #endif
 471 }
 472
 473 int
 474 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 475     struct drm_file *file)
 476 {
 477         struct drm_i915_gem_pin *args;
 478         struct drm_i915_gem_object *obj;
 479         struct drm_gem_object *gobj;
 480         int ret;
 481
 482         args = data;
 483
 484         ret = i915_mutex_lock_interruptible(dev);
 485         if (ret != 0)
 486                 return ret;
 487
 488         gobj = drm_gem_object_lookup(dev, file, args->handle);
 489         if (gobj == NULL) {
 490                 ret = -ENOENT;
 491                 goto unlock;
 492         }
 493         obj = to_intel_bo(gobj);
 494
 495         if (obj->madv != I915_MADV_WILLNEED) {
 496                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
 497                 ret = -EINVAL;
 498                 goto out;
 499         }
 500
 501         if (obj->pin_filp != NULL && obj->pin_filp != file) {
 502                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
 503                     args->handle);
 504                 ret = -EINVAL;
 505                 goto out;
 506         }
 507
 508         obj->user_pin_count++;
 509         obj->pin_filp = file;
 510         if (obj->user_pin_count == 1) {
 511                 ret = i915_gem_object_pin(obj, args->alignment, true);
 512                 if (ret != 0)
 513                         goto out;
 514         }
 515
 516         /* XXX - flush the CPU caches for pinned objects
 517          * as the X server doesn't manage domains yet
 518          */
 519         i915_gem_object_flush_cpu_write_domain(obj);
 520         args->offset = obj->gtt_offset;
 521 out:
 522         drm_gem_object_unreference(&obj->base);
 523 unlock:
 524         DRM_UNLOCK(dev);
 525         return (ret);
 526 }
 527
 528 int
 529 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 530     struct drm_file *file)
 531 {
 532         struct drm_i915_gem_pin *args;
 533         struct drm_i915_gem_object *obj;
 534         int ret;
 535
 536         args = data;
 537         ret = i915_mutex_lock_interruptible(dev);
 538         if (ret != 0)
 539                 return (ret);
 540
 541         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 542         if (&obj->base == NULL) {
 543                 ret = -ENOENT;
 544                 goto unlock;
 545         }
 546
 547         if (obj->pin_filp != file) {
 548                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
 549                     args->handle);
 550                 ret = -EINVAL;
 551                 goto out;
 552         }
 553         obj->user_pin_count--;
 554         if (obj->user_pin_count == 0) {
 555                 obj->pin_filp = NULL;
 556                 i915_gem_object_unpin(obj);
 557         }
 558
 559 out:
 560         drm_gem_object_unreference(&obj->base);
 561 unlock:
 562         DRM_UNLOCK(dev);
 563         return (ret);
 564 }
 565
 566 int
 567 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 568     struct drm_file *file)
 569 {
 570         struct drm_i915_gem_busy *args;
 571         struct drm_i915_gem_object *obj;
 572         struct drm_i915_gem_request *request;
 573         int ret;
 574
 575         args = data;
 576
 577         ret = i915_mutex_lock_interruptible(dev);
 578         if (ret != 0)
 579                 return ret;
 580
 581         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 582         if (&obj->base == NULL) {
 583                 ret = -ENOENT;
 584                 goto unlock;
 585         }
 586
 587         args->busy = obj->active;
 588         if (args->busy) {
 589                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
 590                         ret = i915_gem_flush_ring(obj->ring,
 591                             0, obj->base.write_domain);
 592                 } else if (obj->ring->outstanding_lazy_request ==
 593                     obj->last_rendering_seqno) {
 594                         request = kmalloc(sizeof(*request), DRM_I915_GEM,
 595                             M_WAITOK | M_ZERO);
 596                         ret = i915_add_request(obj->ring, NULL, request);
 597                         if (ret != 0)
 598                                 drm_free(request, DRM_I915_GEM);
 599                 }
 600
 601                 i915_gem_retire_requests_ring(obj->ring);
 602                 args->busy = obj->active;
 603         }
 604
 605         drm_gem_object_unreference(&obj->base);
 606 unlock:
 607         DRM_UNLOCK(dev);
 608         return (ret);
 609 }
 610
 611 static int
 612 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
 613 {
 614
 615         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
 616                 return (0);
 617         return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
 618 }
 619
 620 /**
 621  * Moves a single object to the CPU read, and possibly write domain.
 622  *
 623  * This function returns when the move is complete, including waiting on
 624  * flushes to occur.
 625  */
 626 int
 627 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
 628 {
 629         uint32_t old_write_domain, old_read_domains;
 630         int ret;
 631
 632         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
 633                 return 0;
 634
 635         ret = i915_gem_object_flush_gpu_write_domain(obj);
 636         if (ret != 0)
 637                 return (ret);
 638
 639         ret = i915_gem_object_wait_rendering(obj);
 640         if (ret)
 641                 return ret;
 642
 643         i915_gem_object_flush_gtt_write_domain(obj);
 644
 645         old_write_domain = obj->base.write_domain;
 646         old_read_domains = obj->base.read_domains;
 647
 648         /* Flush the CPU cache if it's still invalid. */
 649         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
 650                 i915_gem_clflush_object(obj);
 651
 652                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
 653         }
 654
 655         /* It should now be out of any other write domains, and we can update
 656          * the domain values for our changes.
 657          */
 658         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
 659
 660         /* If we're writing through the CPU, then the GPU read domains will
 661          * need to be invalidated at next use.
 662          */
 663         if (write) {
 664                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
 665                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 666         }
 667
 668         return 0;
 669 }
 670
 671 /* Throttle our rendering by waiting until the ring has completed our requests
 672  * emitted over 20 msec ago.
 673  *
 674  * Note that if we were to use the current jiffies each time around the loop,
 675  * we wouldn't escape the function with any frames outstanding if the time to
 676  * render a frame was over 20ms.
 677  *
 678  * This should get us reasonable parallelism between CPU and GPU but also
 679  * relatively low latency when blocking on a particular request to finish.
 680  */
 681 static int
 682 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
 683 {
 684         struct drm_i915_private *dev_priv = dev->dev_private;
 685         struct drm_i915_file_private *file_priv = file->driver_priv;
 686         unsigned long recent_enough = ticks - (20 * hz / 1000);
 687         struct drm_i915_gem_request *request;
 688         struct intel_ring_buffer *ring = NULL;
 689         u32 seqno = 0;
 690         int ret;
 691
 692         dev_priv = dev->dev_private;
 693         if (atomic_read(&dev_priv->mm.wedged))
 694                 return -EIO;
 695
 696         recent_enough = ticks - (20 * hz / 1000);
 697         ring = NULL;
 698         seqno = 0;
 699
 700         spin_lock(&file_priv->mm.lock);
 701         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
 702                 if (time_after_eq(request->emitted_jiffies, recent_enough))
 703                         break;
 704
 705                 ring = request->ring;
 706                 seqno = request->seqno;
 707         }
 708         spin_unlock(&file_priv->mm.lock);
 709
 710         if (seqno == 0)
 711                 return 0;
 712
 713         ret = 0;
 714         lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
 715         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
 716                 if (ring->irq_get(ring)) {
 717                         while (ret == 0 &&
 718                             !(i915_seqno_passed(ring->get_seqno(ring), seqno) ||
 719                             atomic_read(&dev_priv->mm.wedged)))
 720                                 ret = -lksleep(ring, &ring->irq_lock, PCATCH,
 721                                     "915thr", 0);
 722                         ring->irq_put(ring);
 723                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
 724                                 ret = -EIO;
 725                 } else if (_intel_wait_for(dev,
 726                     i915_seqno_passed(ring->get_seqno(ring), seqno) ||
 727                     atomic_read(&dev_priv->mm.wedged), 3000, 0, "915rtr")) {
 728                         ret = -EBUSY;
 729                 }
 730         }
 731         lockmgr(&ring->irq_lock, LK_RELEASE);
 732
 733         if (ret == 0)
 734                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
 735
 736         return ret;
 737 }
 738
 739 int
 740 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 741     struct drm_file *file_priv)
 742 {
 743
 744         return (i915_gem_ring_throttle(dev, file_priv));
 745 }
 746
 747 int
 748 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 749                        struct drm_file *file_priv)
 750 {
 751         struct drm_i915_gem_madvise *args = data;
 752         struct drm_i915_gem_object *obj;
 753         int ret;
 754
 755         switch (args->madv) {
 756         case I915_MADV_DONTNEED:
 757         case I915_MADV_WILLNEED:
 758             break;
 759         default:
 760             return -EINVAL;
 761         }
 762
 763         ret = i915_mutex_lock_interruptible(dev);
 764         if (ret)
 765                 return ret;
 766
 767         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
 768         if (&obj->base == NULL) {
 769                 ret = -ENOENT;
 770                 goto unlock;
 771         }
 772
 773         if (obj->pin_count) {
 774                 ret = -EINVAL;
 775                 goto out;
 776         }
 777
 778         if (obj->madv != __I915_MADV_PURGED)
 779                 obj->madv = args->madv;
 780
 781         /* if the object is no longer attached, discard its backing storage */
 782         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
 783                 i915_gem_object_truncate(obj);
 784
 785         args->retained = obj->madv != __I915_MADV_PURGED;
 786
 787 out:
 788         drm_gem_object_unreference(&obj->base);
 789 unlock:
 790         DRM_UNLOCK(dev);
 791         return ret;
 792 }
 793
 794 void
 795 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
 796 {
 797         drm_i915_private_t *dev_priv;
 798         int i;
 799
 800         dev_priv = dev->dev_private;
 801         for (i = 0; i < I915_NUM_RINGS; i++)
 802                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 803 }
 804
 805 int
 806 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 807                        struct drm_file *file_priv)
 808 {
 809         drm_i915_private_t *dev_priv = dev->dev_private;
 810         int ret;
 811
 812         if (drm_core_check_feature(dev, DRIVER_MODESET))
 813                 return 0;
 814
 815         if (atomic_read(&dev_priv->mm.wedged)) {
 816                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
 817                 atomic_set(&dev_priv->mm.wedged, 0);
 818         }
 819
 820         DRM_LOCK(dev);
 821         dev_priv->mm.suspended = 0;
 822
 823         ret = i915_gem_init_hw(dev);
 824         if (ret != 0) {
 825                 DRM_UNLOCK(dev);
 826                 return ret;
 827         }
 828
 829         KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
 830         DRM_UNLOCK(dev);
 831
 832         ret = drm_irq_install(dev);
 833         if (ret)
 834                 goto cleanup_ringbuffer;
 835
 836         return 0;
 837
 838 cleanup_ringbuffer:
 839         DRM_LOCK(dev);
 840         i915_gem_cleanup_ringbuffer(dev);
 841         dev_priv->mm.suspended = 1;
 842         DRM_UNLOCK(dev);
 843
 844         return ret;
 845 }
 846
 847 int
 848 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 849     struct drm_file *file_priv)
 850 {
 851
 852         if (drm_core_check_feature(dev, DRIVER_MODESET))
 853                 return 0;
 854
 855         drm_irq_uninstall(dev);
 856         return (i915_gem_idle(dev));
 857 }
 858
 859 int
 860 i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size,
 861     uint32_t *handle_p)
 862 {
 863         struct drm_i915_gem_object *obj;
 864         uint32_t handle;
 865         int ret;
 866
 867         size = roundup(size, PAGE_SIZE);
 868         if (size == 0)
 869                 return (-EINVAL);
 870
 871         obj = i915_gem_alloc_object(dev, size);
 872         if (obj == NULL)
 873                 return (-ENOMEM);
 874
 875         handle = 0;
 876         ret = drm_gem_handle_create(file, &obj->base, &handle);
 877         if (ret != 0) {
 878                 drm_gem_object_release(&obj->base);
 879                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 880                 drm_free(obj, DRM_I915_GEM);
 881                 return (-ret);
 882         }
 883
 884         /* drop reference from allocate - handle holds it now */
 885         drm_gem_object_unreference(&obj->base);
 886         *handle_p = handle;
 887         return (0);
 888 }
 889
 890 int
 891 i915_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 892     struct drm_mode_create_dumb *args)
 893 {
 894
 895         /* have to work out size/pitch and return them */
 896         args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
 897         args->size = args->pitch * args->height;
 898         return (i915_gem_create(file, dev, args->size, &args->handle));
 899 }
 900
 901 int
 902 i915_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
 903     uint32_t handle)
 904 {
 905
 906         return (drm_gem_handle_delete(file, handle));
 907 }
 908
 909 int
 910 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 911     struct drm_file *file)
 912 {
 913         struct drm_i915_gem_create *args = data;
 914
 915         return (i915_gem_create(file, dev, args->size, &args->handle));
 916 }
 917
 918 static inline void vm_page_reference(vm_page_t m)
 919 {
 920         vm_page_flag_set(m, PG_REFERENCED);
 921 }
 922
 923 static int
 924 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
 925     uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
 926     struct drm_file *file)
 927 {
 928         vm_object_t vm_obj;
 929         vm_page_t m;
 930         struct sf_buf *sf;
 931         vm_offset_t mkva;
 932         vm_pindex_t obj_pi;
 933         int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
 934
 935         if (obj->gtt_offset != 0 && rw == UIO_READ)
 936                 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 937         else
 938                 do_bit17_swizzling = 0;
 939
 940         obj->dirty = 1;
 941         vm_obj = obj->base.vm_obj;
 942         ret = 0;
 943
 944         VM_OBJECT_LOCK(vm_obj);
 945         vm_object_pip_add(vm_obj, 1);
 946         while (size > 0) {
 947                 obj_pi = OFF_TO_IDX(offset);
 948                 obj_po = offset & PAGE_MASK;
 949
 950                 m = i915_gem_wire_page(vm_obj, obj_pi);
 951                 VM_OBJECT_UNLOCK(vm_obj);
 952
 953                 sf = sf_buf_alloc(m);
 954                 mkva = sf_buf_kva(sf);
 955                 length = min(size, PAGE_SIZE - obj_po);
 956                 while (length > 0) {
 957                         if (do_bit17_swizzling &&
 958                             (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
 959                                 cnt = roundup2(obj_po + 1, 64);
 960                                 cnt = min(cnt - obj_po, length);
 961                                 swizzled_po = obj_po ^ 64;
 962                         } else {
 963                                 cnt = length;
 964                                 swizzled_po = obj_po;
 965                         }
 966                         if (rw == UIO_READ)
 967                                 ret = -copyout_nofault(
 968                                     (char *)mkva + swizzled_po,
 969                                     (void *)(uintptr_t)data_ptr, cnt);
 970                         else
 971                                 ret = -copyin_nofault(
 972                                     (void *)(uintptr_t)data_ptr,
 973                                     (char *)mkva + swizzled_po, cnt);
 974                         if (ret != 0)
 975                                 break;
 976                         data_ptr += cnt;
 977                         size -= cnt;
 978                         length -= cnt;
 979                         offset += cnt;
 980                         obj_po += cnt;
 981                 }
 982                 sf_buf_free(sf);
 983                 VM_OBJECT_LOCK(vm_obj);
 984                 if (rw == UIO_WRITE)
 985                         vm_page_dirty(m);
 986                 vm_page_reference(m);
 987                 vm_page_busy_wait(m, FALSE, "i915gem");
 988                 vm_page_unwire(m, 1);
 989                 vm_page_wakeup(m);
 990                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
 991
 992                 if (ret != 0)
 993                         break;
 994         }
 995         vm_object_pip_wakeup(vm_obj);
 996         VM_OBJECT_UNLOCK(vm_obj);
 997
 998         return (ret);
 999 }
1000
1001 static int
1002 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
1003     uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
1004 {
1005         vm_offset_t mkva;
1006         int ret;
1007
1008         /*
1009          * Pass the unaligned physical address and size to pmap_mapdev_attr()
1010          * so it can properly calculate whether an extra page needs to be
1011          * mapped or not to cover the requested range.  The function will
1012          * add the page offset into the returned mkva for us.
1013          */
1014         mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
1015             offset, size, PAT_WRITE_COMBINING);
1016         ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
1017         pmap_unmapdev(mkva, size);
1018         return (ret);
1019 }
1020
1021 static int
1022 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
1023     uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
1024 {
1025         struct drm_i915_gem_object *obj;
1026         vm_page_t *ma;
1027         vm_offset_t start, end;
1028         int npages, ret;
1029
1030         if (size == 0)
1031                 return (0);
1032         start = trunc_page(data_ptr);
1033         end = round_page(data_ptr + size);
1034         npages = howmany(end - start, PAGE_SIZE);
1035         ma = kmalloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
1036             M_ZERO);
1037         npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
1038             (vm_offset_t)data_ptr, size,
1039             (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
1040         if (npages == -1) {
1041                 ret = -EFAULT;
1042                 goto free_ma;
1043         }
1044
1045         ret = i915_mutex_lock_interruptible(dev);
1046         if (ret != 0)
1047                 goto unlocked;
1048
1049         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1050         if (&obj->base == NULL) {
1051                 ret = -ENOENT;
1052                 goto unlock;
1053         }
1054         if (offset > obj->base.size || size > obj->base.size - offset) {
1055                 ret = -EINVAL;
1056                 goto out;
1057         }
1058
1059         if (rw == UIO_READ) {
1060                 ret = i915_gem_object_set_cpu_read_domain_range(obj,
1061                     offset, size);
1062                 if (ret != 0)
1063                         goto out;
1064                 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1065                     UIO_READ, file);
1066         } else {
1067                 if (obj->phys_obj) {
1068                         ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
1069                             size, file);
1070                 } else if (obj->gtt_space &&
1071                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1072                         ret = i915_gem_object_pin(obj, 0, true);
1073                         if (ret != 0)
1074                                 goto out;
1075                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1076                         if (ret != 0)
1077                                 goto out_unpin;
1078                         ret = i915_gem_object_put_fence(obj);
1079                         if (ret != 0)
1080                                 goto out_unpin;
1081                         ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
1082                             offset, file);
1083 out_unpin:
1084                         i915_gem_object_unpin(obj);
1085                 } else {
1086                         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1087                         if (ret != 0)
1088                                 goto out;
1089                         ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1090                             UIO_WRITE, file);
1091                 }
1092         }
1093 out:
1094         drm_gem_object_unreference(&obj->base);
1095 unlock:
1096         DRM_UNLOCK(dev);
1097 unlocked:
1098         vm_page_unhold_pages(ma, npages);
1099 free_ma:
1100         drm_free(ma, DRM_I915_GEM);
1101         return (ret);
1102 }
1103
1104 int
1105 i915_gem_pread_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1106 {
1107         struct drm_i915_gem_pread *args;
1108
1109         args = data;
1110         return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1111             args->offset, UIO_READ, file));
1112 }
1113
1114 int
1115 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1116 {
1117         struct drm_i915_gem_pwrite *args;
1118
1119         args = data;
1120         return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1121             args->offset, UIO_WRITE, file));
1122 }
1123
1124 int
1125 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1126     struct drm_file *file)
1127 {
1128         struct drm_i915_gem_set_domain *args;
1129         struct drm_i915_gem_object *obj;
1130         uint32_t read_domains;
1131         uint32_t write_domain;
1132         int ret;
1133
1134         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1135                 return (-ENODEV);
1136
1137         args = data;
1138         read_domains = args->read_domains;
1139         write_domain = args->write_domain;
1140
1141         if ((write_domain & I915_GEM_GPU_DOMAINS) != 0 ||
1142             (read_domains & I915_GEM_GPU_DOMAINS) != 0 ||
1143             (write_domain != 0 && read_domains != write_domain))
1144                 return (-EINVAL);
1145
1146         ret = i915_mutex_lock_interruptible(dev);
1147         if (ret != 0)
1148                 return (ret);
1149
1150         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1151         if (&obj->base == NULL) {
1152                 ret = -ENOENT;
1153                 goto unlock;
1154         }
1155
1156         if ((read_domains & I915_GEM_DOMAIN_GTT) != 0) {
1157                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1158                 if (ret == -EINVAL)
1159                         ret = 0;
1160         } else
1161                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1162
1163         drm_gem_object_unreference(&obj->base);
1164 unlock:
1165         DRM_UNLOCK(dev);
1166         return (ret);
1167 }
1168
1169 int
1170 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1171     struct drm_file *file)
1172 {
1173         struct drm_i915_gem_sw_finish *args;
1174         struct drm_i915_gem_object *obj;
1175         int ret;
1176
1177         args = data;
1178         ret = 0;
1179         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1180                 return (ENODEV);
1181         ret = i915_mutex_lock_interruptible(dev);
1182         if (ret != 0)
1183                 return (ret);
1184         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1185         if (&obj->base == NULL) {
1186                 ret = -ENOENT;
1187                 goto unlock;
1188         }
1189         if (obj->pin_count != 0)
1190                 i915_gem_object_flush_cpu_write_domain(obj);
1191         drm_gem_object_unreference(&obj->base);
1192 unlock:
1193         DRM_UNLOCK(dev);
1194         return (ret);
1195 }
1196
1197 int
1198 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1199     struct drm_file *file)
1200 {
1201         struct drm_i915_gem_mmap *args;
1202         struct drm_gem_object *obj;
1203         struct proc *p;
1204         vm_map_t map;
1205         vm_offset_t addr;
1206         vm_size_t size;
1207         int error, rv;
1208
1209         args = data;
1210
1211         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1212                 return (-ENODEV);
1213
1214         obj = drm_gem_object_lookup(dev, file, args->handle);
1215         if (obj == NULL)
1216                 return (-ENOENT);
1217         error = 0;
1218         if (args->size == 0)
1219                 goto out;
1220         p = curproc;
1221         map = &p->p_vmspace->vm_map;
1222         size = round_page(args->size);
1223         PROC_LOCK(p);
1224         if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1225                 PROC_UNLOCK(p);
1226                 error = ENOMEM;
1227                 goto out;
1228         }
1229         PROC_UNLOCK(p);
1230
1231         addr = 0;
1232         vm_object_hold(obj->vm_obj);
1233         vm_object_reference_locked(obj->vm_obj);
1234         vm_object_drop(obj->vm_obj);
1235         DRM_UNLOCK(dev);
1236         rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size,
1237             PAGE_SIZE, /* align */
1238             TRUE, /* fitit */
1239             VM_MAPTYPE_NORMAL, /* maptype */
1240             VM_PROT_READ | VM_PROT_WRITE, /* prot */
1241             VM_PROT_READ | VM_PROT_WRITE, /* max */
1242             MAP_SHARED /* cow */);
1243         if (rv != KERN_SUCCESS) {
1244                 vm_object_deallocate(obj->vm_obj);
1245                 error = -vm_mmap_to_errno(rv);
1246         } else {
1247                 args->addr_ptr = (uint64_t)addr;
1248         }
1249         DRM_LOCK(dev);
1250 out:
1251         drm_gem_object_unreference(obj);
1252         return (error);
1253 }
1254
1255 static int
1256 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
1257     vm_ooffset_t foff, struct ucred *cred, u_short *color)
1258 {
1259
1260         *color = 0; /* XXXKIB */
1261         return (0);
1262 }
1263
1264 int i915_intr_pf;
1265
1266 static int
1267 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1268     vm_page_t *mres)
1269 {
1270         struct drm_gem_object *gem_obj;
1271         struct drm_i915_gem_object *obj;
1272         struct drm_device *dev;
1273         drm_i915_private_t *dev_priv;
1274         vm_page_t m, oldm;
1275         int cause, ret;
1276         bool write;
1277
1278         gem_obj = vm_obj->handle;
1279         obj = to_intel_bo(gem_obj);
1280         dev = obj->base.dev;
1281         dev_priv = dev->dev_private;
1282 #if 0
1283         write = (prot & VM_PROT_WRITE) != 0;
1284 #else
1285         write = true;
1286 #endif
1287         vm_object_pip_add(vm_obj, 1);
1288
1289         /*
1290          * Remove the placeholder page inserted by vm_fault() from the
1291          * object before dropping the object lock. If
1292          * i915_gem_release_mmap() is active in parallel on this gem
1293          * object, then it owns the drm device sx and might find the
1294          * placeholder already. Then, since the page is busy,
1295          * i915_gem_release_mmap() sleeps waiting for the busy state
1296          * of the page cleared. We will be not able to acquire drm
1297          * device lock until i915_gem_release_mmap() is able to make a
1298          * progress.
1299          */
1300         if (*mres != NULL) {
1301                 oldm = *mres;
1302                 vm_page_remove(oldm);
1303                 *mres = NULL;
1304         } else
1305                 oldm = NULL;
1306 retry:
1307         VM_OBJECT_UNLOCK(vm_obj);
1308 unlocked_vmobj:
1309         cause = ret = 0;
1310         m = NULL;
1311
1312         if (i915_intr_pf) {
1313                 ret = i915_mutex_lock_interruptible(dev);
1314                 if (ret != 0) {
1315                         cause = 10;
1316                         goto out;
1317                 }
1318         } else
1319                 DRM_LOCK(dev);
1320
1321         /*
1322          * Since the object lock was dropped, other thread might have
1323          * faulted on the same GTT address and instantiated the
1324          * mapping for the page.  Recheck.
1325          */
1326         VM_OBJECT_LOCK(vm_obj);
1327         m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1328         if (m != NULL) {
1329                 if ((m->flags & PG_BUSY) != 0) {
1330                         DRM_UNLOCK(dev);
1331 #if 0 /* XXX */
1332                         vm_page_sleep(m, "915pee");
1333 #endif
1334                         goto retry;
1335                 }
1336                 goto have_page;
1337         } else
1338                 VM_OBJECT_UNLOCK(vm_obj);
1339
1340         /* Now bind it into the GTT if needed */
1341         if (!obj->map_and_fenceable) {
1342                 ret = i915_gem_object_unbind(obj);
1343                 if (ret != 0) {
1344                         cause = 20;
1345                         goto unlock;
1346                 }
1347         }
1348         if (!obj->gtt_space) {
1349                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1350                 if (ret != 0) {
1351                         cause = 30;
1352                         goto unlock;
1353                 }
1354
1355                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1356                 if (ret != 0) {
1357                         cause = 40;
1358                         goto unlock;
1359                 }
1360         }
1361
1362         if (obj->tiling_mode == I915_TILING_NONE)
1363                 ret = i915_gem_object_put_fence(obj);
1364         else
1365                 ret = i915_gem_object_get_fence(obj, NULL);
1366         if (ret != 0) {
1367                 cause = 50;
1368                 goto unlock;
1369         }
1370
1371         if (i915_gem_object_is_inactive(obj))
1372                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1373
1374         obj->fault_mappable = true;
1375         VM_OBJECT_LOCK(vm_obj);
1376         m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
1377             offset);
1378         if (m == NULL) {
1379                 cause = 60;
1380                 ret = -EFAULT;
1381                 goto unlock;
1382         }
1383         KASSERT((m->flags & PG_FICTITIOUS) != 0,
1384             ("not fictitious %p", m));
1385         KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1386
1387         if ((m->flags & PG_BUSY) != 0) {
1388                 DRM_UNLOCK(dev);
1389 #if 0 /* XXX */
1390                 vm_page_sleep(m, "915pbs");
1391 #endif
1392                 goto retry;
1393         }
1394         m->valid = VM_PAGE_BITS_ALL;
1395         vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1396 have_page:
1397         *mres = m;
1398         vm_page_busy_try(m, false);
1399
1400         DRM_UNLOCK(dev);
1401         if (oldm != NULL) {
1402                 vm_page_free(oldm);
1403         }
1404         vm_object_pip_wakeup(vm_obj);
1405         return (VM_PAGER_OK);
1406
1407 unlock:
1408         DRM_UNLOCK(dev);
1409 out:
1410         KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1411         if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1412                 goto unlocked_vmobj;
1413         }
1414         VM_OBJECT_LOCK(vm_obj);
1415         vm_object_pip_wakeup(vm_obj);
1416         return (VM_PAGER_ERROR);
1417 }
1418
1419 static void
1420 i915_gem_pager_dtor(void *handle)
1421 {
1422         struct drm_gem_object *obj;
1423         struct drm_device *dev;
1424
1425         obj = handle;
1426         dev = obj->dev;
1427
1428         DRM_LOCK(dev);
1429         drm_gem_free_mmap_offset(obj);
1430         i915_gem_release_mmap(to_intel_bo(obj));
1431         drm_gem_object_unreference(obj);
1432         DRM_UNLOCK(dev);
1433 }
1434
1435 struct cdev_pager_ops i915_gem_pager_ops = {
1436         .cdev_pg_fault  = i915_gem_pager_fault,
1437         .cdev_pg_ctor   = i915_gem_pager_ctor,
1438         .cdev_pg_dtor   = i915_gem_pager_dtor
1439 };
1440
1441 int
1442 i915_gem_mmap_gtt(struct drm_file *file, struct drm_device *dev,
1443     uint32_t handle, uint64_t *offset)
1444 {
1445         struct drm_i915_private *dev_priv;
1446         struct drm_i915_gem_object *obj;
1447         int ret;
1448
1449         if (!(dev->driver->driver_features & DRIVER_GEM))
1450                 return (-ENODEV);
1451
1452         dev_priv = dev->dev_private;
1453
1454         ret = i915_mutex_lock_interruptible(dev);
1455         if (ret != 0)
1456                 return (ret);
1457
1458         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1459         if (&obj->base == NULL) {
1460                 ret = -ENOENT;
1461                 goto unlock;
1462         }
1463
1464         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1465                 ret = -E2BIG;
1466                 goto out;
1467         }
1468
1469         if (obj->madv != I915_MADV_WILLNEED) {
1470                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1471                 ret = -EINVAL;
1472                 goto out;
1473         }
1474
1475         ret = drm_gem_create_mmap_offset(&obj->base);
1476         if (ret != 0)
1477                 goto out;
1478
1479         *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1480             DRM_GEM_MAPPING_KEY;
1481 out:
1482         drm_gem_object_unreference(&obj->base);
1483 unlock:
1484         DRM_UNLOCK(dev);
1485         return (ret);
1486 }
1487
1488 int
1489 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1490     struct drm_file *file)
1491 {
1492         struct drm_i915_private *dev_priv;
1493         struct drm_i915_gem_mmap_gtt *args;
1494
1495         dev_priv = dev->dev_private;
1496         args = data;
1497
1498         return (i915_gem_mmap_gtt(file, dev, args->handle, &args->offset));
1499 }
1500
1501 struct drm_i915_gem_object *
1502 i915_gem_alloc_object(struct drm_device *dev, size_t size)
1503 {
1504         struct drm_i915_private *dev_priv;
1505         struct drm_i915_gem_object *obj;
1506
1507         dev_priv = dev->dev_private;
1508
1509         obj = kmalloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
1510
1511         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
1512                 drm_free(obj, DRM_I915_GEM);
1513                 return (NULL);
1514         }
1515
1516         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1517         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1518
1519         if (HAS_LLC(dev))
1520                 obj->cache_level = I915_CACHE_LLC;
1521         else
1522                 obj->cache_level = I915_CACHE_NONE;
1523         obj->base.driver_private = NULL;
1524         obj->fence_reg = I915_FENCE_REG_NONE;
1525         INIT_LIST_HEAD(&obj->mm_list);
1526         INIT_LIST_HEAD(&obj->gtt_list);
1527         INIT_LIST_HEAD(&obj->ring_list);
1528         INIT_LIST_HEAD(&obj->exec_list);
1529         INIT_LIST_HEAD(&obj->gpu_write_list);
1530         obj->madv = I915_MADV_WILLNEED;
1531         /* Avoid an unnecessary call to unbind on the first bind. */
1532         obj->map_and_fenceable = true;
1533
1534         i915_gem_info_add_obj(dev_priv, size);
1535
1536         return (obj);
1537 }
1538
1539 void
1540 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
1541 {
1542
1543         /* If we don't have a page list set up, then we're not pinned
1544          * to GPU, and we can ignore the cache flush because it'll happen
1545          * again at bind time.
1546          */
1547         if (obj->pages == NULL)
1548                 return;
1549
1550         /* If the GPU is snooping the contents of the CPU cache,
1551          * we do not need to manually clear the CPU cache lines.  However,
1552          * the caches are only snooped when the render cache is
1553          * flushed/invalidated.  As we always have to emit invalidations
1554          * and flushes when moving into and out of the RENDER domain, correct
1555          * snooping behaviour occurs naturally as the result of our domain
1556          * tracking.
1557          */
1558         if (obj->cache_level != I915_CACHE_NONE)
1559                 return;
1560
1561         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
1562 }
1563
1564 static void
1565 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
1566 {
1567         uint32_t old_write_domain;
1568
1569         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
1570                 return;
1571
1572         i915_gem_clflush_object(obj);
1573         intel_gtt_chipset_flush();
1574         old_write_domain = obj->base.write_domain;
1575         obj->base.write_domain = 0;
1576 }
1577
1578 /** Flushes the GTT write domain for the object if it's dirty. */
1579 static void
1580 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
1581 {
1582         uint32_t old_write_domain;
1583
1584         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
1585                 return;
1586
1587         /* No actual flushing is required for the GTT write domain.  Writes
1588          * to it immediately go to main memory as far as we know, so there's
1589          * no chipset flush.  It also doesn't land in render cache.
1590          *
1591          * However, we do have to enforce the order so that all writes through
1592          * the GTT land before any writes to the device, such as updates to
1593          * the GATT itself.
1594          */
1595         cpu_sfence();
1596
1597         old_write_domain = obj->base.write_domain;
1598         obj->base.write_domain = 0;
1599 }
1600
1601 int
1602 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
1603 {
1604         uint32_t old_write_domain, old_read_domains;
1605         int ret;
1606
1607         if (obj->gtt_space == NULL)
1608                 return (-EINVAL);
1609
1610         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
1611                 return 0;
1612
1613         ret = i915_gem_object_flush_gpu_write_domain(obj);
1614         if (ret != 0)
1615                 return (ret);
1616
1617         if (obj->pending_gpu_write || write) {
1618                 ret = i915_gem_object_wait_rendering(obj);
1619                 if (ret != 0)
1620                         return (ret);
1621         }
1622
1623         i915_gem_object_flush_cpu_write_domain(obj);
1624
1625         old_write_domain = obj->base.write_domain;
1626         old_read_domains = obj->base.read_domains;
1627
1628         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1629             ("In GTT write domain"));
1630         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1631         if (write) {
1632                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
1633                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
1634                 obj->dirty = 1;
1635         }
1636
1637         return (0);
1638 }
1639
1640 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1641                                     enum i915_cache_level cache_level)
1642 {
1643         struct drm_device *dev = obj->base.dev;
1644         drm_i915_private_t *dev_priv = dev->dev_private;
1645         int ret;
1646
1647         if (obj->cache_level == cache_level)
1648                 return 0;
1649
1650         if (obj->pin_count) {
1651                 DRM_DEBUG("can not change the cache level of pinned objects\n");
1652                 return -EBUSY;
1653         }
1654
1655         if (obj->gtt_space) {
1656                 ret = i915_gem_object_finish_gpu(obj);
1657                 if (ret != 0)
1658                         return (ret);
1659
1660                 i915_gem_object_finish_gtt(obj);
1661
1662                 /* Before SandyBridge, you could not use tiling or fence
1663                  * registers with snooped memory, so relinquish any fences
1664                  * currently pointing to our region in the aperture.
1665                  */
1666                 if (INTEL_INFO(obj->base.dev)->gen < 6) {
1667                         ret = i915_gem_object_put_fence(obj);
1668                         if (ret)
1669                                 return ret;
1670                 }
1671
1672                 if (obj->has_global_gtt_mapping)
1673                         i915_gem_gtt_bind_object(obj, cache_level);
1674                 if (obj->has_aliasing_ppgtt_mapping)
1675                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
1676                                                obj, cache_level);
1677         }
1678
1679         if (cache_level == I915_CACHE_NONE) {
1680                 u32 old_read_domains, old_write_domain;
1681
1682                 /* If we're coming from LLC cached, then we haven't
1683                  * actually been tracking whether the data is in the
1684                  * CPU cache or not, since we only allow one bit set
1685                  * in obj->write_domain and have been skipping the clflushes.
1686                  * Just set it to the CPU cache for now.
1687                  */
1688                 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1689                     ("obj %p in CPU write domain", obj));
1690                 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
1691                     ("obj %p in CPU read domain", obj));
1692
1693                 old_read_domains = obj->base.read_domains;
1694                 old_write_domain = obj->base.write_domain;
1695
1696                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1697                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1698
1699         }
1700
1701         obj->cache_level = cache_level;
1702         return (0);
1703 }
1704
1705 int
1706 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1707     u32 alignment, struct intel_ring_buffer *pipelined)
1708 {
1709         u32 old_read_domains, old_write_domain;
1710         int ret;
1711
1712         ret = i915_gem_object_flush_gpu_write_domain(obj);
1713         if (ret != 0)
1714                 return (ret);
1715
1716         if (pipelined != obj->ring) {
1717                 ret = i915_gem_object_wait_rendering(obj);
1718                 if (ret == -ERESTART || ret == -EINTR)
1719                         return (ret);
1720         }
1721
1722         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
1723         if (ret != 0)
1724                 return (ret);
1725
1726         ret = i915_gem_object_pin(obj, alignment, true);
1727         if (ret != 0)
1728                 return (ret);
1729
1730         i915_gem_object_flush_cpu_write_domain(obj);
1731
1732         old_write_domain = obj->base.write_domain;
1733         old_read_domains = obj->base.read_domains;
1734
1735         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1736             ("obj %p in GTT write domain", obj));
1737         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1738
1739         return (0);
1740 }
1741
1742 int
1743 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
1744 {
1745         int ret;
1746
1747         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
1748                 return (0);
1749
1750         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1751                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
1752                 if (ret != 0)
1753                         return (ret);
1754         }
1755
1756         ret = i915_gem_object_wait_rendering(obj);
1757         if (ret != 0)
1758                 return (ret);
1759
1760         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1761
1762         return (0);
1763 }
1764
1765 static int
1766 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
1767     uint64_t offset, uint64_t size)
1768 {
1769         uint32_t old_read_domains;
1770         int i, ret;
1771
1772         if (offset == 0 && size == obj->base.size)
1773                 return (i915_gem_object_set_to_cpu_domain(obj, 0));
1774
1775         ret = i915_gem_object_flush_gpu_write_domain(obj);
1776         if (ret != 0)
1777                 return (ret);
1778         ret = i915_gem_object_wait_rendering(obj);
1779         if (ret != 0)
1780                 return (ret);
1781
1782         i915_gem_object_flush_gtt_write_domain(obj);
1783
1784         if (obj->page_cpu_valid == NULL &&
1785             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
1786                 return (0);
1787
1788         if (obj->page_cpu_valid == NULL) {
1789                 obj->page_cpu_valid = kmalloc(obj->base.size / PAGE_SIZE,
1790                     DRM_I915_GEM, M_WAITOK | M_ZERO);
1791         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
1792                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
1793
1794         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
1795              i++) {
1796                 if (obj->page_cpu_valid[i])
1797                         continue;
1798                 drm_clflush_pages(obj->pages + i, 1);
1799                 obj->page_cpu_valid[i] = 1;
1800         }
1801
1802         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1803             ("In gpu write domain"));
1804
1805         old_read_domains = obj->base.read_domains;
1806         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
1807
1808         return (0);
1809 }
1810
1811 static uint32_t
1812 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1813 {
1814         uint32_t gtt_size;
1815
1816         if (INTEL_INFO(dev)->gen >= 4 ||
1817             tiling_mode == I915_TILING_NONE)
1818                 return (size);
1819
1820         /* Previous chips need a power-of-two fence region when tiling */
1821         if (INTEL_INFO(dev)->gen == 3)
1822                 gtt_size = 1024*1024;
1823         else
1824                 gtt_size = 512*1024;
1825
1826         while (gtt_size < size)
1827                 gtt_size <<= 1;
1828
1829         return (gtt_size);
1830 }
1831
1832 /**
1833  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1834  * @obj: object to check
1835  *
1836  * Return the required GTT alignment for an object, taking into account
1837  * potential fence register mapping.
1838  */
1839 static uint32_t
1840 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1841      int tiling_mode)
1842 {
1843
1844         /*
1845          * Minimum alignment is 4k (GTT page size), but might be greater
1846          * if a fence register is needed for the object.
1847          */
1848         if (INTEL_INFO(dev)->gen >= 4 ||
1849             tiling_mode == I915_TILING_NONE)
1850                 return (4096);
1851
1852         /*
1853          * Previous chips need to be aligned to the size of the smallest
1854          * fence register that can contain the object.
1855          */
1856         return (i915_gem_get_gtt_size(dev, size, tiling_mode));
1857 }
1858
1859 uint32_t
1860 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, uint32_t size,
1861     int tiling_mode)
1862 {
1863
1864         if (tiling_mode == I915_TILING_NONE)
1865                 return (4096);
1866
1867         /*
1868          * Minimum alignment is 4k (GTT page size) for sane hw.
1869          */
1870         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
1871                 return (4096);
1872
1873         /*
1874          * Previous hardware however needs to be aligned to a power-of-two
1875          * tile height. The simplest method for determining this is to reuse
1876          * the power-of-tile object size.
1877          */
1878         return (i915_gem_get_gtt_size(dev, size, tiling_mode));
1879 }
1880
1881 static int
1882 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
1883     unsigned alignment, bool map_and_fenceable)
1884 {
1885         struct drm_device *dev;
1886         struct drm_i915_private *dev_priv;
1887         struct drm_mm_node *free_space;
1888         uint32_t size, fence_size, fence_alignment, unfenced_alignment;
1889         bool mappable, fenceable;
1890         int ret;
1891
1892         dev = obj->base.dev;
1893         dev_priv = dev->dev_private;
1894
1895         if (obj->madv != I915_MADV_WILLNEED) {
1896                 DRM_ERROR("Attempting to bind a purgeable object\n");
1897                 return (-EINVAL);
1898         }
1899
1900         fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
1901             obj->tiling_mode);
1902         fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
1903             obj->tiling_mode);
1904         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
1905             obj->base.size, obj->tiling_mode);
1906         if (alignment == 0)
1907                 alignment = map_and_fenceable ? fence_alignment :
1908                     unfenced_alignment;
1909         if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
1910                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1911                 return (-EINVAL);
1912         }
1913
1914         size = map_and_fenceable ? fence_size : obj->base.size;
1915
1916         /* If the object is bigger than the entire aperture, reject it early
1917          * before evicting everything in a vain attempt to find space.
1918          */
1919         if (obj->base.size > (map_and_fenceable ?
1920             dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
1921                 DRM_ERROR(
1922 "Attempting to bind an object larger than the aperture\n");
1923                 return (-E2BIG);
1924         }
1925
1926  search_free:
1927         if (map_and_fenceable)
1928                 free_space = drm_mm_search_free_in_range(
1929                     &dev_priv->mm.gtt_space, size, alignment, 0,
1930                     dev_priv->mm.gtt_mappable_end, 0);
1931         else
1932                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1933                     size, alignment, 0);
1934         if (free_space != NULL) {
1935                 int color = 0;
1936                 if (map_and_fenceable)
1937                         obj->gtt_space = drm_mm_get_block_range_generic(
1938                             free_space, size, alignment, color, 0,
1939                             dev_priv->mm.gtt_mappable_end, 1);
1940                 else
1941                         obj->gtt_space = drm_mm_get_block_generic(free_space,
1942                             size, alignment, color, 1);
1943         }
1944         if (obj->gtt_space == NULL) {
1945                 ret = i915_gem_evict_something(dev, size, alignment,
1946                     map_and_fenceable);
1947                 if (ret != 0)
1948                         return (ret);
1949                 goto search_free;
1950         }
1951         ret = i915_gem_object_get_pages_gtt(obj, 0);
1952         if (ret != 0) {
1953                 drm_mm_put_block(obj->gtt_space);
1954                 obj->gtt_space = NULL;
1955                 /*
1956                  * i915_gem_object_get_pages_gtt() cannot return
1957                  * ENOMEM, since we use vm_page_grab(VM_ALLOC_RETRY)
1958                  * (which does not support operation without a flag
1959                  * anyway).
1960                  */
1961                 return (ret);
1962         }
1963
1964         i915_gem_gtt_bind_object(obj, obj->cache_level);
1965         if (ret != 0) {
1966                 i915_gem_object_put_pages_gtt(obj);
1967                 drm_mm_put_block(obj->gtt_space);
1968                 obj->gtt_space = NULL;
1969                 if (i915_gem_evict_everything(dev, false))
1970                         return (ret);
1971                 goto search_free;
1972         }
1973
1974         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
1975         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1976
1977         obj->gtt_offset = obj->gtt_space->start;
1978
1979         fenceable =
1980                 obj->gtt_space->size == fence_size &&
1981                 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
1982
1983         mappable =
1984                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
1985         obj->map_and_fenceable = mappable && fenceable;
1986
1987         return (0);
1988 }
1989
1990 static void
1991 i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
1992 {
1993         u32 old_write_domain, old_read_domains;
1994
1995         /* Act a barrier for all accesses through the GTT */
1996         cpu_mfence();
1997
1998         /* Force a pagefault for domain tracking on next user access */
1999         i915_gem_release_mmap(obj);
2000
2001         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2002                 return;
2003
2004         old_read_domains = obj->base.read_domains;
2005         old_write_domain = obj->base.write_domain;
2006
2007         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2008         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2009
2010 }
2011
2012 int
2013 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2014 {
2015         drm_i915_private_t *dev_priv;
2016         int ret;
2017
2018         dev_priv = obj->base.dev->dev_private;
2019         ret = 0;
2020         if (obj->gtt_space == NULL)
2021                 return (0);
2022         if (obj->pin_count != 0) {
2023                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2024                 return (-EINVAL);
2025         }
2026
2027         ret = i915_gem_object_finish_gpu(obj);
2028         if (ret == -ERESTART || ret == -EINTR)
2029                 return (ret);
2030
2031         i915_gem_object_finish_gtt(obj);
2032
2033         if (ret == 0)
2034                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2035         if (ret == -ERESTART || ret == -EINTR)
2036                 return (ret);
2037         if (ret != 0) {
2038                 i915_gem_clflush_object(obj);
2039                 obj->base.read_domains = obj->base.write_domain =
2040                     I915_GEM_DOMAIN_CPU;
2041         }
2042
2043         ret = i915_gem_object_put_fence(obj);
2044         if (ret == -ERESTART)
2045                 return (ret);
2046
2047         i915_gem_gtt_unbind_object(obj);
2048         if (obj->has_aliasing_ppgtt_mapping) {
2049                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2050                 obj->has_aliasing_ppgtt_mapping = 0;
2051         }
2052         i915_gem_object_put_pages_gtt(obj);
2053
2054         list_del_init(&obj->gtt_list);
2055         list_del_init(&obj->mm_list);
2056         obj->map_and_fenceable = true;
2057
2058         drm_mm_put_block(obj->gtt_space);
2059         obj->gtt_space = NULL;
2060         obj->gtt_offset = 0;
2061
2062         if (i915_gem_object_is_purgeable(obj))
2063                 i915_gem_object_truncate(obj);
2064
2065         return (ret);
2066 }
2067
2068 static int
2069 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
2070     int flags)
2071 {
2072         struct drm_device *dev;
2073         vm_object_t vm_obj;
2074         vm_page_t m;
2075         int page_count, i, j;
2076
2077         dev = obj->base.dev;
2078         KASSERT(obj->pages == NULL, ("Obj already has pages"));
2079         page_count = obj->base.size / PAGE_SIZE;
2080         obj->pages = kmalloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
2081             M_WAITOK);
2082         vm_obj = obj->base.vm_obj;
2083         VM_OBJECT_LOCK(vm_obj);
2084         for (i = 0; i < page_count; i++) {
2085                 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
2086                         goto failed;
2087         }
2088         VM_OBJECT_UNLOCK(vm_obj);
2089         if (i915_gem_object_needs_bit17_swizzle(obj))
2090                 i915_gem_object_do_bit_17_swizzle(obj);
2091         return (0);
2092
2093 failed:
2094         for (j = 0; j < i; j++) {
2095                 m = obj->pages[j];
2096                 vm_page_busy_wait(m, FALSE, "i915gem");
2097                 vm_page_unwire(m, 0);
2098                 vm_page_wakeup(m);
2099                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2100         }
2101         VM_OBJECT_UNLOCK(vm_obj);
2102         drm_free(obj->pages, DRM_I915_GEM);
2103         obj->pages = NULL;
2104         return (-EIO);
2105 }
2106
2107 #define GEM_PARANOID_CHECK_GTT 0
2108 #if GEM_PARANOID_CHECK_GTT
2109 static void
2110 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
2111     int page_count)
2112 {
2113         struct drm_i915_private *dev_priv;
2114         vm_paddr_t pa;
2115         unsigned long start, end;
2116         u_int i;
2117         int j;
2118
2119         dev_priv = dev->dev_private;
2120         start = OFF_TO_IDX(dev_priv->mm.gtt_start);
2121         end = OFF_TO_IDX(dev_priv->mm.gtt_end);
2122         for (i = start; i < end; i++) {
2123                 pa = intel_gtt_read_pte_paddr(i);
2124                 for (j = 0; j < page_count; j++) {
2125                         if (pa == VM_PAGE_TO_PHYS(ma[j])) {
2126                                 panic("Page %p in GTT pte index %d pte %x",
2127                                     ma[i], i, intel_gtt_read_pte(i));
2128                         }
2129                 }
2130         }
2131 }
2132 #endif
2133
2134 static void
2135 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2136 {
2137         vm_page_t m;
2138         int page_count, i;
2139
2140         BUG_ON(obj->madv == __I915_MADV_PURGED);
2141
2142         if (obj->tiling_mode != I915_TILING_NONE)
2143                 i915_gem_object_save_bit_17_swizzle(obj);
2144         if (obj->madv == I915_MADV_DONTNEED)
2145                 obj->dirty = 0;
2146         page_count = obj->base.size / PAGE_SIZE;
2147         VM_OBJECT_LOCK(obj->base.vm_obj);
2148 #if GEM_PARANOID_CHECK_GTT
2149         i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
2150 #endif
2151         for (i = 0; i < page_count; i++) {
2152                 m = obj->pages[i];
2153                 if (obj->dirty)
2154                         vm_page_dirty(m);
2155                 if (obj->madv == I915_MADV_WILLNEED)
2156                         vm_page_reference(m);
2157                 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
2158                 vm_page_unwire(obj->pages[i], 1);
2159                 vm_page_wakeup(obj->pages[i]);
2160                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2161         }
2162         VM_OBJECT_UNLOCK(obj->base.vm_obj);
2163         obj->dirty = 0;
2164         drm_free(obj->pages, DRM_I915_GEM);
2165         obj->pages = NULL;
2166 }
2167
2168 void
2169 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2170 {
2171         vm_object_t devobj;
2172         vm_page_t m;
2173         int i, page_count;
2174
2175         if (!obj->fault_mappable)
2176                 return;
2177
2178         devobj = cdev_pager_lookup(obj);
2179         if (devobj != NULL) {
2180                 page_count = OFF_TO_IDX(obj->base.size);
2181
2182                 VM_OBJECT_LOCK(devobj);
2183                 for (i = 0; i < page_count; i++) {
2184                         m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
2185                         if (m == NULL)
2186                                 continue;
2187                         cdev_pager_free_page(devobj, m);
2188                 }
2189                 VM_OBJECT_UNLOCK(devobj);
2190                 vm_object_deallocate(devobj);
2191         }
2192
2193         obj->fault_mappable = false;
2194 }
2195
2196 int
2197 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2198 {
2199         u32 seqno;
2200         int ret;
2201
2202
2203         seqno = obj->last_rendering_seqno;
2204         if (seqno == 0)
2205                 return 0;
2206
2207         if (obj->active) {
2208                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno,
2209                     true);
2210                 if (ret != 0)
2211                         return (ret);
2212         }
2213
2214         /* Manually manage the write flush as we may have not yet
2215          * retired the buffer.
2216          */
2217         if (obj->last_rendering_seqno &&
2218             i915_seqno_passed(seqno, obj->last_rendering_seqno)) {
2219                 obj->last_rendering_seqno = 0;
2220                 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
2221         }
2222
2223         return 0;
2224 }
2225
2226 void
2227 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2228     struct intel_ring_buffer *ring, uint32_t seqno)
2229 {
2230         struct drm_device *dev = obj->base.dev;
2231         struct drm_i915_private *dev_priv = dev->dev_private;
2232         struct drm_i915_fence_reg *reg;
2233
2234         obj->ring = ring;
2235         KASSERT(ring != NULL, ("NULL ring"));
2236
2237         /* Add a reference if we're newly entering the active list. */
2238         if (!obj->active) {
2239                 drm_gem_object_reference(&obj->base);
2240                 obj->active = 1;
2241         }
2242
2243         /* Move from whatever list we were on to the tail of execution. */
2244         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
2245         list_move_tail(&obj->ring_list, &ring->active_list);
2246
2247         obj->last_rendering_seqno = seqno;
2248         if (obj->fenced_gpu_access) {
2249                 obj->last_fenced_seqno = seqno;
2250                 obj->last_fenced_ring = ring;
2251
2252                 /* Bump MRU to take account of the delayed flush */
2253                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2254                         reg = &dev_priv->fence_regs[obj->fence_reg];
2255                         list_move_tail(&reg->lru_list,
2256                                        &dev_priv->mm.fence_list);
2257                 }
2258         }
2259 }
2260
2261 static void
2262 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
2263 {
2264         list_del_init(&obj->ring_list);
2265         obj->last_rendering_seqno = 0;
2266         obj->last_fenced_seqno = 0;
2267 }
2268
2269 static void
2270 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
2271 {
2272         struct drm_device *dev = obj->base.dev;
2273         drm_i915_private_t *dev_priv = dev->dev_private;
2274
2275         KASSERT(obj->active, ("Object not active"));
2276         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
2277
2278         i915_gem_object_move_off_active(obj);
2279 }
2280
2281 static void
2282 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2283 {
2284         struct drm_device *dev = obj->base.dev;
2285         struct drm_i915_private *dev_priv = dev->dev_private;
2286
2287         if (obj->pin_count != 0)
2288                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
2289         else
2290                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2291
2292         KASSERT(list_empty(&obj->gpu_write_list), ("On gpu_write_list"));
2293         KASSERT(obj->active, ("Object not active"));
2294         obj->ring = NULL;
2295         obj->last_fenced_ring = NULL;
2296
2297         i915_gem_object_move_off_active(obj);
2298         obj->fenced_gpu_access = false;
2299
2300         obj->active = 0;
2301         obj->pending_gpu_write = false;
2302         drm_gem_object_unreference(&obj->base);
2303
2304 #if 1
2305         KIB_NOTYET();
2306 #else
2307         WARN_ON(i915_verify_lists(dev));
2308 #endif
2309 }
2310
2311 /* Immediately discard the backing storage */
2312 static void
2313 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2314 {
2315         vm_object_t vm_obj;
2316
2317         vm_obj = obj->base.vm_obj;
2318         VM_OBJECT_LOCK(vm_obj);
2319         vm_object_page_remove(vm_obj, 0, 0, false);
2320         VM_OBJECT_UNLOCK(vm_obj);
2321         obj->madv = __I915_MADV_PURGED;
2322 }
2323
2324 static inline int
2325 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
2326 {
2327
2328         return (obj->madv == I915_MADV_DONTNEED);
2329 }
2330
2331 static void
2332 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
2333     uint32_t flush_domains)
2334 {
2335         struct drm_i915_gem_object *obj, *next;
2336         uint32_t old_write_domain;
2337
2338         list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
2339             gpu_write_list) {
2340                 if (obj->base.write_domain & flush_domains) {
2341                         old_write_domain = obj->base.write_domain;
2342                         obj->base.write_domain = 0;
2343                         list_del_init(&obj->gpu_write_list);
2344                         i915_gem_object_move_to_active(obj, ring,
2345                             i915_gem_next_request_seqno(ring));
2346                 }
2347         }
2348 }
2349
2350 static int
2351 i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2352 {
2353         drm_i915_private_t *dev_priv;
2354
2355         dev_priv = obj->base.dev->dev_private;
2356         return (dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2357             obj->tiling_mode != I915_TILING_NONE);
2358 }
2359
2360 #define VM_OBJECT_LOCK_ASSERT_OWNED(object)
2361
2362 static vm_page_t
2363 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
2364 {
2365         vm_page_t m;
2366         int rv;
2367
2368         VM_OBJECT_LOCK_ASSERT_OWNED(object);
2369         m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_RETRY);
2370         if (m->valid != VM_PAGE_BITS_ALL) {
2371                 if (vm_pager_has_page(object, pindex)) {
2372                         rv = vm_pager_get_page(object, &m, 1);
2373                         m = vm_page_lookup(object, pindex);
2374                         if (m == NULL)
2375                                 return (NULL);
2376                         if (rv != VM_PAGER_OK) {
2377                                 vm_page_free(m);
2378                                 return (NULL);
2379                         }
2380                 } else {
2381                         pmap_zero_page(VM_PAGE_TO_PHYS(m));
2382                         m->valid = VM_PAGE_BITS_ALL;
2383                         m->dirty = 0;
2384                 }
2385         }
2386         vm_page_wire(m);
2387         vm_page_wakeup(m);
2388         atomic_add_long(&i915_gem_wired_pages_cnt, 1);
2389         return (m);
2390 }
2391
2392 int
2393 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
2394     uint32_t flush_domains)
2395 {
2396         int ret;
2397
2398         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2399                 return 0;
2400
2401         ret = ring->flush(ring, invalidate_domains, flush_domains);
2402         if (ret)
2403                 return ret;
2404
2405         if (flush_domains & I915_GEM_GPU_DOMAINS)
2406                 i915_gem_process_flushing_list(ring, flush_domains);
2407         return 0;
2408 }
2409
2410 static int
2411 i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire)
2412 {
2413         int ret;
2414
2415         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2416                 return 0;
2417
2418         if (!list_empty(&ring->gpu_write_list)) {
2419                 ret = i915_gem_flush_ring(ring, I915_GEM_GPU_DOMAINS,
2420                     I915_GEM_GPU_DOMAINS);
2421                 if (ret != 0)
2422                         return ret;
2423         }
2424
2425         return (i915_wait_request(ring, i915_gem_next_request_seqno(ring),
2426             do_retire));
2427 }
2428
2429 int
2430 i915_gpu_idle(struct drm_device *dev, bool do_retire)
2431 {
2432         drm_i915_private_t *dev_priv = dev->dev_private;
2433         int ret, i;
2434
2435         /* Flush everything onto the inactive list. */
2436         for (i = 0; i < I915_NUM_RINGS; i++) {
2437                 ret = i915_ring_idle(&dev_priv->ring[i], do_retire);
2438                 if (ret)
2439                         return ret;
2440         }
2441
2442         return 0;
2443 }
2444
2445 int
2446 i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno, bool do_retire)
2447 {
2448         drm_i915_private_t *dev_priv;
2449         struct drm_i915_gem_request *request;
2450         uint32_t ier;
2451         int flags, ret;
2452         bool recovery_complete;
2453
2454         KASSERT(seqno != 0, ("Zero seqno"));
2455
2456         dev_priv = ring->dev->dev_private;
2457         ret = 0;
2458
2459         if (atomic_read(&dev_priv->mm.wedged) != 0) {
2460                 /* Give the error handler a chance to run. */
2461                 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
2462                 recovery_complete = (&dev_priv->error_completion) > 0;
2463                 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
2464                 return (recovery_complete ? -EIO : -EAGAIN);
2465         }
2466
2467         if (seqno == ring->outstanding_lazy_request) {
2468                 request = kmalloc(sizeof(*request), DRM_I915_GEM,
2469                     M_WAITOK | M_ZERO);
2470                 if (request == NULL)
2471                         return (-ENOMEM);
2472
2473                 ret = i915_add_request(ring, NULL, request);
2474                 if (ret != 0) {
2475                         drm_free(request, DRM_I915_GEM);
2476                         return (ret);
2477                 }
2478
2479                 seqno = request->seqno;
2480         }
2481
2482         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2483                 if (HAS_PCH_SPLIT(ring->dev))
2484                         ier = I915_READ(DEIER) | I915_READ(GTIER);
2485                 else
2486                         ier = I915_READ(IER);
2487                 if (!ier) {
2488                         DRM_ERROR("something (likely vbetool) disabled "
2489                                   "interrupts, re-enabling\n");
2490                         ring->dev->driver->irq_preinstall(ring->dev);
2491                         ring->dev->driver->irq_postinstall(ring->dev);
2492                 }
2493
2494                 ring->waiting_seqno = seqno;
2495                 lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
2496                 if (ring->irq_get(ring)) {
2497                         flags = dev_priv->mm.interruptible ? PCATCH : 0;
2498                         while (!i915_seqno_passed(ring->get_seqno(ring), seqno)
2499                             && !atomic_read(&dev_priv->mm.wedged) &&
2500                             ret == 0) {
2501                                 ret = -lksleep(ring, &ring->irq_lock, flags,
2502                                     "915gwr", 0);
2503                         }
2504                         ring->irq_put(ring);
2505                         lockmgr(&ring->irq_lock, LK_RELEASE);
2506                 } else {
2507                         lockmgr(&ring->irq_lock, LK_RELEASE);
2508                         if (_intel_wait_for(ring->dev,
2509                             i915_seqno_passed(ring->get_seqno(ring), seqno) ||
2510                             atomic_read(&dev_priv->mm.wedged), 3000,
2511                             0, "i915wrq") != 0)
2512                                 ret = -EBUSY;
2513                 }
2514                 ring->waiting_seqno = 0;
2515
2516         }
2517         if (atomic_read(&dev_priv->mm.wedged))
2518                 ret = -EAGAIN;
2519
2520         /* Directly dispatch request retiring.  While we have the work queue
2521          * to handle this, the waiter on a request often wants an associated
2522          * buffer to have made it to the inactive list, and we would need
2523          * a separate wait queue to handle that.
2524          */
2525         if (ret == 0 && do_retire)
2526                 i915_gem_retire_requests_ring(ring);
2527
2528         return (ret);
2529 }
2530
2531 static u32
2532 i915_gem_get_seqno(struct drm_device *dev)
2533 {
2534         drm_i915_private_t *dev_priv = dev->dev_private;
2535         u32 seqno = dev_priv->next_seqno;
2536
2537         /* reserve 0 for non-seqno */
2538         if (++dev_priv->next_seqno == 0)
2539                 dev_priv->next_seqno = 1;
2540
2541         return seqno;
2542 }
2543
2544 u32
2545 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
2546 {
2547         if (ring->outstanding_lazy_request == 0)
2548                 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
2549
2550         return ring->outstanding_lazy_request;
2551 }
2552
2553 int
2554 i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file,
2555      struct drm_i915_gem_request *request)
2556 {
2557         drm_i915_private_t *dev_priv;
2558         struct drm_i915_file_private *file_priv;
2559         uint32_t seqno;
2560         u32 request_ring_position;
2561         int was_empty;
2562         int ret;
2563
2564         KASSERT(request != NULL, ("NULL request in add"));
2565         DRM_LOCK_ASSERT(ring->dev);
2566         dev_priv = ring->dev->dev_private;
2567
2568         seqno = i915_gem_next_request_seqno(ring);
2569         request_ring_position = intel_ring_get_tail(ring);
2570
2571         ret = ring->add_request(ring, &seqno);
2572         if (ret != 0)
2573             return ret;
2574
2575         request->seqno = seqno;
2576         request->ring = ring;
2577         request->tail = request_ring_position;
2578         request->emitted_jiffies = ticks;
2579         was_empty = list_empty(&ring->request_list);
2580         list_add_tail(&request->list, &ring->request_list);
2581
2582         if (file != NULL) {
2583                 file_priv = file->driver_priv;
2584
2585                 spin_lock(&file_priv->mm.lock);
2586                 request->file_priv = file_priv;
2587                 list_add_tail(&request->client_list,
2588                     &file_priv->mm.request_list);
2589                 spin_unlock(&file_priv->mm.lock);
2590         }
2591
2592         ring->outstanding_lazy_request = 0;
2593
2594         if (!dev_priv->mm.suspended) {
2595                 if (i915_enable_hangcheck) {
2596                         mod_timer(&dev_priv->hangcheck_timer,
2597                                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2598                 }
2599                 if (was_empty) {
2600                         queue_delayed_work(dev_priv->wq,
2601                                            &dev_priv->mm.retire_work,
2602                                            round_jiffies_up_relative(hz));
2603                         intel_mark_busy(dev_priv->dev);
2604                 }
2605         }
2606         return (0);
2607 }
2608
2609 static inline void
2610 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2611 {
2612         struct drm_i915_file_private *file_priv = request->file_priv;
2613
2614         if (!file_priv)
2615                 return;
2616
2617         DRM_LOCK_ASSERT(request->ring->dev);
2618
2619         spin_lock(&file_priv->mm.lock);
2620         if (request->file_priv != NULL) {
2621                 list_del(&request->client_list);
2622                 request->file_priv = NULL;
2623         }
2624         spin_unlock(&file_priv->mm.lock);
2625 }
2626
2627 void
2628 i915_gem_release(struct drm_device *dev, struct drm_file *file)
2629 {
2630         struct drm_i915_file_private *file_priv;
2631         struct drm_i915_gem_request *request;
2632
2633         file_priv = file->driver_priv;
2634
2635         /* Clean up our request list when the client is going away, so that
2636          * later retire_requests won't dereference our soon-to-be-gone
2637          * file_priv.
2638          */
2639         spin_lock(&file_priv->mm.lock);
2640         while (!list_empty(&file_priv->mm.request_list)) {
2641                 request = list_first_entry(&file_priv->mm.request_list,
2642                                            struct drm_i915_gem_request,
2643                                            client_list);
2644                 list_del(&request->client_list);
2645                 request->file_priv = NULL;
2646         }
2647         spin_unlock(&file_priv->mm.lock);
2648 }
2649
2650 static void
2651 i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2652     struct intel_ring_buffer *ring)
2653 {
2654
2655         if (ring->dev != NULL)
2656                 DRM_LOCK_ASSERT(ring->dev);
2657
2658         while (!list_empty(&ring->request_list)) {
2659                 struct drm_i915_gem_request *request;
2660
2661                 request = list_first_entry(&ring->request_list,
2662                     struct drm_i915_gem_request, list);
2663
2664                 list_del(&request->list);
2665                 i915_gem_request_remove_from_client(request);
2666                 drm_free(request, DRM_I915_GEM);
2667         }
2668
2669         while (!list_empty(&ring->active_list)) {
2670                 struct drm_i915_gem_object *obj;
2671
2672                 obj = list_first_entry(&ring->active_list,
2673                     struct drm_i915_gem_object, ring_list);
2674
2675                 obj->base.write_domain = 0;
2676                 list_del_init(&obj->gpu_write_list);
2677                 i915_gem_object_move_to_inactive(obj);
2678         }
2679 }
2680
2681 static void
2682 i915_gem_reset_fences(struct drm_device *dev)
2683 {
2684         struct drm_i915_private *dev_priv = dev->dev_private;
2685         int i;
2686
2687         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2688                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2689                 struct drm_i915_gem_object *obj = reg->obj;
2690
2691                 if (!obj)
2692                         continue;
2693
2694                 if (obj->tiling_mode)
2695                         i915_gem_release_mmap(obj);
2696
2697                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
2698                 reg->obj->fenced_gpu_access = false;
2699                 reg->obj->last_fenced_seqno = 0;
2700                 reg->obj->last_fenced_ring = NULL;
2701                 i915_gem_clear_fence_reg(dev, reg);
2702         }
2703 }
2704
2705 void
2706 i915_gem_reset(struct drm_device *dev)
2707 {
2708         struct drm_i915_private *dev_priv = dev->dev_private;
2709         struct drm_i915_gem_object *obj;
2710         int i;
2711
2712         for (i = 0; i < I915_NUM_RINGS; i++)
2713                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
2714
2715         /* Remove anything from the flushing lists. The GPU cache is likely
2716          * to be lost on reset along with the data, so simply move the
2717          * lost bo to the inactive list.
2718          */
2719         while (!list_empty(&dev_priv->mm.flushing_list)) {
2720                 obj = list_first_entry(&dev_priv->mm.flushing_list,
2721                                       struct drm_i915_gem_object,
2722                                       mm_list);
2723
2724                 obj->base.write_domain = 0;
2725                 list_del_init(&obj->gpu_write_list);
2726                 i915_gem_object_move_to_inactive(obj);
2727         }
2728
2729         /* Move everything out of the GPU domains to ensure we do any
2730          * necessary invalidation upon reuse.
2731          */
2732         list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
2733                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2734         }
2735
2736         /* The fence registers are invalidated so clear them out */
2737         i915_gem_reset_fences(dev);
2738 }
2739
2740 /**
2741  * This function clears the request list as sequence numbers are passed.
2742  */
2743 void
2744 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2745 {
2746         uint32_t seqno;
2747         int i;
2748
2749         if (list_empty(&ring->request_list))
2750                 return;
2751
2752         seqno = ring->get_seqno(ring);
2753         for (i = 0; i < DRM_ARRAY_SIZE(ring->sync_seqno); i++)
2754                 if (seqno >= ring->sync_seqno[i])
2755                         ring->sync_seqno[i] = 0;
2756
2757         while (!list_empty(&ring->request_list)) {
2758                 struct drm_i915_gem_request *request;
2759
2760                 request = list_first_entry(&ring->request_list,
2761                                            struct drm_i915_gem_request,
2762                                            list);
2763
2764                 if (!i915_seqno_passed(seqno, request->seqno))
2765                         break;
2766
2767                 ring->last_retired_head = request->tail;
2768
2769                 list_del(&request->list);
2770                 i915_gem_request_remove_from_client(request);
2771                 drm_free(request, DRM_I915_GEM);
2772         }
2773
2774         /* Move any buffers on the active list that are no longer referenced
2775          * by the ringbuffer to the flushing/inactive lists as appropriate.
2776          */
2777         while (!list_empty(&ring->active_list)) {
2778                 struct drm_i915_gem_object *obj;
2779
2780                 obj = list_first_entry(&ring->active_list,
2781                                       struct drm_i915_gem_object,
2782                                       ring_list);
2783
2784                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
2785                         break;
2786
2787                 if (obj->base.write_domain != 0)
2788                         i915_gem_object_move_to_flushing(obj);
2789                 else
2790                         i915_gem_object_move_to_inactive(obj);
2791         }
2792
2793         if (ring->trace_irq_seqno &&
2794             i915_seqno_passed(seqno, ring->trace_irq_seqno)) {
2795                 lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
2796                 ring->irq_put(ring);
2797                 lockmgr(&ring->irq_lock, LK_RELEASE);
2798                 ring->trace_irq_seqno = 0;
2799         }
2800 }
2801
2802 void
2803 i915_gem_retire_requests(struct drm_device *dev)
2804 {
2805         drm_i915_private_t *dev_priv = dev->dev_private;
2806         struct drm_i915_gem_object *obj, *next;
2807         int i;
2808
2809         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
2810                 list_for_each_entry_safe(obj, next,
2811                     &dev_priv->mm.deferred_free_list, mm_list)
2812                         i915_gem_free_object_tail(obj);
2813         }
2814
2815         for (i = 0; i < I915_NUM_RINGS; i++)
2816                 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
2817 }
2818
2819 static int
2820 sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2821     struct intel_ring_buffer *pipelined)
2822 {
2823         struct drm_device *dev = obj->base.dev;
2824         drm_i915_private_t *dev_priv = dev->dev_private;
2825         u32 size = obj->gtt_space->size;
2826         int regnum = obj->fence_reg;
2827         uint64_t val;
2828
2829         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2830                          0xfffff000) << 32;
2831         val |= obj->gtt_offset & 0xfffff000;
2832         val |= (uint64_t)((obj->stride / 128) - 1) <<
2833                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2834
2835         if (obj->tiling_mode == I915_TILING_Y)
2836                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2837         val |= I965_FENCE_REG_VALID;
2838
2839         if (pipelined) {
2840                 int ret = intel_ring_begin(pipelined, 6);
2841                 if (ret)
2842                         return ret;
2843
2844                 intel_ring_emit(pipelined, MI_NOOP);
2845                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2846                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2847                 intel_ring_emit(pipelined, (u32)val);
2848                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2849                 intel_ring_emit(pipelined, (u32)(val >> 32));
2850                 intel_ring_advance(pipelined);
2851         } else
2852                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2853
2854         return 0;
2855 }
2856
2857 static int
2858 i965_write_fence_reg(struct drm_i915_gem_object *obj,
2859     struct intel_ring_buffer *pipelined)
2860 {
2861         struct drm_device *dev = obj->base.dev;
2862         drm_i915_private_t *dev_priv = dev->dev_private;
2863         u32 size = obj->gtt_space->size;
2864         int regnum = obj->fence_reg;
2865         uint64_t val;
2866
2867         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2868                     0xfffff000) << 32;
2869         val |= obj->gtt_offset & 0xfffff000;
2870         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2871         if (obj->tiling_mode == I915_TILING_Y)
2872                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2873         val |= I965_FENCE_REG_VALID;
2874
2875         if (pipelined) {
2876                 int ret = intel_ring_begin(pipelined, 6);
2877                 if (ret)
2878                         return ret;
2879
2880                 intel_ring_emit(pipelined, MI_NOOP);
2881                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2882                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2883                 intel_ring_emit(pipelined, (u32)val);
2884                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2885                 intel_ring_emit(pipelined, (u32)(val >> 32));
2886                 intel_ring_advance(pipelined);
2887         } else
2888                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2889
2890         return 0;
2891 }
2892
2893 static int
2894 i915_write_fence_reg(struct drm_i915_gem_object *obj,
2895     struct intel_ring_buffer *pipelined)
2896 {
2897         struct drm_device *dev = obj->base.dev;
2898         drm_i915_private_t *dev_priv = dev->dev_private;
2899         u32 size = obj->gtt_space->size;
2900         u32 fence_reg, val, pitch_val;
2901         int tile_width;
2902
2903         if ((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2904             (size & -size) != size || (obj->gtt_offset & (size - 1))) {
2905                 kprintf(
2906 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2907                  obj->gtt_offset, obj->map_and_fenceable, size);
2908                 return -EINVAL;
2909         }
2910
2911         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2912                 tile_width = 128;
2913         else
2914                 tile_width = 512;
2915
2916         /* Note: pitch better be a power of two tile widths */
2917         pitch_val = obj->stride / tile_width;
2918         pitch_val = ffs(pitch_val) - 1;
2919
2920         val = obj->gtt_offset;
2921         if (obj->tiling_mode == I915_TILING_Y)
2922                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2923         val |= I915_FENCE_SIZE_BITS(size);
2924         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2925         val |= I830_FENCE_REG_VALID;
2926
2927         fence_reg = obj->fence_reg;
2928         if (fence_reg < 8)
2929                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2930         else
2931                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2932
2933         if (pipelined) {
2934                 int ret = intel_ring_begin(pipelined, 4);
2935                 if (ret)
2936                         return ret;
2937
2938                 intel_ring_emit(pipelined, MI_NOOP);
2939                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2940                 intel_ring_emit(pipelined, fence_reg);
2941                 intel_ring_emit(pipelined, val);
2942                 intel_ring_advance(pipelined);
2943         } else
2944                 I915_WRITE(fence_reg, val);
2945
2946         return 0;
2947 }
2948
2949 static int
2950 i830_write_fence_reg(struct drm_i915_gem_object *obj,
2951     struct intel_ring_buffer *pipelined)
2952 {
2953         struct drm_device *dev = obj->base.dev;
2954         drm_i915_private_t *dev_priv = dev->dev_private;
2955         u32 size = obj->gtt_space->size;
2956         int regnum = obj->fence_reg;
2957         uint32_t val;
2958         uint32_t pitch_val;
2959
2960         if ((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2961             (size & -size) != size || (obj->gtt_offset & (size - 1))) {
2962                 kprintf(
2963 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2964                     obj->gtt_offset, size);
2965                 return -EINVAL;
2966         }
2967
2968         pitch_val = obj->stride / 128;
2969         pitch_val = ffs(pitch_val) - 1;
2970
2971         val = obj->gtt_offset;
2972         if (obj->tiling_mode == I915_TILING_Y)
2973                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2974         val |= I830_FENCE_SIZE_BITS(size);
2975         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2976         val |= I830_FENCE_REG_VALID;
2977
2978         if (pipelined) {
2979                 int ret = intel_ring_begin(pipelined, 4);
2980                 if (ret)
2981                         return ret;
2982
2983                 intel_ring_emit(pipelined, MI_NOOP);
2984                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2985                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2986                 intel_ring_emit(pipelined, val);
2987                 intel_ring_advance(pipelined);
2988         } else
2989                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2990
2991         return 0;
2992 }
2993
2994 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2995 {
2996         return i915_seqno_passed(ring->get_seqno(ring), seqno);
2997 }
2998
2999 static int
3000 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
3001     struct intel_ring_buffer *pipelined)
3002 {
3003         int ret;
3004
3005         if (obj->fenced_gpu_access) {
3006                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3007                         ret = i915_gem_flush_ring(obj->last_fenced_ring, 0,
3008                             obj->base.write_domain);
3009                         if (ret)
3010                                 return ret;
3011                 }
3012
3013                 obj->fenced_gpu_access = false;
3014         }
3015
3016         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
3017                 if (!ring_passed_seqno(obj->last_fenced_ring,
3018                                        obj->last_fenced_seqno)) {
3019                         ret = i915_wait_request(obj->last_fenced_ring,
3020                                                 obj->last_fenced_seqno,
3021                                                 true);
3022                         if (ret)
3023                                 return ret;
3024                 }
3025
3026                 obj->last_fenced_seqno = 0;
3027                 obj->last_fenced_ring = NULL;
3028         }
3029
3030         /* Ensure that all CPU reads are completed before installing a fence
3031          * and all writes before removing the fence.
3032          */
3033         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
3034                 cpu_mfence();
3035
3036         return 0;
3037 }
3038
3039 int
3040 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3041 {
3042         int ret;
3043
3044         if (obj->tiling_mode)
3045                 i915_gem_release_mmap(obj);
3046
3047         ret = i915_gem_object_flush_fence(obj, NULL);
3048         if (ret)
3049                 return ret;
3050
3051         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3052                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3053
3054                 if (dev_priv->fence_regs[obj->fence_reg].pin_count != 0)
3055                         kprintf("%s: pin_count %d\n", __func__,
3056                             dev_priv->fence_regs[obj->fence_reg].pin_count);
3057                 i915_gem_clear_fence_reg(obj->base.dev,
3058                                          &dev_priv->fence_regs[obj->fence_reg]);
3059
3060                 obj->fence_reg = I915_FENCE_REG_NONE;
3061         }
3062
3063         return 0;
3064 }
3065
3066 static struct drm_i915_fence_reg *
3067 i915_find_fence_reg(struct drm_device *dev, struct intel_ring_buffer *pipelined)
3068 {
3069         struct drm_i915_private *dev_priv = dev->dev_private;
3070         struct drm_i915_fence_reg *reg, *first, *avail;
3071         int i;
3072
3073         /* First try to find a free reg */
3074         avail = NULL;
3075         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3076                 reg = &dev_priv->fence_regs[i];
3077                 if (!reg->obj)
3078                         return reg;
3079
3080                 if (!reg->pin_count)
3081                         avail = reg;
3082         }
3083
3084         if (avail == NULL)
3085                 return NULL;
3086
3087         /* None available, try to steal one or wait for a user to finish */
3088         avail = first = NULL;
3089         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3090                 if (reg->pin_count)
3091                         continue;
3092
3093                 if (first == NULL)
3094                         first = reg;
3095
3096                 if (!pipelined ||
3097                     !reg->obj->last_fenced_ring ||
3098                     reg->obj->last_fenced_ring == pipelined) {
3099                         avail = reg;
3100                         break;
3101                 }
3102         }
3103
3104         if (avail == NULL)
3105                 avail = first;
3106
3107         return avail;
3108 }
3109
3110 int
3111 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
3112     struct intel_ring_buffer *pipelined)
3113 {
3114         struct drm_device *dev = obj->base.dev;
3115         struct drm_i915_private *dev_priv = dev->dev_private;
3116         struct drm_i915_fence_reg *reg;
3117         int ret;
3118
3119         pipelined = NULL;
3120         ret = 0;
3121
3122         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3123                 reg = &dev_priv->fence_regs[obj->fence_reg];
3124                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
3125
3126                 if (obj->tiling_changed) {
3127                         ret = i915_gem_object_flush_fence(obj, pipelined);
3128                         if (ret)
3129                                 return ret;
3130
3131                         if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3132                                 pipelined = NULL;
3133
3134                         if (pipelined) {
3135                                 reg->setup_seqno =
3136                                         i915_gem_next_request_seqno(pipelined);
3137                                 obj->last_fenced_seqno = reg->setup_seqno;
3138                                 obj->last_fenced_ring = pipelined;
3139                         }
3140
3141                         goto update;
3142                 }
3143
3144                 if (!pipelined) {
3145                         if (reg->setup_seqno) {
3146                                 if (!ring_passed_seqno(obj->last_fenced_ring,
3147                                     reg->setup_seqno)) {
3148                                         ret = i915_wait_request(
3149                                             obj->last_fenced_ring,
3150                                             reg->setup_seqno,
3151                                             true);
3152                                         if (ret)
3153                                                 return ret;
3154                                 }
3155
3156                                 reg->setup_seqno = 0;
3157                         }
3158                 } else if (obj->last_fenced_ring &&
3159                            obj->last_fenced_ring != pipelined) {
3160                         ret = i915_gem_object_flush_fence(obj, pipelined);
3161                         if (ret)
3162                                 return ret;
3163                 }
3164
3165                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3166                         pipelined = NULL;
3167                 KASSERT(pipelined || reg->setup_seqno == 0, ("!pipelined"));
3168
3169                 if (obj->tiling_changed) {
3170                         if (pipelined) {
3171                                 reg->setup_seqno =
3172                                         i915_gem_next_request_seqno(pipelined);
3173                                 obj->last_fenced_seqno = reg->setup_seqno;
3174                                 obj->last_fenced_ring = pipelined;
3175                         }
3176                         goto update;
3177                 }
3178
3179                 return 0;
3180         }
3181
3182         reg = i915_find_fence_reg(dev, pipelined);
3183         if (reg == NULL)
3184                 return -EDEADLK;
3185
3186         ret = i915_gem_object_flush_fence(obj, pipelined);
3187         if (ret)
3188                 return ret;
3189
3190         if (reg->obj) {
3191                 struct drm_i915_gem_object *old = reg->obj;
3192
3193                 drm_gem_object_reference(&old->base);
3194
3195                 if (old->tiling_mode)
3196                         i915_gem_release_mmap(old);
3197
3198                 ret = i915_gem_object_flush_fence(old, pipelined);
3199                 if (ret) {
3200                         drm_gem_object_unreference(&old->base);
3201                         return ret;
3202                 }
3203
3204                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
3205                         pipelined = NULL;
3206
3207                 old->fence_reg = I915_FENCE_REG_NONE;
3208                 old->last_fenced_ring = pipelined;
3209                 old->last_fenced_seqno =
3210                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3211
3212                 drm_gem_object_unreference(&old->base);
3213         } else if (obj->last_fenced_seqno == 0)
3214                 pipelined = NULL;
3215
3216         reg->obj = obj;
3217         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
3218         obj->fence_reg = reg - dev_priv->fence_regs;
3219         obj->last_fenced_ring = pipelined;
3220
3221         reg->setup_seqno =
3222                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3223         obj->last_fenced_seqno = reg->setup_seqno;
3224
3225 update:
3226         obj->tiling_changed = false;
3227         switch (INTEL_INFO(dev)->gen) {
3228         case 7:
3229         case 6:
3230                 ret = sandybridge_write_fence_reg(obj, pipelined);
3231                 break;
3232         case 5:
3233         case 4:
3234                 ret = i965_write_fence_reg(obj, pipelined);
3235                 break;
3236         case 3:
3237                 ret = i915_write_fence_reg(obj, pipelined);
3238                 break;
3239         case 2:
3240                 ret = i830_write_fence_reg(obj, pipelined);
3241                 break;
3242         }
3243
3244         return ret;
3245 }
3246
3247 static void
3248 i915_gem_clear_fence_reg(struct drm_device *dev, struct drm_i915_fence_reg *reg)
3249 {
3250         drm_i915_private_t *dev_priv = dev->dev_private;
3251         uint32_t fence_reg = reg - dev_priv->fence_regs;
3252
3253         switch (INTEL_INFO(dev)->gen) {
3254         case 7:
3255         case 6:
3256                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
3257                 break;
3258         case 5:
3259         case 4:
3260                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
3261                 break;
3262         case 3:
3263                 if (fence_reg >= 8)
3264                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3265                 else
3266         case 2:
3267                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3268
3269                 I915_WRITE(fence_reg, 0);
3270                 break;
3271         }
3272
3273         list_del_init(&reg->lru_list);
3274         reg->obj = NULL;
3275         reg->setup_seqno = 0;
3276         reg->pin_count = 0;
3277 }
3278
3279 int
3280 i915_gem_init_object(struct drm_gem_object *obj)
3281 {
3282
3283         kprintf("i915_gem_init_object called\n");
3284         return (0);
3285 }
3286
3287 static bool
3288 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
3289 {
3290
3291         return (obj->gtt_space && !obj->active && obj->pin_count == 0);
3292 }
3293
3294 static void
3295 i915_gem_retire_work_handler(struct work_struct *work)
3296 {
3297         drm_i915_private_t *dev_priv;
3298         struct drm_device *dev;
3299         struct intel_ring_buffer *ring;
3300         bool idle;
3301         int i;
3302
3303         dev_priv = container_of(work, drm_i915_private_t,
3304                                 mm.retire_work.work);
3305         dev = dev_priv->dev;
3306
3307         /* Come back later if the device is busy... */
3308         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT)) {
3309                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
3310                                    round_jiffies_up_relative(hz));
3311                 return;
3312         }
3313
3314         i915_gem_retire_requests(dev);
3315
3316         /* Send a periodic flush down the ring so we don't hold onto GEM
3317          * objects indefinitely.
3318          */
3319         idle = true;
3320         for (i = 0; i < I915_NUM_RINGS; i++) {
3321                 ring = &dev_priv->ring[i];
3322
3323                 if (!list_empty(&ring->gpu_write_list)) {
3324                         struct drm_i915_gem_request *request;
3325                         int ret;
3326
3327                         ret = i915_gem_flush_ring(ring,
3328                                                   0, I915_GEM_GPU_DOMAINS);
3329                         request = kmalloc(sizeof(*request), DRM_I915_GEM,
3330                             M_WAITOK | M_ZERO);
3331                         if (ret || request == NULL ||
3332                             i915_add_request(ring, NULL, request))
3333                                 drm_free(request, DRM_I915_GEM);
3334                 }
3335
3336                 idle &= list_empty(&ring->request_list);
3337         }
3338
3339         if (!dev_priv->mm.suspended && !idle)
3340                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
3341                                    round_jiffies_up_relative(hz));
3342
3343         DRM_UNLOCK(dev);
3344 }
3345
3346 void
3347 i915_gem_lastclose(struct drm_device *dev)
3348 {
3349         int ret;
3350
3351         if (drm_core_check_feature(dev, DRIVER_MODESET))
3352                 return;
3353
3354         ret = i915_gem_idle(dev);
3355         if (ret != 0)
3356                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3357 }
3358
3359 static int
3360 i915_gem_init_phys_object(struct drm_device *dev, int id, int size, int align)
3361 {
3362         drm_i915_private_t *dev_priv;
3363         struct drm_i915_gem_phys_object *phys_obj;
3364         int ret;
3365
3366         dev_priv = dev->dev_private;
3367         if (dev_priv->mm.phys_objs[id - 1] != NULL || size == 0)
3368                 return (0);
3369
3370         phys_obj = kmalloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
3371             M_WAITOK | M_ZERO);
3372
3373         phys_obj->id = id;
3374
3375         phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
3376         if (phys_obj->handle == NULL) {
3377                 ret = -ENOMEM;
3378                 goto free_obj;
3379         }
3380         pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3381             size / PAGE_SIZE, PAT_WRITE_COMBINING);
3382
3383         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3384
3385         return (0);
3386
3387 free_obj:
3388         drm_free(phys_obj, DRM_I915_GEM);
3389         return (ret);
3390 }
3391
3392 static void
3393 i915_gem_free_phys_object(struct drm_device *dev, int id)
3394 {
3395         drm_i915_private_t *dev_priv;
3396         struct drm_i915_gem_phys_object *phys_obj;
3397
3398         dev_priv = dev->dev_private;
3399         if (dev_priv->mm.phys_objs[id - 1] == NULL)
3400                 return;
3401
3402         phys_obj = dev_priv->mm.phys_objs[id - 1];
3403         if (phys_obj->cur_obj != NULL)
3404                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3405
3406         drm_pci_free(dev, phys_obj->handle);
3407         drm_free(phys_obj, DRM_I915_GEM);
3408         dev_priv->mm.phys_objs[id - 1] = NULL;
3409 }
3410
3411 void
3412 i915_gem_free_all_phys_object(struct drm_device *dev)
3413 {
3414         int i;
3415
3416         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3417                 i915_gem_free_phys_object(dev, i);
3418 }
3419
3420 void
3421 i915_gem_detach_phys_object(struct drm_device *dev,
3422     struct drm_i915_gem_object *obj)
3423 {
3424         vm_page_t m;
3425         struct sf_buf *sf;
3426         char *vaddr, *dst;
3427         int i, page_count;
3428
3429         if (obj->phys_obj == NULL)
3430                 return;
3431         vaddr = obj->phys_obj->handle->vaddr;
3432
3433         page_count = obj->base.size / PAGE_SIZE;
3434         VM_OBJECT_LOCK(obj->base.vm_obj);
3435         for (i = 0; i < page_count; i++) {
3436                 m = i915_gem_wire_page(obj->base.vm_obj, i);
3437                 if (m == NULL)
3438                         continue; /* XXX */
3439
3440                 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3441                 sf = sf_buf_alloc(m);
3442                 if (sf != NULL) {
3443                         dst = (char *)sf_buf_kva(sf);
3444                         memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3445                         sf_buf_free(sf);
3446                 }
3447                 drm_clflush_pages(&m, 1);
3448
3449                 VM_OBJECT_LOCK(obj->base.vm_obj);
3450                 vm_page_reference(m);
3451                 vm_page_dirty(m);
3452                 vm_page_busy_wait(m, FALSE, "i915gem");
3453                 vm_page_unwire(m, 0);
3454                 vm_page_wakeup(m);
3455                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3456         }
3457         VM_OBJECT_UNLOCK(obj->base.vm_obj);
3458         intel_gtt_chipset_flush();
3459
3460         obj->phys_obj->cur_obj = NULL;
3461         obj->phys_obj = NULL;
3462 }
3463
3464 static void
3465 init_ring_lists(struct intel_ring_buffer *ring)
3466 {
3467
3468         INIT_LIST_HEAD(&ring->active_list);
3469         INIT_LIST_HEAD(&ring->request_list);
3470         INIT_LIST_HEAD(&ring->gpu_write_list);
3471 }
3472
3473 void
3474 i915_gem_load(struct drm_device *dev)
3475 {
3476         int i;
3477         drm_i915_private_t *dev_priv = dev->dev_private;
3478
3479         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3480         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3481         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3482         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3483         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3484         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3485         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3486         for (i = 0; i < I915_NUM_RINGS; i++)
3487                 init_ring_lists(&dev_priv->ring[i]);
3488         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3489                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3490         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3491                           i915_gem_retire_work_handler);
3492         dev_priv->error_completion = 0;
3493
3494         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3495         if (IS_GEN3(dev)) {
3496                 I915_WRITE(MI_ARB_STATE,
3497                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3498         }
3499
3500         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3501
3502         /* Old X drivers will take 0-2 for front, back, depth buffers */
3503         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3504                 dev_priv->fence_reg_start = 3;
3505
3506         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3507                 dev_priv->num_fence_regs = 16;
3508         else
3509                 dev_priv->num_fence_regs = 8;
3510
3511         /* Initialize fence registers to zero */
3512         i915_gem_reset_fences(dev);
3513
3514         i915_gem_detect_bit_6_swizzle(dev);
3515
3516         dev_priv->mm.interruptible = true;
3517
3518         dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
3519             i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
3520 }
3521
3522 int
3523 i915_gem_attach_phys_object(struct drm_device *dev,
3524     struct drm_i915_gem_object *obj, int id, int align)
3525 {
3526         drm_i915_private_t *dev_priv;
3527         vm_page_t m;
3528         struct sf_buf *sf;
3529         char *dst, *src;
3530         int i, page_count, ret;
3531
3532         if (id > I915_MAX_PHYS_OBJECT)
3533                 return (-EINVAL);
3534
3535         if (obj->phys_obj != NULL) {
3536                 if (obj->phys_obj->id == id)
3537                         return (0);
3538                 i915_gem_detach_phys_object(dev, obj);
3539         }
3540
3541         dev_priv = dev->dev_private;
3542         if (dev_priv->mm.phys_objs[id - 1] == NULL) {
3543                 ret = i915_gem_init_phys_object(dev, id, obj->base.size, align);
3544                 if (ret != 0) {
3545                         DRM_ERROR("failed to init phys object %d size: %zu\n",
3546                                   id, obj->base.size);
3547                         return (ret);
3548                 }
3549         }
3550
3551         /* bind to the object */
3552         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3553         obj->phys_obj->cur_obj = obj;
3554
3555         page_count = obj->base.size / PAGE_SIZE;
3556
3557         VM_OBJECT_LOCK(obj->base.vm_obj);
3558         ret = 0;
3559         for (i = 0; i < page_count; i++) {
3560                 m = i915_gem_wire_page(obj->base.vm_obj, i);
3561                 if (m == NULL) {
3562                         ret = -EIO;
3563                         break;
3564                 }
3565                 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3566                 sf = sf_buf_alloc(m);
3567                 src = (char *)sf_buf_kva(sf);
3568                 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3569                 memcpy(dst, src, PAGE_SIZE);
3570                 sf_buf_free(sf);
3571
3572                 VM_OBJECT_LOCK(obj->base.vm_obj);
3573
3574                 vm_page_reference(m);
3575                 vm_page_busy_wait(m, FALSE, "i915gem");
3576                 vm_page_unwire(m, 0);
3577                 vm_page_wakeup(m);
3578                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3579         }
3580         VM_OBJECT_UNLOCK(obj->base.vm_obj);
3581
3582         return (0);
3583 }
3584
3585 static int
3586 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_i915_gem_object *obj,
3587     uint64_t data_ptr, uint64_t offset, uint64_t size,
3588     struct drm_file *file_priv)
3589 {
3590         char *user_data, *vaddr;
3591         int ret;
3592
3593         vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3594         user_data = (char *)(uintptr_t)data_ptr;
3595
3596         if (copyin_nofault(user_data, vaddr, size) != 0) {
3597                 /* The physical object once assigned is fixed for the lifetime
3598                  * of the obj, so we can safely drop the lock and continue
3599                  * to access vaddr.
3600                  */
3601                 DRM_UNLOCK(dev);
3602                 ret = -copyin(user_data, vaddr, size);
3603                 DRM_LOCK(dev);
3604                 if (ret != 0)
3605                         return (ret);
3606         }
3607
3608         intel_gtt_chipset_flush();
3609         return (0);
3610 }
3611
3612 static int
3613 i915_gpu_is_active(struct drm_device *dev)
3614 {
3615         drm_i915_private_t *dev_priv;
3616
3617         dev_priv = dev->dev_private;
3618         return (!list_empty(&dev_priv->mm.flushing_list) ||
3619             !list_empty(&dev_priv->mm.active_list));
3620 }
3621
3622 static void
3623 i915_gem_lowmem(void *arg)
3624 {
3625         struct drm_device *dev;
3626         struct drm_i915_private *dev_priv;
3627         struct drm_i915_gem_object *obj, *next;
3628         int cnt, cnt_fail, cnt_total;
3629
3630         dev = arg;
3631         dev_priv = dev->dev_private;
3632
3633         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
3634                 return;
3635
3636 rescan:
3637         /* first scan for clean buffers */
3638         i915_gem_retire_requests(dev);
3639
3640         cnt_total = cnt_fail = cnt = 0;
3641
3642         list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3643             mm_list) {
3644                 if (i915_gem_object_is_purgeable(obj)) {
3645                         if (i915_gem_object_unbind(obj) != 0)
3646                                 cnt_total++;
3647                 } else
3648                         cnt_total++;
3649         }
3650
3651         /* second pass, evict/count anything still on the inactive list */
3652         list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3653             mm_list) {
3654                 if (i915_gem_object_unbind(obj) == 0)
3655                         cnt++;
3656                 else
3657                         cnt_fail++;
3658         }
3659
3660         if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
3661                 /*
3662                  * We are desperate for pages, so as a last resort, wait
3663                  * for the GPU to finish and discard whatever we can.
3664                  * This has a dramatic impact to reduce the number of
3665                  * OOM-killer events whilst running the GPU aggressively.
3666                  */
3667                 if (i915_gpu_idle(dev, true) == 0)
3668                         goto rescan;
3669         }
3670         DRM_UNLOCK(dev);
3671 }
3672
3673 void
3674 i915_gem_unload(struct drm_device *dev)
3675 {
3676         struct drm_i915_private *dev_priv;
3677
3678         dev_priv = dev->dev_private;
3679         EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);
3680 }