3 * Header for the Direct Rendering Manager
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
39 * The Direct Rendering Manager (DRM) is a device-independent kernel-level
40 * device driver that provides support for the XFree86 Direct Rendering
41 * Infrastructure (DRI).
43 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
45 * -# The DRM provides synchronized access to the graphics hardware via
46 * the use of an optimized two-tiered lock.
47 * -# The DRM enforces the DRI security policy for access to the graphics
48 * hardware by only allowing authenticated X11 clients access to
49 * restricted regions of memory.
50 * -# The DRM provides a generic DMA engine, complete with multiple
51 * queues and the ability to detect the need for an OpenGL context
53 * -# The DRM is extensible via the use of small device-specific modules
54 * that rely extensively on the API exported by the DRM module.
69 # define DEPRECATED __attribute__ ((deprecated))
74 #if defined(__linux__)
75 #include <asm/ioctl.h> /* For _IO* macros */
76 #define DRM_IOCTL_NR(n) _IOC_NR(n)
77 #define DRM_IOC_VOID _IOC_NONE
78 #define DRM_IOC_READ _IOC_READ
79 #define DRM_IOC_WRITE _IOC_WRITE
80 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
81 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
82 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
83 #include <sys/ioccom.h>
84 #define DRM_IOCTL_NR(n) ((n) & 0xff)
85 #define DRM_IOC_VOID IOC_VOID
86 #define DRM_IOC_READ IOC_OUT
87 #define DRM_IOC_WRITE IOC_IN
88 #define DRM_IOC_READWRITE IOC_INOUT
89 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
95 #if defined(__linux__) || defined(__NetBSD__)
99 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
100 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
101 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
102 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
104 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
105 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
106 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
107 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
108 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
110 #if defined(__linux__)
111 typedef unsigned int drm_handle_t;
113 #include <sys/types.h>
114 typedef unsigned long drm_handle_t; /**< To mapped regions */
116 typedef unsigned int drm_context_t; /**< GLXContext handle */
117 typedef unsigned int drm_drawable_t;
118 typedef unsigned int drm_magic_t; /**< Magic for authentication */
123 * \warning If you change this structure, make sure you change
124 * XF86DRIClipRectRec in the server as well
126 * \note KW: Actually it's illegal to change either for
127 * backwards-compatibility reasons.
129 struct drm_clip_rect {
139 struct drm_tex_region {
142 unsigned char in_use;
143 unsigned char padding;
150 * The lock structure is a simple cache-line aligned integer. To avoid
151 * processor bus contention on a multiprocessor system, there should not be any
152 * other data stored in the same cache line.
155 __volatile__ unsigned int lock; /**< lock variable */
156 char padding[60]; /**< Pad to cache line */
159 /* This is beyond ugly, and only works on GCC. However, it allows me to use
160 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
161 * fix is to use uint32_t instead of size_t, but that fix will break existing
162 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will*
163 * eventually happen, though. I chose 'unsigned long' to be the fallback type
164 * because that works on all the platforms I know about. Hopefully, the
165 * real fix will happen before that bites us.
169 # define DRM_SIZE_T __SIZE_TYPE__
171 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
172 # define DRM_SIZE_T unsigned long
176 * DRM_IOCTL_VERSION ioctl argument type.
178 * \sa drmGetVersion().
181 int version_major; /**< Major version */
182 int version_minor; /**< Minor version */
183 int version_patchlevel; /**< Patch level */
184 DRM_SIZE_T name_len; /**< Length of name buffer */
185 char __user *name; /**< Name of driver */
186 DRM_SIZE_T date_len; /**< Length of date buffer */
187 char __user *date; /**< User-space buffer to hold date */
188 DRM_SIZE_T desc_len; /**< Length of desc buffer */
189 char __user *desc; /**< User-space buffer to hold desc */
193 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
195 * \sa drmGetBusid() and drmSetBusId().
198 DRM_SIZE_T unique_len; /**< Length of unique */
199 char __user *unique; /**< Unique name for driver instantiation */
205 int count; /**< Length of user-space structures */
206 struct drm_version __user *version;
214 * DRM_IOCTL_CONTROL ioctl argument type.
216 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
229 * Type of memory to map.
232 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
233 _DRM_REGISTERS = 1, /**< no caching, no core dump */
234 _DRM_SHM = 2, /**< shared, cached */
235 _DRM_AGP = 3, /**< AGP/GART */
236 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
237 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
242 * Memory mapping flags.
245 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
246 _DRM_READ_ONLY = 0x02,
247 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
248 _DRM_KERNEL = 0x08, /**< kernel requires access */
249 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
250 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
251 _DRM_REMOVABLE = 0x40, /**< Removable mapping */
252 _DRM_DRIVER = 0x80 /**< Managed by driver */
255 struct drm_ctx_priv_map {
256 unsigned int ctx_id; /**< Context requesting private mapping */
257 void *handle; /**< Handle of map */
261 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
267 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
268 unsigned long size; /**< Requested physical size (bytes) */
269 enum drm_map_type type; /**< Type of memory to map */
270 enum drm_map_flags flags; /**< Flags */
271 void *handle; /**< User-space: "Handle" to pass to mmap() */
272 /**< Kernel-space: kernel-virtual address */
273 int mtrr; /**< MTRR slot used */
278 * DRM_IOCTL_GET_CLIENT ioctl argument type.
281 int idx; /**< Which client desired? */
282 int auth; /**< Is client authenticated? */
283 unsigned long pid; /**< Process ID */
284 unsigned long uid; /**< User ID */
285 unsigned long magic; /**< Magic */
286 unsigned long iocs; /**< Ioctl count */
296 _DRM_STAT_VALUE, /**< Generic value */
297 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
298 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
300 _DRM_STAT_IRQ, /**< IRQ */
301 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
302 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
303 _DRM_STAT_DMA, /**< DMA */
304 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
305 _DRM_STAT_MISSED /**< Missed DMA opportunity */
306 /* Add to the *END* of the list */
310 * DRM_IOCTL_GET_STATS ioctl argument type.
316 enum drm_stat_type type;
321 * Hardware locking flags.
323 enum drm_lock_flags {
324 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
325 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
326 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
327 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
328 /* These *HALT* flags aren't supported yet
329 -- they will be used to support the
330 full-screen DGA-like mode. */
331 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
332 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
336 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
338 * \sa drmGetLock() and drmUnlock().
342 enum drm_lock_flags flags;
349 * These values \e must match xf86drm.h.
354 /* Flags for DMA buffer dispatch */
355 _DRM_DMA_BLOCK = 0x01, /**<
356 * Block until buffer dispatched.
358 * \note The buffer may not yet have
359 * been processed by the hardware --
360 * getting a hardware lock with the
361 * hardware quiescent will ensure
362 * that the buffer has been
365 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
366 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
368 /* Flags for DMA buffer request */
369 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
370 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
371 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
375 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
379 struct drm_buf_desc {
380 int count; /**< Number of buffers of this size */
381 int size; /**< Size in bytes */
382 int low_mark; /**< Low water mark */
383 int high_mark; /**< High water mark */
385 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
386 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
387 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
388 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
389 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
391 unsigned long agp_start; /**<
392 * Start address of where the AGP buffers are
393 * in the AGP aperture
398 * DRM_IOCTL_INFO_BUFS ioctl argument type.
400 struct drm_buf_info {
401 int count; /**< Number of buffers described in list */
402 struct drm_buf_desc __user *list; /**< List of buffer descriptions */
406 * DRM_IOCTL_FREE_BUFS ioctl argument type.
408 struct drm_buf_free {
419 int idx; /**< Index into the master buffer list */
420 int total; /**< Buffer size */
421 int used; /**< Amount of buffer in use (for DMA) */
422 void __user *address; /**< Address of buffer */
426 * DRM_IOCTL_MAP_BUFS ioctl argument type.
429 int count; /**< Length of the buffer list */
430 #if defined(__cplusplus)
431 void __user *c_virtual;
433 void __user *virtual; /**< Mmap'd area in user-virtual */
435 struct drm_buf_pub __user *list; /**< Buffer information */
439 * DRM_IOCTL_DMA ioctl argument type.
441 * Indices here refer to the offset into the buffer list in drm_buf_get.
446 int context; /**< Context handle */
447 int send_count; /**< Number of buffers to send */
448 int __user *send_indices; /**< List of handles to buffers */
449 int __user *send_sizes; /**< Lengths of data to send */
450 enum drm_dma_flags flags; /**< Flags */
451 int request_count; /**< Number of buffers requested */
452 int request_size; /**< Desired size for buffers */
453 int __user *request_indices; /**< Buffer information */
454 int __user *request_sizes;
455 int granted_count; /**< Number of buffers granted */
459 _DRM_CONTEXT_PRESERVED = 0x01,
460 _DRM_CONTEXT_2DONLY = 0x02
464 * DRM_IOCTL_ADD_CTX ioctl argument type.
466 * \sa drmCreateContext() and drmDestroyContext().
469 drm_context_t handle;
470 enum drm_ctx_flags flags;
474 * DRM_IOCTL_RES_CTX ioctl argument type.
478 struct drm_ctx __user *contexts;
482 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
485 drm_drawable_t handle;
489 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
492 DRM_DRAWABLE_CLIPRECTS,
493 } drm_drawable_info_type_t;
495 struct drm_update_draw {
496 drm_drawable_t handle;
499 unsigned long long data;
503 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
510 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
512 * \sa drmGetInterruptFromBusID().
514 struct drm_irq_busid {
515 int irq; /**< IRQ number */
516 int busnum; /**< bus number */
517 int devnum; /**< device number */
518 int funcnum; /**< function number */
521 enum drm_vblank_seq_type {
522 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
523 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
524 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
525 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
526 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
527 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
530 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
531 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
532 _DRM_VBLANK_NEXTONMISS)
534 struct drm_wait_vblank_request {
535 enum drm_vblank_seq_type type;
536 unsigned int sequence;
537 unsigned long signal;
540 struct drm_wait_vblank_reply {
541 enum drm_vblank_seq_type type;
542 unsigned int sequence;
548 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
550 * \sa drmWaitVBlank().
552 union drm_wait_vblank {
553 struct drm_wait_vblank_request request;
554 struct drm_wait_vblank_reply reply;
558 #define _DRM_PRE_MODESET 1
559 #define _DRM_POST_MODESET 2
562 * DRM_IOCTL_MODESET_CTL ioctl argument type
564 * \sa drmModesetCtl().
566 struct drm_modeset_ctl {
572 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
574 * \sa drmAgpEnable().
576 struct drm_agp_mode {
577 unsigned long mode; /**< AGP mode */
581 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
583 * \sa drmAgpAlloc() and drmAgpFree().
585 struct drm_agp_buffer {
586 unsigned long size; /**< In bytes -- will round to page boundary */
587 unsigned long handle; /**< Used for binding / unbinding */
588 unsigned long type; /**< Type of memory to allocate */
589 unsigned long physical; /**< Physical used by i810 */
593 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
595 * \sa drmAgpBind() and drmAgpUnbind().
597 struct drm_agp_binding {
598 unsigned long handle; /**< From drm_agp_buffer */
599 unsigned long offset; /**< In bytes -- will round to page boundary */
603 * DRM_IOCTL_AGP_INFO ioctl argument type.
605 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
606 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
607 * drmAgpVendorId() and drmAgpDeviceId().
609 struct drm_agp_info {
610 int agp_version_major;
611 int agp_version_minor;
613 unsigned long aperture_base; /**< physical address */
614 unsigned long aperture_size; /**< bytes */
615 unsigned long memory_allowed; /**< bytes */
616 unsigned long memory_used;
618 /** \name PCI information */
620 unsigned short id_vendor;
621 unsigned short id_device;
626 * DRM_IOCTL_SG_ALLOC ioctl argument type.
628 struct drm_scatter_gather {
629 unsigned long size; /**< In bytes -- will round to page boundary */
630 unsigned long handle; /**< Used for mapping / unmapping */
634 * DRM_IOCTL_SET_VERSION ioctl argument type.
636 struct drm_set_version {
644 #define DRM_FENCE_FLAG_EMIT 0x00000001
645 #define DRM_FENCE_FLAG_SHAREABLE 0x00000002
647 * On hardware with no interrupt events for operation completion,
648 * indicates that the kernel should sleep while waiting for any blocking
649 * operation to complete rather than spinning.
651 * Has no effect otherwise.
653 #define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
654 #define DRM_FENCE_FLAG_NO_USER 0x00000010
656 /* Reserved for driver use */
657 #define DRM_FENCE_MASK_DRIVER 0xFF000000
659 #define DRM_FENCE_TYPE_EXE 0x00000001
661 struct drm_fence_arg {
663 unsigned int fence_class;
666 unsigned int signaled;
668 unsigned int sequence;
670 uint64_t expand_pad[2]; /*Future expansion */
673 /* Buffer permissions, referring to how the GPU uses the buffers.
674 * these translate to fence types used for the buffers.
675 * Typically a texture buffer is read, A destination buffer is write and
676 * a command (batch-) buffer is exe. Can be or-ed together.
679 #define DRM_BO_FLAG_READ (1ULL << 0)
680 #define DRM_BO_FLAG_WRITE (1ULL << 1)
681 #define DRM_BO_FLAG_EXE (1ULL << 2)
684 * All of the bits related to access mode
686 #define DRM_BO_MASK_ACCESS (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE | DRM_BO_FLAG_EXE)
688 * Status flags. Can be read to determine the actual state of a buffer.
689 * Can also be set in the buffer mask before validation.
693 * Mask: Never evict this buffer. Not even with force. This type of buffer is only
694 * available to root and must be manually removed before buffer manager shutdown
698 #define DRM_BO_FLAG_NO_EVICT (1ULL << 4)
701 * Mask: Require that the buffer is placed in mappable memory when validated.
702 * If not set the buffer may or may not be in mappable memory when validated.
703 * Flags: If set, the buffer is in mappable memory.
705 #define DRM_BO_FLAG_MAPPABLE (1ULL << 5)
707 /* Mask: The buffer should be shareable with other processes.
708 * Flags: The buffer is shareable with other processes.
710 #define DRM_BO_FLAG_SHAREABLE (1ULL << 6)
712 /* Mask: If set, place the buffer in cache-coherent memory if available.
713 * If clear, never place the buffer in cache coherent memory if validated.
714 * Flags: The buffer is currently in cache-coherent memory.
716 #define DRM_BO_FLAG_CACHED (1ULL << 7)
718 /* Mask: Make sure that every time this buffer is validated,
719 * it ends up on the same location provided that the memory mask is the same.
720 * The buffer will also not be evicted when claiming space for
721 * other buffers. Basically a pinned buffer but it may be thrown out as
722 * part of buffer manager shutdown or locking.
723 * Flags: Acknowledge.
725 #define DRM_BO_FLAG_NO_MOVE (1ULL << 8)
727 /* Mask: Make sure the buffer is in cached memory when mapped. In conjunction
728 * with DRM_BO_FLAG_CACHED it also allows the buffer to be bound into the GART
729 * with unsnooped PTEs instead of snooped, by using chipset-specific cache
730 * flushing at bind time. A better name might be DRM_BO_FLAG_TT_UNSNOOPED,
731 * as the eviction to local memory (TTM unbind) on map is just a side effect
732 * to prevent aggressive cache prefetch from the GPU disturbing the cache
733 * management that the DRM is doing.
735 * Flags: Acknowledge.
736 * Buffers allocated with this flag should not be used for suballocators
737 * This type may have issues on CPUs with over-aggressive caching
738 * http://marc.info/?l=linux-kernel&m=102376926732464&w=2
740 #define DRM_BO_FLAG_CACHED_MAPPED (1ULL << 19)
743 /* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set.
744 * Flags: Acknowledge.
746 #define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13)
749 * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear.
750 * Flags: Acknowledge.
752 #define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14)
753 #define DRM_BO_FLAG_TILE (1ULL << 15)
756 * Memory type flags that can be or'ed together in the mask, but only
757 * one appears in flags.
761 #define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24)
762 /* Translation table memory */
763 #define DRM_BO_FLAG_MEM_TT (1ULL << 25)
765 #define DRM_BO_FLAG_MEM_VRAM (1ULL << 26)
766 /* Up to the driver to define. */
767 #define DRM_BO_FLAG_MEM_PRIV0 (1ULL << 27)
768 #define DRM_BO_FLAG_MEM_PRIV1 (1ULL << 28)
769 #define DRM_BO_FLAG_MEM_PRIV2 (1ULL << 29)
770 #define DRM_BO_FLAG_MEM_PRIV3 (1ULL << 30)
771 #define DRM_BO_FLAG_MEM_PRIV4 (1ULL << 31)
772 /* We can add more of these now with a 64-bit flag type */
775 * This is a mask covering all of the memory type flags; easier to just
776 * use a single constant than a bunch of | values. It covers
777 * DRM_BO_FLAG_MEM_LOCAL through DRM_BO_FLAG_MEM_PRIV4
779 #define DRM_BO_MASK_MEM 0x00000000FF000000ULL
781 * This adds all of the CPU-mapping options in with the memory
782 * type to label all bits which change how the page gets mapped
784 #define DRM_BO_MASK_MEMTYPE (DRM_BO_MASK_MEM | \
785 DRM_BO_FLAG_CACHED_MAPPED | \
786 DRM_BO_FLAG_CACHED | \
787 DRM_BO_FLAG_MAPPABLE)
789 /* Driver-private flags */
790 #define DRM_BO_MASK_DRIVER 0xFFFF000000000000ULL
793 * Don't block on validate and map. Instead, return EBUSY.
795 #define DRM_BO_HINT_DONT_BLOCK 0x00000002
797 * Don't place this buffer on the unfenced list. This means
798 * that the buffer will not end up having a fence associated
799 * with it as a result of this operation
801 #define DRM_BO_HINT_DONT_FENCE 0x00000004
803 * On hardware with no interrupt events for operation completion,
804 * indicates that the kernel should sleep while waiting for any blocking
805 * operation to complete rather than spinning.
807 * Has no effect otherwise.
809 #define DRM_BO_HINT_WAIT_LAZY 0x00000008
811 * The client has compute relocations refering to this buffer using the
812 * offset in the presumed_offset field. If that offset ends up matching
813 * where this buffer lands, the kernel is free to skip executing those
816 #define DRM_BO_HINT_PRESUMED_OFFSET 0x00000010
818 #define DRM_BO_INIT_MAGIC 0xfe769812
819 #define DRM_BO_INIT_MAJOR 1
820 #define DRM_BO_INIT_MINOR 0
821 #define DRM_BO_INIT_PATCH 0
824 struct drm_bo_info_req {
829 unsigned int fence_class;
830 unsigned int desired_tile_stride;
831 unsigned int tile_info;
833 uint64_t presumed_offset;
836 struct drm_bo_create_req {
839 uint64_t buffer_start;
841 unsigned int page_alignment;
849 #define DRM_BO_REP_BUSY 0x00000001
851 struct drm_bo_info_rep {
853 uint64_t proposed_flags;
857 uint64_t buffer_start;
859 unsigned int fence_flags;
860 unsigned int rep_flags;
861 unsigned int page_alignment;
862 unsigned int desired_tile_stride;
863 unsigned int hw_tile_stride;
864 unsigned int tile_info;
866 uint64_t expand_pad[4]; /*Future expansion */
869 struct drm_bo_arg_rep {
870 struct drm_bo_info_rep bo_info;
875 struct drm_bo_create_arg {
877 struct drm_bo_create_req req;
878 struct drm_bo_info_rep rep;
882 struct drm_bo_handle_arg {
886 struct drm_bo_reference_info_arg {
888 struct drm_bo_handle_arg req;
889 struct drm_bo_info_rep rep;
893 struct drm_bo_map_wait_idle_arg {
895 struct drm_bo_info_req req;
896 struct drm_bo_info_rep rep;
900 struct drm_bo_op_req {
906 unsigned int arg_handle;
907 struct drm_bo_info_req bo_req;
911 struct drm_bo_op_arg {
914 struct drm_bo_op_req req;
915 struct drm_bo_arg_rep rep;
922 #define DRM_BO_MEM_LOCAL 0
923 #define DRM_BO_MEM_TT 1
924 #define DRM_BO_MEM_VRAM 2
925 #define DRM_BO_MEM_PRIV0 3
926 #define DRM_BO_MEM_PRIV1 4
927 #define DRM_BO_MEM_PRIV2 5
928 #define DRM_BO_MEM_PRIV3 6
929 #define DRM_BO_MEM_PRIV4 7
931 #define DRM_BO_MEM_TYPES 8 /* For now. */
933 #define DRM_BO_LOCK_UNLOCK_BM (1 << 0)
934 #define DRM_BO_LOCK_IGNORE_NO_EVICT (1 << 1)
936 struct drm_bo_version_arg {
942 struct drm_mm_type_arg {
943 unsigned int mem_type;
944 unsigned int lock_flags;
947 struct drm_mm_init_arg {
951 unsigned int mem_type;
956 struct drm_mm_info_arg {
957 unsigned int mem_type;
961 struct drm_gem_close {
962 /** Handle of the object to be closed. */
967 struct drm_gem_flink {
968 /** Handle for the object being named */
971 /** Returned global name */
975 struct drm_gem_open {
976 /** Name of object being opened */
979 /** Returned handle for the object */
982 /** Returned size of the object */
987 * \name Ioctls Definitions
991 #define DRM_IOCTL_BASE 'd'
992 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
993 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
994 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
995 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
997 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
998 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
999 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
1000 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
1001 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
1002 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
1003 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
1004 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
1005 #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
1007 #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
1008 #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
1009 #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
1011 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
1012 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
1013 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
1014 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
1015 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
1016 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
1017 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
1018 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
1019 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
1020 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
1021 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
1023 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
1025 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
1026 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
1028 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
1029 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
1030 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
1031 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
1032 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
1033 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
1034 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
1035 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
1036 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
1037 #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
1038 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
1039 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
1040 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
1042 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
1043 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
1044 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
1045 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
1046 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
1047 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
1048 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
1049 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
1051 #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
1052 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
1054 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
1056 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
1058 #define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg)
1059 #define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg)
1060 #define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg)
1061 #define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg)
1063 #define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg)
1064 #define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg)
1065 #define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg)
1066 #define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg)
1067 #define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg)
1068 #define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg)
1069 #define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg)
1070 #define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg)
1072 #define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg)
1073 #define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg)
1074 #define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg)
1075 #define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg)
1076 #define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg)
1077 #define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg)
1078 #define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg)
1079 #define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg)
1080 #define DRM_IOCTL_BO_VERSION DRM_IOR(0xd6, struct drm_bo_version_arg)
1081 #define DRM_IOCTL_MM_INFO DRM_IOWR(0xd7, struct drm_mm_info_arg)
1086 * Device specific ioctls should only be in their respective headers
1087 * The device specific ioctl range is from 0x40 to 0x99.
1088 * Generic IOCTLS restart at 0xA0.
1090 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
1091 * drmCommandReadWrite().
1093 #define DRM_COMMAND_BASE 0x40
1094 #define DRM_COMMAND_END 0xA0
1098 typedef struct drm_clip_rect drm_clip_rect_t;
1099 typedef struct drm_tex_region drm_tex_region_t;
1100 typedef struct drm_hw_lock drm_hw_lock_t;
1101 typedef struct drm_version drm_version_t;
1102 typedef struct drm_unique drm_unique_t;
1103 typedef struct drm_list drm_list_t;
1104 typedef struct drm_block drm_block_t;
1105 typedef struct drm_control drm_control_t;
1106 typedef enum drm_map_type drm_map_type_t;
1107 typedef enum drm_map_flags drm_map_flags_t;
1108 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
1109 typedef struct drm_map drm_map_t;
1110 typedef struct drm_client drm_client_t;
1111 typedef enum drm_stat_type drm_stat_type_t;
1112 typedef struct drm_stats drm_stats_t;
1113 typedef enum drm_lock_flags drm_lock_flags_t;
1114 typedef struct drm_lock drm_lock_t;
1115 typedef enum drm_dma_flags drm_dma_flags_t;
1116 typedef struct drm_buf_desc drm_buf_desc_t;
1117 typedef struct drm_buf_info drm_buf_info_t;
1118 typedef struct drm_buf_free drm_buf_free_t;
1119 typedef struct drm_buf_pub drm_buf_pub_t;
1120 typedef struct drm_buf_map drm_buf_map_t;
1121 typedef struct drm_dma drm_dma_t;
1122 typedef union drm_wait_vblank drm_wait_vblank_t;
1123 typedef struct drm_agp_mode drm_agp_mode_t;
1124 typedef enum drm_ctx_flags drm_ctx_flags_t;
1125 typedef struct drm_ctx drm_ctx_t;
1126 typedef struct drm_ctx_res drm_ctx_res_t;
1127 typedef struct drm_draw drm_draw_t;
1128 typedef struct drm_update_draw drm_update_draw_t;
1129 typedef struct drm_auth drm_auth_t;
1130 typedef struct drm_irq_busid drm_irq_busid_t;
1131 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
1132 typedef struct drm_agp_buffer drm_agp_buffer_t;
1133 typedef struct drm_agp_binding drm_agp_binding_t;
1134 typedef struct drm_agp_info drm_agp_info_t;
1135 typedef struct drm_scatter_gather drm_scatter_gather_t;
1136 typedef struct drm_set_version drm_set_version_t;
1138 typedef struct drm_fence_arg drm_fence_arg_t;
1139 typedef struct drm_mm_type_arg drm_mm_type_arg_t;
1140 typedef struct drm_mm_init_arg drm_mm_init_arg_t;
1141 typedef enum drm_bo_type drm_bo_type_t;