sys/dev/drm/radeon/r600_blit.c

   1 /*
   2  * Copyright 2009 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  *
  26  * $FreeBSD: head/sys/dev/drm2/radeon/r600_blit.c 254885 2013-08-25 19:37:15Z dumbbell $
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <uapi_drm/radeon_drm.h>
  31 #include "radeon_drv.h"
  32
  33 #include "r600_blit_shaders.h"
  34
  35 #define DI_PT_RECTLIST        0x11
  36 #define DI_INDEX_SIZE_16_BIT  0x0
  37 #define DI_SRC_SEL_AUTO_INDEX 0x2
  38
  39 #define FMT_8                 0x1
  40 #define FMT_5_6_5             0x8
  41 #define FMT_8_8_8_8           0x1a
  42 #define COLOR_8               0x1
  43 #define COLOR_5_6_5           0x8
  44 #define COLOR_8_8_8_8         0x1a
  45
  46 static void
  47 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr)
  48 {
  49         u32 cb_color_info;
  50         int pitch, slice;
  51         RING_LOCALS;
  52         DRM_DEBUG("\n");
  53
  54         h = roundup2(h, 8);
  55         if (h < 8)
  56                 h = 8;
  57
  58         cb_color_info = ((format << 2) | (1 << 27));
  59         pitch = (w / 8) - 1;
  60         slice = ((w * h) / 64) - 1;
  61
  62         if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) &&
  63             ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) {
  64                 BEGIN_RING(21 + 2);
  65                 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
  66                 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
  67                 OUT_RING(gpu_addr >> 8);
  68                 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
  69                 OUT_RING(2 << 0);
  70         } else {
  71                 BEGIN_RING(21);
  72                 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
  73                 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
  74                 OUT_RING(gpu_addr >> 8);
  75         }
  76
  77         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
  78         OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
  79         OUT_RING((pitch << 0) | (slice << 10));
  80
  81         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
  82         OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2);
  83         OUT_RING(0);
  84
  85         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
  86         OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2);
  87         OUT_RING(cb_color_info);
  88
  89         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
  90         OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
  91         OUT_RING(0);
  92
  93         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
  94         OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2);
  95         OUT_RING(0);
  96
  97         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
  98         OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2);
  99         OUT_RING(0);
 100
 101         ADVANCE_RING();
 102 }
 103
 104 static void
 105 cp_set_surface_sync(drm_radeon_private_t *dev_priv,
 106                     u32 sync_type, u32 size, u64 mc_addr)
 107 {
 108         u32 cp_coher_size;
 109         RING_LOCALS;
 110         DRM_DEBUG("\n");
 111
 112         if (size == 0xffffffff)
 113                 cp_coher_size = 0xffffffff;
 114         else
 115                 cp_coher_size = ((size + 255) >> 8);
 116
 117         BEGIN_RING(5);
 118         OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
 119         OUT_RING(sync_type);
 120         OUT_RING(cp_coher_size);
 121         OUT_RING((mc_addr >> 8));
 122         OUT_RING(10); /* poll interval */
 123         ADVANCE_RING();
 124 }
 125
 126 static void
 127 set_shaders(struct drm_device *dev)
 128 {
 129         drm_radeon_private_t *dev_priv = dev->dev_private;
 130         u64 gpu_addr;
 131         int i;
 132         u32 *vs, *ps;
 133         uint32_t sq_pgm_resources;
 134         RING_LOCALS;
 135         DRM_DEBUG("\n");
 136
 137         /* load shaders */
 138         vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset);
 139         ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
 140
 141         for (i = 0; i < r6xx_vs_size; i++)
 142                 vs[i] = cpu_to_le32(r6xx_vs[i]);
 143         for (i = 0; i < r6xx_ps_size; i++)
 144                 ps[i] = cpu_to_le32(r6xx_ps[i]);
 145
 146         dev_priv->blit_vb->used = 512;
 147
 148         gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset;
 149
 150         /* setup shader regs */
 151         sq_pgm_resources = (1 << 0);
 152
 153         BEGIN_RING(9 + 12);
 154         /* VS */
 155         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
 156         OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
 157         OUT_RING(gpu_addr >> 8);
 158
 159         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
 160         OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
 161         OUT_RING(sq_pgm_resources);
 162
 163         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
 164         OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
 165         OUT_RING(0);
 166
 167         /* PS */
 168         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
 169         OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
 170         OUT_RING((gpu_addr + 256) >> 8);
 171
 172         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
 173         OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
 174         OUT_RING(sq_pgm_resources | (1 << 28));
 175
 176         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
 177         OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
 178         OUT_RING(2);
 179
 180         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
 181         OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
 182         OUT_RING(0);
 183         ADVANCE_RING();
 184
 185         cp_set_surface_sync(dev_priv,
 186                             R600_SH_ACTION_ENA, 512, gpu_addr);
 187 }
 188
 189 static void
 190 set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
 191 {
 192         uint32_t sq_vtx_constant_word2;
 193         RING_LOCALS;
 194         DRM_DEBUG("\n");
 195
 196         sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8));
 197 #ifdef __BIG_ENDIAN
 198         sq_vtx_constant_word2 |= (2 << 30);
 199 #endif
 200
 201         BEGIN_RING(9);
 202         OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
 203         OUT_RING(0x460);
 204         OUT_RING(gpu_addr & 0xffffffff);
 205         OUT_RING(48 - 1);
 206         OUT_RING(sq_vtx_constant_word2);
 207         OUT_RING(1 << 0);
 208         OUT_RING(0);
 209         OUT_RING(0);
 210         OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30);
 211         ADVANCE_RING();
 212
 213         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 214             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 215             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 216             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
 217             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
 218                 cp_set_surface_sync(dev_priv,
 219                                     R600_TC_ACTION_ENA, 48, gpu_addr);
 220         else
 221                 cp_set_surface_sync(dev_priv,
 222                                     R600_VC_ACTION_ENA, 48, gpu_addr);
 223 }
 224
 225 static void
 226 set_tex_resource(drm_radeon_private_t *dev_priv,
 227                  int format, int w, int h, int pitch, u64 gpu_addr)
 228 {
 229         uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
 230         RING_LOCALS;
 231         DRM_DEBUG("\n");
 232
 233         if (h < 1)
 234                 h = 1;
 235
 236         sq_tex_resource_word0 = (1 << 0);
 237         sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
 238                                   ((w - 1) << 19));
 239
 240         sq_tex_resource_word1 = (format << 26);
 241         sq_tex_resource_word1 |= ((h - 1) << 0);
 242
 243         sq_tex_resource_word4 = ((1 << 14) |
 244                                  (0 << 16) |
 245                                  (1 << 19) |
 246                                  (2 << 22) |
 247                                  (3 << 25));
 248
 249         BEGIN_RING(9);
 250         OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
 251         OUT_RING(0);
 252         OUT_RING(sq_tex_resource_word0);
 253         OUT_RING(sq_tex_resource_word1);
 254         OUT_RING(gpu_addr >> 8);
 255         OUT_RING(gpu_addr >> 8);
 256         OUT_RING(sq_tex_resource_word4);
 257         OUT_RING(0);
 258         OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30);
 259         ADVANCE_RING();
 260
 261 }
 262
 263 static void
 264 set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
 265 {
 266         RING_LOCALS;
 267         DRM_DEBUG("\n");
 268
 269         BEGIN_RING(12);
 270         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
 271         OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
 272         OUT_RING((x1 << 0) | (y1 << 16));
 273         OUT_RING((x2 << 0) | (y2 << 16));
 274
 275         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
 276         OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
 277         OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
 278         OUT_RING((x2 << 0) | (y2 << 16));
 279
 280         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
 281         OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
 282         OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
 283         OUT_RING((x2 << 0) | (y2 << 16));
 284         ADVANCE_RING();
 285 }
 286
 287 static void
 288 draw_auto(drm_radeon_private_t *dev_priv)
 289 {
 290         RING_LOCALS;
 291         DRM_DEBUG("\n");
 292
 293         BEGIN_RING(10);
 294         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
 295         OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2);
 296         OUT_RING(DI_PT_RECTLIST);
 297
 298         OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
 299 #ifdef __BIG_ENDIAN
 300         OUT_RING((2 << 2) | DI_INDEX_SIZE_16_BIT);
 301 #else
 302         OUT_RING(DI_INDEX_SIZE_16_BIT);
 303 #endif
 304
 305         OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
 306         OUT_RING(1);
 307
 308         OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
 309         OUT_RING(3);
 310         OUT_RING(DI_SRC_SEL_AUTO_INDEX);
 311
 312         ADVANCE_RING();
 313         COMMIT_RING();
 314 }
 315
 316 static void
 317 set_default_state(drm_radeon_private_t *dev_priv)
 318 {
 319         int i;
 320         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
 321         u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
 322         int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
 323         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 324         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 325         RING_LOCALS;
 326
 327         switch ((dev_priv->flags & RADEON_FAMILY_MASK)) {
 328         case CHIP_R600:
 329                 num_ps_gprs = 192;
 330                 num_vs_gprs = 56;
 331                 num_temp_gprs = 4;
 332                 num_gs_gprs = 0;
 333                 num_es_gprs = 0;
 334                 num_ps_threads = 136;
 335                 num_vs_threads = 48;
 336                 num_gs_threads = 4;
 337                 num_es_threads = 4;
 338                 num_ps_stack_entries = 128;
 339                 num_vs_stack_entries = 128;
 340                 num_gs_stack_entries = 0;
 341                 num_es_stack_entries = 0;
 342                 break;
 343         case CHIP_RV630:
 344         case CHIP_RV635:
 345                 num_ps_gprs = 84;
 346                 num_vs_gprs = 36;
 347                 num_temp_gprs = 4;
 348                 num_gs_gprs = 0;
 349                 num_es_gprs = 0;
 350                 num_ps_threads = 144;
 351                 num_vs_threads = 40;
 352                 num_gs_threads = 4;
 353                 num_es_threads = 4;
 354                 num_ps_stack_entries = 40;
 355                 num_vs_stack_entries = 40;
 356                 num_gs_stack_entries = 32;
 357                 num_es_stack_entries = 16;
 358                 break;
 359         case CHIP_RV610:
 360         case CHIP_RV620:
 361         case CHIP_RS780:
 362         case CHIP_RS880:
 363         default:
 364                 num_ps_gprs = 84;
 365                 num_vs_gprs = 36;
 366                 num_temp_gprs = 4;
 367                 num_gs_gprs = 0;
 368                 num_es_gprs = 0;
 369                 num_ps_threads = 136;
 370                 num_vs_threads = 48;
 371                 num_gs_threads = 4;
 372                 num_es_threads = 4;
 373                 num_ps_stack_entries = 40;
 374                 num_vs_stack_entries = 40;
 375                 num_gs_stack_entries = 32;
 376                 num_es_stack_entries = 16;
 377                 break;
 378         case CHIP_RV670:
 379                 num_ps_gprs = 144;
 380                 num_vs_gprs = 40;
 381                 num_temp_gprs = 4;
 382                 num_gs_gprs = 0;
 383                 num_es_gprs = 0;
 384                 num_ps_threads = 136;
 385                 num_vs_threads = 48;
 386                 num_gs_threads = 4;
 387                 num_es_threads = 4;
 388                 num_ps_stack_entries = 40;
 389                 num_vs_stack_entries = 40;
 390                 num_gs_stack_entries = 32;
 391                 num_es_stack_entries = 16;
 392                 break;
 393         case CHIP_RV770:
 394                 num_ps_gprs = 192;
 395                 num_vs_gprs = 56;
 396                 num_temp_gprs = 4;
 397                 num_gs_gprs = 0;
 398                 num_es_gprs = 0;
 399                 num_ps_threads = 188;
 400                 num_vs_threads = 60;
 401                 num_gs_threads = 0;
 402                 num_es_threads = 0;
 403                 num_ps_stack_entries = 256;
 404                 num_vs_stack_entries = 256;
 405                 num_gs_stack_entries = 0;
 406                 num_es_stack_entries = 0;
 407                 break;
 408         case CHIP_RV730:
 409         case CHIP_RV740:
 410                 num_ps_gprs = 84;
 411                 num_vs_gprs = 36;
 412                 num_temp_gprs = 4;
 413                 num_gs_gprs = 0;
 414                 num_es_gprs = 0;
 415                 num_ps_threads = 188;
 416                 num_vs_threads = 60;
 417                 num_gs_threads = 0;
 418                 num_es_threads = 0;
 419                 num_ps_stack_entries = 128;
 420                 num_vs_stack_entries = 128;
 421                 num_gs_stack_entries = 0;
 422                 num_es_stack_entries = 0;
 423                 break;
 424         case CHIP_RV710:
 425                 num_ps_gprs = 192;
 426                 num_vs_gprs = 56;
 427                 num_temp_gprs = 4;
 428                 num_gs_gprs = 0;
 429                 num_es_gprs = 0;
 430                 num_ps_threads = 144;
 431                 num_vs_threads = 48;
 432                 num_gs_threads = 0;
 433                 num_es_threads = 0;
 434                 num_ps_stack_entries = 128;
 435                 num_vs_stack_entries = 128;
 436                 num_gs_stack_entries = 0;
 437                 num_es_stack_entries = 0;
 438                 break;
 439         }
 440
 441         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 442             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 443             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 444             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
 445             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
 446                 sq_config = 0;
 447         else
 448                 sq_config = R600_VC_ENABLE;
 449
 450         sq_config |= (R600_DX9_CONSTS |
 451                       R600_ALU_INST_PREFER_VECTOR |
 452                       R600_PS_PRIO(0) |
 453                       R600_VS_PRIO(1) |
 454                       R600_GS_PRIO(2) |
 455                       R600_ES_PRIO(3));
 456
 457         sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(num_ps_gprs) |
 458                                   R600_NUM_VS_GPRS(num_vs_gprs) |
 459                                   R600_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 460         sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(num_gs_gprs) |
 461                                   R600_NUM_ES_GPRS(num_es_gprs));
 462         sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(num_ps_threads) |
 463                                    R600_NUM_VS_THREADS(num_vs_threads) |
 464                                    R600_NUM_GS_THREADS(num_gs_threads) |
 465                                    R600_NUM_ES_THREADS(num_es_threads));
 466         sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 467                                     R600_NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 468         sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 469                                     R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 470
 471         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 472                 BEGIN_RING(r7xx_default_size + 10);
 473                 for (i = 0; i < r7xx_default_size; i++)
 474                         OUT_RING(r7xx_default_state[i]);
 475         } else {
 476                 BEGIN_RING(r6xx_default_size + 10);
 477                 for (i = 0; i < r6xx_default_size; i++)
 478                         OUT_RING(r6xx_default_state[i]);
 479         }
 480         OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
 481         OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
 482         /* SQ config */
 483         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6));
 484         OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2);
 485         OUT_RING(sq_config);
 486         OUT_RING(sq_gpr_resource_mgmt_1);
 487         OUT_RING(sq_gpr_resource_mgmt_2);
 488         OUT_RING(sq_thread_resource_mgmt);
 489         OUT_RING(sq_stack_resource_mgmt_1);
 490         OUT_RING(sq_stack_resource_mgmt_2);
 491         ADVANCE_RING();
 492 }
 493
 494 /* 23 bits of float fractional data */
 495 #define I2F_FRAC_BITS  23
 496 #define I2F_MASK ((1 << I2F_FRAC_BITS) - 1)
 497
 498 /*
 499  * Converts unsigned integer into 32-bit IEEE floating point representation.
 500  * Will be exact from 0 to 2^24.  Above that, we round towards zero
 501  * as the fractional bits will not fit in a float.  (It would be better to
 502  * round towards even as the fpu does, but that is slower.)
 503  */
 504 __pure uint32_t int2float(uint32_t x)
 505 {
 506         uint32_t msb, exponent, fraction;
 507
 508         /* Zero is special */
 509         if (!x) return 0;
 510
 511         /* Get location of the most significant bit */
 512         msb = fls(x);
 513
 514         /*
 515          * Use a rotate instead of a shift because that works both leftwards
 516          * and rightwards due to the mod(32) behaviour.  This means we don't
 517          * need to check to see if we are above 2^24 or not.
 518          */
 519         fraction = ror32(x, (msb - I2F_FRAC_BITS) & 0x1f) & I2F_MASK;
 520         exponent = (127 + msb) << I2F_FRAC_BITS;
 521
 522         return fraction + exponent;
 523 }
 524
 525 static int r600_nomm_get_vb(struct drm_device *dev)
 526 {
 527         drm_radeon_private_t *dev_priv = dev->dev_private;
 528         dev_priv->blit_vb = radeon_freelist_get(dev);
 529         if (!dev_priv->blit_vb) {
 530                 DRM_ERROR("Unable to allocate vertex buffer for blit\n");
 531                 return -EAGAIN;
 532         }
 533         return 0;
 534 }
 535
 536 static void r600_nomm_put_vb(struct drm_device *dev)
 537 {
 538         drm_radeon_private_t *dev_priv = dev->dev_private;
 539
 540         dev_priv->blit_vb->used = 0;
 541         radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->masterp, dev_priv->blit_vb);
 542 }
 543
 544 static void *r600_nomm_get_vb_ptr(struct drm_device *dev)
 545 {
 546         drm_radeon_private_t *dev_priv = dev->dev_private;
 547         return (((char *)dev->agp_buffer_map->handle +
 548                  dev_priv->blit_vb->offset + dev_priv->blit_vb->used));
 549 }
 550
 551 int
 552 r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv)
 553 {
 554         drm_radeon_private_t *dev_priv = dev->dev_private;
 555         int ret;
 556         DRM_DEBUG("\n");
 557
 558         ret = r600_nomm_get_vb(dev);
 559         if (ret)
 560                 return ret;
 561
 562         dev_priv->blit_vb->file_priv = file_priv;
 563
 564         set_default_state(dev_priv);
 565         set_shaders(dev);
 566
 567         return 0;
 568 }
 569
 570
 571 void
 572 r600_done_blit_copy(struct drm_device *dev)
 573 {
 574         drm_radeon_private_t *dev_priv = dev->dev_private;
 575         RING_LOCALS;
 576         DRM_DEBUG("\n");
 577
 578         BEGIN_RING(5);
 579         OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
 580         OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
 581         /* wait for 3D idle clean */
 582         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
 583         OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
 584         OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
 585
 586         ADVANCE_RING();
 587         COMMIT_RING();
 588
 589         r600_nomm_put_vb(dev);
 590 }
 591
 592 void
 593 r600_blit_copy(struct drm_device *dev,
 594                uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
 595                int size_bytes)
 596 {
 597         drm_radeon_private_t *dev_priv = dev->dev_private;
 598         int max_bytes;
 599         u64 vb_addr;
 600         u32 *vb;
 601
 602         vb = r600_nomm_get_vb_ptr(dev);
 603
 604         if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
 605                 max_bytes = 8192;
 606
 607                 while (size_bytes) {
 608                         int cur_size = size_bytes;
 609                         int src_x = src_gpu_addr & 255;
 610                         int dst_x = dst_gpu_addr & 255;
 611                         int h = 1;
 612                         src_gpu_addr = src_gpu_addr & ~255;
 613                         dst_gpu_addr = dst_gpu_addr & ~255;
 614
 615                         if (!src_x && !dst_x) {
 616                                 h = (cur_size / max_bytes);
 617                                 if (h > 8192)
 618                                         h = 8192;
 619                                 if (h == 0)
 620                                         h = 1;
 621                                 else
 622                                         cur_size = max_bytes;
 623                         } else {
 624                                 if (cur_size > max_bytes)
 625                                         cur_size = max_bytes;
 626                                 if (cur_size > (max_bytes - dst_x))
 627                                         cur_size = (max_bytes - dst_x);
 628                                 if (cur_size > (max_bytes - src_x))
 629                                         cur_size = (max_bytes - src_x);
 630                         }
 631
 632                         if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
 633
 634                                 r600_nomm_put_vb(dev);
 635                                 r600_nomm_get_vb(dev);
 636                                 if (!dev_priv->blit_vb)
 637                                         return;
 638                                 set_shaders(dev);
 639                                 vb = r600_nomm_get_vb_ptr(dev);
 640                         }
 641
 642                         vb[0] = int2float(dst_x);
 643                         vb[1] = 0;
 644                         vb[2] = int2float(src_x);
 645                         vb[3] = 0;
 646
 647                         vb[4] = int2float(dst_x);
 648                         vb[5] = int2float(h);
 649                         vb[6] = int2float(src_x);
 650                         vb[7] = int2float(h);
 651
 652                         vb[8] = int2float(dst_x + cur_size);
 653                         vb[9] = int2float(h);
 654                         vb[10] = int2float(src_x + cur_size);
 655                         vb[11] = int2float(h);
 656
 657                         /* src */
 658                         set_tex_resource(dev_priv, FMT_8,
 659                                          src_x + cur_size, h, src_x + cur_size,
 660                                          src_gpu_addr);
 661
 662                         cp_set_surface_sync(dev_priv,
 663                                             R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 664
 665                         /* dst */
 666                         set_render_target(dev_priv, COLOR_8,
 667                                           dst_x + cur_size, h,
 668                                           dst_gpu_addr);
 669
 670                         /* scissors */
 671                         set_scissors(dev_priv, dst_x, 0, dst_x + cur_size, h);
 672
 673                         /* Vertex buffer setup */
 674                         vb_addr = dev_priv->gart_buffers_offset +
 675                                 dev_priv->blit_vb->offset +
 676                                 dev_priv->blit_vb->used;
 677                         set_vtx_resource(dev_priv, vb_addr);
 678
 679                         /* draw */
 680                         draw_auto(dev_priv);
 681
 682                         cp_set_surface_sync(dev_priv,
 683                                             R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
 684                                             cur_size * h, dst_gpu_addr);
 685
 686                         vb += 12;
 687                         dev_priv->blit_vb->used += 12 * 4;
 688
 689                         src_gpu_addr += cur_size * h;
 690                         dst_gpu_addr += cur_size * h;
 691                         size_bytes -= cur_size * h;
 692                 }
 693         } else {
 694                 max_bytes = 8192 * 4;
 695
 696                 while (size_bytes) {
 697                         int cur_size = size_bytes;
 698                         int src_x = (src_gpu_addr & 255);
 699                         int dst_x = (dst_gpu_addr & 255);
 700                         int h = 1;
 701                         src_gpu_addr = src_gpu_addr & ~255;
 702                         dst_gpu_addr = dst_gpu_addr & ~255;
 703
 704                         if (!src_x && !dst_x) {
 705                                 h = (cur_size / max_bytes);
 706                                 if (h > 8192)
 707                                         h = 8192;
 708                                 if (h == 0)
 709                                         h = 1;
 710                                 else
 711                                         cur_size = max_bytes;
 712                         } else {
 713                                 if (cur_size > max_bytes)
 714                                         cur_size = max_bytes;
 715                                 if (cur_size > (max_bytes - dst_x))
 716                                         cur_size = (max_bytes - dst_x);
 717                                 if (cur_size > (max_bytes - src_x))
 718                                         cur_size = (max_bytes - src_x);
 719                         }
 720
 721                         if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
 722                                 r600_nomm_put_vb(dev);
 723                                 r600_nomm_get_vb(dev);
 724                                 if (!dev_priv->blit_vb)
 725                                         return;
 726
 727                                 set_shaders(dev);
 728                                 vb = r600_nomm_get_vb_ptr(dev);
 729                         }
 730
 731                         vb[0] = int2float(dst_x / 4);
 732                         vb[1] = 0;
 733                         vb[2] = int2float(src_x / 4);
 734                         vb[3] = 0;
 735
 736                         vb[4] = int2float(dst_x / 4);
 737                         vb[5] = int2float(h);
 738                         vb[6] = int2float(src_x / 4);
 739                         vb[7] = int2float(h);
 740
 741                         vb[8] = int2float((dst_x + cur_size) / 4);
 742                         vb[9] = int2float(h);
 743                         vb[10] = int2float((src_x + cur_size) / 4);
 744                         vb[11] = int2float(h);
 745
 746                         /* src */
 747                         set_tex_resource(dev_priv, FMT_8_8_8_8,
 748                                          (src_x + cur_size) / 4,
 749                                          h, (src_x + cur_size) / 4,
 750                                          src_gpu_addr);
 751
 752                         cp_set_surface_sync(dev_priv,
 753                                             R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 754
 755                         /* dst */
 756                         set_render_target(dev_priv, COLOR_8_8_8_8,
 757                                           (dst_x + cur_size) / 4, h,
 758                                           dst_gpu_addr);
 759
 760                         /* scissors */
 761                         set_scissors(dev_priv, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
 762
 763                         /* Vertex buffer setup */
 764                         vb_addr = dev_priv->gart_buffers_offset +
 765                                 dev_priv->blit_vb->offset +
 766                                 dev_priv->blit_vb->used;
 767                         set_vtx_resource(dev_priv, vb_addr);
 768
 769                         /* draw */
 770                         draw_auto(dev_priv);
 771
 772                         cp_set_surface_sync(dev_priv,
 773                                             R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
 774                                             cur_size * h, dst_gpu_addr);
 775
 776                         vb += 12;
 777                         dev_priv->blit_vb->used += 12 * 4;
 778
 779                         src_gpu_addr += cur_size * h;
 780                         dst_gpu_addr += cur_size * h;
 781                         size_bytes -= cur_size * h;
 782                 }
 783         }
 784 }
 785
 786 void
 787 r600_blit_swap(struct drm_device *dev,
 788                uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
 789                int sx, int sy, int dx, int dy,
 790                int w, int h, int src_pitch, int dst_pitch, int cpp)
 791 {
 792         drm_radeon_private_t *dev_priv = dev->dev_private;
 793         int cb_format, tex_format;
 794         int sx2, sy2, dx2, dy2;
 795         u64 vb_addr;
 796         u32 *vb;
 797
 798         if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
 799
 800                 r600_nomm_put_vb(dev);
 801                 r600_nomm_get_vb(dev);
 802                 if (!dev_priv->blit_vb)
 803                         return;
 804
 805                 set_shaders(dev);
 806         }
 807         vb = r600_nomm_get_vb_ptr(dev);
 808
 809         sx2 = sx + w;
 810         sy2 = sy + h;
 811         dx2 = dx + w;
 812         dy2 = dy + h;
 813
 814         vb[0] = int2float(dx);
 815         vb[1] = int2float(dy);
 816         vb[2] = int2float(sx);
 817         vb[3] = int2float(sy);
 818
 819         vb[4] = int2float(dx);
 820         vb[5] = int2float(dy2);
 821         vb[6] = int2float(sx);
 822         vb[7] = int2float(sy2);
 823
 824         vb[8] = int2float(dx2);
 825         vb[9] = int2float(dy2);
 826         vb[10] = int2float(sx2);
 827         vb[11] = int2float(sy2);
 828
 829         switch(cpp) {
 830         case 4:
 831                 cb_format = COLOR_8_8_8_8;
 832                 tex_format = FMT_8_8_8_8;
 833                 break;
 834         case 2:
 835                 cb_format = COLOR_5_6_5;
 836                 tex_format = FMT_5_6_5;
 837                 break;
 838         default:
 839                 cb_format = COLOR_8;
 840                 tex_format = FMT_8;
 841                 break;
 842         }
 843
 844         /* src */
 845         set_tex_resource(dev_priv, tex_format,
 846                          src_pitch / cpp,
 847                          sy2, src_pitch / cpp,
 848                          src_gpu_addr);
 849
 850         cp_set_surface_sync(dev_priv,
 851                             R600_TC_ACTION_ENA, src_pitch * sy2, src_gpu_addr);
 852
 853         /* dst */
 854         set_render_target(dev_priv, cb_format,
 855                           dst_pitch / cpp, dy2,
 856                           dst_gpu_addr);
 857
 858         /* scissors */
 859         set_scissors(dev_priv, dx, dy, dx2, dy2);
 860
 861         /* Vertex buffer setup */
 862         vb_addr = dev_priv->gart_buffers_offset +
 863                 dev_priv->blit_vb->offset +
 864                 dev_priv->blit_vb->used;
 865         set_vtx_resource(dev_priv, vb_addr);
 866
 867         /* draw */
 868         draw_auto(dev_priv);
 869
 870         cp_set_surface_sync(dev_priv,
 871                             R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
 872                             dst_pitch * dy2, dst_gpu_addr);
 873
 874         dev_priv->blit_vb->used += 12 * 4;
 875 }