1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 /* $FreeBSD: src/contrib/binutils/gas/config/tc-i386.c,v 1.4.2.4 2002/09/01 23:44:03 obrien Exp $ */
27 /* Intel 80386 machine specific gas.
28 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
29 x86_64 support by Jan Hubicka (jh@suse.cz)
30 Bugs & suggestions are completely welcome. This is free software.
31 Please help us make it better. */
34 #include "safe-ctype.h"
36 #include "dwarf2dbg.h"
37 #include "opcode/i386.h"
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef INFER_ADDR_PREFIX
44 #define INFER_ADDR_PREFIX 1
47 #ifndef SCALE1_WHEN_NO_INDEX
48 /* Specifying a scale factor besides 1 when there is no index is
49 futile. eg. `mov (%ebx,2),%al' does exactly the same as
50 `mov (%ebx),%al'. To slavishly follow what the programmer
51 specified, set SCALE1_WHEN_NO_INDEX to 0. */
52 #define SCALE1_WHEN_NO_INDEX 1
56 #define RELOC_ENUM enum bfd_reloc_code_real
58 #define RELOC_ENUM int
62 #define DEFAULT_ARCH "i386"
67 #define INLINE __inline__
73 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
74 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
75 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
76 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
77 static INLINE int fits_in_signed_word PARAMS ((offsetT));
78 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
79 static INLINE int fits_in_signed_long PARAMS ((offsetT));
80 static int smallest_imm_type PARAMS ((offsetT));
81 static offsetT offset_in_range PARAMS ((offsetT, int));
82 static int add_prefix PARAMS ((unsigned int));
83 static void set_code_flag PARAMS ((int));
84 static void set_16bit_gcc_code_flag PARAMS ((int));
85 static void set_intel_syntax PARAMS ((int));
86 static void set_cpu_arch PARAMS ((int));
87 static char *output_invalid PARAMS ((int c));
88 static int i386_operand PARAMS ((char *operand_string));
89 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
90 static const reg_entry *parse_register PARAMS ((char *reg_string,
92 static char *parse_insn PARAMS ((char *, char *));
93 static char *parse_operands PARAMS ((char *, const char *));
94 static void swap_operands PARAMS ((void));
95 static void optimize_imm PARAMS ((void));
96 static void optimize_disp PARAMS ((void));
97 static int match_template PARAMS ((void));
98 static int check_string PARAMS ((void));
99 static int process_suffix PARAMS ((void));
100 static int check_byte_reg PARAMS ((void));
101 static int check_long_reg PARAMS ((void));
102 static int check_qword_reg PARAMS ((void));
103 static int check_word_reg PARAMS ((void));
104 static int finalize_imm PARAMS ((void));
105 static int process_operands PARAMS ((void));
106 static const seg_entry *build_modrm_byte PARAMS ((void));
107 static void output_insn PARAMS ((void));
108 static void output_branch PARAMS ((void));
109 static void output_jump PARAMS ((void));
110 static void output_interseg_jump PARAMS ((void));
111 static void output_imm PARAMS ((void));
112 static void output_disp PARAMS ((void));
114 static void s_bss PARAMS ((int));
117 static const char *default_arch = DEFAULT_ARCH;
119 /* 'md_assemble ()' gathers together information and puts it into a
126 const reg_entry *regs;
131 /* TM holds the template for the insn were currently assembling. */
134 /* SUFFIX holds the instruction mnemonic suffix if given.
135 (e.g. 'l' for 'movl') */
138 /* OPERANDS gives the number of given operands. */
139 unsigned int operands;
141 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
142 of given register, displacement, memory operands and immediate
144 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
146 /* TYPES [i] is the type (see above #defines) which tells us how to
147 use OP[i] for the corresponding operand. */
148 unsigned int types[MAX_OPERANDS];
150 /* Displacement expression, immediate expression, or register for each
152 union i386_op op[MAX_OPERANDS];
154 /* Flags for operands. */
155 unsigned int flags[MAX_OPERANDS];
156 #define Operand_PCrel 1
158 /* Relocation type for operand */
159 RELOC_ENUM reloc[MAX_OPERANDS];
161 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
162 the base index byte below. */
163 const reg_entry *base_reg;
164 const reg_entry *index_reg;
165 unsigned int log2_scale_factor;
167 /* SEG gives the seg_entries of this insn. They are zero unless
168 explicit segment overrides are given. */
169 const seg_entry *seg[2];
171 /* PREFIX holds all the given prefix opcodes (usually null).
172 PREFIXES is the number of prefix opcodes. */
173 unsigned int prefixes;
174 unsigned char prefix[MAX_PREFIXES];
176 /* RM and SIB are the modrm byte and the sib byte where the
177 addressing modes of this insn are encoded. */
184 typedef struct _i386_insn i386_insn;
186 /* List of chars besides those in app.c:symbol_chars that can start an
187 operand. Used to prevent the scrubber eating vital white-space. */
189 const char extra_symbol_chars[] = "*%-(@[";
191 const char extra_symbol_chars[] = "*%-([";
194 #if (defined (TE_I386AIX) \
195 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
196 && !defined (TE_LINUX) \
197 && !defined (TE_FreeBSD) \
198 && !defined (TE_NetBSD)))
199 /* This array holds the chars that always start a comment. If the
200 pre-processor is disabled, these aren't very useful. */
201 const char comment_chars[] = "#/";
202 #define PREFIX_SEPARATOR '\\'
204 /* This array holds the chars that only start a comment at the beginning of
205 a line. If the line seems to have the form '# 123 filename'
206 .line and .file directives will appear in the pre-processed output.
207 Note that input_file.c hand checks for '#' at the beginning of the
208 first line of the input file. This is because the compiler outputs
209 #NO_APP at the beginning of its output.
210 Also note that comments started like this one will always work if
211 '/' isn't otherwise defined. */
212 const char line_comment_chars[] = "";
215 /* Putting '/' here makes it impossible to use the divide operator.
216 However, we need it for compatibility with SVR4 systems. */
217 const char comment_chars[] = "#";
218 #define PREFIX_SEPARATOR '/'
220 const char line_comment_chars[] = "/";
223 const char line_separator_chars[] = ";";
225 /* Chars that can be used to separate mant from exp in floating point
227 const char EXP_CHARS[] = "eE";
229 /* Chars that mean this number is a floating point constant
232 const char FLT_CHARS[] = "fFdDxX";
234 /* Tables for lexical analysis. */
235 static char mnemonic_chars[256];
236 static char register_chars[256];
237 static char operand_chars[256];
238 static char identifier_chars[256];
239 static char digit_chars[256];
241 /* Lexical macros. */
242 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
243 #define is_operand_char(x) (operand_chars[(unsigned char) x])
244 #define is_register_char(x) (register_chars[(unsigned char) x])
245 #define is_space_char(x) ((x) == ' ')
246 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
247 #define is_digit_char(x) (digit_chars[(unsigned char) x])
249 /* All non-digit non-letter charcters that may occur in an operand. */
250 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
252 /* md_assemble() always leaves the strings it's passed unaltered. To
253 effect this we maintain a stack of saved characters that we've smashed
254 with '\0's (indicating end of strings for various sub-fields of the
255 assembler instruction). */
256 static char save_stack[32];
257 static char *save_stack_p;
258 #define END_STRING_AND_SAVE(s) \
259 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
260 #define RESTORE_END_STRING(s) \
261 do { *(s) = *--save_stack_p; } while (0)
263 /* The instruction we're assembling. */
266 /* Possible templates for current insn. */
267 static const templates *current_templates;
269 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
270 static expressionS disp_expressions[2], im_expressions[2];
272 /* Current operand we are working on. */
273 static int this_operand;
275 /* We support four different modes. FLAG_CODE variable is used to distinguish
282 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
284 static enum flag_code flag_code;
285 static int use_rela_relocations = 0;
287 /* The names used to print error messages. */
288 static const char *flag_code_names[] =
295 /* 1 for intel syntax,
297 static int intel_syntax = 0;
299 /* 1 if register prefix % not required. */
300 static int allow_naked_reg = 0;
302 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
303 leave, push, and pop instructions so that gcc has the same stack
304 frame as in 32 bit mode. */
305 static char stackop_size = '\0';
307 /* Non-zero to quieten some warnings. */
308 static int quiet_warnings = 0;
311 static const char *cpu_arch_name = NULL;
313 /* CPU feature flags. */
314 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
316 /* If set, conditional jumps are not automatically promoted to handle
317 larger than a byte offset. */
318 static unsigned int no_cond_jump_promotion = 0;
320 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
323 /* Interface to relax_segment.
324 There are 3 major relax states for 386 jump insns because the
325 different types of jumps add different sizes to frags when we're
326 figuring out what sort of jump to choose to reach a given label. */
329 #define UNCOND_JUMP 0
331 #define COND_JUMP86 2
336 #define SMALL16 (SMALL | CODE16)
338 #define BIG16 (BIG | CODE16)
342 #define INLINE __inline__
348 #define ENCODE_RELAX_STATE(type, size) \
349 ((relax_substateT) (((type) << 2) | (size)))
350 #define TYPE_FROM_RELAX_STATE(s) \
352 #define DISP_SIZE_FROM_RELAX_STATE(s) \
353 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
355 /* This table is used by relax_frag to promote short jumps to long
356 ones where necessary. SMALL (short) jumps may be promoted to BIG
357 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
358 don't allow a short jump in a 32 bit code segment to be promoted to
359 a 16 bit offset jump because it's slower (requires data size
360 prefix), and doesn't work, unless the destination is in the bottom
361 64k of the code segment (The top 16 bits of eip are zeroed). */
363 const relax_typeS md_relax_table[] =
366 1) most positive reach of this state,
367 2) most negative reach of this state,
368 3) how many bytes this mode will have in the variable part of the frag
369 4) which index into the table to try if we can't fit into this one. */
371 /* UNCOND_JUMP states. */
372 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
373 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
374 /* dword jmp adds 4 bytes to frag:
375 0 extra opcode bytes, 4 displacement bytes. */
377 /* word jmp adds 2 byte2 to frag:
378 0 extra opcode bytes, 2 displacement bytes. */
381 /* COND_JUMP states. */
382 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
383 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
384 /* dword conditionals adds 5 bytes to frag:
385 1 extra opcode byte, 4 displacement bytes. */
387 /* word conditionals add 3 bytes to frag:
388 1 extra opcode byte, 2 displacement bytes. */
391 /* COND_JUMP86 states. */
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
394 /* dword conditionals adds 5 bytes to frag:
395 1 extra opcode byte, 4 displacement bytes. */
397 /* word conditionals add 4 bytes to frag:
398 1 displacement byte and a 3 byte long branch insn. */
402 static const arch_entry cpu_arch[] = {
404 {"i186", Cpu086|Cpu186 },
405 {"i286", Cpu086|Cpu186|Cpu286 },
406 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
407 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
408 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
409 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
410 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
411 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
412 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
413 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
414 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
415 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
419 const pseudo_typeS md_pseudo_table[] =
421 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
422 {"align", s_align_bytes, 0},
424 {"align", s_align_ptwo, 0},
426 {"arch", set_cpu_arch, 0},
430 {"ffloat", float_cons, 'f'},
431 {"dfloat", float_cons, 'd'},
432 {"tfloat", float_cons, 'x'},
434 {"noopt", s_ignore, 0},
435 {"optim", s_ignore, 0},
436 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
437 {"code16", set_code_flag, CODE_16BIT},
438 {"code32", set_code_flag, CODE_32BIT},
439 {"code64", set_code_flag, CODE_64BIT},
440 {"intel_syntax", set_intel_syntax, 1},
441 {"att_syntax", set_intel_syntax, 0},
442 {"file", dwarf2_directive_file, 0},
443 {"loc", dwarf2_directive_loc, 0},
447 /* For interface with expression (). */
448 extern char *input_line_pointer;
450 /* Hash table for instruction mnemonic lookup. */
451 static struct hash_control *op_hash;
453 /* Hash table for register lookup. */
454 static struct hash_control *reg_hash;
457 i386_align_code (fragP, count)
461 /* Various efficient no-op patterns for aligning code labels.
462 Note: Don't try to assemble the instructions in the comments.
463 0L and 0w are not legal. */
464 static const char f32_1[] =
466 static const char f32_2[] =
467 {0x89,0xf6}; /* movl %esi,%esi */
468 static const char f32_3[] =
469 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
470 static const char f32_4[] =
471 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
472 static const char f32_5[] =
474 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
475 static const char f32_6[] =
476 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
477 static const char f32_7[] =
478 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
479 static const char f32_8[] =
481 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
482 static const char f32_9[] =
483 {0x89,0xf6, /* movl %esi,%esi */
484 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
485 static const char f32_10[] =
486 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
487 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
488 static const char f32_11[] =
489 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
490 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
491 static const char f32_12[] =
492 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
493 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
494 static const char f32_13[] =
495 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
496 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
497 static const char f32_14[] =
498 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
499 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
500 static const char f32_15[] =
501 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
502 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
503 static const char f16_3[] =
504 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
505 static const char f16_4[] =
506 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
507 static const char f16_5[] =
509 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
510 static const char f16_6[] =
511 {0x89,0xf6, /* mov %si,%si */
512 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
513 static const char f16_7[] =
514 {0x8d,0x74,0x00, /* lea 0(%si),%si */
515 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
516 static const char f16_8[] =
517 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
518 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
519 static const char *const f32_patt[] = {
520 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
521 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
523 static const char *const f16_patt[] = {
524 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
525 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
528 /* ??? We can't use these fillers for x86_64, since they often kills the
529 upper halves. Solve later. */
530 if (flag_code == CODE_64BIT)
533 if (count > 0 && count <= 15)
535 if (flag_code == CODE_16BIT)
537 memcpy (fragP->fr_literal + fragP->fr_fix,
538 f16_patt[count - 1], count);
540 /* Adjust jump offset. */
541 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
544 memcpy (fragP->fr_literal + fragP->fr_fix,
545 f32_patt[count - 1], count);
546 fragP->fr_var = count;
550 static INLINE unsigned int
551 mode_from_disp_size (t)
554 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
558 fits_in_signed_byte (num)
561 return (num >= -128) && (num <= 127);
565 fits_in_unsigned_byte (num)
568 return (num & 0xff) == num;
572 fits_in_unsigned_word (num)
575 return (num & 0xffff) == num;
579 fits_in_signed_word (num)
582 return (-32768 <= num) && (num <= 32767);
585 fits_in_signed_long (num)
586 offsetT num ATTRIBUTE_UNUSED;
591 return (!(((offsetT) -1 << 31) & num)
592 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
594 } /* fits_in_signed_long() */
596 fits_in_unsigned_long (num)
597 offsetT num ATTRIBUTE_UNUSED;
602 return (num & (((offsetT) 2 << 31) - 1)) == num;
604 } /* fits_in_unsigned_long() */
607 smallest_imm_type (num)
610 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
612 /* This code is disabled on the 486 because all the Imm1 forms
613 in the opcode table are slower on the i486. They're the
614 versions with the implicitly specified single-position
615 displacement, which has another syntax if you really want to
618 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
620 return (fits_in_signed_byte (num)
621 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
622 : fits_in_unsigned_byte (num)
623 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
624 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
625 ? (Imm16 | Imm32 | Imm32S | Imm64)
626 : fits_in_signed_long (num)
627 ? (Imm32 | Imm32S | Imm64)
628 : fits_in_unsigned_long (num)
634 offset_in_range (val, size)
642 case 1: mask = ((addressT) 1 << 8) - 1; break;
643 case 2: mask = ((addressT) 1 << 16) - 1; break;
644 case 4: mask = ((addressT) 2 << 31) - 1; break;
646 case 8: mask = ((addressT) 2 << 63) - 1; break;
651 /* If BFD64, sign extend val. */
652 if (!use_rela_relocations)
653 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
654 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
656 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
658 char buf1[40], buf2[40];
660 sprint_value (buf1, val);
661 sprint_value (buf2, val & mask);
662 as_warn (_("%s shortened to %s"), buf1, buf2);
667 /* Returns 0 if attempting to add a prefix where one from the same
668 class already exists, 1 if non rep/repne added, 2 if rep/repne
677 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
678 && flag_code == CODE_64BIT)
686 case CS_PREFIX_OPCODE:
687 case DS_PREFIX_OPCODE:
688 case ES_PREFIX_OPCODE:
689 case FS_PREFIX_OPCODE:
690 case GS_PREFIX_OPCODE:
691 case SS_PREFIX_OPCODE:
695 case REPNE_PREFIX_OPCODE:
696 case REPE_PREFIX_OPCODE:
699 case LOCK_PREFIX_OPCODE:
707 case ADDR_PREFIX_OPCODE:
711 case DATA_PREFIX_OPCODE:
716 if (i.prefix[q] != 0)
718 as_bad (_("same type of prefix used twice"));
723 i.prefix[q] = prefix;
728 set_code_flag (value)
732 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
733 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
734 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
736 as_bad (_("64bit mode not supported on this CPU."));
738 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
740 as_bad (_("32bit mode not supported on this CPU."));
746 set_16bit_gcc_code_flag (new_code_flag)
749 flag_code = new_code_flag;
750 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
751 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
756 set_intel_syntax (syntax_flag)
759 /* Find out if register prefixing is specified. */
760 int ask_naked_reg = 0;
763 if (!is_end_of_line[(unsigned char) *input_line_pointer])
765 char *string = input_line_pointer;
766 int e = get_symbol_end ();
768 if (strcmp (string, "prefix") == 0)
770 else if (strcmp (string, "noprefix") == 0)
773 as_bad (_("bad argument to syntax directive."));
774 *input_line_pointer = e;
776 demand_empty_rest_of_line ();
778 intel_syntax = syntax_flag;
780 if (ask_naked_reg == 0)
783 allow_naked_reg = (intel_syntax
784 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
786 /* Conservative default. */
791 allow_naked_reg = (ask_naked_reg < 0);
796 int dummy ATTRIBUTE_UNUSED;
800 if (!is_end_of_line[(unsigned char) *input_line_pointer])
802 char *string = input_line_pointer;
803 int e = get_symbol_end ();
806 for (i = 0; cpu_arch[i].name; i++)
808 if (strcmp (string, cpu_arch[i].name) == 0)
810 cpu_arch_name = cpu_arch[i].name;
811 cpu_arch_flags = (cpu_arch[i].flags
812 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
816 if (!cpu_arch[i].name)
817 as_bad (_("no such architecture: `%s'"), string);
819 *input_line_pointer = e;
822 as_bad (_("missing cpu architecture"));
824 no_cond_jump_promotion = 0;
825 if (*input_line_pointer == ','
826 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
828 char *string = ++input_line_pointer;
829 int e = get_symbol_end ();
831 if (strcmp (string, "nojumps") == 0)
832 no_cond_jump_promotion = 1;
833 else if (strcmp (string, "jumps") == 0)
836 as_bad (_("no such architecture modifier: `%s'"), string);
838 *input_line_pointer = e;
841 demand_empty_rest_of_line ();
848 if (!strcmp (default_arch, "x86_64"))
849 return bfd_mach_x86_64;
850 else if (!strcmp (default_arch, "i386"))
851 return bfd_mach_i386_i386;
853 as_fatal (_("Unknown architecture"));
860 const char *hash_err;
862 /* Initialize op_hash hash table. */
863 op_hash = hash_new ();
866 const template *optab;
867 templates *core_optab;
869 /* Setup for loop. */
871 core_optab = (templates *) xmalloc (sizeof (templates));
872 core_optab->start = optab;
877 if (optab->name == NULL
878 || strcmp (optab->name, (optab - 1)->name) != 0)
880 /* different name --> ship out current template list;
881 add to hash table; & begin anew. */
882 core_optab->end = optab;
883 hash_err = hash_insert (op_hash,
888 as_fatal (_("Internal Error: Can't hash %s: %s"),
892 if (optab->name == NULL)
894 core_optab = (templates *) xmalloc (sizeof (templates));
895 core_optab->start = optab;
900 /* Initialize reg_hash hash table. */
901 reg_hash = hash_new ();
903 const reg_entry *regtab;
905 for (regtab = i386_regtab;
906 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
909 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
911 as_fatal (_("Internal Error: Can't hash %s: %s"),
917 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
922 for (c = 0; c < 256; c++)
927 mnemonic_chars[c] = c;
928 register_chars[c] = c;
929 operand_chars[c] = c;
931 else if (ISLOWER (c))
933 mnemonic_chars[c] = c;
934 register_chars[c] = c;
935 operand_chars[c] = c;
937 else if (ISUPPER (c))
939 mnemonic_chars[c] = TOLOWER (c);
940 register_chars[c] = mnemonic_chars[c];
941 operand_chars[c] = c;
944 if (ISALPHA (c) || ISDIGIT (c))
945 identifier_chars[c] = c;
948 identifier_chars[c] = c;
949 operand_chars[c] = c;
954 identifier_chars['@'] = '@';
956 digit_chars['-'] = '-';
957 identifier_chars['_'] = '_';
958 identifier_chars['.'] = '.';
960 for (p = operand_special_chars; *p != '\0'; p++)
961 operand_chars[(unsigned char) *p] = *p;
964 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
965 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
967 record_alignment (text_section, 2);
968 record_alignment (data_section, 2);
969 record_alignment (bss_section, 2);
975 i386_print_statistics (file)
978 hash_print_statistics (file, "i386 opcode", op_hash);
979 hash_print_statistics (file, "i386 register", reg_hash);
984 /* Debugging routines for md_assemble. */
985 static void pi PARAMS ((char *, i386_insn *));
986 static void pte PARAMS ((template *));
987 static void pt PARAMS ((unsigned int));
988 static void pe PARAMS ((expressionS *));
989 static void ps PARAMS ((symbolS *));
998 fprintf (stdout, "%s: template ", line);
1000 fprintf (stdout, " address: base %s index %s scale %x\n",
1001 x->base_reg ? x->base_reg->reg_name : "none",
1002 x->index_reg ? x->index_reg->reg_name : "none",
1003 x->log2_scale_factor);
1004 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1005 x->rm.mode, x->rm.reg, x->rm.regmem);
1006 fprintf (stdout, " sib: base %x index %x scale %x\n",
1007 x->sib.base, x->sib.index, x->sib.scale);
1008 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1009 (x->rex & REX_MODE64) != 0,
1010 (x->rex & REX_EXTX) != 0,
1011 (x->rex & REX_EXTY) != 0,
1012 (x->rex & REX_EXTZ) != 0);
1013 for (i = 0; i < x->operands; i++)
1015 fprintf (stdout, " #%d: ", i + 1);
1017 fprintf (stdout, "\n");
1019 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1020 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1021 if (x->types[i] & Imm)
1023 if (x->types[i] & Disp)
1024 pe (x->op[i].disps);
1033 fprintf (stdout, " %d operands ", t->operands);
1034 fprintf (stdout, "opcode %x ", t->base_opcode);
1035 if (t->extension_opcode != None)
1036 fprintf (stdout, "ext %x ", t->extension_opcode);
1037 if (t->opcode_modifier & D)
1038 fprintf (stdout, "D");
1039 if (t->opcode_modifier & W)
1040 fprintf (stdout, "W");
1041 fprintf (stdout, "\n");
1042 for (i = 0; i < t->operands; i++)
1044 fprintf (stdout, " #%d type ", i + 1);
1045 pt (t->operand_types[i]);
1046 fprintf (stdout, "\n");
1054 fprintf (stdout, " operation %d\n", e->X_op);
1055 fprintf (stdout, " add_number %ld (%lx)\n",
1056 (long) e->X_add_number, (long) e->X_add_number);
1057 if (e->X_add_symbol)
1059 fprintf (stdout, " add_symbol ");
1060 ps (e->X_add_symbol);
1061 fprintf (stdout, "\n");
1065 fprintf (stdout, " op_symbol ");
1066 ps (e->X_op_symbol);
1067 fprintf (stdout, "\n");
1075 fprintf (stdout, "%s type %s%s",
1077 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1078 segment_name (S_GET_SEGMENT (s)));
1087 static const type_names[] =
1100 { BaseIndex, "BaseIndex" },
1104 { Disp32S, "d32s" },
1106 { InOutPortReg, "InOutPortReg" },
1107 { ShiftCount, "ShiftCount" },
1108 { Control, "control reg" },
1109 { Test, "test reg" },
1110 { Debug, "debug reg" },
1111 { FloatReg, "FReg" },
1112 { FloatAcc, "FAcc" },
1116 { JumpAbsolute, "Jump Absolute" },
1127 const struct type_name *ty;
1129 for (ty = type_names; ty->mask; ty++)
1131 fprintf (stdout, "%s, ", ty->tname);
1135 #endif /* DEBUG386 */
1138 tc_i386_force_relocation (fixp)
1141 #ifdef BFD_ASSEMBLER
1142 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1143 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1148 return fixp->fx_r_type == 7;
1152 #ifdef BFD_ASSEMBLER
1153 static bfd_reloc_code_real_type reloc
1154 PARAMS ((int, int, int, bfd_reloc_code_real_type));
1156 static bfd_reloc_code_real_type
1157 reloc (size, pcrel, sign, other)
1161 bfd_reloc_code_real_type other;
1163 if (other != NO_RELOC)
1169 as_bad (_("There are no unsigned pc-relative relocations"));
1172 case 1: return BFD_RELOC_8_PCREL;
1173 case 2: return BFD_RELOC_16_PCREL;
1174 case 4: return BFD_RELOC_32_PCREL;
1176 as_bad (_("can not do %d byte pc-relative relocation"), size);
1183 case 4: return BFD_RELOC_X86_64_32S;
1188 case 1: return BFD_RELOC_8;
1189 case 2: return BFD_RELOC_16;
1190 case 4: return BFD_RELOC_32;
1191 case 8: return BFD_RELOC_64;
1193 as_bad (_("can not do %s %d byte relocation"),
1194 sign ? "signed" : "unsigned", size);
1198 return BFD_RELOC_NONE;
1201 /* Here we decide which fixups can be adjusted to make them relative to
1202 the beginning of the section instead of the symbol. Basically we need
1203 to make sure that the dynamic relocations are done correctly, so in
1204 some cases we force the original symbol to be used. */
1207 tc_i386_fix_adjustable (fixP)
1210 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1211 /* Prevent all adjustments to global symbols, or else dynamic
1212 linking will not work correctly. */
1213 if (S_IS_EXTERNAL (fixP->fx_addsy)
1214 || S_IS_WEAK (fixP->fx_addsy)
1215 /* Don't adjust pc-relative references to merge sections in 64-bit
1217 || (use_rela_relocations
1218 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1222 /* adjust_reloc_syms doesn't know about the GOT. */
1223 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1224 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1225 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1226 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1227 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1228 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1229 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1230 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1235 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1236 #define BFD_RELOC_16 0
1237 #define BFD_RELOC_32 0
1238 #define BFD_RELOC_16_PCREL 0
1239 #define BFD_RELOC_32_PCREL 0
1240 #define BFD_RELOC_386_PLT32 0
1241 #define BFD_RELOC_386_GOT32 0
1242 #define BFD_RELOC_386_GOTOFF 0
1243 #define BFD_RELOC_X86_64_PLT32 0
1244 #define BFD_RELOC_X86_64_GOT32 0
1245 #define BFD_RELOC_X86_64_GOTPCREL 0
1248 static int intel_float_operand PARAMS ((const char *mnemonic));
1251 intel_float_operand (mnemonic)
1252 const char *mnemonic;
1254 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
1257 if (mnemonic[0] == 'f')
1263 /* This is the guts of the machine-dependent assembler. LINE points to a
1264 machine dependent instruction. This function is supposed to emit
1265 the frags/bytes it assembles to. */
1272 char mnemonic[MAX_MNEM_SIZE];
1274 /* Initialize globals. */
1275 memset (&i, '\0', sizeof (i));
1276 for (j = 0; j < MAX_OPERANDS; j++)
1277 i.reloc[j] = NO_RELOC;
1278 memset (disp_expressions, '\0', sizeof (disp_expressions));
1279 memset (im_expressions, '\0', sizeof (im_expressions));
1280 save_stack_p = save_stack;
1282 /* First parse an instruction mnemonic & call i386_operand for the operands.
1283 We assume that the scrubber has arranged it so that line[0] is the valid
1284 start of a (possibly prefixed) mnemonic. */
1286 line = parse_insn (line, mnemonic);
1290 line = parse_operands (line, mnemonic);
1294 /* Now we've parsed the mnemonic into a set of templates, and have the
1295 operands at hand. */
1297 /* All intel opcodes have reversed operands except for "bound" and
1298 "enter". We also don't reverse intersegment "jmp" and "call"
1299 instructions with 2 immediate operands so that the immediate segment
1300 precedes the offset, as it does when in AT&T mode. "enter" and the
1301 intersegment "jmp" and "call" instructions are the only ones that
1302 have two immediate operands. */
1303 if (intel_syntax && i.operands > 1
1304 && (strcmp (mnemonic, "bound") != 0)
1305 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1311 if (i.disp_operands)
1314 /* Next, we find a template that matches the given insn,
1315 making sure the overlap of the given operands types is consistent
1316 with the template operand types. */
1318 if (!match_template ())
1321 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1324 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1325 i.tm.base_opcode ^= FloatR;
1327 if (i.tm.opcode_modifier & FWait)
1328 if (!add_prefix (FWAIT_OPCODE))
1331 /* Check string instruction segment overrides. */
1332 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1334 if (!check_string ())
1338 if (!process_suffix ())
1341 /* Make still unresolved immediate matches conform to size of immediate
1342 given in i.suffix. */
1343 if (!finalize_imm ())
1346 if (i.types[0] & Imm1)
1347 i.imm_operands = 0; /* kludge for shift insns. */
1348 if (i.types[0] & ImplicitRegister)
1350 if (i.types[1] & ImplicitRegister)
1352 if (i.types[2] & ImplicitRegister)
1355 if (i.tm.opcode_modifier & ImmExt)
1357 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1358 opcode suffix which is coded in the same place as an 8-bit
1359 immediate field would be. Here we fake an 8-bit immediate
1360 operand from the opcode suffix stored in tm.extension_opcode. */
1364 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1366 exp = &im_expressions[i.imm_operands++];
1367 i.op[i.operands].imms = exp;
1368 i.types[i.operands++] = Imm8;
1369 exp->X_op = O_constant;
1370 exp->X_add_number = i.tm.extension_opcode;
1371 i.tm.extension_opcode = None;
1374 /* For insns with operands there are more diddles to do to the opcode. */
1377 if (!process_operands ())
1380 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1382 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1383 as_warn (_("translating to `%sp'"), i.tm.name);
1386 /* Handle conversion of 'int $3' --> special int3 insn. */
1387 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1389 i.tm.base_opcode = INT3_OPCODE;
1393 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1394 && i.op[0].disps->X_op == O_constant)
1396 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1397 the absolute address given by the constant. Since ix86 jumps and
1398 calls are pc relative, we need to generate a reloc. */
1399 i.op[0].disps->X_add_symbol = &abs_symbol;
1400 i.op[0].disps->X_op = O_symbol;
1403 if ((i.tm.opcode_modifier & Rex64) != 0)
1404 i.rex |= REX_MODE64;
1406 /* For 8 bit registers we need an empty rex prefix. Also if the
1407 instruction already has a prefix, we need to convert old
1408 registers to new ones. */
1410 if (((i.types[0] & Reg8) != 0
1411 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1412 || ((i.types[1] & Reg8) != 0
1413 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1414 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1419 i.rex |= REX_OPCODE;
1420 for (x = 0; x < 2; x++)
1422 /* Look for 8 bit operand that uses old registers. */
1423 if ((i.types[x] & Reg8) != 0
1424 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1426 /* In case it is "hi" register, give up. */
1427 if (i.op[x].regs->reg_num > 3)
1428 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1429 i.op[x].regs->reg_name);
1431 /* Otherwise it is equivalent to the extended register.
1432 Since the encoding doesn't change this is merely
1433 cosmetic cleanup for debug output. */
1435 i.op[x].regs = i.op[x].regs + 8;
1441 add_prefix (REX_OPCODE | i.rex);
1443 /* We are ready to output the insn. */
1448 parse_insn (line, mnemonic)
1453 char *token_start = l;
1456 /* Non-zero if we found a prefix only acceptable with string insns. */
1457 const char *expecting_string_instruction = NULL;
1462 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1465 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1467 as_bad (_("no such instruction: `%s'"), token_start);
1472 if (!is_space_char (*l)
1473 && *l != END_OF_INSN
1474 && *l != PREFIX_SEPARATOR
1477 as_bad (_("invalid character %s in mnemonic"),
1478 output_invalid (*l));
1481 if (token_start == l)
1483 if (*l == PREFIX_SEPARATOR)
1484 as_bad (_("expecting prefix; got nothing"));
1486 as_bad (_("expecting mnemonic; got nothing"));
1490 /* Look up instruction (or prefix) via hash table. */
1491 current_templates = hash_find (op_hash, mnemonic);
1493 if (*l != END_OF_INSN
1494 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1495 && current_templates
1496 && (current_templates->start->opcode_modifier & IsPrefix))
1498 /* If we are in 16-bit mode, do not allow addr16 or data16.
1499 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1500 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1501 && flag_code != CODE_64BIT
1502 && (((current_templates->start->opcode_modifier & Size32) != 0)
1503 ^ (flag_code == CODE_16BIT)))
1505 as_bad (_("redundant %s prefix"),
1506 current_templates->start->name);
1509 /* Add prefix, checking for repeated prefixes. */
1510 switch (add_prefix (current_templates->start->base_opcode))
1515 expecting_string_instruction = current_templates->start->name;
1518 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1525 if (!current_templates)
1527 /* See if we can get a match by trimming off a suffix. */
1530 case WORD_MNEM_SUFFIX:
1531 case BYTE_MNEM_SUFFIX:
1532 case QWORD_MNEM_SUFFIX:
1533 i.suffix = mnem_p[-1];
1535 current_templates = hash_find (op_hash, mnemonic);
1537 case SHORT_MNEM_SUFFIX:
1538 case LONG_MNEM_SUFFIX:
1541 i.suffix = mnem_p[-1];
1543 current_templates = hash_find (op_hash, mnemonic);
1551 if (intel_float_operand (mnemonic))
1552 i.suffix = SHORT_MNEM_SUFFIX;
1554 i.suffix = LONG_MNEM_SUFFIX;
1556 current_templates = hash_find (op_hash, mnemonic);
1560 if (!current_templates)
1562 as_bad (_("no such instruction: `%s'"), token_start);
1567 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1569 /* Check for a branch hint. We allow ",pt" and ",pn" for
1570 predict taken and predict not taken respectively.
1571 I'm not sure that branch hints actually do anything on loop
1572 and jcxz insns (JumpByte) for current Pentium4 chips. They
1573 may work in the future and it doesn't hurt to accept them
1575 if (l[0] == ',' && l[1] == 'p')
1579 if (!add_prefix (DS_PREFIX_OPCODE))
1583 else if (l[2] == 'n')
1585 if (!add_prefix (CS_PREFIX_OPCODE))
1591 /* Any other comma loses. */
1594 as_bad (_("invalid character %s in mnemonic"),
1595 output_invalid (*l));
1599 /* Check if instruction is supported on specified architecture. */
1600 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1601 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1603 as_warn (_("`%s' is not supported on `%s'"),
1604 current_templates->start->name, cpu_arch_name);
1606 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1608 as_warn (_("use .code16 to ensure correct addressing mode"));
1611 /* Check for rep/repne without a string instruction. */
1612 if (expecting_string_instruction
1613 && !(current_templates->start->opcode_modifier & IsString))
1615 as_bad (_("expecting string instruction after `%s'"),
1616 expecting_string_instruction);
1624 parse_operands (l, mnemonic)
1626 const char *mnemonic;
1630 /* 1 if operand is pending after ','. */
1631 unsigned int expecting_operand = 0;
1633 /* Non-zero if operand parens not balanced. */
1634 unsigned int paren_not_balanced;
1636 while (*l != END_OF_INSN)
1638 /* Skip optional white space before operand. */
1639 if (is_space_char (*l))
1641 if (!is_operand_char (*l) && *l != END_OF_INSN)
1643 as_bad (_("invalid character %s before operand %d"),
1644 output_invalid (*l),
1648 token_start = l; /* after white space */
1649 paren_not_balanced = 0;
1650 while (paren_not_balanced || *l != ',')
1652 if (*l == END_OF_INSN)
1654 if (paren_not_balanced)
1657 as_bad (_("unbalanced parenthesis in operand %d."),
1660 as_bad (_("unbalanced brackets in operand %d."),
1665 break; /* we are done */
1667 else if (!is_operand_char (*l) && !is_space_char (*l))
1669 as_bad (_("invalid character %s in operand %d"),
1670 output_invalid (*l),
1677 ++paren_not_balanced;
1679 --paren_not_balanced;
1684 ++paren_not_balanced;
1686 --paren_not_balanced;
1690 if (l != token_start)
1691 { /* Yes, we've read in another operand. */
1692 unsigned int operand_ok;
1693 this_operand = i.operands++;
1694 if (i.operands > MAX_OPERANDS)
1696 as_bad (_("spurious operands; (%d operands/instruction max)"),
1700 /* Now parse operand adding info to 'i' as we go along. */
1701 END_STRING_AND_SAVE (l);
1705 i386_intel_operand (token_start,
1706 intel_float_operand (mnemonic));
1708 operand_ok = i386_operand (token_start);
1710 RESTORE_END_STRING (l);
1716 if (expecting_operand)
1718 expecting_operand_after_comma:
1719 as_bad (_("expecting operand after ','; got nothing"));
1724 as_bad (_("expecting operand before ','; got nothing"));
1729 /* Now *l must be either ',' or END_OF_INSN. */
1732 if (*++l == END_OF_INSN)
1734 /* Just skip it, if it's \n complain. */
1735 goto expecting_operand_after_comma;
1737 expecting_operand = 1;
1746 union i386_op temp_op;
1747 unsigned int temp_type;
1748 RELOC_ENUM temp_reloc;
1752 if (i.operands == 2)
1757 else if (i.operands == 3)
1762 temp_type = i.types[xchg2];
1763 i.types[xchg2] = i.types[xchg1];
1764 i.types[xchg1] = temp_type;
1765 temp_op = i.op[xchg2];
1766 i.op[xchg2] = i.op[xchg1];
1767 i.op[xchg1] = temp_op;
1768 temp_reloc = i.reloc[xchg2];
1769 i.reloc[xchg2] = i.reloc[xchg1];
1770 i.reloc[xchg1] = temp_reloc;
1772 if (i.mem_operands == 2)
1774 const seg_entry *temp_seg;
1775 temp_seg = i.seg[0];
1776 i.seg[0] = i.seg[1];
1777 i.seg[1] = temp_seg;
1781 /* Try to ensure constant immediates are represented in the smallest
1786 char guess_suffix = 0;
1790 guess_suffix = i.suffix;
1791 else if (i.reg_operands)
1793 /* Figure out a suffix from the last register operand specified.
1794 We can't do this properly yet, ie. excluding InOutPortReg,
1795 but the following works for instructions with immediates.
1796 In any case, we can't set i.suffix yet. */
1797 for (op = i.operands; --op >= 0;)
1798 if (i.types[op] & Reg)
1800 if (i.types[op] & Reg8)
1801 guess_suffix = BYTE_MNEM_SUFFIX;
1802 else if (i.types[op] & Reg16)
1803 guess_suffix = WORD_MNEM_SUFFIX;
1804 else if (i.types[op] & Reg32)
1805 guess_suffix = LONG_MNEM_SUFFIX;
1806 else if (i.types[op] & Reg64)
1807 guess_suffix = QWORD_MNEM_SUFFIX;
1811 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1812 guess_suffix = WORD_MNEM_SUFFIX;
1814 for (op = i.operands; --op >= 0;)
1815 if (i.types[op] & Imm)
1817 switch (i.op[op].imms->X_op)
1820 /* If a suffix is given, this operand may be shortened. */
1821 switch (guess_suffix)
1823 case LONG_MNEM_SUFFIX:
1824 i.types[op] |= Imm32 | Imm64;
1826 case WORD_MNEM_SUFFIX:
1827 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1829 case BYTE_MNEM_SUFFIX:
1830 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1834 /* If this operand is at most 16 bits, convert it
1835 to a signed 16 bit number before trying to see
1836 whether it will fit in an even smaller size.
1837 This allows a 16-bit operand such as $0xffe0 to
1838 be recognised as within Imm8S range. */
1839 if ((i.types[op] & Imm16)
1840 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
1842 i.op[op].imms->X_add_number =
1843 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1845 if ((i.types[op] & Imm32)
1846 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1849 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1850 ^ ((offsetT) 1 << 31))
1851 - ((offsetT) 1 << 31));
1853 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
1855 /* We must avoid matching of Imm32 templates when 64bit
1856 only immediate is available. */
1857 if (guess_suffix == QWORD_MNEM_SUFFIX)
1858 i.types[op] &= ~Imm32;
1865 /* Symbols and expressions. */
1867 /* Convert symbolic operand to proper sizes for matching. */
1868 switch (guess_suffix)
1870 case QWORD_MNEM_SUFFIX:
1871 i.types[op] = Imm64 | Imm32S;
1873 case LONG_MNEM_SUFFIX:
1874 i.types[op] = Imm32 | Imm64;
1876 case WORD_MNEM_SUFFIX:
1877 i.types[op] = Imm16 | Imm32 | Imm64;
1880 case BYTE_MNEM_SUFFIX:
1881 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1890 /* Try to use the smallest displacement type too. */
1896 for (op = i.operands; --op >= 0;)
1897 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
1899 offsetT disp = i.op[op].disps->X_add_number;
1901 if (i.types[op] & Disp16)
1903 /* We know this operand is at most 16 bits, so
1904 convert to a signed 16 bit number before trying
1905 to see whether it will fit in an even smaller
1908 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
1910 else if (i.types[op] & Disp32)
1912 /* We know this operand is at most 32 bits, so convert to a
1913 signed 32 bit number before trying to see whether it will
1914 fit in an even smaller size. */
1915 disp &= (((offsetT) 2 << 31) - 1);
1916 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1918 if (flag_code == CODE_64BIT)
1920 if (fits_in_signed_long (disp))
1921 i.types[op] |= Disp32S;
1922 if (fits_in_unsigned_long (disp))
1923 i.types[op] |= Disp32;
1925 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1926 && fits_in_signed_byte (disp))
1927 i.types[op] |= Disp8;
1934 /* Points to template once we've found it. */
1936 unsigned int overlap0, overlap1, overlap2;
1937 unsigned int found_reverse_match;
1940 #define MATCH(overlap, given, template) \
1941 ((overlap & ~JumpAbsolute) \
1942 && (((given) & (BaseIndex | JumpAbsolute)) \
1943 == ((overlap) & (BaseIndex | JumpAbsolute))))
1945 /* If given types r0 and r1 are registers they must be of the same type
1946 unless the expected operand type register overlap is null.
1947 Note that Acc in a template matches every size of reg. */
1948 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1949 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1950 || ((g0) & Reg) == ((g1) & Reg) \
1951 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1956 found_reverse_match = 0;
1957 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1959 : (i.suffix == WORD_MNEM_SUFFIX
1961 : (i.suffix == SHORT_MNEM_SUFFIX
1963 : (i.suffix == LONG_MNEM_SUFFIX
1965 : (i.suffix == QWORD_MNEM_SUFFIX
1967 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
1968 ? No_xSuf : 0))))));
1970 for (t = current_templates->start;
1971 t < current_templates->end;
1974 /* Must have right number of operands. */
1975 if (i.operands != t->operands)
1978 /* Check the suffix, except for some instructions in intel mode. */
1979 if ((t->opcode_modifier & suffix_check)
1981 && (t->opcode_modifier & IgnoreSize))
1983 && t->base_opcode == 0xd9
1984 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
1985 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
1988 /* Do not verify operands when there are none. */
1989 else if (!t->operands)
1991 if (t->cpu_flags & ~cpu_arch_flags)
1993 /* We've found a match; break out of loop. */
1997 overlap0 = i.types[0] & t->operand_types[0];
1998 switch (t->operands)
2001 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2006 overlap1 = i.types[1] & t->operand_types[1];
2007 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2008 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2009 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2010 t->operand_types[0],
2011 overlap1, i.types[1],
2012 t->operand_types[1]))
2014 /* Check if other direction is valid ... */
2015 if ((t->opcode_modifier & (D | FloatD)) == 0)
2018 /* Try reversing direction of operands. */
2019 overlap0 = i.types[0] & t->operand_types[1];
2020 overlap1 = i.types[1] & t->operand_types[0];
2021 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2022 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2023 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2024 t->operand_types[1],
2025 overlap1, i.types[1],
2026 t->operand_types[0]))
2028 /* Does not match either direction. */
2031 /* found_reverse_match holds which of D or FloatDR
2033 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2035 /* Found a forward 2 operand match here. */
2036 else if (t->operands == 3)
2038 /* Here we make use of the fact that there are no
2039 reverse match 3 operand instructions, and all 3
2040 operand instructions only need to be checked for
2041 register consistency between operands 2 and 3. */
2042 overlap2 = i.types[2] & t->operand_types[2];
2043 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2044 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2045 t->operand_types[1],
2046 overlap2, i.types[2],
2047 t->operand_types[2]))
2051 /* Found either forward/reverse 2 or 3 operand match here:
2052 slip through to break. */
2054 if (t->cpu_flags & ~cpu_arch_flags)
2056 found_reverse_match = 0;
2059 /* We've found a match; break out of loop. */
2063 if (t == current_templates->end)
2065 /* We found no match. */
2066 as_bad (_("suffix or operands invalid for `%s'"),
2067 current_templates->start->name);
2071 if (!quiet_warnings)
2074 && ((i.types[0] & JumpAbsolute)
2075 != (t->operand_types[0] & JumpAbsolute)))
2077 as_warn (_("indirect %s without `*'"), t->name);
2080 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2081 == (IsPrefix | IgnoreSize))
2083 /* Warn them that a data or address size prefix doesn't
2084 affect assembly of the next line of code. */
2085 as_warn (_("stand-alone `%s' prefix"), t->name);
2089 /* Copy the template we found. */
2091 if (found_reverse_match)
2093 /* If we found a reverse match we must alter the opcode
2094 direction bit. found_reverse_match holds bits to change
2095 (different for int & float insns). */
2097 i.tm.base_opcode ^= found_reverse_match;
2099 i.tm.operand_types[0] = t->operand_types[1];
2100 i.tm.operand_types[1] = t->operand_types[0];
2109 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2110 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2112 if (i.seg[0] != NULL && i.seg[0] != &es)
2114 as_bad (_("`%s' operand %d must use `%%es' segment"),
2119 /* There's only ever one segment override allowed per instruction.
2120 This instruction possibly has a legal segment override on the
2121 second operand, so copy the segment to where non-string
2122 instructions store it, allowing common code. */
2123 i.seg[0] = i.seg[1];
2125 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2127 if (i.seg[1] != NULL && i.seg[1] != &es)
2129 as_bad (_("`%s' operand %d must use `%%es' segment"),
2141 /* If matched instruction specifies an explicit instruction mnemonic
2143 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2145 if (i.tm.opcode_modifier & Size16)
2146 i.suffix = WORD_MNEM_SUFFIX;
2147 else if (i.tm.opcode_modifier & Size64)
2148 i.suffix = QWORD_MNEM_SUFFIX;
2150 i.suffix = LONG_MNEM_SUFFIX;
2152 else if (i.reg_operands)
2154 /* If there's no instruction mnemonic suffix we try to invent one
2155 based on register operands. */
2158 /* We take i.suffix from the last register operand specified,
2159 Destination register type is more significant than source
2162 for (op = i.operands; --op >= 0;)
2163 if ((i.types[op] & Reg)
2164 && !(i.tm.operand_types[op] & InOutPortReg))
2166 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2167 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2168 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2173 else if (i.suffix == BYTE_MNEM_SUFFIX)
2175 if (!check_byte_reg ())
2178 else if (i.suffix == LONG_MNEM_SUFFIX)
2180 if (!check_long_reg ())
2183 else if (i.suffix == QWORD_MNEM_SUFFIX)
2185 if (!check_qword_reg ())
2188 else if (i.suffix == WORD_MNEM_SUFFIX)
2190 if (!check_word_reg ())
2193 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2194 /* Do nothing if the instruction is going to ignore the prefix. */
2199 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2201 i.suffix = stackop_size;
2204 /* Change the opcode based on the operand size given by i.suffix;
2205 We need not change things for byte insns. */
2207 if (!i.suffix && (i.tm.opcode_modifier & W))
2209 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2213 /* For movzx and movsx, need to check the register type. */
2215 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)
2216 && i.suffix == BYTE_MNEM_SUFFIX)
2218 unsigned int prefix = DATA_PREFIX_OPCODE;
2220 if ((i.op[1].regs->reg_type & Reg16) != 0)
2221 if (!add_prefix (prefix))
2225 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2227 /* It's not a byte, select word/dword operation. */
2228 if (i.tm.opcode_modifier & W)
2230 if (i.tm.opcode_modifier & ShortForm)
2231 i.tm.base_opcode |= 8;
2233 i.tm.base_opcode |= 1;
2236 /* Now select between word & dword operations via the operand
2237 size prefix, except for instructions that will ignore this
2239 if (i.suffix != QWORD_MNEM_SUFFIX
2240 && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2241 && !(i.tm.opcode_modifier & IgnoreSize))
2243 unsigned int prefix = DATA_PREFIX_OPCODE;
2244 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2245 prefix = ADDR_PREFIX_OPCODE;
2247 if (!add_prefix (prefix))
2251 if (i.suffix != QWORD_MNEM_SUFFIX && (flag_code == CODE_64BIT)
2252 && !(i.tm.opcode_modifier & IgnoreSize)
2253 && (i.tm.opcode_modifier & JumpByte))
2255 if (!add_prefix (ADDR_PREFIX_OPCODE))
2259 /* Set mode64 for an operand. */
2260 if (i.suffix == QWORD_MNEM_SUFFIX
2261 && (i.tm.opcode_modifier & NoRex64) == 0)
2263 i.rex |= REX_MODE64;
2264 if (flag_code < CODE_64BIT)
2266 as_bad (_("64bit operations available only in 64bit modes."));
2271 /* Size floating point instruction. */
2272 if (i.suffix == LONG_MNEM_SUFFIX)
2274 if (i.tm.opcode_modifier & FloatMF)
2275 i.tm.base_opcode ^= 4;
2286 for (op = i.operands; --op >= 0;)
2288 /* If this is an eight bit register, it's OK. If it's the 16 or
2289 32 bit version of an eight bit register, we will just use the
2290 low portion, and that's OK too. */
2291 if (i.types[op] & Reg8)
2294 /* movzx and movsx should not generate this warning. */
2296 && (i.tm.base_opcode == 0xfb7
2297 || i.tm.base_opcode == 0xfb6
2298 || i.tm.base_opcode == 0x63
2299 || i.tm.base_opcode == 0xfbe
2300 || i.tm.base_opcode == 0xfbf))
2303 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2305 /* Check that the template allows eight bit regs. This
2306 kills insns such as `orb $1,%edx', which maybe should be
2308 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2312 /* Prohibit these changes in the 64bit mode, since the
2313 lowering is more complicated. */
2314 if (flag_code == CODE_64BIT
2315 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2317 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2318 i.op[op].regs->reg_name,
2322 #if REGISTER_WARNINGS
2324 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2325 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2326 (i.op[op].regs + (i.types[op] & Reg16
2327 ? REGNAM_AL - REGNAM_AX
2328 : REGNAM_AL - REGNAM_EAX))->reg_name,
2329 i.op[op].regs->reg_name,
2334 /* Any other register is bad. */
2335 if (i.types[op] & (Reg | RegMMX | RegXMM
2337 | Control | Debug | Test
2338 | FloatReg | FloatAcc))
2340 as_bad (_("`%%%s' not allowed with `%s%c'"),
2341 i.op[op].regs->reg_name,
2355 for (op = i.operands; --op >= 0;)
2356 /* Reject eight bit registers, except where the template requires
2357 them. (eg. movzb) */
2358 if ((i.types[op] & Reg8) != 0
2359 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2361 as_bad (_("`%%%s' not allowed with `%s%c'"),
2362 i.op[op].regs->reg_name,
2367 /* Warn if the e prefix on a general reg is missing. */
2368 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2369 && (i.types[op] & Reg16) != 0
2370 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2372 /* Prohibit these changes in the 64bit mode, since the
2373 lowering is more complicated. */
2374 if (flag_code == CODE_64BIT)
2376 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2377 i.op[op].regs->reg_name,
2381 #if REGISTER_WARNINGS
2383 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2384 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2385 i.op[op].regs->reg_name,
2389 /* Warn if the r prefix on a general reg is missing. */
2390 else if ((i.types[op] & Reg64) != 0
2391 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2393 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2394 i.op[op].regs->reg_name,
2406 for (op = i.operands; --op >= 0; )
2407 /* Reject eight bit registers, except where the template requires
2408 them. (eg. movzb) */
2409 if ((i.types[op] & Reg8) != 0
2410 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2412 as_bad (_("`%%%s' not allowed with `%s%c'"),
2413 i.op[op].regs->reg_name,
2418 /* Warn if the e prefix on a general reg is missing. */
2419 else if (((i.types[op] & Reg16) != 0
2420 || (i.types[op] & Reg32) != 0)
2421 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2423 /* Prohibit these changes in the 64bit mode, since the
2424 lowering is more complicated. */
2425 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2426 i.op[op].regs->reg_name,
2437 for (op = i.operands; --op >= 0;)
2438 /* Reject eight bit registers, except where the template requires
2439 them. (eg. movzb) */
2440 if ((i.types[op] & Reg8) != 0
2441 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2443 as_bad (_("`%%%s' not allowed with `%s%c'"),
2444 i.op[op].regs->reg_name,
2449 /* Warn if the e prefix on a general reg is present. */
2450 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2451 && (i.types[op] & Reg32) != 0
2452 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
2454 /* Prohibit these changes in the 64bit mode, since the
2455 lowering is more complicated. */
2456 if (flag_code == CODE_64BIT)
2458 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2459 i.op[op].regs->reg_name,
2464 #if REGISTER_WARNINGS
2465 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2466 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2467 i.op[op].regs->reg_name,
2477 unsigned int overlap0, overlap1, overlap2;
2479 overlap0 = i.types[0] & i.tm.operand_types[0];
2480 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2481 && overlap0 != Imm8 && overlap0 != Imm8S
2482 && overlap0 != Imm16 && overlap0 != Imm32S
2483 && overlap0 != Imm32 && overlap0 != Imm64)
2487 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2489 : (i.suffix == WORD_MNEM_SUFFIX
2491 : (i.suffix == QWORD_MNEM_SUFFIX
2495 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2496 || overlap0 == (Imm16 | Imm32)
2497 || overlap0 == (Imm16 | Imm32S))
2499 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2502 if (overlap0 != Imm8 && overlap0 != Imm8S
2503 && overlap0 != Imm16 && overlap0 != Imm32S
2504 && overlap0 != Imm32 && overlap0 != Imm64)
2506 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2510 i.types[0] = overlap0;
2512 overlap1 = i.types[1] & i.tm.operand_types[1];
2513 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2514 && overlap1 != Imm8 && overlap1 != Imm8S
2515 && overlap1 != Imm16 && overlap1 != Imm32S
2516 && overlap1 != Imm32 && overlap1 != Imm64)
2520 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2522 : (i.suffix == WORD_MNEM_SUFFIX
2524 : (i.suffix == QWORD_MNEM_SUFFIX
2528 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2529 || overlap1 == (Imm16 | Imm32)
2530 || overlap1 == (Imm16 | Imm32S))
2532 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2535 if (overlap1 != Imm8 && overlap1 != Imm8S
2536 && overlap1 != Imm16 && overlap1 != Imm32S
2537 && overlap1 != Imm32 && overlap1 != Imm64)
2539 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2543 i.types[1] = overlap1;
2545 overlap2 = i.types[2] & i.tm.operand_types[2];
2546 assert ((overlap2 & Imm) == 0);
2547 i.types[2] = overlap2;
2555 /* Default segment register this instruction will use for memory
2556 accesses. 0 means unknown. This is only for optimizing out
2557 unnecessary segment overrides. */
2558 const seg_entry *default_seg = 0;
2560 /* The imul $imm, %reg instruction is converted into
2561 imul $imm, %reg, %reg, and the clr %reg instruction
2562 is converted into xor %reg, %reg. */
2563 if (i.tm.opcode_modifier & regKludge)
2565 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2566 /* Pretend we saw the extra register operand. */
2567 assert (i.op[first_reg_op + 1].regs == 0);
2568 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2569 i.types[first_reg_op + 1] = i.types[first_reg_op];
2573 if (i.tm.opcode_modifier & ShortForm)
2575 /* The register or float register operand is in operand 0 or 1. */
2576 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2577 /* Register goes in low 3 bits of opcode. */
2578 i.tm.base_opcode |= i.op[op].regs->reg_num;
2579 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2581 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2583 /* Warn about some common errors, but press on regardless.
2584 The first case can be generated by gcc (<= 2.8.1). */
2585 if (i.operands == 2)
2587 /* Reversed arguments on faddp, fsubp, etc. */
2588 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2589 i.op[1].regs->reg_name,
2590 i.op[0].regs->reg_name);
2594 /* Extraneous `l' suffix on fp insn. */
2595 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2596 i.op[0].regs->reg_name);
2600 else if (i.tm.opcode_modifier & Modrm)
2602 /* The opcode is completed (modulo i.tm.extension_opcode which
2603 must be put into the modrm byte).
2604 Now, we make the modrm & index base bytes based on all the
2605 info we've collected. */
2607 default_seg = build_modrm_byte ();
2609 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2611 if (i.tm.base_opcode == POP_SEG_SHORT
2612 && i.op[0].regs->reg_num == 1)
2614 as_bad (_("you can't `pop %%cs'"));
2617 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2618 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2621 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2625 else if ((i.tm.opcode_modifier & IsString) != 0)
2627 /* For the string instructions that allow a segment override
2628 on one of their operands, the default segment is ds. */
2632 /* If a segment was explicitly specified,
2633 and the specified segment is not the default,
2634 use an opcode prefix to select it.
2635 If we never figured out what the default segment is,
2636 then default_seg will be zero at this point,
2637 and the specified segment prefix will always be used. */
2638 if ((i.seg[0]) && (i.seg[0] != default_seg))
2640 if (!add_prefix (i.seg[0]->seg_prefix))
2646 static const seg_entry *
2649 const seg_entry *default_seg = 0;
2651 /* i.reg_operands MUST be the number of real register operands;
2652 implicit registers do not count. */
2653 if (i.reg_operands == 2)
2655 unsigned int source, dest;
2656 source = ((i.types[0]
2657 & (Reg | RegMMX | RegXMM
2659 | Control | Debug | Test))
2664 /* One of the register operands will be encoded in the i.tm.reg
2665 field, the other in the combined i.tm.mode and i.tm.regmem
2666 fields. If no form of this instruction supports a memory
2667 destination operand, then we assume the source operand may
2668 sometimes be a memory operand and so we need to store the
2669 destination in the i.rm.reg field. */
2670 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2672 i.rm.reg = i.op[dest].regs->reg_num;
2673 i.rm.regmem = i.op[source].regs->reg_num;
2674 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2676 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2681 i.rm.reg = i.op[source].regs->reg_num;
2682 i.rm.regmem = i.op[dest].regs->reg_num;
2683 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2685 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2690 { /* If it's not 2 reg operands... */
2693 unsigned int fake_zero_displacement = 0;
2694 unsigned int op = ((i.types[0] & AnyMem)
2696 : (i.types[1] & AnyMem) ? 1 : 2);
2700 if (i.base_reg == 0)
2703 if (!i.disp_operands)
2704 fake_zero_displacement = 1;
2705 if (i.index_reg == 0)
2707 /* Operand is just <disp> */
2708 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2709 && (flag_code != CODE_64BIT))
2711 i.rm.regmem = NO_BASE_REGISTER_16;
2712 i.types[op] &= ~Disp;
2713 i.types[op] |= Disp16;
2715 else if (flag_code != CODE_64BIT
2716 || (i.prefix[ADDR_PREFIX] != 0))
2718 i.rm.regmem = NO_BASE_REGISTER;
2719 i.types[op] &= ~Disp;
2720 i.types[op] |= Disp32;
2724 /* 64bit mode overwrites the 32bit absolute
2725 addressing by RIP relative addressing and
2726 absolute addressing is encoded by one of the
2727 redundant SIB forms. */
2728 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2729 i.sib.base = NO_BASE_REGISTER;
2730 i.sib.index = NO_INDEX_REGISTER;
2731 i.types[op] &= ~Disp;
2732 i.types[op] |= Disp32S;
2735 else /* !i.base_reg && i.index_reg */
2737 i.sib.index = i.index_reg->reg_num;
2738 i.sib.base = NO_BASE_REGISTER;
2739 i.sib.scale = i.log2_scale_factor;
2740 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2741 i.types[op] &= ~Disp;
2742 if (flag_code != CODE_64BIT)
2743 i.types[op] |= Disp32; /* Must be 32 bit */
2745 i.types[op] |= Disp32S;
2746 if ((i.index_reg->reg_flags & RegRex) != 0)
2750 /* RIP addressing for 64bit mode. */
2751 else if (i.base_reg->reg_type == BaseIndex)
2753 i.rm.regmem = NO_BASE_REGISTER;
2754 i.types[op] &= ~Disp;
2755 i.types[op] |= Disp32S;
2756 i.flags[op] = Operand_PCrel;
2758 else if (i.base_reg->reg_type & Reg16)
2760 switch (i.base_reg->reg_num)
2763 if (i.index_reg == 0)
2765 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2766 i.rm.regmem = i.index_reg->reg_num - 6;
2770 if (i.index_reg == 0)
2773 if ((i.types[op] & Disp) == 0)
2775 /* fake (%bp) into 0(%bp) */
2776 i.types[op] |= Disp8;
2777 fake_zero_displacement = 1;
2780 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2781 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2783 default: /* (%si) -> 4 or (%di) -> 5 */
2784 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2786 i.rm.mode = mode_from_disp_size (i.types[op]);
2788 else /* i.base_reg and 32/64 bit mode */
2790 if (flag_code == CODE_64BIT
2791 && (i.types[op] & Disp))
2793 if (i.types[op] & Disp8)
2794 i.types[op] = Disp8 | Disp32S;
2796 i.types[op] = Disp32S;
2798 i.rm.regmem = i.base_reg->reg_num;
2799 if ((i.base_reg->reg_flags & RegRex) != 0)
2801 i.sib.base = i.base_reg->reg_num;
2802 /* x86-64 ignores REX prefix bit here to avoid decoder
2804 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2807 if (i.disp_operands == 0)
2809 fake_zero_displacement = 1;
2810 i.types[op] |= Disp8;
2813 else if (i.base_reg->reg_num == ESP_REG_NUM)
2817 i.sib.scale = i.log2_scale_factor;
2818 if (i.index_reg == 0)
2820 /* <disp>(%esp) becomes two byte modrm with no index
2821 register. We've already stored the code for esp
2822 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2823 Any base register besides %esp will not use the
2824 extra modrm byte. */
2825 i.sib.index = NO_INDEX_REGISTER;
2826 #if !SCALE1_WHEN_NO_INDEX
2827 /* Another case where we force the second modrm byte. */
2828 if (i.log2_scale_factor)
2829 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2834 i.sib.index = i.index_reg->reg_num;
2835 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2836 if ((i.index_reg->reg_flags & RegRex) != 0)
2839 i.rm.mode = mode_from_disp_size (i.types[op]);
2842 if (fake_zero_displacement)
2844 /* Fakes a zero displacement assuming that i.types[op]
2845 holds the correct displacement size. */
2848 assert (i.op[op].disps == 0);
2849 exp = &disp_expressions[i.disp_operands++];
2850 i.op[op].disps = exp;
2851 exp->X_op = O_constant;
2852 exp->X_add_number = 0;
2853 exp->X_add_symbol = (symbolS *) 0;
2854 exp->X_op_symbol = (symbolS *) 0;
2858 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2859 (if any) based on i.tm.extension_opcode. Again, we must be
2860 careful to make sure that segment/control/debug/test/MMX
2861 registers are coded into the i.rm.reg field. */
2866 & (Reg | RegMMX | RegXMM
2868 | Control | Debug | Test))
2871 & (Reg | RegMMX | RegXMM
2873 | Control | Debug | Test))
2876 /* If there is an extension opcode to put here, the register
2877 number must be put into the regmem field. */
2878 if (i.tm.extension_opcode != None)
2880 i.rm.regmem = i.op[op].regs->reg_num;
2881 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2886 i.rm.reg = i.op[op].regs->reg_num;
2887 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2891 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2892 must set it to 3 to indicate this is a register operand
2893 in the regmem field. */
2894 if (!i.mem_operands)
2898 /* Fill in i.rm.reg field with extension opcode (if any). */
2899 if (i.tm.extension_opcode != None)
2900 i.rm.reg = i.tm.extension_opcode;
2911 relax_substateT subtype;
2916 if (flag_code == CODE_16BIT)
2920 if (i.prefix[DATA_PREFIX] != 0)
2926 /* Pentium4 branch hints. */
2927 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2928 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2933 if (i.prefix[REX_PREFIX] != 0)
2939 if (i.prefixes != 0 && !intel_syntax)
2940 as_warn (_("skipping prefixes on this instruction"));
2942 /* It's always a symbol; End frag & setup for relax.
2943 Make sure there is enough room in this frag for the largest
2944 instruction we may generate in md_convert_frag. This is 2
2945 bytes for the opcode and room for the prefix and largest
2947 frag_grow (prefix + 2 + 4);
2948 /* Prefix and 1 opcode byte go in fr_fix. */
2949 p = frag_more (prefix + 1);
2950 if (i.prefix[DATA_PREFIX] != 0)
2951 *p++ = DATA_PREFIX_OPCODE;
2952 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2953 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2954 *p++ = i.prefix[SEG_PREFIX];
2955 if (i.prefix[REX_PREFIX] != 0)
2956 *p++ = i.prefix[REX_PREFIX];
2957 *p = i.tm.base_opcode;
2959 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2960 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2961 else if ((cpu_arch_flags & Cpu386) != 0)
2962 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2964 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2967 sym = i.op[0].disps->X_add_symbol;
2968 off = i.op[0].disps->X_add_number;
2970 if (i.op[0].disps->X_op != O_constant
2971 && i.op[0].disps->X_op != O_symbol)
2973 /* Handle complex expressions. */
2974 sym = make_expr_symbol (i.op[0].disps);
2978 /* 1 possible extra opcode + 4 byte displacement go in var part.
2979 Pass reloc in fr_var. */
2980 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
2989 if (i.tm.opcode_modifier & JumpByte)
2991 /* This is a loop or jecxz type instruction. */
2993 if (i.prefix[ADDR_PREFIX] != 0)
2995 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2998 /* Pentium4 branch hints. */
2999 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3000 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3002 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3011 if (flag_code == CODE_16BIT)
3014 if (i.prefix[DATA_PREFIX] != 0)
3016 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3026 if (i.prefix[REX_PREFIX] != 0)
3028 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3032 if (i.prefixes != 0 && !intel_syntax)
3033 as_warn (_("skipping prefixes on this instruction"));
3035 p = frag_more (1 + size);
3036 *p++ = i.tm.base_opcode;
3038 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3039 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3043 output_interseg_jump ()
3051 if (flag_code == CODE_16BIT)
3055 if (i.prefix[DATA_PREFIX] != 0)
3061 if (i.prefix[REX_PREFIX] != 0)
3071 if (i.prefixes != 0 && !intel_syntax)
3072 as_warn (_("skipping prefixes on this instruction"));
3074 /* 1 opcode; 2 segment; offset */
3075 p = frag_more (prefix + 1 + 2 + size);
3077 if (i.prefix[DATA_PREFIX] != 0)
3078 *p++ = DATA_PREFIX_OPCODE;
3080 if (i.prefix[REX_PREFIX] != 0)
3081 *p++ = i.prefix[REX_PREFIX];
3083 *p++ = i.tm.base_opcode;
3084 if (i.op[1].imms->X_op == O_constant)
3086 offsetT n = i.op[1].imms->X_add_number;
3089 && !fits_in_unsigned_word (n)
3090 && !fits_in_signed_word (n))
3092 as_bad (_("16-bit jump out of range"));
3095 md_number_to_chars (p, n, size);
3098 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3099 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3100 if (i.op[0].imms->X_op != O_constant)
3101 as_bad (_("can't handle non absolute segment in `%s'"),
3103 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3109 /* Tie dwarf2 debug info to the address at the start of the insn.
3110 We can't do this after the insn has been output as the current
3111 frag may have been closed off. eg. by frag_var. */
3112 dwarf2_emit_insn (0);
3115 if (i.tm.opcode_modifier & Jump)
3117 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3119 else if (i.tm.opcode_modifier & JumpInterSegment)
3120 output_interseg_jump ();
3123 /* Output normal instructions here. */
3127 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3128 byte for the SSE instructions to specify a prefix they require. */
3129 if (i.tm.base_opcode & 0xff0000)
3130 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
3132 /* The prefix bytes. */
3134 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3140 md_number_to_chars (p, (valueT) *q, 1);
3144 /* Now the opcode; be careful about word order here! */
3145 if (fits_in_unsigned_byte (i.tm.base_opcode))
3147 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3152 /* Put out high byte first: can't use md_number_to_chars! */
3153 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3154 *p = i.tm.base_opcode & 0xff;
3157 /* Now the modrm byte and sib byte (if present). */
3158 if (i.tm.opcode_modifier & Modrm)
3161 md_number_to_chars (p,
3162 (valueT) (i.rm.regmem << 0
3166 /* If i.rm.regmem == ESP (4)
3167 && i.rm.mode != (Register mode)
3169 ==> need second modrm byte. */
3170 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3172 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3175 md_number_to_chars (p,
3176 (valueT) (i.sib.base << 0
3178 | i.sib.scale << 6),
3183 if (i.disp_operands)
3195 #endif /* DEBUG386 */
3204 for (n = 0; n < i.operands; n++)
3206 if (i.types[n] & Disp)
3208 if (i.op[n].disps->X_op == O_constant)
3214 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3217 if (i.types[n] & Disp8)
3219 if (i.types[n] & Disp64)
3222 val = offset_in_range (i.op[n].disps->X_add_number,
3224 p = frag_more (size);
3225 md_number_to_chars (p, val, size);
3231 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3233 /* The PC relative address is computed relative
3234 to the instruction boundary, so in case immediate
3235 fields follows, we need to adjust the value. */
3236 if (pcrel && i.imm_operands)
3241 for (n1 = 0; n1 < i.operands; n1++)
3242 if (i.types[n1] & Imm)
3244 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
3247 if (i.types[n1] & (Imm8 | Imm8S))
3249 if (i.types[n1] & Imm64)
3254 /* We should find the immediate. */
3255 if (n1 == i.operands)
3257 i.op[n].disps->X_add_number -= imm_size;
3260 if (i.types[n] & Disp32S)
3263 if (i.types[n] & (Disp16 | Disp64))
3266 if (i.types[n] & Disp64)
3270 p = frag_more (size);
3271 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3272 i.op[n].disps, pcrel,
3273 reloc (size, pcrel, sign, i.reloc[n]));
3285 for (n = 0; n < i.operands; n++)
3287 if (i.types[n] & Imm)
3289 if (i.op[n].imms->X_op == O_constant)
3295 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3298 if (i.types[n] & (Imm8 | Imm8S))
3300 else if (i.types[n] & Imm64)
3303 val = offset_in_range (i.op[n].imms->X_add_number,
3305 p = frag_more (size);
3306 md_number_to_chars (p, val, size);
3310 /* Not absolute_section.
3311 Need a 32-bit fixup (don't support 8bit
3312 non-absolute imms). Try to support other
3314 RELOC_ENUM reloc_type;
3318 if ((i.types[n] & (Imm32S))
3319 && i.suffix == QWORD_MNEM_SUFFIX)
3321 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3324 if (i.types[n] & (Imm8 | Imm8S))
3326 if (i.types[n] & Imm64)
3330 p = frag_more (size);
3331 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3332 #ifdef BFD_ASSEMBLER
3333 if (reloc_type == BFD_RELOC_32
3335 && GOT_symbol == i.op[n].imms->X_add_symbol
3336 && (i.op[n].imms->X_op == O_symbol
3337 || (i.op[n].imms->X_op == O_add
3338 && ((symbol_get_value_expression
3339 (i.op[n].imms->X_op_symbol)->X_op)
3342 /* We don't support dynamic linking on x86-64 yet. */
3343 if (flag_code == CODE_64BIT)
3345 reloc_type = BFD_RELOC_386_GOTPC;
3346 i.op[n].imms->X_add_number += 3;
3349 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3350 i.op[n].imms, 0, reloc_type);
3357 static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3359 /* Parse operands of the form
3360 <symbol>@GOTOFF+<nnn>
3361 and similar .plt or .got references.
3363 If we find one, set up the correct relocation in RELOC and copy the
3364 input string, minus the `@GOTOFF' into a malloc'd buffer for
3365 parsing by the calling routine. Return this buffer, and if ADJUST
3366 is non-null set it to the length of the string we removed from the
3367 input line. Otherwise return NULL. */
3369 lex_got (reloc, adjust)
3373 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3374 static const struct {
3376 const RELOC_ENUM rel[NUM_FLAG_CODE];
3378 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3379 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3380 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3381 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
3386 for (cp = input_line_pointer; *cp != '@'; cp++)
3387 if (is_end_of_line[(unsigned char) *cp])
3390 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3394 len = strlen (gotrel[j].str);
3395 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
3397 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3400 char *tmpbuf, *past_reloc;
3402 *reloc = gotrel[j].rel[(unsigned int) flag_code];
3406 if (GOT_symbol == NULL)
3407 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3409 /* Replace the relocation token with ' ', so that
3410 errors like foo@GOTOFF1 will be detected. */
3412 /* The length of the first part of our input line. */
3413 first = cp - input_line_pointer;
3415 /* The second part goes from after the reloc token until
3416 (and including) an end_of_line char. Don't use strlen
3417 here as the end_of_line char may not be a NUL. */
3418 past_reloc = cp + 1 + len;
3419 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3421 second = cp - past_reloc;
3423 /* Allocate and copy string. The trailing NUL shouldn't
3424 be necessary, but be safe. */
3425 tmpbuf = xmalloc (first + second + 2);
3426 memcpy (tmpbuf, input_line_pointer, first);
3427 tmpbuf[first] = ' ';
3428 memcpy (tmpbuf + first + 1, past_reloc, second);
3429 tmpbuf[first + second + 1] = '\0';
3433 as_bad (_("@%s reloc is not supported in %s bit mode"),
3434 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3439 /* Might be a symbol version string. Don't as_bad here. */
3443 /* x86_cons_fix_new is called via the expression parsing code when a
3444 reloc is needed. We use this hook to get the correct .got reloc. */
3445 static RELOC_ENUM got_reloc = NO_RELOC;
3448 x86_cons_fix_new (frag, off, len, exp)
3454 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3455 got_reloc = NO_RELOC;
3456 fix_new_exp (frag, off, len, exp, 0, r);
3460 x86_cons (exp, size)
3466 /* Handle @GOTOFF and the like in an expression. */
3468 char *gotfree_input_line;
3471 save = input_line_pointer;
3472 gotfree_input_line = lex_got (&got_reloc, &adjust);
3473 if (gotfree_input_line)
3474 input_line_pointer = gotfree_input_line;
3478 if (gotfree_input_line)
3480 /* expression () has merrily parsed up to the end of line,
3481 or a comma - in the wrong buffer. Transfer how far
3482 input_line_pointer has moved to the right buffer. */
3483 input_line_pointer = (save
3484 + (input_line_pointer - gotfree_input_line)
3486 free (gotfree_input_line);
3494 static int i386_immediate PARAMS ((char *));
3497 i386_immediate (imm_start)
3500 char *save_input_line_pointer;
3502 char *gotfree_input_line;
3507 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3509 as_bad (_("only 1 or 2 immediate operands are allowed"));
3513 exp = &im_expressions[i.imm_operands++];
3514 i.op[this_operand].imms = exp;
3516 if (is_space_char (*imm_start))
3519 save_input_line_pointer = input_line_pointer;
3520 input_line_pointer = imm_start;
3523 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3524 if (gotfree_input_line)
3525 input_line_pointer = gotfree_input_line;
3528 exp_seg = expression (exp);
3531 if (*input_line_pointer)
3532 as_bad (_("junk `%s' after expression"), input_line_pointer);
3534 input_line_pointer = save_input_line_pointer;
3536 if (gotfree_input_line)
3537 free (gotfree_input_line);
3540 if (exp->X_op == O_absent || exp->X_op == O_big)
3542 /* Missing or bad expr becomes absolute 0. */
3543 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3545 exp->X_op = O_constant;
3546 exp->X_add_number = 0;
3547 exp->X_add_symbol = (symbolS *) 0;
3548 exp->X_op_symbol = (symbolS *) 0;
3550 else if (exp->X_op == O_constant)
3552 /* Size it properly later. */
3553 i.types[this_operand] |= Imm64;
3554 /* If BFD64, sign extend val. */
3555 if (!use_rela_relocations)
3556 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3557 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
3559 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3561 #ifdef BFD_ASSEMBLER
3562 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3564 && exp_seg != text_section
3565 && exp_seg != data_section
3566 && exp_seg != bss_section
3567 && exp_seg != undefined_section
3568 #ifdef BFD_ASSEMBLER
3569 && !bfd_is_com_section (exp_seg)
3573 #ifdef BFD_ASSEMBLER
3574 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3576 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3583 /* This is an address. The size of the address will be
3584 determined later, depending on destination register,
3585 suffix, or the default for the section. */
3586 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3592 static char *i386_scale PARAMS ((char *));
3599 char *save = input_line_pointer;
3601 input_line_pointer = scale;
3602 val = get_absolute_expression ();
3608 i.log2_scale_factor = 0;
3611 i.log2_scale_factor = 1;
3614 i.log2_scale_factor = 2;
3617 i.log2_scale_factor = 3;
3620 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3622 input_line_pointer = save;
3625 if (i.log2_scale_factor != 0 && i.index_reg == 0)
3627 as_warn (_("scale factor of %d without an index register"),
3628 1 << i.log2_scale_factor);
3629 #if SCALE1_WHEN_NO_INDEX
3630 i.log2_scale_factor = 0;
3633 scale = input_line_pointer;
3634 input_line_pointer = save;
3638 static int i386_displacement PARAMS ((char *, char *));
3641 i386_displacement (disp_start, disp_end)
3647 char *save_input_line_pointer;
3649 char *gotfree_input_line;
3651 int bigdisp = Disp32;
3653 if (flag_code == CODE_64BIT)
3655 if (i.prefix[ADDR_PREFIX] == 0)
3658 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3660 i.types[this_operand] |= bigdisp;
3662 exp = &disp_expressions[i.disp_operands];
3663 i.op[this_operand].disps = exp;
3665 save_input_line_pointer = input_line_pointer;
3666 input_line_pointer = disp_start;
3667 END_STRING_AND_SAVE (disp_end);
3669 #ifndef GCC_ASM_O_HACK
3670 #define GCC_ASM_O_HACK 0
3673 END_STRING_AND_SAVE (disp_end + 1);
3674 if ((i.types[this_operand] & BaseIndex) != 0
3675 && displacement_string_end[-1] == '+')
3677 /* This hack is to avoid a warning when using the "o"
3678 constraint within gcc asm statements.
3681 #define _set_tssldt_desc(n,addr,limit,type) \
3682 __asm__ __volatile__ ( \
3684 "movw %w1,2+%0\n\t" \
3686 "movb %b1,4+%0\n\t" \
3687 "movb %4,5+%0\n\t" \
3688 "movb $0,6+%0\n\t" \
3689 "movb %h1,7+%0\n\t" \
3691 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3693 This works great except that the output assembler ends
3694 up looking a bit weird if it turns out that there is
3695 no offset. You end up producing code that looks like:
3708 So here we provide the missing zero. */
3710 *displacement_string_end = '0';
3714 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3715 if (gotfree_input_line)
3716 input_line_pointer = gotfree_input_line;
3719 exp_seg = expression (exp);
3722 if (*input_line_pointer)
3723 as_bad (_("junk `%s' after expression"), input_line_pointer);
3725 RESTORE_END_STRING (disp_end + 1);
3727 RESTORE_END_STRING (disp_end);
3728 input_line_pointer = save_input_line_pointer;
3730 if (gotfree_input_line)
3731 free (gotfree_input_line);
3734 #ifdef BFD_ASSEMBLER
3735 /* We do this to make sure that the section symbol is in
3736 the symbol table. We will ultimately change the relocation
3737 to be relative to the beginning of the section. */
3738 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3739 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3741 if (exp->X_op != O_symbol)
3743 as_bad (_("bad expression used with @%s"),
3744 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3750 if (S_IS_LOCAL (exp->X_add_symbol)
3751 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3752 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
3753 exp->X_op = O_subtract;
3754 exp->X_op_symbol = GOT_symbol;
3755 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3756 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
3758 i.reloc[this_operand] = BFD_RELOC_32;
3762 if (exp->X_op == O_absent || exp->X_op == O_big)
3764 /* Missing or bad expr becomes absolute 0. */
3765 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3767 exp->X_op = O_constant;
3768 exp->X_add_number = 0;
3769 exp->X_add_symbol = (symbolS *) 0;
3770 exp->X_op_symbol = (symbolS *) 0;
3773 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3774 if (exp->X_op != O_constant
3775 #ifdef BFD_ASSEMBLER
3776 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3778 && exp_seg != text_section
3779 && exp_seg != data_section
3780 && exp_seg != bss_section
3781 && exp_seg != undefined_section)
3783 #ifdef BFD_ASSEMBLER
3784 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3786 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3791 else if (flag_code == CODE_64BIT)
3792 i.types[this_operand] |= Disp32S | Disp32;
3796 static int i386_index_check PARAMS ((const char *));
3798 /* Make sure the memory operand we've been dealt is valid.
3799 Return 1 on success, 0 on a failure. */
3802 i386_index_check (operand_string)
3803 const char *operand_string;
3806 #if INFER_ADDR_PREFIX
3812 if (flag_code == CODE_64BIT)
3814 if (i.prefix[ADDR_PREFIX] == 0)
3818 && ((i.base_reg->reg_type & Reg64) == 0)
3819 && (i.base_reg->reg_type != BaseIndex
3822 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3823 != (Reg64 | BaseIndex))))
3830 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3832 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3833 != (Reg32 | BaseIndex))))
3839 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3843 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3844 != (Reg16 | BaseIndex)))
3846 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3847 != (Reg16 | BaseIndex))
3849 && i.base_reg->reg_num < 6
3850 && i.index_reg->reg_num >= 6
3851 && i.log2_scale_factor == 0))))
3858 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3860 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3861 != (Reg32 | BaseIndex))))
3867 #if INFER_ADDR_PREFIX
3868 if (flag_code != CODE_64BIT
3869 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
3871 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3873 /* Change the size of any displacement too. At most one of
3874 Disp16 or Disp32 is set.
3875 FIXME. There doesn't seem to be any real need for separate
3876 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3877 Removing them would probably clean up the code quite a lot. */
3878 if (i.types[this_operand] & (Disp16 | Disp32))
3879 i.types[this_operand] ^= (Disp16 | Disp32);
3884 as_bad (_("`%s' is not a valid base/index expression"),
3888 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3890 flag_code_names[flag_code]);
3896 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3900 i386_operand (operand_string)
3901 char *operand_string;
3905 char *op_string = operand_string;
3907 if (is_space_char (*op_string))
3910 /* We check for an absolute prefix (differentiating,
3911 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3912 if (*op_string == ABSOLUTE_PREFIX)
3915 if (is_space_char (*op_string))
3917 i.types[this_operand] |= JumpAbsolute;
3920 /* Check if operand is a register. */
3921 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3922 && (r = parse_register (op_string, &end_op)) != NULL)
3924 /* Check for a segment override by searching for ':' after a
3925 segment register. */
3927 if (is_space_char (*op_string))
3929 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3934 i.seg[i.mem_operands] = &es;
3937 i.seg[i.mem_operands] = &cs;
3940 i.seg[i.mem_operands] = &ss;
3943 i.seg[i.mem_operands] = &ds;
3946 i.seg[i.mem_operands] = &fs;
3949 i.seg[i.mem_operands] = &gs;
3953 /* Skip the ':' and whitespace. */
3955 if (is_space_char (*op_string))
3958 if (!is_digit_char (*op_string)
3959 && !is_identifier_char (*op_string)
3960 && *op_string != '('
3961 && *op_string != ABSOLUTE_PREFIX)
3963 as_bad (_("bad memory operand `%s'"), op_string);
3966 /* Handle case of %es:*foo. */
3967 if (*op_string == ABSOLUTE_PREFIX)
3970 if (is_space_char (*op_string))
3972 i.types[this_operand] |= JumpAbsolute;
3974 goto do_memory_reference;
3978 as_bad (_("junk `%s' after register"), op_string);
3981 i.types[this_operand] |= r->reg_type & ~BaseIndex;
3982 i.op[this_operand].regs = r;
3985 else if (*op_string == REGISTER_PREFIX)
3987 as_bad (_("bad register name `%s'"), op_string);
3990 else if (*op_string == IMMEDIATE_PREFIX)
3993 if (i.types[this_operand] & JumpAbsolute)
3995 as_bad (_("immediate operand illegal with absolute jump"));
3998 if (!i386_immediate (op_string))
4001 else if (is_digit_char (*op_string)
4002 || is_identifier_char (*op_string)
4003 || *op_string == '(')
4005 /* This is a memory reference of some sort. */
4008 /* Start and end of displacement string expression (if found). */
4009 char *displacement_string_start;
4010 char *displacement_string_end;
4012 do_memory_reference:
4013 if ((i.mem_operands == 1
4014 && (current_templates->start->opcode_modifier & IsString) == 0)
4015 || i.mem_operands == 2)
4017 as_bad (_("too many memory references for `%s'"),
4018 current_templates->start->name);
4022 /* Check for base index form. We detect the base index form by
4023 looking for an ')' at the end of the operand, searching
4024 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4026 base_string = op_string + strlen (op_string);
4029 if (is_space_char (*base_string))
4032 /* If we only have a displacement, set-up for it to be parsed later. */
4033 displacement_string_start = op_string;
4034 displacement_string_end = base_string + 1;
4036 if (*base_string == ')')
4039 unsigned int parens_balanced = 1;
4040 /* We've already checked that the number of left & right ()'s are
4041 equal, so this loop will not be infinite. */
4045 if (*base_string == ')')
4047 if (*base_string == '(')
4050 while (parens_balanced);
4052 temp_string = base_string;
4054 /* Skip past '(' and whitespace. */
4056 if (is_space_char (*base_string))
4059 if (*base_string == ','
4060 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4061 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
4063 displacement_string_end = temp_string;
4065 i.types[this_operand] |= BaseIndex;
4069 base_string = end_op;
4070 if (is_space_char (*base_string))
4074 /* There may be an index reg or scale factor here. */
4075 if (*base_string == ',')
4078 if (is_space_char (*base_string))
4081 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4082 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
4084 base_string = end_op;
4085 if (is_space_char (*base_string))
4087 if (*base_string == ',')
4090 if (is_space_char (*base_string))
4093 else if (*base_string != ')')
4095 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4100 else if (*base_string == REGISTER_PREFIX)
4102 as_bad (_("bad register name `%s'"), base_string);
4106 /* Check for scale factor. */
4107 if (*base_string != ')')
4109 char *end_scale = i386_scale (base_string);
4114 base_string = end_scale;
4115 if (is_space_char (*base_string))
4117 if (*base_string != ')')
4119 as_bad (_("expecting `)' after scale factor in `%s'"),
4124 else if (!i.index_reg)
4126 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4131 else if (*base_string != ')')
4133 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4138 else if (*base_string == REGISTER_PREFIX)
4140 as_bad (_("bad register name `%s'"), base_string);
4145 /* If there's an expression beginning the operand, parse it,
4146 assuming displacement_string_start and
4147 displacement_string_end are meaningful. */
4148 if (displacement_string_start != displacement_string_end)
4150 if (!i386_displacement (displacement_string_start,
4151 displacement_string_end))
4155 /* Special case for (%dx) while doing input/output op. */
4157 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4159 && i.log2_scale_factor == 0
4160 && i.seg[i.mem_operands] == 0
4161 && (i.types[this_operand] & Disp) == 0)
4163 i.types[this_operand] = InOutPortReg;
4167 if (i386_index_check (operand_string) == 0)
4173 /* It's not a memory operand; argh! */
4174 as_bad (_("invalid char %s beginning operand %d `%s'"),
4175 output_invalid (*op_string),
4180 return 1; /* Normal return. */
4183 /* md_estimate_size_before_relax()
4185 Called just before relax() for rs_machine_dependent frags. The x86
4186 assembler uses these frags to handle variable size jump
4189 Any symbol that is now undefined will not become defined.
4190 Return the correct fr_subtype in the frag.
4191 Return the initial "guess for variable size of frag" to caller.
4192 The guess is actually the growth beyond the fixed part. Whatever
4193 we do to grow the fixed or variable part contributes to our
4197 md_estimate_size_before_relax (fragP, segment)
4201 /* We've already got fragP->fr_subtype right; all we have to do is
4202 check for un-relaxable symbols. On an ELF system, we can't relax
4203 an externally visible symbol, because it may be overridden by a
4205 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
4206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4207 || S_IS_EXTERNAL (fragP->fr_symbol)
4208 || S_IS_WEAK (fragP->fr_symbol)
4212 /* Symbol is undefined in this segment, or we need to keep a
4213 reloc so that weak symbols can be overridden. */
4214 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
4215 RELOC_ENUM reloc_type;
4216 unsigned char *opcode;
4219 if (fragP->fr_var != NO_RELOC)
4220 reloc_type = fragP->fr_var;
4222 reloc_type = BFD_RELOC_16_PCREL;
4224 reloc_type = BFD_RELOC_32_PCREL;
4226 old_fr_fix = fragP->fr_fix;
4227 opcode = (unsigned char *) fragP->fr_opcode;
4229 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
4232 /* Make jmp (0xeb) a (d)word displacement jump. */
4234 fragP->fr_fix += size;
4235 fix_new (fragP, old_fr_fix, size,
4237 fragP->fr_offset, 1,
4243 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
4245 /* Negate the condition, and branch past an
4246 unconditional jump. */
4249 /* Insert an unconditional jump. */
4251 /* We added two extra opcode bytes, and have a two byte
4253 fragP->fr_fix += 2 + 2;
4254 fix_new (fragP, old_fr_fix + 2, 2,
4256 fragP->fr_offset, 1,
4263 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4266 fix_new (fragP, old_fr_fix, 1,
4268 fragP->fr_offset, 1,
4273 /* This changes the byte-displacement jump 0x7N
4274 to the (d)word-displacement jump 0x0f,0x8N. */
4275 opcode[1] = opcode[0] + 0x10;
4276 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4277 /* We've added an opcode byte. */
4278 fragP->fr_fix += 1 + size;
4279 fix_new (fragP, old_fr_fix + 1, size,
4281 fragP->fr_offset, 1,
4286 BAD_CASE (fragP->fr_subtype);
4290 return fragP->fr_fix - old_fr_fix;
4293 /* Guess size depending on current relax state. Initially the relax
4294 state will correspond to a short jump and we return 1, because
4295 the variable part of the frag (the branch offset) is one byte
4296 long. However, we can relax a section more than once and in that
4297 case we must either set fr_subtype back to the unrelaxed state,
4298 or return the value for the appropriate branch. */
4299 return md_relax_table[fragP->fr_subtype].rlx_length;
4302 /* Called after relax() is finished.
4304 In: Address of frag.
4305 fr_type == rs_machine_dependent.
4306 fr_subtype is what the address relaxed to.
4308 Out: Any fixSs and constants are set up.
4309 Caller will turn frag into a ".space 0". */
4311 #ifndef BFD_ASSEMBLER
4313 md_convert_frag (headers, sec, fragP)
4314 object_headers *headers ATTRIBUTE_UNUSED;
4315 segT sec ATTRIBUTE_UNUSED;
4319 md_convert_frag (abfd, sec, fragP)
4320 bfd *abfd ATTRIBUTE_UNUSED;
4321 segT sec ATTRIBUTE_UNUSED;
4325 unsigned char *opcode;
4326 unsigned char *where_to_put_displacement = NULL;
4327 offsetT target_address;
4328 offsetT opcode_address;
4329 unsigned int extension = 0;
4330 offsetT displacement_from_opcode_start;
4332 opcode = (unsigned char *) fragP->fr_opcode;
4334 /* Address we want to reach in file space. */
4335 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4337 /* Address opcode resides at in file space. */
4338 opcode_address = fragP->fr_address + fragP->fr_fix;
4340 /* Displacement from opcode start to fill into instruction. */
4341 displacement_from_opcode_start = target_address - opcode_address;
4343 if ((fragP->fr_subtype & BIG) == 0)
4345 /* Don't have to change opcode. */
4346 extension = 1; /* 1 opcode + 1 displacement */
4347 where_to_put_displacement = &opcode[1];
4351 if (no_cond_jump_promotion
4352 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4353 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4355 switch (fragP->fr_subtype)
4357 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4358 extension = 4; /* 1 opcode + 4 displacement */
4360 where_to_put_displacement = &opcode[1];
4363 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4364 extension = 2; /* 1 opcode + 2 displacement */
4366 where_to_put_displacement = &opcode[1];
4369 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4370 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4371 extension = 5; /* 2 opcode + 4 displacement */
4372 opcode[1] = opcode[0] + 0x10;
4373 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4374 where_to_put_displacement = &opcode[2];
4377 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4378 extension = 3; /* 2 opcode + 2 displacement */
4379 opcode[1] = opcode[0] + 0x10;
4380 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4381 where_to_put_displacement = &opcode[2];
4384 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4389 where_to_put_displacement = &opcode[3];
4393 BAD_CASE (fragP->fr_subtype);
4398 /* Now put displacement after opcode. */
4399 md_number_to_chars ((char *) where_to_put_displacement,
4400 (valueT) (displacement_from_opcode_start - extension),
4401 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4402 fragP->fr_fix += extension;
4405 /* Size of byte displacement jmp. */
4406 int md_short_jump_size = 2;
4408 /* Size of dword displacement jmp. */
4409 int md_long_jump_size = 5;
4411 /* Size of relocation record. */
4412 const int md_reloc_size = 8;
4415 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4417 addressT from_addr, to_addr;
4418 fragS *frag ATTRIBUTE_UNUSED;
4419 symbolS *to_symbol ATTRIBUTE_UNUSED;
4423 offset = to_addr - (from_addr + 2);
4424 /* Opcode for byte-disp jump. */
4425 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4426 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4430 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4432 addressT from_addr, to_addr;
4433 fragS *frag ATTRIBUTE_UNUSED;
4434 symbolS *to_symbol ATTRIBUTE_UNUSED;
4438 offset = to_addr - (from_addr + 5);
4439 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4440 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4443 /* Apply a fixup (fixS) to segment data, once it has been determined
4444 by our caller that we have all the info we need to fix it up.
4446 On the 386, immediates, displacements, and data pointers are all in
4447 the same (little-endian) format, so we don't need to care about which
4451 md_apply_fix3 (fixP, valP, seg)
4452 /* The fix we're to put in. */
4454 /* Pointer to the value of the bits. */
4456 /* Segment fix is from. */
4457 segT seg ATTRIBUTE_UNUSED;
4459 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4460 valueT value = * valP;
4462 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4465 switch (fixP->fx_r_type)
4471 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4474 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4477 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4482 /* This is a hack. There should be a better way to handle this.
4483 This covers for the fact that bfd_install_relocation will
4484 subtract the current location (for partial_inplace, PC relative
4485 relocations); see more below. */
4486 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
4487 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4488 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4489 && fixP->fx_addsy && !use_rela_relocations)
4492 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4494 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4497 value += fixP->fx_where + fixP->fx_frag->fr_address;
4499 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4500 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4502 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4505 || (symbol_section_p (fixP->fx_addsy)
4506 && fseg != absolute_section))
4507 && !S_IS_EXTERNAL (fixP->fx_addsy)
4508 && !S_IS_WEAK (fixP->fx_addsy)
4509 && S_IS_DEFINED (fixP->fx_addsy)
4510 && !S_IS_COMMON (fixP->fx_addsy))
4512 /* Yes, we add the values in twice. This is because
4513 bfd_perform_relocation subtracts them out again. I think
4514 bfd_perform_relocation is broken, but I don't dare change
4516 value += fixP->fx_where + fixP->fx_frag->fr_address;
4520 #if defined (OBJ_COFF) && defined (TE_PE)
4521 /* For some reason, the PE format does not store a section
4522 address offset for a PC relative symbol. */
4523 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4524 value += md_pcrel_from (fixP);
4528 /* Fix a few things - the dynamic linker expects certain values here,
4529 and we must not dissappoint it. */
4530 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4531 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4533 switch (fixP->fx_r_type)
4535 case BFD_RELOC_386_PLT32:
4536 case BFD_RELOC_X86_64_PLT32:
4537 /* Make the jump instruction point to the address of the operand. At
4538 runtime we merely add the offset to the actual PLT entry. */
4541 case BFD_RELOC_386_GOTPC:
4543 /* This is tough to explain. We end up with this one if we have
4544 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4545 * here is to obtain the absolute address of the GOT, and it is strongly
4546 * preferable from a performance point of view to avoid using a runtime
4547 * relocation for this. The actual sequence of instructions often look
4553 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4555 * The call and pop essentially return the absolute address of
4556 * the label .L66 and store it in %ebx. The linker itself will
4557 * ultimately change the first operand of the addl so that %ebx points to
4558 * the GOT, but to keep things simple, the .o file must have this operand
4559 * set so that it generates not the absolute address of .L66, but the
4560 * absolute address of itself. This allows the linker itself simply
4561 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4562 * added in, and the addend of the relocation is stored in the operand
4563 * field for the instruction itself.
4565 * Our job here is to fix the operand so that it would add the correct
4566 * offset so that %ebx would point to itself. The thing that is tricky is
4567 * that .-.L66 will point to the beginning of the instruction, so we need
4568 * to further modify the operand so that it will point to itself.
4569 * There are other cases where you have something like:
4571 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4573 * and here no correction would be required. Internally in the assembler
4574 * we treat operands of this form as not being pcrel since the '.' is
4575 * explicitly mentioned, and I wonder whether it would simplify matters
4576 * to do it this way. Who knows. In earlier versions of the PIC patches,
4577 * the pcrel_adjust field was used to store the correction, but since the
4578 * expression is not pcrel, I felt it would be confusing to do it this
4583 case BFD_RELOC_386_GOT32:
4584 case BFD_RELOC_X86_64_GOT32:
4585 value = 0; /* Fully resolved at runtime. No addend. */
4587 case BFD_RELOC_386_GOTOFF:
4588 case BFD_RELOC_X86_64_GOTPCREL:
4591 case BFD_RELOC_VTABLE_INHERIT:
4592 case BFD_RELOC_VTABLE_ENTRY:
4599 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4601 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4603 /* Are we finished with this relocation now? */
4604 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4606 #ifdef BFD_ASSEMBLER
4607 else if (use_rela_relocations)
4609 fixP->fx_no_overflow = 1;
4610 /* Remember value for tc_gen_reloc. */
4611 fixP->fx_addnumber = value;
4615 md_number_to_chars (p, value, fixP->fx_size);
4618 #define MAX_LITTLENUMS 6
4620 /* Turn the string pointed to by litP into a floating point constant
4621 of type TYPE, and emit the appropriate bytes. The number of
4622 LITTLENUMS emitted is stored in *SIZEP. An error message is
4623 returned, or NULL on OK. */
4626 md_atof (type, litP, sizeP)
4632 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4633 LITTLENUM_TYPE *wordP;
4655 return _("Bad call to md_atof ()");
4657 t = atof_ieee (input_line_pointer, type, words);
4659 input_line_pointer = t;
4661 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4662 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4663 the bigendian 386. */
4664 for (wordP = words + prec - 1; prec--;)
4666 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4667 litP += sizeof (LITTLENUM_TYPE);
4672 char output_invalid_buf[8];
4679 sprintf (output_invalid_buf, "'%c'", c);
4681 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4682 return output_invalid_buf;
4685 /* REG_STRING starts *before* REGISTER_PREFIX. */
4687 static const reg_entry *
4688 parse_register (reg_string, end_op)
4692 char *s = reg_string;
4694 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4697 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4698 if (*s == REGISTER_PREFIX)
4701 if (is_space_char (*s))
4705 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
4707 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
4708 return (const reg_entry *) NULL;
4712 /* For naked regs, make sure that we are not dealing with an identifier.
4713 This prevents confusing an identifier like `eax_var' with register
4715 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4716 return (const reg_entry *) NULL;
4720 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4722 /* Handle floating point regs, allowing spaces in the (i) part. */
4723 if (r == i386_regtab /* %st is first entry of table */)
4725 if (is_space_char (*s))
4730 if (is_space_char (*s))
4732 if (*s >= '0' && *s <= '7')
4734 r = &i386_float_regtab[*s - '0'];
4736 if (is_space_char (*s))
4744 /* We have "%st(" then garbage. */
4745 return (const reg_entry *) NULL;
4750 && (r->reg_flags & (RegRex64 | RegRex)) != 0
4751 && flag_code != CODE_64BIT)
4753 return (const reg_entry *) NULL;
4759 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4760 const char *md_shortopts = "kVQ:sq";
4762 const char *md_shortopts = "q";
4765 struct option md_longopts[] = {
4766 #define OPTION_32 (OPTION_MD_BASE + 0)
4767 {"32", no_argument, NULL, OPTION_32},
4768 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4769 #define OPTION_64 (OPTION_MD_BASE + 1)
4770 {"64", no_argument, NULL, OPTION_64},
4772 {NULL, no_argument, NULL, 0}
4774 size_t md_longopts_size = sizeof (md_longopts);
4777 md_parse_option (c, arg)
4779 char *arg ATTRIBUTE_UNUSED;
4787 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4788 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4789 should be emitted or not. FIXME: Not implemented. */
4793 /* -V: SVR4 argument to print version ID. */
4795 print_version_id ();
4798 /* -k: Ignore for FreeBSD compatibility. */
4803 /* -s: On i386 Solaris, this tells the native assembler to use
4804 .stab instead of .stab.excl. We always use .stab anyhow. */
4809 const char **list, **l;
4811 list = bfd_target_list ();
4812 for (l = list; *l != NULL; l++)
4813 if (strcmp (*l, "elf64-x86-64") == 0)
4815 default_arch = "x86_64";
4819 as_fatal (_("No compiled in support for x86_64"));
4826 default_arch = "i386";
4836 md_show_usage (stream)
4839 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4840 fprintf (stream, _("\
4842 -V print assembler version number\n\
4844 -q quieten some warnings\n\
4847 fprintf (stream, _("\
4848 -q quieten some warnings\n"));
4852 #ifdef BFD_ASSEMBLER
4853 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4854 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4856 /* Pick the target format to use. */
4859 i386_target_format ()
4861 if (!strcmp (default_arch, "x86_64"))
4862 set_code_flag (CODE_64BIT);
4863 else if (!strcmp (default_arch, "i386"))
4864 set_code_flag (CODE_32BIT);
4866 as_fatal (_("Unknown architecture"));
4867 switch (OUTPUT_FLAVOR)
4869 #ifdef OBJ_MAYBE_AOUT
4870 case bfd_target_aout_flavour:
4871 return AOUT_TARGET_FORMAT;
4873 #ifdef OBJ_MAYBE_COFF
4874 case bfd_target_coff_flavour:
4877 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4878 case bfd_target_elf_flavour:
4880 if (flag_code == CODE_64BIT)
4881 use_rela_relocations = 1;
4882 return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386";
4891 #endif /* OBJ_MAYBE_ more than one */
4893 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4894 void i386_elf_emit_arch_note ()
4896 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4897 && cpu_arch_name != NULL)
4900 asection *seg = now_seg;
4901 subsegT subseg = now_subseg;
4902 Elf_Internal_Note i_note;
4903 Elf_External_Note e_note;
4904 asection *note_secp;
4907 /* Create the .note section. */
4908 note_secp = subseg_new (".note", 0);
4909 bfd_set_section_flags (stdoutput,
4911 SEC_HAS_CONTENTS | SEC_READONLY);
4913 /* Process the arch string. */
4914 len = strlen (cpu_arch_name);
4916 i_note.namesz = len + 1;
4918 i_note.type = NT_ARCH;
4919 p = frag_more (sizeof (e_note.namesz));
4920 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
4921 p = frag_more (sizeof (e_note.descsz));
4922 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
4923 p = frag_more (sizeof (e_note.type));
4924 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
4925 p = frag_more (len + 1);
4926 strcpy (p, cpu_arch_name);
4928 frag_align (2, 0, 0);
4930 subseg_set (seg, subseg);
4934 #endif /* BFD_ASSEMBLER */
4937 md_undefined_symbol (name)
4940 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
4941 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
4942 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
4943 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
4947 if (symbol_find (name))
4948 as_bad (_("GOT already in symbol table"));
4949 GOT_symbol = symbol_new (name, undefined_section,
4950 (valueT) 0, &zero_address_frag);
4957 /* Round up a section size to the appropriate boundary. */
4960 md_section_align (segment, size)
4961 segT segment ATTRIBUTE_UNUSED;
4964 #ifdef BFD_ASSEMBLER
4965 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4966 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
4968 /* For a.out, force the section size to be aligned. If we don't do
4969 this, BFD will align it for us, but it will not write out the
4970 final bytes of the section. This may be a bug in BFD, but it is
4971 easier to fix it here since that is how the other a.out targets
4975 align = bfd_get_section_alignment (stdoutput, segment);
4976 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
4984 /* On the i386, PC-relative offsets are relative to the start of the
4985 next instruction. That is, the address of the offset, plus its
4986 size, since the offset is always the last part of the insn. */
4989 md_pcrel_from (fixP)
4992 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
4999 int ignore ATTRIBUTE_UNUSED;
5003 temp = get_absolute_expression ();
5004 subseg_set (bss_section, (subsegT) temp);
5005 demand_empty_rest_of_line ();
5010 #ifdef BFD_ASSEMBLER
5013 i386_validate_fix (fixp)
5016 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5018 /* GOTOFF relocation are nonsense in 64bit mode. */
5019 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5021 if (flag_code != CODE_64BIT)
5023 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5027 if (flag_code == CODE_64BIT)
5029 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5036 tc_gen_reloc (section, fixp)
5037 asection *section ATTRIBUTE_UNUSED;
5041 bfd_reloc_code_real_type code;
5043 switch (fixp->fx_r_type)
5045 case BFD_RELOC_X86_64_PLT32:
5046 case BFD_RELOC_X86_64_GOT32:
5047 case BFD_RELOC_X86_64_GOTPCREL:
5048 case BFD_RELOC_386_PLT32:
5049 case BFD_RELOC_386_GOT32:
5050 case BFD_RELOC_386_GOTOFF:
5051 case BFD_RELOC_386_GOTPC:
5052 case BFD_RELOC_X86_64_32S:
5054 case BFD_RELOC_VTABLE_ENTRY:
5055 case BFD_RELOC_VTABLE_INHERIT:
5056 code = fixp->fx_r_type;
5061 switch (fixp->fx_size)
5064 as_bad_where (fixp->fx_file, fixp->fx_line,
5065 _("can not do %d byte pc-relative relocation"),
5067 code = BFD_RELOC_32_PCREL;
5069 case 1: code = BFD_RELOC_8_PCREL; break;
5070 case 2: code = BFD_RELOC_16_PCREL; break;
5071 case 4: code = BFD_RELOC_32_PCREL; break;
5076 switch (fixp->fx_size)
5079 as_bad_where (fixp->fx_file, fixp->fx_line,
5080 _("can not do %d byte relocation"),
5082 code = BFD_RELOC_32;
5084 case 1: code = BFD_RELOC_8; break;
5085 case 2: code = BFD_RELOC_16; break;
5086 case 4: code = BFD_RELOC_32; break;
5088 case 8: code = BFD_RELOC_64; break;
5095 if (code == BFD_RELOC_32
5097 && fixp->fx_addsy == GOT_symbol)
5099 /* We don't support GOTPC on 64bit targets. */
5100 if (flag_code == CODE_64BIT)
5102 code = BFD_RELOC_386_GOTPC;
5105 rel = (arelent *) xmalloc (sizeof (arelent));
5106 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5107 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5109 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
5110 if (!use_rela_relocations)
5112 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5113 vtable entry to be used in the relocation's section offset. */
5114 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5115 rel->address = fixp->fx_offset;
5118 rel->addend = fixp->fx_addnumber;
5122 /* Use the rela in 64bit mode. */
5125 if (!fixp->fx_pcrel)
5126 rel->addend = fixp->fx_offset;
5130 case BFD_RELOC_X86_64_PLT32:
5131 case BFD_RELOC_X86_64_GOT32:
5132 case BFD_RELOC_X86_64_GOTPCREL:
5133 rel->addend = fixp->fx_offset - fixp->fx_size;
5136 rel->addend = (section->vma
5138 + fixp->fx_addnumber
5139 + md_pcrel_from (fixp));
5144 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5145 if (rel->howto == NULL)
5147 as_bad_where (fixp->fx_file, fixp->fx_line,
5148 _("cannot represent relocation type %s"),
5149 bfd_get_reloc_code_name (code));
5150 /* Set howto to a garbage value so that we can keep going. */
5151 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5152 assert (rel->howto != NULL);
5158 #else /* !BFD_ASSEMBLER */
5160 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5162 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5165 relax_addressT segment_address_in_file;
5167 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5168 Out: GNU LD relocation length code: 0, 1, or 2. */
5170 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
5173 know (fixP->fx_addsy != NULL);
5175 md_number_to_chars (where,
5176 (valueT) (fixP->fx_frag->fr_address
5177 + fixP->fx_where - segment_address_in_file),
5180 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5181 ? S_GET_TYPE (fixP->fx_addsy)
5182 : fixP->fx_addsy->sy_number);
5184 where[6] = (r_symbolnum >> 16) & 0x0ff;
5185 where[5] = (r_symbolnum >> 8) & 0x0ff;
5186 where[4] = r_symbolnum & 0x0ff;
5187 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
5188 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
5189 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
5192 #endif /* OBJ_AOUT or OBJ_BOUT. */
5194 #if defined (I386COFF)
5197 tc_coff_fix2rtype (fixP)
5200 if (fixP->fx_r_type == R_IMAGEBASE)
5203 return (fixP->fx_pcrel ?
5204 (fixP->fx_size == 1 ? R_PCRBYTE :
5205 fixP->fx_size == 2 ? R_PCRWORD :
5207 (fixP->fx_size == 1 ? R_RELBYTE :
5208 fixP->fx_size == 2 ? R_RELWORD :
5213 tc_coff_sizemachdep (frag)
5217 return (frag->fr_next->fr_address - frag->fr_address);
5222 #endif /* I386COFF */
5224 #endif /* !BFD_ASSEMBLER */
5226 /* Parse operands using Intel syntax. This implements a recursive descent
5227 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5230 FIXME: We do not recognize the full operand grammar defined in the MASM
5231 documentation. In particular, all the structure/union and
5232 high-level macro operands are missing.
5234 Uppercase words are terminals, lower case words are non-terminals.
5235 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5236 bars '|' denote choices. Most grammar productions are implemented in
5237 functions called 'intel_<production>'.
5239 Initial production is 'expr'.
5245 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5247 constant digits [[ radixOverride ]]
5249 dataType BYTE | WORD | DWORD | QWORD | XWORD
5282 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5283 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5285 hexdigit a | b | c | d | e | f
5286 | A | B | C | D | E | F
5296 register specialRegister
5300 segmentRegister CS | DS | ES | FS | GS | SS
5302 specialRegister CR0 | CR2 | CR3
5303 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5304 | TR3 | TR4 | TR5 | TR6 | TR7
5306 We simplify the grammar in obvious places (e.g., register parsing is
5307 done by calling parse_register) and eliminate immediate left recursion
5308 to implement a recursive-descent parser.
5348 /* Parsing structure for the intel syntax parser. Used to implement the
5349 semantic actions for the operand grammar. */
5350 struct intel_parser_s
5352 char *op_string; /* The string being parsed. */
5353 int got_a_float; /* Whether the operand is a float. */
5354 int op_modifier; /* Operand modifier. */
5355 int is_mem; /* 1 if operand is memory reference. */
5356 const reg_entry *reg; /* Last register reference found. */
5357 char *disp; /* Displacement string being built. */
5360 static struct intel_parser_s intel_parser;
5362 /* Token structure for parsing intel syntax. */
5365 int code; /* Token code. */
5366 const reg_entry *reg; /* Register entry for register tokens. */
5367 char *str; /* String representation. */
5370 static struct intel_token cur_token, prev_token;
5372 /* Token codes for the intel parser. Since T_SHORT is already used
5373 by COFF, undefine it first to prevent a warning. */
5388 /* Prototypes for intel parser functions. */
5389 static int intel_match_token PARAMS ((int code));
5390 static void intel_get_token PARAMS ((void));
5391 static void intel_putback_token PARAMS ((void));
5392 static int intel_expr PARAMS ((void));
5393 static int intel_e05 PARAMS ((void));
5394 static int intel_e05_1 PARAMS ((void));
5395 static int intel_e06 PARAMS ((void));
5396 static int intel_e06_1 PARAMS ((void));
5397 static int intel_e09 PARAMS ((void));
5398 static int intel_e09_1 PARAMS ((void));
5399 static int intel_e10 PARAMS ((void));
5400 static int intel_e10_1 PARAMS ((void));
5401 static int intel_e11 PARAMS ((void));
5404 i386_intel_operand (operand_string, got_a_float)
5405 char *operand_string;
5411 /* Initialize token holders. */
5412 cur_token.code = prev_token.code = T_NIL;
5413 cur_token.reg = prev_token.reg = NULL;
5414 cur_token.str = prev_token.str = NULL;
5416 /* Initialize parser structure. */
5417 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
5420 strcpy (intel_parser.op_string, operand_string);
5421 intel_parser.got_a_float = got_a_float;
5422 intel_parser.op_modifier = -1;
5423 intel_parser.is_mem = 0;
5424 intel_parser.reg = NULL;
5425 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
5426 if (intel_parser.disp == NULL)
5428 intel_parser.disp[0] = '\0';
5430 /* Read the first token and start the parser. */
5432 ret = intel_expr ();
5436 /* If we found a memory reference, hand it over to i386_displacement
5437 to fill in the rest of the operand fields. */
5438 if (intel_parser.is_mem)
5440 if ((i.mem_operands == 1
5441 && (current_templates->start->opcode_modifier & IsString) == 0)
5442 || i.mem_operands == 2)
5444 as_bad (_("too many memory references for '%s'"),
5445 current_templates->start->name);
5450 char *s = intel_parser.disp;
5453 /* Add the displacement expression. */
5455 ret = i386_displacement (s, s + strlen (s))
5456 && i386_index_check (s);
5460 /* Constant and OFFSET expressions are handled by i386_immediate. */
5461 else if (intel_parser.op_modifier == OFFSET_FLAT
5462 || intel_parser.reg == NULL)
5463 ret = i386_immediate (intel_parser.disp);
5467 free (intel_parser.disp);
5477 /* expr SHORT e05 */
5478 if (cur_token.code == T_SHORT)
5480 intel_parser.op_modifier = SHORT;
5481 intel_match_token (T_SHORT);
5483 return (intel_e05 ());
5488 return intel_e05 ();
5498 return (intel_e06 () && intel_e05_1 ());
5504 /* e05' addOp e06 e05' */
5505 if (cur_token.code == '+' || cur_token.code == '-')
5507 strcat (intel_parser.disp, cur_token.str);
5508 intel_match_token (cur_token.code);
5510 return (intel_e06 () && intel_e05_1 ());
5525 return (intel_e09 () && intel_e06_1 ());
5531 /* e06' mulOp e09 e06' */
5532 if (cur_token.code == '*' || cur_token.code == '/')
5534 strcat (intel_parser.disp, cur_token.str);
5535 intel_match_token (cur_token.code);
5537 return (intel_e09 () && intel_e06_1 ());
5545 /* e09 OFFSET e10 e09'
5554 /* e09 OFFSET e10 e09' */
5555 if (cur_token.code == T_OFFSET)
5557 intel_parser.is_mem = 0;
5558 intel_parser.op_modifier = OFFSET_FLAT;
5559 intel_match_token (T_OFFSET);
5561 return (intel_e10 () && intel_e09_1 ());
5566 return (intel_e10 () && intel_e09_1 ());
5572 /* e09' PTR e10 e09' */
5573 if (cur_token.code == T_PTR)
5575 if (prev_token.code == T_BYTE)
5576 i.suffix = BYTE_MNEM_SUFFIX;
5578 else if (prev_token.code == T_WORD)
5580 if (intel_parser.got_a_float == 2) /* "fi..." */
5581 i.suffix = SHORT_MNEM_SUFFIX;
5583 i.suffix = WORD_MNEM_SUFFIX;
5586 else if (prev_token.code == T_DWORD)
5588 if (intel_parser.got_a_float == 1) /* "f..." */
5589 i.suffix = SHORT_MNEM_SUFFIX;
5591 i.suffix = LONG_MNEM_SUFFIX;
5594 else if (prev_token.code == T_QWORD)
5596 if (intel_parser.got_a_float == 1) /* "f..." */
5597 i.suffix = LONG_MNEM_SUFFIX;
5599 i.suffix = QWORD_MNEM_SUFFIX;
5602 else if (prev_token.code == T_XWORD)
5603 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5607 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5611 intel_match_token (T_PTR);
5613 return (intel_e10 () && intel_e09_1 ());
5616 /* e09 : e10 e09' */
5617 else if (cur_token.code == ':')
5619 /* Mark as a memory operand only if it's not already known to be an
5620 offset expression. */
5621 if (intel_parser.op_modifier != OFFSET_FLAT)
5622 intel_parser.is_mem = 1;
5624 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5639 return (intel_e11 () && intel_e10_1 ());
5645 /* e10' [ expr ] e10' */
5646 if (cur_token.code == '[')
5648 intel_match_token ('[');
5650 /* Mark as a memory operand only if it's not already known to be an
5651 offset expression. If it's an offset expression, we need to keep
5653 if (intel_parser.op_modifier != OFFSET_FLAT)
5654 intel_parser.is_mem = 1;
5656 strcat (intel_parser.disp, "[");
5658 /* Add a '+' to the displacement string if necessary. */
5659 if (*intel_parser.disp != '\0'
5660 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5661 strcat (intel_parser.disp, "+");
5663 if (intel_expr () && intel_match_token (']'))
5665 /* Preserve brackets when the operand is an offset expression. */
5666 if (intel_parser.op_modifier == OFFSET_FLAT)
5667 strcat (intel_parser.disp, "]");
5669 return intel_e10_1 ();
5696 if (cur_token.code == '(')
5698 intel_match_token ('(');
5699 strcat (intel_parser.disp, "(");
5701 if (intel_expr () && intel_match_token (')'))
5703 strcat (intel_parser.disp, ")");
5711 else if (cur_token.code == '[')
5713 intel_match_token ('[');
5715 /* Mark as a memory operand only if it's not already known to be an
5716 offset expression. If it's an offset expression, we need to keep
5718 if (intel_parser.op_modifier != OFFSET_FLAT)
5719 intel_parser.is_mem = 1;
5721 strcat (intel_parser.disp, "[");
5723 /* Operands for jump/call inside brackets denote absolute addresses. */
5724 if (current_templates->start->opcode_modifier & Jump
5725 || current_templates->start->opcode_modifier & JumpDword
5726 || current_templates->start->opcode_modifier & JumpByte
5727 || current_templates->start->opcode_modifier & JumpInterSegment)
5728 i.types[this_operand] |= JumpAbsolute;
5730 /* Add a '+' to the displacement string if necessary. */
5731 if (*intel_parser.disp != '\0'
5732 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5733 strcat (intel_parser.disp, "+");
5735 if (intel_expr () && intel_match_token (']'))
5737 /* Preserve brackets when the operand is an offset expression. */
5738 if (intel_parser.op_modifier == OFFSET_FLAT)
5739 strcat (intel_parser.disp, "]");
5752 else if (cur_token.code == T_BYTE
5753 || cur_token.code == T_WORD
5754 || cur_token.code == T_DWORD
5755 || cur_token.code == T_QWORD
5756 || cur_token.code == T_XWORD)
5758 intel_match_token (cur_token.code);
5765 else if (cur_token.code == '$' || cur_token.code == '.')
5767 strcat (intel_parser.disp, cur_token.str);
5768 intel_match_token (cur_token.code);
5770 /* Mark as a memory operand only if it's not already known to be an
5771 offset expression. */
5772 if (intel_parser.op_modifier != OFFSET_FLAT)
5773 intel_parser.is_mem = 1;
5779 else if (cur_token.code == T_REG)
5781 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5783 intel_match_token (T_REG);
5785 /* Check for segment change. */
5786 if (cur_token.code == ':')
5788 if (reg->reg_type & (SReg2 | SReg3))
5790 switch (reg->reg_num)
5793 i.seg[i.mem_operands] = &es;
5796 i.seg[i.mem_operands] = &cs;
5799 i.seg[i.mem_operands] = &ss;
5802 i.seg[i.mem_operands] = &ds;
5805 i.seg[i.mem_operands] = &fs;
5808 i.seg[i.mem_operands] = &gs;
5814 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5819 /* Not a segment register. Check for register scaling. */
5820 else if (cur_token.code == '*')
5822 if (!intel_parser.is_mem)
5824 as_bad (_("Register scaling only allowed in memory operands."));
5828 /* What follows must be a valid scale. */
5829 if (intel_match_token ('*')
5830 && strchr ("01248", *cur_token.str))
5833 i.types[this_operand] |= BaseIndex;
5835 /* Set the scale after setting the register (otherwise,
5836 i386_scale will complain) */
5837 i386_scale (cur_token.str);
5838 intel_match_token (T_CONST);
5842 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5848 /* No scaling. If this is a memory operand, the register is either a
5849 base register (first occurrence) or an index register (second
5851 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5853 if (i.base_reg && i.index_reg)
5855 as_bad (_("Too many register references in memory operand.\n"));
5859 if (i.base_reg == NULL)
5864 i.types[this_operand] |= BaseIndex;
5867 /* Offset modifier. Add the register to the displacement string to be
5868 parsed as an immediate expression after we're done. */
5869 else if (intel_parser.op_modifier == OFFSET_FLAT)
5870 strcat (intel_parser.disp, reg->reg_name);
5872 /* It's neither base nor index nor offset. */
5875 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5876 i.op[this_operand].regs = reg;
5880 /* Since registers are not part of the displacement string (except
5881 when we're parsing offset operands), we may need to remove any
5882 preceding '+' from the displacement string. */
5883 if (*intel_parser.disp != '\0'
5884 && intel_parser.op_modifier != OFFSET_FLAT)
5886 char *s = intel_parser.disp;
5887 s += strlen (s) - 1;
5896 else if (cur_token.code == T_ID)
5898 /* Add the identifier to the displacement string. */
5899 strcat (intel_parser.disp, cur_token.str);
5900 intel_match_token (T_ID);
5902 /* The identifier represents a memory reference only if it's not
5903 preceded by an offset modifier. */
5904 if (intel_parser.op_modifier != OFFSET_FLAT)
5905 intel_parser.is_mem = 1;
5911 else if (cur_token.code == T_CONST
5912 || cur_token.code == '-'
5913 || cur_token.code == '+')
5917 /* Allow constants that start with `+' or `-'. */
5918 if (cur_token.code == '-' || cur_token.code == '+')
5920 strcat (intel_parser.disp, cur_token.str);
5921 intel_match_token (cur_token.code);
5922 if (cur_token.code != T_CONST)
5924 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5930 save_str = (char *) malloc (strlen (cur_token.str) + 1);
5931 if (save_str == NULL)
5933 strcpy (save_str, cur_token.str);
5935 /* Get the next token to check for register scaling. */
5936 intel_match_token (cur_token.code);
5938 /* Check if this constant is a scaling factor for an index register. */
5939 if (cur_token.code == '*')
5941 if (intel_match_token ('*') && cur_token.code == T_REG)
5943 if (!intel_parser.is_mem)
5945 as_bad (_("Register scaling only allowed in memory operands."));
5949 /* The constant is followed by `* reg', so it must be
5951 if (strchr ("01248", *save_str))
5953 i.index_reg = cur_token.reg;
5954 i.types[this_operand] |= BaseIndex;
5956 /* Set the scale after setting the register (otherwise,
5957 i386_scale will complain) */
5958 i386_scale (save_str);
5959 intel_match_token (T_REG);
5961 /* Since registers are not part of the displacement
5962 string, we may need to remove any preceding '+' from
5963 the displacement string. */
5964 if (*intel_parser.disp != '\0')
5966 char *s = intel_parser.disp;
5967 s += strlen (s) - 1;
5980 /* The constant was not used for register scaling. Since we have
5981 already consumed the token following `*' we now need to put it
5982 back in the stream. */
5984 intel_putback_token ();
5987 /* Add the constant to the displacement string. */
5988 strcat (intel_parser.disp, save_str);
5994 as_bad (_("Unrecognized token '%s'"), cur_token.str);
5998 /* Match the given token against cur_token. If they match, read the next
5999 token from the operand string. */
6001 intel_match_token (code)
6004 if (cur_token.code == code)
6011 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6016 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6021 const reg_entry *reg;
6022 struct intel_token new_token;
6024 new_token.code = T_NIL;
6025 new_token.reg = NULL;
6026 new_token.str = NULL;
6028 /* Free the memory allocated to the previous token and move
6029 cur_token to prev_token. */
6031 free (prev_token.str);
6033 prev_token = cur_token;
6035 /* Skip whitespace. */
6036 while (is_space_char (*intel_parser.op_string))
6037 intel_parser.op_string++;
6039 /* Return an empty token if we find nothing else on the line. */
6040 if (*intel_parser.op_string == '\0')
6042 cur_token = new_token;
6046 /* The new token cannot be larger than the remainder of the operand
6048 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
6049 if (new_token.str == NULL)
6051 new_token.str[0] = '\0';
6053 if (strchr ("0123456789", *intel_parser.op_string))
6055 char *p = new_token.str;
6056 char *q = intel_parser.op_string;
6057 new_token.code = T_CONST;
6059 /* Allow any kind of identifier char to encompass floating point and
6060 hexadecimal numbers. */
6061 while (is_identifier_char (*q))
6065 /* Recognize special symbol names [0-9][bf]. */
6066 if (strlen (intel_parser.op_string) == 2
6067 && (intel_parser.op_string[1] == 'b'
6068 || intel_parser.op_string[1] == 'f'))
6069 new_token.code = T_ID;
6072 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6074 new_token.code = *intel_parser.op_string;
6075 new_token.str[0] = *intel_parser.op_string;
6076 new_token.str[1] = '\0';
6079 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6080 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6082 new_token.code = T_REG;
6083 new_token.reg = reg;
6085 if (*intel_parser.op_string == REGISTER_PREFIX)
6087 new_token.str[0] = REGISTER_PREFIX;
6088 new_token.str[1] = '\0';
6091 strcat (new_token.str, reg->reg_name);
6094 else if (is_identifier_char (*intel_parser.op_string))
6096 char *p = new_token.str;
6097 char *q = intel_parser.op_string;
6099 /* A '.' or '$' followed by an identifier char is an identifier.
6100 Otherwise, it's operator '.' followed by an expression. */
6101 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6103 new_token.code = *q;
6104 new_token.str[0] = *q;
6105 new_token.str[1] = '\0';
6109 while (is_identifier_char (*q) || *q == '@')
6113 if (strcasecmp (new_token.str, "BYTE") == 0)
6114 new_token.code = T_BYTE;
6116 else if (strcasecmp (new_token.str, "WORD") == 0)
6117 new_token.code = T_WORD;
6119 else if (strcasecmp (new_token.str, "DWORD") == 0)
6120 new_token.code = T_DWORD;
6122 else if (strcasecmp (new_token.str, "QWORD") == 0)
6123 new_token.code = T_QWORD;
6125 else if (strcasecmp (new_token.str, "XWORD") == 0)
6126 new_token.code = T_XWORD;
6128 else if (strcasecmp (new_token.str, "PTR") == 0)
6129 new_token.code = T_PTR;
6131 else if (strcasecmp (new_token.str, "SHORT") == 0)
6132 new_token.code = T_SHORT;
6134 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6136 new_token.code = T_OFFSET;
6138 /* ??? This is not mentioned in the MASM grammar but gcc
6139 makes use of it with -mintel-syntax. OFFSET may be
6140 followed by FLAT: */
6141 if (strncasecmp (q, " FLAT:", 6) == 0)
6142 strcat (new_token.str, " FLAT:");
6145 /* ??? This is not mentioned in the MASM grammar. */
6146 else if (strcasecmp (new_token.str, "FLAT") == 0)
6147 new_token.code = T_OFFSET;
6150 new_token.code = T_ID;
6155 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6157 intel_parser.op_string += strlen (new_token.str);
6158 cur_token = new_token;
6161 /* Put cur_token back into the token stream and make cur_token point to
6164 intel_putback_token ()
6166 intel_parser.op_string -= strlen (cur_token.str);
6167 free (cur_token.str);
6168 cur_token = prev_token;
6170 /* Forget prev_token. */
6171 prev_token.code = T_NIL;
6172 prev_token.reg = NULL;
6173 prev_token.str = NULL;