1 /* Subroutines for insn-output.c for Intel X86.
2 Copyright (C) 1988, 92, 94-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
21 /* $FreeBSD: src/contrib/gcc/config/i386/i386.c,v 1.7 2000/01/29 13:06:33 obrien Exp $ */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
43 #ifdef EXTRA_CONSTRAINT
44 /* If EXTRA_CONSTRAINT is defined, then the 'S'
45 constraint in REG_CLASS_FROM_LETTER will no longer work, and various
46 asm statements that need 'S' for class SIREG will break. */
47 error EXTRA_CONSTRAINT conflicts with S constraint letter
48 /* The previous line used to be #error, but some compilers barf
49 even if the conditional was untrue. */
52 #ifndef CHECK_STACK_LIMIT
53 #define CHECK_STACK_LIMIT -1
56 #define PIC_REG_USED \
57 (flag_pic && (current_function_uses_pic_offset_table \
58 || current_function_uses_const_pool \
59 || profile_flag || profile_block_flag))
61 /* Type of an operand for ix86_{binary,unary}_operator_ok */
69 /* Processor costs (relative to an add) */
70 struct processor_costs i386_cost = { /* 386 specific costs */
71 1, /* cost of an add instruction */
72 1, /* cost of a lea instruction */
73 3, /* variable shift costs */
74 2, /* constant shift costs */
75 6, /* cost of starting a multiply */
76 1, /* cost of multiply per each bit set */
77 23 /* cost of a divide/mod */
80 struct processor_costs i486_cost = { /* 486 specific costs */
81 1, /* cost of an add instruction */
82 1, /* cost of a lea instruction */
83 3, /* variable shift costs */
84 2, /* constant shift costs */
85 12, /* cost of starting a multiply */
86 1, /* cost of multiply per each bit set */
87 40 /* cost of a divide/mod */
90 struct processor_costs pentium_cost = {
91 1, /* cost of an add instruction */
92 1, /* cost of a lea instruction */
93 4, /* variable shift costs */
94 1, /* constant shift costs */
95 11, /* cost of starting a multiply */
96 0, /* cost of multiply per each bit set */
97 25 /* cost of a divide/mod */
100 struct processor_costs pentiumpro_cost = {
101 1, /* cost of an add instruction */
102 1, /* cost of a lea instruction */
103 3, /* variable shift costs */
104 1, /* constant shift costs */
105 4, /* cost of starting a multiply */
106 0, /* cost of multiply per each bit set */
107 17 /* cost of a divide/mod */
110 /* We use decoding time together with execution time.
111 To get correct vale add 1 for short decodable, 2 for long decodable
112 and 4 for vector decodable instruction to execution time and divide
113 by two (because CPU is able to do two insns at a time). */
115 struct processor_costs k6_cost = {
116 1, /* cost of an add instruction */
117 1, /* cost of a lea instruction */
118 1, /* variable shift costs */
119 1, /* constant shift costs */
120 3, /* cost of starting a multiply */
121 0, /* cost of multiply per each bit set */
122 20 /* cost of a divide/mod */
125 struct processor_costs *ix86_cost = &pentium_cost;
127 /* Processor feature/optimization bitmasks. */
128 #define m_386 (1<<PROCESSOR_I386)
129 #define m_486 (1<<PROCESSOR_I486)
130 #define m_PENT (1<<PROCESSOR_PENTIUM)
131 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
132 #define m_K6 (1<<PROCESSOR_K6)
134 const int x86_use_leave = m_386 | m_K6;
135 const int x86_push_memory = m_386 | m_K6;
136 const int x86_zero_extend_with_and = m_486 | m_PENT;
137 const int x86_movx = m_386 | m_PPRO | m_K6;
138 const int x86_double_with_add = ~(m_386 | m_PENT | m_PPRO);
139 const int x86_use_bit_test = m_386;
140 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO;
141 const int x86_use_q_reg = m_PENT | m_PPRO | m_K6;
142 const int x86_use_any_reg = m_486;
143 const int x86_cmove = m_PPRO;
144 const int x86_deep_branch = m_PPRO| m_K6;
146 #define AT_BP(mode) (gen_rtx_MEM ((mode), frame_pointer_rtx))
148 extern FILE *asm_out_file;
149 extern char *strcat ();
151 static void ix86_epilogue PROTO((int));
152 static void ix86_prologue PROTO((int));
154 char *singlemove_string ();
155 char *output_move_const_single ();
156 char *output_fp_cc0_set ();
158 char *hi_reg_name[] = HI_REGISTER_NAMES;
159 char *qi_reg_name[] = QI_REGISTER_NAMES;
160 char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
162 /* Array of the smallest class containing reg number REGNO, indexed by
163 REGNO. Used by REGNO_REG_CLASS in i386.h. */
165 enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
168 AREG, DREG, CREG, BREG,
170 SIREG, DIREG, INDEX_REGS, GENERAL_REGS,
172 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
173 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
178 /* Test and compare insns in i386.md store the information needed to
179 generate branch and scc insns here. */
181 struct rtx_def *i386_compare_op0 = NULL_RTX;
182 struct rtx_def *i386_compare_op1 = NULL_RTX;
183 struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
185 /* which cpu are we scheduling for */
186 enum processor_type ix86_cpu;
188 /* which instruction set architecture to use. */
191 /* Strings to hold which cpu and instruction set architecture to use. */
192 char *ix86_cpu_string; /* for -mcpu=<xxx> */
193 char *ix86_arch_string; /* for -march=<xxx> */
195 /* Register allocation order */
196 char *i386_reg_alloc_order;
197 static char regs_allocated[FIRST_PSEUDO_REGISTER];
199 /* # of registers to use to pass arguments. */
200 char *i386_regparm_string;
202 /* i386_regparm_string as a number */
205 /* Alignment to use for loops and jumps: */
207 /* Power of two alignment for loops. */
208 char *i386_align_loops_string;
210 /* Power of two alignment for non-loop jumps. */
211 char *i386_align_jumps_string;
213 /* Power of two alignment for stack boundary in bytes. */
214 char *i386_preferred_stack_boundary_string;
216 /* Preferred alignment for stack boundary in bits. */
217 int i386_preferred_stack_boundary;
219 /* Values 1-5: see jump.c */
220 int i386_branch_cost;
221 char *i386_branch_cost_string;
223 /* Power of two alignment for functions. */
224 int i386_align_funcs;
225 char *i386_align_funcs_string;
227 /* Power of two alignment for loops. */
228 int i386_align_loops;
230 /* Power of two alignment for non-loop jumps. */
231 int i386_align_jumps;
233 /* Sometimes certain combinations of command options do not make
234 sense on a particular target machine. You can define a macro
235 `OVERRIDE_OPTIONS' to take account of this. This macro, if
236 defined, is executed once just after all the command options have
239 Don't use this macro to turn on various extra optimizations for
240 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
250 char *name; /* Canonical processor name. */
251 enum processor_type processor; /* Processor type enum value. */
252 struct processor_costs *cost; /* Processor costs */
253 int target_enable; /* Target flags to enable. */
254 int target_disable; /* Target flags to disable. */
255 } processor_target_table[] = {
256 {PROCESSOR_I386_STRING, PROCESSOR_I386, &i386_cost, 0, 0},
257 {PROCESSOR_I486_STRING, PROCESSOR_I486, &i486_cost, 0, 0},
258 {PROCESSOR_I586_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
259 {PROCESSOR_PENTIUM_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
260 {PROCESSOR_I686_STRING, PROCESSOR_PENTIUMPRO, &pentiumpro_cost, 0, 0},
261 {PROCESSOR_PENTIUMPRO_STRING, PROCESSOR_PENTIUMPRO,
262 &pentiumpro_cost, 0, 0},
263 {PROCESSOR_K6_STRING, PROCESSOR_K6, &k6_cost, 0, 0}
266 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
268 #ifdef SUBTARGET_OVERRIDE_OPTIONS
269 SUBTARGET_OVERRIDE_OPTIONS;
272 /* Validate registers in register allocation order. */
273 if (i386_reg_alloc_order)
275 for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
281 case 'a': regno = 0; break;
282 case 'd': regno = 1; break;
283 case 'c': regno = 2; break;
284 case 'b': regno = 3; break;
285 case 'S': regno = 4; break;
286 case 'D': regno = 5; break;
287 case 'B': regno = 6; break;
289 default: fatal ("Register '%c' is unknown", ch);
292 if (regs_allocated[regno])
293 fatal ("Register '%c' already specified in allocation order", ch);
295 regs_allocated[regno] = 1;
299 if (ix86_arch_string == 0)
301 ix86_arch_string = PROCESSOR_PENTIUM_STRING;
302 if (ix86_cpu_string == 0)
303 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
306 for (i = 0; i < ptt_size; i++)
307 if (! strcmp (ix86_arch_string, processor_target_table[i].name))
309 ix86_arch = processor_target_table[i].processor;
310 if (ix86_cpu_string == 0)
311 ix86_cpu_string = processor_target_table[i].name;
317 error ("bad value (%s) for -march= switch", ix86_arch_string);
318 ix86_arch_string = PROCESSOR_PENTIUM_STRING;
319 ix86_arch = PROCESSOR_DEFAULT;
322 if (ix86_cpu_string == 0)
323 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
325 for (j = 0; j < ptt_size; j++)
326 if (! strcmp (ix86_cpu_string, processor_target_table[j].name))
328 ix86_cpu = processor_target_table[j].processor;
329 ix86_cost = processor_target_table[j].cost;
330 if (i > j && (int) ix86_arch >= (int) PROCESSOR_K6)
331 error ("-mcpu=%s does not support -march=%s",
332 ix86_cpu_string, ix86_arch_string);
334 target_flags |= processor_target_table[j].target_enable;
335 target_flags &= ~processor_target_table[j].target_disable;
341 error ("bad value (%s) for -mcpu= switch", ix86_cpu_string);
342 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
343 ix86_cpu = PROCESSOR_DEFAULT;
346 /* Validate -mregparm= value. */
347 if (i386_regparm_string)
349 i386_regparm = atoi (i386_regparm_string);
350 if (i386_regparm < 0 || i386_regparm > REGPARM_MAX)
351 fatal ("-mregparm=%d is not between 0 and %d",
352 i386_regparm, REGPARM_MAX);
355 /* The 486 suffers more from non-aligned cache line fills, and the
356 larger code size results in a larger cache foot-print and more misses.
357 The 486 has a 16 byte cache line, pentium and pentiumpro have a 32 byte
359 def_align = (TARGET_486) ? 4 : 2;
361 /* Validate -malign-loops= value, or provide default. */
362 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
363 i386_align_loops = 4;
365 i386_align_loops = 2;
367 if (i386_align_loops_string)
369 i386_align_loops = atoi (i386_align_loops_string);
370 if (i386_align_loops < 0 || i386_align_loops > MAX_CODE_ALIGN)
371 fatal ("-malign-loops=%d is not between 0 and %d",
372 i386_align_loops, MAX_CODE_ALIGN);
375 /* Validate -malign-jumps= value, or provide default. */
376 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
377 i386_align_jumps = 4;
379 i386_align_jumps = def_align;
381 if (i386_align_jumps_string)
383 i386_align_jumps = atoi (i386_align_jumps_string);
384 if (i386_align_jumps < 0 || i386_align_jumps > MAX_CODE_ALIGN)
385 fatal ("-malign-jumps=%d is not between 0 and %d",
386 i386_align_jumps, MAX_CODE_ALIGN);
389 /* Validate -malign-functions= value, or provide default. */
390 i386_align_funcs = def_align;
391 if (i386_align_funcs_string)
393 i386_align_funcs = atoi (i386_align_funcs_string);
394 if (i386_align_funcs < 0 || i386_align_funcs > MAX_CODE_ALIGN)
395 fatal ("-malign-functions=%d is not between 0 and %d",
396 i386_align_funcs, MAX_CODE_ALIGN);
399 /* Validate -mpreferred_stack_boundary= value, or provide default.
400 The default of 128 bits is for Pentium III's SSE __m128. */
401 i386_preferred_stack_boundary = 128;
402 if (i386_preferred_stack_boundary_string)
404 i = atoi (i386_preferred_stack_boundary_string);
406 fatal ("-mpreferred_stack_boundary=%d is not between 2 and 31", i);
407 i386_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
410 /* Validate -mbranch-cost= value, or provide default. */
411 i386_branch_cost = 1;
412 if (i386_branch_cost_string)
414 i386_branch_cost = atoi (i386_branch_cost_string);
415 if (i386_branch_cost < 0 || i386_branch_cost > 5)
416 fatal ("-mbranch-cost=%d is not between 0 and 5", i386_branch_cost);
419 /* Keep nonleaf frame pointers. */
420 if (TARGET_OMIT_LEAF_FRAME_POINTER)
421 flag_omit_frame_pointer = 1;
424 /* A C statement (sans semicolon) to choose the order in which to
425 allocate hard registers for pseudo-registers local to a basic
428 Store the desired register order in the array `reg_alloc_order'.
429 Element 0 should be the register to allocate first; element 1, the
430 next register; and so on.
432 The macro body should not assume anything about the contents of
433 `reg_alloc_order' before execution of the macro.
435 On most machines, it is not necessary to define this macro. */
438 order_regs_for_local_alloc ()
442 /* User specified the register allocation order. */
444 if (i386_reg_alloc_order)
446 for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
452 case 'a': regno = 0; break;
453 case 'd': regno = 1; break;
454 case 'c': regno = 2; break;
455 case 'b': regno = 3; break;
456 case 'S': regno = 4; break;
457 case 'D': regno = 5; break;
458 case 'B': regno = 6; break;
461 reg_alloc_order[order++] = regno;
464 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
466 if (! regs_allocated[i])
467 reg_alloc_order[order++] = i;
471 /* If user did not specify a register allocation order, use natural order. */
474 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
475 reg_alloc_order[i] = i;
480 optimization_options (level, size)
482 int size ATTRIBUTE_UNUSED;
484 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
485 make the problem with not enough registers even worse. */
486 #ifdef INSN_SCHEDULING
488 flag_schedule_insns = 0;
492 /* Sign-extend a 16-bit constant */
495 i386_sext16_if_const (op)
498 if (GET_CODE (op) == CONST_INT)
500 HOST_WIDE_INT val = INTVAL (op);
501 HOST_WIDE_INT sext_val;
503 sext_val = val | ~0xffff;
505 sext_val = val & 0xffff;
507 op = GEN_INT (sext_val);
512 /* Return nonzero if the rtx is aligned */
515 i386_aligned_reg_p (regno)
518 return (regno == STACK_POINTER_REGNUM
519 || (! flag_omit_frame_pointer && regno == FRAME_POINTER_REGNUM));
526 /* Registers and immediate operands are always "aligned". */
527 if (GET_CODE (op) != MEM)
530 /* Don't even try to do any aligned optimizations with volatiles. */
531 if (MEM_VOLATILE_P (op))
534 /* Get address of memory operand. */
537 switch (GET_CODE (op))
544 /* Match "reg + offset" */
546 if (GET_CODE (XEXP (op, 1)) != CONST_INT)
548 if (INTVAL (XEXP (op, 1)) & 3)
552 if (GET_CODE (op) != REG)
555 /* ... fall through ... */
558 return i386_aligned_reg_p (REGNO (op));
567 /* Return nonzero if INSN looks like it won't compute useful cc bits
568 as a side effect. This information is only a hint. */
571 i386_cc_probably_useless_p (insn)
574 return ! next_cc0_user (insn);
577 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
578 attribute for DECL. The attributes in ATTRIBUTES have previously been
582 i386_valid_decl_attribute_p (decl, attributes, identifier, args)
583 tree decl ATTRIBUTE_UNUSED;
584 tree attributes ATTRIBUTE_UNUSED;
585 tree identifier ATTRIBUTE_UNUSED;
586 tree args ATTRIBUTE_UNUSED;
591 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
592 attribute for TYPE. The attributes in ATTRIBUTES have previously been
596 i386_valid_type_attribute_p (type, attributes, identifier, args)
598 tree attributes ATTRIBUTE_UNUSED;
602 if (TREE_CODE (type) != FUNCTION_TYPE
603 && TREE_CODE (type) != METHOD_TYPE
604 && TREE_CODE (type) != FIELD_DECL
605 && TREE_CODE (type) != TYPE_DECL)
608 /* Stdcall attribute says callee is responsible for popping arguments
609 if they are not variable. */
610 if (is_attribute_p ("stdcall", identifier))
611 return (args == NULL_TREE);
613 /* Cdecl attribute says the callee is a normal C declaration. */
614 if (is_attribute_p ("cdecl", identifier))
615 return (args == NULL_TREE);
617 /* Regparm attribute specifies how many integer arguments are to be
618 passed in registers. */
619 if (is_attribute_p ("regparm", identifier))
623 if (! args || TREE_CODE (args) != TREE_LIST
624 || TREE_CHAIN (args) != NULL_TREE
625 || TREE_VALUE (args) == NULL_TREE)
628 cst = TREE_VALUE (args);
629 if (TREE_CODE (cst) != INTEGER_CST)
632 if (TREE_INT_CST_HIGH (cst) != 0
633 || TREE_INT_CST_LOW (cst) < 0
634 || TREE_INT_CST_LOW (cst) > REGPARM_MAX)
643 /* Return 0 if the attributes for two types are incompatible, 1 if they
644 are compatible, and 2 if they are nearly compatible (which causes a
645 warning to be generated). */
648 i386_comp_type_attributes (type1, type2)
652 /* Check for mismatch of non-default calling convention. */
653 char *rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
655 if (TREE_CODE (type1) != FUNCTION_TYPE)
658 /* Check for mismatched return types (cdecl vs stdcall). */
659 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
660 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
666 /* Value is the number of bytes of arguments automatically
667 popped when returning from a subroutine call.
668 FUNDECL is the declaration node of the function (as a tree),
669 FUNTYPE is the data type of the function (as a tree),
670 or for a library call it is an identifier node for the subroutine name.
671 SIZE is the number of bytes of arguments passed on the stack.
673 On the 80386, the RTD insn may be used to pop them if the number
674 of args is fixed, but if the number is variable then the caller
675 must pop them all. RTD can't be used for library calls now
676 because the library is compiled with the Unix compiler.
677 Use of RTD is a selectable option, since it is incompatible with
678 standard Unix calling sequences. If the option is not selected,
679 the caller must always pop the args.
681 The attribute stdcall is equivalent to RTD on a per module basis. */
684 i386_return_pops_args (fundecl, funtype, size)
689 int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
691 /* Cdecl functions override -mrtd, and never pop the stack. */
692 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {
694 /* Stdcall functions will pop the stack if not variable args. */
695 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype)))
699 && (TYPE_ARG_TYPES (funtype) == NULL_TREE
700 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype)))
705 /* Lose any fake structure return argument. */
706 if (aggregate_value_p (TREE_TYPE (funtype)))
707 return GET_MODE_SIZE (Pmode);
713 /* Argument support functions. */
715 /* Initialize a variable CUM of type CUMULATIVE_ARGS
716 for a call to a function whose data type is FNTYPE.
717 For a library call, FNTYPE is 0. */
720 init_cumulative_args (cum, fntype, libname)
721 CUMULATIVE_ARGS *cum; /* Argument info to initialize */
722 tree fntype; /* tree ptr for function decl */
723 rtx libname; /* SYMBOL_REF of library name or 0 */
725 static CUMULATIVE_ARGS zero_cum;
726 tree param, next_param;
728 if (TARGET_DEBUG_ARG)
730 fprintf (stderr, "\ninit_cumulative_args (");
732 fprintf (stderr, "fntype code = %s, ret code = %s",
733 tree_code_name[(int) TREE_CODE (fntype)],
734 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]);
736 fprintf (stderr, "no fntype");
739 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
744 /* Set up the number of registers to use for passing arguments. */
745 cum->nregs = i386_regparm;
748 tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype));
751 cum->nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
754 /* Determine if this function has variable arguments. This is
755 indicated by the last argument being 'void_type_mode' if there
756 are no variable arguments. If there are variable arguments, then
757 we won't pass anything in registers */
761 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
762 param != 0; param = next_param)
764 next_param = TREE_CHAIN (param);
765 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
770 if (TARGET_DEBUG_ARG)
771 fprintf (stderr, ", nregs=%d )\n", cum->nregs);
776 /* Update the data in CUM to advance over an argument
777 of mode MODE and data type TYPE.
778 (TYPE is null for libcalls where that information may not be available.) */
781 function_arg_advance (cum, mode, type, named)
782 CUMULATIVE_ARGS *cum; /* current arg information */
783 enum machine_mode mode; /* current arg mode */
784 tree type; /* type of the argument or 0 if lib support */
785 int named; /* whether or not the argument was named */
788 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
789 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
791 if (TARGET_DEBUG_ARG)
793 "function_adv (sz=%d, wds=%2d, nregs=%d, mode=%s, named=%d)\n\n",
794 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
809 /* Define where to put the arguments to a function.
810 Value is zero to push the argument on the stack,
811 or a hard register in which to store the argument.
813 MODE is the argument's machine mode.
814 TYPE is the data type of the argument (as a tree).
815 This is null for libcalls where that information may
817 CUM is a variable of type CUMULATIVE_ARGS which gives info about
818 the preceding args and about the function being called.
819 NAMED is nonzero if this argument is a named parameter
820 (otherwise it is an extra parameter matching an ellipsis). */
823 function_arg (cum, mode, type, named)
824 CUMULATIVE_ARGS *cum; /* current arg information */
825 enum machine_mode mode; /* current arg mode */
826 tree type; /* type of the argument or 0 if lib support */
827 int named; /* != 0 for normal args, == 0 for ... args */
831 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
832 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
836 /* For now, pass fp/complex values on the stack. */
845 if (words <= cum->nregs)
846 ret = gen_rtx_REG (mode, cum->regno);
850 if (TARGET_DEBUG_ARG)
853 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d",
854 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
857 fprintf (stderr, ", reg=%%e%s", reg_names[ REGNO(ret) ]);
859 fprintf (stderr, ", stack");
861 fprintf (stderr, " )\n");
867 /* For an arg passed partly in registers and partly in memory,
868 this is the number of registers used.
869 For args passed entirely in registers or entirely in memory, zero. */
872 function_arg_partial_nregs (cum, mode, type, named)
873 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; /* current arg information */
874 enum machine_mode mode ATTRIBUTE_UNUSED; /* current arg mode */
875 tree type ATTRIBUTE_UNUSED; /* type of the argument or 0 if lib support */
876 int named ATTRIBUTE_UNUSED; /* != 0 for normal args, == 0 for ... args */
882 singlemove_string (operands)
886 if (GET_CODE (operands[0]) == MEM
887 && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC)
889 if (XEXP (x, 0) != stack_pointer_rtx)
893 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
894 return output_move_const_single (operands);
895 else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG)
896 return AS2 (mov%L0,%1,%0);
897 else if (CONSTANT_P (operands[1]))
898 return AS2 (mov%L0,%1,%0);
901 output_asm_insn ("push%L1 %1", operands);
906 /* Output an insn to add the constant N to the register X. */
917 output_asm_insn (AS1 (dec%L0,%0), xops);
919 output_asm_insn (AS1 (inc%L0,%0), xops);
920 else if (n < 0 || n == 128)
922 xops[1] = GEN_INT (-n);
923 output_asm_insn (AS2 (sub%L0,%1,%0), xops);
927 xops[1] = GEN_INT (n);
928 output_asm_insn (AS2 (add%L0,%1,%0), xops);
932 /* Output assembler code to perform a doubleword move insn
933 with operands OPERANDS. */
936 output_move_double (operands)
939 enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
943 int dest_overlapped_low = 0;
944 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
949 /* First classify both operands. */
951 if (REG_P (operands[0]))
953 else if (offsettable_memref_p (operands[0]))
955 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
957 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
959 else if (GET_CODE (operands[0]) == MEM)
964 if (REG_P (operands[1]))
966 else if (CONSTANT_P (operands[1]))
968 else if (offsettable_memref_p (operands[1]))
970 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
972 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
974 else if (GET_CODE (operands[1]) == MEM)
979 /* Check for the cases that are not supposed to happen
980 either due to the operand constraints or the fact
981 that all memory operands on the x86 are offsettable.
982 Abort if we get one, because generating code for these
985 if (optype0 == RNDOP || optype1 == RNDOP
986 || optype0 == MEMOP || optype1 == MEMOP)
989 /* If one operand is decrementing and one is incrementing
990 decrement the former register explicitly
991 and change that operand into ordinary indexing. */
993 if (optype0 == PUSHOP && optype1 == POPOP)
995 /* ??? Can this ever happen on i386? */
996 operands[0] = XEXP (XEXP (operands[0], 0), 0);
997 asm_add (-size, operands[0]);
998 if (GET_MODE (operands[1]) == XFmode)
999 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
1000 else if (GET_MODE (operands[0]) == DFmode)
1001 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
1003 operands[0] = gen_rtx_MEM (DImode, operands[0]);
1007 if (optype0 == POPOP && optype1 == PUSHOP)
1009 /* ??? Can this ever happen on i386? */
1010 operands[1] = XEXP (XEXP (operands[1], 0), 0);
1011 asm_add (-size, operands[1]);
1012 if (GET_MODE (operands[1]) == XFmode)
1013 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
1014 else if (GET_MODE (operands[1]) == DFmode)
1015 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
1017 operands[1] = gen_rtx_MEM (DImode, operands[1]);
1021 /* Ok, we can do one word at a time.
1022 Normally we do the low-numbered word first,
1023 but if either operand is autodecrementing then we
1024 do the high-numbered word first.
1026 In either case, set up in LATEHALF the operands to use
1027 for the high-numbered word and in some cases alter the
1028 operands in OPERANDS to be suitable for the low-numbered word. */
1032 if (optype0 == REGOP)
1034 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1035 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
1037 else if (optype0 == OFFSOP)
1039 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
1040 latehalf[0] = adj_offsettable_operand (operands[0], 8);
1044 middlehalf[0] = operands[0];
1045 latehalf[0] = operands[0];
1048 if (optype1 == REGOP)
1050 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1051 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1053 else if (optype1 == OFFSOP)
1055 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
1056 latehalf[1] = adj_offsettable_operand (operands[1], 8);
1058 else if (optype1 == CNSTOP)
1060 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1062 REAL_VALUE_TYPE r; long l[3];
1064 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1065 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
1066 operands[1] = GEN_INT (l[0]);
1067 middlehalf[1] = GEN_INT (l[1]);
1068 latehalf[1] = GEN_INT (l[2]);
1070 else if (CONSTANT_P (operands[1]))
1071 /* No non-CONST_DOUBLE constant should ever appear here. */
1076 middlehalf[1] = operands[1];
1077 latehalf[1] = operands[1];
1083 /* Size is not 12. */
1085 if (optype0 == REGOP)
1086 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1087 else if (optype0 == OFFSOP)
1088 latehalf[0] = adj_offsettable_operand (operands[0], 4);
1090 latehalf[0] = operands[0];
1092 if (optype1 == REGOP)
1093 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1094 else if (optype1 == OFFSOP)
1095 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1096 else if (optype1 == CNSTOP)
1097 split_double (operands[1], &operands[1], &latehalf[1]);
1099 latehalf[1] = operands[1];
1102 /* If insn is effectively movd N (sp),-(sp) then we will do the
1103 high word first. We should use the adjusted operand 1
1104 (which is N+4 (sp) or N+8 (sp))
1105 for the low word and middle word as well,
1106 to compensate for the first decrement of sp. */
1107 if (optype0 == PUSHOP
1108 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1109 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
1110 middlehalf[1] = operands[1] = latehalf[1];
1112 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1113 if the upper part of reg N does not appear in the MEM, arrange to
1114 emit the move late-half first. Otherwise, compute the MEM address
1115 into the upper part of N and use that as a pointer to the memory
1117 if (optype0 == REGOP && optype1 == OFFSOP)
1119 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
1120 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1122 /* If both halves of dest are used in the src memory address,
1123 compute the address into latehalf of dest. */
1125 xops[0] = latehalf[0];
1126 xops[1] = XEXP (operands[1], 0);
1127 output_asm_insn (AS2 (lea%L0,%a1,%0), xops);
1128 if (GET_MODE (operands[1]) == XFmode)
1130 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
1131 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
1132 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1136 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
1137 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1142 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0)))
1144 /* Check for two regs used by both source and dest. */
1145 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
1146 || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1149 /* Only the middle reg conflicts; simply put it last. */
1150 output_asm_insn (singlemove_string (operands), operands);
1151 output_asm_insn (singlemove_string (latehalf), latehalf);
1152 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1156 else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
1157 /* If the low half of dest is mentioned in the source memory
1158 address, the arrange to emit the move late half first. */
1159 dest_overlapped_low = 1;
1162 /* If one or both operands autodecrementing,
1163 do the two words, high-numbered first. */
1165 /* Likewise, the first move would clobber the source of the second one,
1166 do them in the other order. This happens only for registers;
1167 such overlap can't happen in memory unless the user explicitly
1168 sets it up, and that is an undefined circumstance. */
1171 if (optype0 == PUSHOP || optype1 == PUSHOP
1172 || (optype0 == REGOP && optype1 == REGOP
1173 && REGNO (operands[0]) == REGNO (latehalf[1]))
1174 || dest_overlapped_low)
1177 if (optype0 == PUSHOP || optype1 == PUSHOP
1178 || (optype0 == REGOP && optype1 == REGOP
1179 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
1180 || REGNO (operands[0]) == REGNO (latehalf[1])))
1181 || dest_overlapped_low)
1183 /* Do the high-numbered word. */
1184 output_asm_insn (singlemove_string (latehalf), latehalf);
1187 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1189 /* Do low-numbered word. */
1190 return singlemove_string (operands);
1193 /* Normal case: do the two words, low-numbered first. */
1195 output_asm_insn (singlemove_string (operands), operands);
1197 /* Do the middle one of the three words for long double */
1199 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1201 /* Do the high-numbered word. */
1202 output_asm_insn (singlemove_string (latehalf), latehalf);
1207 #define MAX_TMPS 2 /* max temporary registers used */
1209 /* Output the appropriate code to move push memory on the stack */
1212 output_move_pushmem (operands, insn, length, tmp_start, n_operands)
1224 } tmp_info[MAX_TMPS];
1226 rtx src = operands[1];
1229 int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src);
1230 int stack_offset = 0;
1234 if (! offsettable_memref_p (src))
1235 fatal_insn ("Source is not offsettable", insn);
1237 if ((length & 3) != 0)
1238 fatal_insn ("Pushing non-word aligned size", insn);
1240 /* Figure out which temporary registers we have available */
1241 for (i = tmp_start; i < n_operands; i++)
1243 if (GET_CODE (operands[i]) == REG)
1245 if (reg_overlap_mentioned_p (operands[i], src))
1248 tmp_info[ max_tmps++ ].xops[1] = operands[i];
1249 if (max_tmps == MAX_TMPS)
1255 for (offset = length - 4; offset >= 0; offset -= 4)
1257 xops[0] = adj_offsettable_operand (src, offset + stack_offset);
1258 output_asm_insn (AS1(push%L0,%0), xops);
1264 for (offset = length - 4; offset >= 0; )
1266 for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++)
1268 tmp_info[num_tmps].load = AS2(mov%L0,%0,%1);
1269 tmp_info[num_tmps].push = AS1(push%L0,%1);
1270 tmp_info[num_tmps].xops[0]
1271 = adj_offsettable_operand (src, offset + stack_offset);
1275 for (i = 0; i < num_tmps; i++)
1276 output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
1278 for (i = 0; i < num_tmps; i++)
1279 output_asm_insn (tmp_info[i].push, tmp_info[i].xops);
1282 stack_offset += 4*num_tmps;
1289 standard_80387_constant_p (x)
1292 #if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
1297 if (setjmp (handler))
1300 set_float_handler (handler);
1301 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1302 is0 = REAL_VALUES_EQUAL (d, dconst0) && !REAL_VALUE_MINUS_ZERO (d);
1303 is1 = REAL_VALUES_EQUAL (d, dconst1);
1304 set_float_handler (NULL_PTR);
1312 /* Note that on the 80387, other constants, such as pi,
1313 are much slower to load as standard constants
1314 than to load from doubles in memory! */
1315 /* ??? Not true on K6: all constants are equal cost. */
1322 output_move_const_single (operands)
1325 if (FP_REG_P (operands[0]))
1327 int conval = standard_80387_constant_p (operands[1]);
1336 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1338 REAL_VALUE_TYPE r; long l;
1340 if (GET_MODE (operands[1]) == XFmode)
1343 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1344 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1345 operands[1] = GEN_INT (l);
1348 return singlemove_string (operands);
1351 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1352 reference and a constant. */
1355 symbolic_operand (op, mode)
1357 enum machine_mode mode ATTRIBUTE_UNUSED;
1359 switch (GET_CODE (op))
1367 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1368 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1369 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1376 /* Return nonzero if OP is a constant shift count small enough to
1377 encode into an lea instruction. */
1380 small_shift_operand (op, mode)
1382 enum machine_mode mode ATTRIBUTE_UNUSED;
1384 return (GET_CODE (op) == CONST_INT && INTVAL (op) > 0 && INTVAL (op) < 4);
1387 /* Test for a valid operand for a call instruction.
1388 Don't allow the arg pointer register or virtual regs
1389 since they may change into reg + const, which the patterns
1390 can't handle yet. */
1393 call_insn_operand (op, mode)
1395 enum machine_mode mode ATTRIBUTE_UNUSED;
1397 if (GET_CODE (op) == MEM
1398 && ((CONSTANT_ADDRESS_P (XEXP (op, 0))
1399 /* This makes a difference for PIC. */
1400 && general_operand (XEXP (op, 0), Pmode))
1401 || (GET_CODE (XEXP (op, 0)) == REG
1402 && XEXP (op, 0) != arg_pointer_rtx
1403 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1404 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1410 /* Like call_insn_operand but allow (mem (symbol_ref ...))
1414 expander_call_insn_operand (op, mode)
1416 enum machine_mode mode ATTRIBUTE_UNUSED;
1418 if (GET_CODE (op) == MEM
1419 && (CONSTANT_ADDRESS_P (XEXP (op, 0))
1420 || (GET_CODE (XEXP (op, 0)) == REG
1421 && XEXP (op, 0) != arg_pointer_rtx
1422 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1423 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1429 /* Return 1 if OP is a comparison operator that can use the condition code
1430 generated by an arithmetic operation. */
1433 arithmetic_comparison_operator (op, mode)
1435 enum machine_mode mode;
1439 if (mode != VOIDmode && mode != GET_MODE (op))
1442 code = GET_CODE (op);
1443 if (GET_RTX_CLASS (code) != '<')
1446 return (code != GT && code != LE);
1450 ix86_logical_operator (op, mode)
1452 enum machine_mode mode ATTRIBUTE_UNUSED;
1454 return GET_CODE (op) == AND || GET_CODE (op) == IOR || GET_CODE (op) == XOR;
1458 /* Returns 1 if OP contains a symbol reference */
1461 symbolic_reference_mentioned_p (op)
1467 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1470 fmt = GET_RTX_FORMAT (GET_CODE (op));
1471 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
1477 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
1478 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
1482 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
1489 /* Attempt to expand a binary operator. Make the expansion closer to the
1490 actual machine, then just general_operand, which will allow 3 separate
1491 memory references (one output, two input) in a single insn. Return
1492 whether the insn fails, or succeeds. */
1495 ix86_expand_binary_operator (code, mode, operands)
1497 enum machine_mode mode;
1502 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
1503 if (GET_RTX_CLASS (code) == 'c'
1504 && (rtx_equal_p (operands[0], operands[2])
1505 || immediate_operand (operands[1], mode)))
1507 rtx temp = operands[1];
1508 operands[1] = operands[2];
1512 /* If optimizing, copy to regs to improve CSE */
1513 if (TARGET_PSEUDO && optimize
1514 && ((reload_in_progress | reload_completed) == 0))
1516 if (GET_CODE (operands[1]) == MEM
1517 && ! rtx_equal_p (operands[0], operands[1]))
1518 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1520 if (GET_CODE (operands[2]) == MEM)
1521 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
1523 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
1525 rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
1527 emit_move_insn (temp, operands[1]);
1533 if (!ix86_binary_operator_ok (code, mode, operands))
1535 /* If not optimizing, try to make a valid insn (optimize code
1536 previously did this above to improve chances of CSE) */
1538 if ((! TARGET_PSEUDO || !optimize)
1539 && ((reload_in_progress | reload_completed) == 0)
1540 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM))
1543 if (GET_CODE (operands[1]) == MEM
1544 && ! rtx_equal_p (operands[0], operands[1]))
1546 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1550 if (GET_CODE (operands[2]) == MEM)
1552 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
1556 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
1558 rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
1560 emit_move_insn (temp, operands[1]);
1565 if (modified && ! ix86_binary_operator_ok (code, mode, operands))
1575 /* Return TRUE or FALSE depending on whether the binary operator meets the
1576 appropriate constraints. */
1579 ix86_binary_operator_ok (code, mode, operands)
1581 enum machine_mode mode ATTRIBUTE_UNUSED;
1584 return (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
1585 && (GET_CODE (operands[1]) != CONST_INT || GET_RTX_CLASS (code) == 'c');
1588 /* Attempt to expand a unary operator. Make the expansion closer to the
1589 actual machine, then just general_operand, which will allow 2 separate
1590 memory references (one output, one input) in a single insn. Return
1591 whether the insn fails, or succeeds. */
1594 ix86_expand_unary_operator (code, mode, operands)
1596 enum machine_mode mode;
1599 /* If optimizing, copy to regs to improve CSE */
1602 && ((reload_in_progress | reload_completed) == 0)
1603 && GET_CODE (operands[1]) == MEM)
1604 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1606 if (! ix86_unary_operator_ok (code, mode, operands))
1608 if ((! TARGET_PSEUDO || optimize == 0)
1609 && ((reload_in_progress | reload_completed) == 0)
1610 && GET_CODE (operands[1]) == MEM)
1612 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1613 if (! ix86_unary_operator_ok (code, mode, operands))
1623 /* Return TRUE or FALSE depending on whether the unary operator meets the
1624 appropriate constraints. */
1627 ix86_unary_operator_ok (code, mode, operands)
1628 enum rtx_code code ATTRIBUTE_UNUSED;
1629 enum machine_mode mode ATTRIBUTE_UNUSED;
1630 rtx operands[2] ATTRIBUTE_UNUSED;
1635 static rtx pic_label_rtx;
1636 static char pic_label_name [256];
1637 static int pic_label_no = 0;
1639 /* This function generates code for -fpic that loads %ebx with
1640 the return address of the caller and then returns. */
1643 asm_output_function_prefix (file, name)
1645 char *name ATTRIBUTE_UNUSED;
1648 xops[0] = pic_offset_table_rtx;
1649 xops[1] = stack_pointer_rtx;
1651 /* Deep branch prediction favors having a return for every call. */
1652 if (PIC_REG_USED && TARGET_DEEP_BRANCH_PREDICTION)
1656 if (pic_label_rtx == 0)
1658 pic_label_rtx = gen_label_rtx ();
1659 ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++);
1660 LABEL_NAME (pic_label_rtx) = pic_label_name;
1663 prologue_node = make_node (FUNCTION_DECL);
1664 DECL_RESULT (prologue_node) = 0;
1666 /* This used to call ASM_DECLARE_FUNCTION_NAME() but since it's an
1667 internal (non-global) label that's being emitted, it didn't make
1668 sense to have .type information for local labels. This caused
1669 the SCO OpenServer 5.0.4 ELF assembler grief (why are you giving
1670 me debug info for a label that you're declaring non-global?) this
1671 was changed to call ASM_OUTPUT_LABEL() instead. */
1674 ASM_OUTPUT_LABEL (file, pic_label_name);
1675 output_asm_insn ("movl (%1),%0", xops);
1676 output_asm_insn ("ret", xops);
1680 /* Generate the assembly code for function entry.
1681 FILE is an stdio stream to output the code to.
1682 SIZE is an int: how many units of temporary storage to allocate. */
1685 function_prologue (file, size)
1686 FILE *file ATTRIBUTE_UNUSED;
1687 int size ATTRIBUTE_UNUSED;
1689 if (TARGET_SCHEDULE_PROLOGUE)
1698 /* Expand the prologue into a bunch of separate insns. */
1701 ix86_expand_prologue ()
1703 if (! TARGET_SCHEDULE_PROLOGUE)
1710 load_pic_register (do_rtl)
1715 if (TARGET_DEEP_BRANCH_PREDICTION)
1717 xops[0] = pic_offset_table_rtx;
1718 if (pic_label_rtx == 0)
1720 pic_label_rtx = gen_label_rtx ();
1721 ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++);
1722 LABEL_NAME (pic_label_rtx) = pic_label_name;
1725 xops[1] = gen_rtx_MEM (QImode,
1726 gen_rtx (SYMBOL_REF, Pmode,
1727 LABEL_NAME (pic_label_rtx)));
1731 emit_insn (gen_prologue_get_pc (xops[0], xops[1]));
1732 emit_insn (gen_prologue_set_got (xops[0],
1733 #ifdef YES_UNDERSCORES
1734 gen_rtx_SYMBOL_REF (Pmode,
1735 "$__GLOBAL_OFFSET_TABLE_"),
1737 gen_rtx_SYMBOL_REF (Pmode,
1738 "$_GLOBAL_OFFSET_TABLE_"),
1744 output_asm_insn (AS1 (call,%X1), xops);
1745 output_asm_insn ("addl $%__GLOBAL_OFFSET_TABLE_,%0", xops);
1752 xops[0] = pic_offset_table_rtx;
1753 xops[1] = gen_label_rtx ();
1757 /* We can't put a raw CODE_LABEL into the RTL, and we can't emit
1758 a new CODE_LABEL after reload, so we need a single pattern to
1759 emit the 3 necessary instructions. */
1760 emit_insn (gen_prologue_get_pc_and_set_got (xops[0]));
1764 output_asm_insn (AS1 (call,%P1), xops);
1765 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1766 CODE_LABEL_NUMBER (xops[1]));
1767 output_asm_insn (AS1 (pop%L0,%0), xops);
1768 output_asm_insn ("addl $%__GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops);
1772 /* When -fpic, we must emit a scheduling barrier, so that the instruction
1773 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get
1774 moved before any instruction which implicitly uses the got. */
1777 emit_insn (gen_blockage ());
1780 /* Compute the size of local storage taking into consideration the
1781 desired stack alignment which is to be maintained. Also determine
1782 the number of registers saved below the local storage. */
1785 ix86_compute_frame_size (size, nregs_on_stack)
1787 int *nregs_on_stack;
1793 int pic_reg_used = PIC_REG_USED;
1794 HOST_WIDE_INT total_size;
1796 limit = frame_pointer_needed
1797 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM;
1801 for (regno = limit - 1; regno >= 0; regno--)
1802 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1803 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1807 total_size = size + (nregs * UNITS_PER_WORD);
1809 #ifdef PREFERRED_STACK_BOUNDARY
1812 int preferred_alignment = PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT;
1815 if (frame_pointer_needed)
1816 offset += UNITS_PER_WORD;
1818 total_size += offset;
1820 padding = ((total_size + preferred_alignment - 1)
1821 & -preferred_alignment) - total_size;
1823 if (padding < (((offset + preferred_alignment - 1)
1824 & -preferred_alignment) - offset))
1825 padding += preferred_alignment;
1827 /* Don't bother aligning the stack of a leaf function
1828 which doesn't allocate any stack slots. */
1829 if (size == 0 && current_function_is_leaf)
1835 *nregs_on_stack = nregs;
1837 return size + padding;
1841 ix86_prologue (do_rtl)
1847 int pic_reg_used = PIC_REG_USED;
1848 HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), (int *)0);
1850 int cfa_offset = INCOMING_FRAME_SP_OFFSET, cfa_store_offset = cfa_offset;
1852 xops[0] = stack_pointer_rtx;
1853 xops[1] = frame_pointer_rtx;
1854 xops[2] = GEN_INT (tsize);
1856 if (frame_pointer_needed)
1860 insn = emit_insn (gen_rtx (SET, VOIDmode,
1861 gen_rtx_MEM (SImode,
1862 gen_rtx (PRE_DEC, SImode,
1863 stack_pointer_rtx)),
1864 frame_pointer_rtx));
1866 RTX_FRAME_RELATED_P (insn) = 1;
1867 insn = emit_move_insn (xops[1], xops[0]);
1868 RTX_FRAME_RELATED_P (insn) = 1;
1873 output_asm_insn ("push%L1 %1", xops);
1874 #ifdef INCOMING_RETURN_ADDR_RTX
1875 if (dwarf2out_do_frame ())
1877 char *l = dwarf2out_cfi_label ();
1879 cfa_store_offset += 4;
1880 cfa_offset = cfa_store_offset;
1881 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
1882 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, - cfa_store_offset);
1886 output_asm_insn (AS2 (mov%L0,%0,%1), xops);
1887 #ifdef INCOMING_RETURN_ADDR_RTX
1888 if (dwarf2out_do_frame ())
1889 dwarf2out_def_cfa ("", FRAME_POINTER_REGNUM, cfa_offset);
1896 else if (! TARGET_STACK_PROBE || tsize < CHECK_STACK_LIMIT)
1900 insn = emit_insn (gen_prologue_set_stack_ptr (xops[2]));
1901 RTX_FRAME_RELATED_P (insn) = 1;
1905 output_asm_insn (AS2 (sub%L0,%2,%0), xops);
1906 #ifdef INCOMING_RETURN_ADDR_RTX
1907 if (dwarf2out_do_frame ())
1909 cfa_store_offset += tsize;
1910 if (! frame_pointer_needed)
1912 cfa_offset = cfa_store_offset;
1913 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset);
1921 xops[3] = gen_rtx_REG (SImode, 0);
1923 emit_move_insn (xops[3], xops[2]);
1925 output_asm_insn (AS2 (mov%L0,%2,%3), xops);
1927 xops[3] = gen_rtx_MEM (FUNCTION_MODE,
1928 gen_rtx (SYMBOL_REF, Pmode, "_alloca"));
1931 emit_call_insn (gen_rtx (CALL, VOIDmode, xops[3], const0_rtx));
1933 output_asm_insn (AS1 (call,%P3), xops);
1936 /* Note If use enter it is NOT reversed args.
1937 This one is not reversed from intel!!
1938 I think enter is slower. Also sdb doesn't like it.
1939 But if you want it the code is:
1941 xops[3] = const0_rtx;
1942 output_asm_insn ("enter %2,%3", xops);
1946 limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
1947 for (regno = limit - 1; regno >= 0; regno--)
1948 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1949 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1951 xops[0] = gen_rtx_REG (SImode, regno);
1954 insn = emit_insn (gen_rtx (SET, VOIDmode,
1955 gen_rtx_MEM (SImode,
1956 gen_rtx (PRE_DEC, SImode,
1957 stack_pointer_rtx)),
1960 RTX_FRAME_RELATED_P (insn) = 1;
1964 output_asm_insn ("push%L0 %0", xops);
1965 #ifdef INCOMING_RETURN_ADDR_RTX
1966 if (dwarf2out_do_frame ())
1968 char *l = dwarf2out_cfi_label ();
1970 cfa_store_offset += 4;
1971 if (! frame_pointer_needed)
1973 cfa_offset = cfa_store_offset;
1974 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
1977 dwarf2out_reg_save (l, regno, - cfa_store_offset);
1983 #ifdef SUBTARGET_PROLOGUE
1988 load_pic_register (do_rtl);
1990 /* If we are profiling, make sure no instructions are scheduled before
1991 the call to mcount. However, if -fpic, the above call will have
1993 if ((profile_flag || profile_block_flag)
1994 && ! pic_reg_used && do_rtl)
1995 emit_insn (gen_blockage ());
1998 /* Return 1 if it is appropriate to emit `ret' instructions in the
1999 body of a function. Do this only if the epilogue is simple, needing a
2000 couple of insns. Prior to reloading, we can't tell how many registers
2001 must be saved, so return 0 then. Return 0 if there is no frame
2002 marker to de-allocate.
2004 If NON_SAVING_SETJMP is defined and true, then it is not possible
2005 for the epilogue to be simple, so return 0. This is a special case
2006 since NON_SAVING_SETJMP will not cause regs_ever_live to change
2007 until final, but jump_optimize may need to know sooner if a
2011 ix86_can_use_return_insn_p ()
2015 int reglimit = (frame_pointer_needed
2016 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
2018 #ifdef TARGET_PROFILER_EPILOGUE
2019 if (TARGET_PROFILER_EPILOGUE)
2023 #ifdef NON_SAVING_SETJMP
2024 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
2028 if (! reload_completed)
2031 for (regno = reglimit - 1; regno >= 0; regno--)
2032 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2033 || (regno == PIC_OFFSET_TABLE_REGNUM && PIC_REG_USED))
2036 return nregs == 0 || ! frame_pointer_needed;
2039 /* This function generates the assembly code for function exit.
2040 FILE is an stdio stream to output the code to.
2041 SIZE is an int: how many units of temporary storage to deallocate. */
2044 function_epilogue (file, size)
2045 FILE *file ATTRIBUTE_UNUSED;
2046 int size ATTRIBUTE_UNUSED;
2051 /* Restore function stack, frame, and registers. */
2054 ix86_expand_epilogue ()
2060 ix86_epilogue (do_rtl)
2067 int pic_reg_used = PIC_REG_USED;
2068 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
2069 HOST_WIDE_INT offset;
2070 HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), &nregs);
2072 /* sp is often unreliable so we may have to go off the frame pointer. */
2074 offset = -(tsize + nregs * UNITS_PER_WORD);
2076 xops[2] = stack_pointer_rtx;
2078 /* When -fpic, we must emit a scheduling barrier, so that the instruction
2079 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get
2080 moved before any instruction which implicitly uses the got. This
2081 includes any instruction which uses a SYMBOL_REF or a LABEL_REF.
2083 Alternatively, this could be fixed by making the dependence on the
2084 PIC_OFFSET_TABLE_REGNUM explicit in the RTL. */
2086 if (flag_pic || profile_flag || profile_block_flag)
2087 emit_insn (gen_blockage ());
2089 #ifdef FUNCTION_PROFILER_EPILOGUE
2090 FUNCTION_PROFILER_EPILOGUE (asm_out_file, do_rtl);
2093 /* If we're only restoring one register and sp is not valid then
2094 using a move instruction to restore the register since it's
2095 less work than reloading sp and popping the register. Otherwise,
2096 restore sp (if necessary) and pop the registers. */
2098 limit = frame_pointer_needed
2099 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM;
2101 if (nregs > 1 || sp_valid)
2105 xops[0] = adj_offsettable_operand (AT_BP (QImode), offset);
2107 emit_insn (gen_movsi_lea (xops[2], XEXP (xops[0], 0)));
2109 output_asm_insn (AS2 (lea%L2,%0,%2), xops);
2112 for (regno = 0; regno < limit; regno++)
2113 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2114 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2116 xops[0] = gen_rtx_REG (SImode, regno);
2119 emit_insn (gen_pop (xops[0]));
2121 output_asm_insn ("pop%L0 %0", xops);
2126 for (regno = 0; regno < limit; regno++)
2127 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2128 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2130 xops[0] = gen_rtx_REG (SImode, regno);
2131 xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset);
2134 emit_move_insn (xops[0], xops[1]);
2136 output_asm_insn (AS2 (mov%L0,%1,%0), xops);
2141 if (frame_pointer_needed)
2143 /* If not an i386, mov & pop is faster than "leave". */
2145 if (TARGET_USE_LEAVE)
2148 emit_insn (gen_leave());
2150 output_asm_insn ("leave", xops);
2154 xops[0] = frame_pointer_rtx;
2155 xops[1] = stack_pointer_rtx;
2159 emit_insn (gen_epilogue_set_stack_ptr());
2160 emit_insn (gen_pop (xops[0]));
2164 output_asm_insn (AS2 (mov%L2,%0,%2), xops);
2165 output_asm_insn ("pop%L0 %0", xops);
2172 /* Intel's docs say that for 4 or 8 bytes of stack frame one should
2173 use `pop' and not `add'. */
2174 int use_pop = tsize == 4;
2176 /* Use two pops only for the Pentium processors. */
2177 if (tsize == 8 && !TARGET_386 && !TARGET_486)
2179 rtx retval = current_function_return_rtx;
2181 xops[1] = gen_rtx_REG (SImode, 1); /* %edx */
2183 /* This case is a bit more complex. Since we cannot pop into
2184 %ecx twice we need a second register. But this is only
2185 available if the return value is not of DImode in which
2186 case the %edx register is not available. */
2187 use_pop = (retval == NULL
2188 || ! reg_overlap_mentioned_p (xops[1], retval));
2193 xops[0] = gen_rtx_REG (SImode, 2); /* %ecx */
2197 /* We have to prevent the two pops here from being scheduled.
2198 GCC otherwise would try in some situation to put other
2199 instructions in between them which has a bad effect. */
2200 emit_insn (gen_blockage ());
2201 emit_insn (gen_pop (xops[0]));
2203 emit_insn (gen_pop (xops[1]));
2207 output_asm_insn ("pop%L0 %0", xops);
2209 output_asm_insn ("pop%L1 %1", xops);
2214 /* If there is no frame pointer, we must still release the frame. */
2215 xops[0] = GEN_INT (tsize);
2218 emit_insn (gen_rtx (SET, VOIDmode, xops[2],
2219 gen_rtx (PLUS, SImode, xops[2], xops[0])));
2221 output_asm_insn (AS2 (add%L2,%0,%2), xops);
2225 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
2226 if (profile_block_flag == 2)
2228 /* XXX this is hosed like FUNCTION_PROFILER_EPILOGUE () was. */
2229 FUNCTION_BLOCK_PROFILER_EXIT(file);
2233 if (current_function_pops_args && current_function_args_size)
2235 xops[1] = GEN_INT (current_function_pops_args);
2237 /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If
2238 asked to pop more, pop return address, do explicit add, and jump
2239 indirectly to the caller. */
2241 if (current_function_pops_args >= 32768)
2243 /* ??? Which register to use here? */
2244 xops[0] = gen_rtx_REG (SImode, 2);
2248 emit_insn (gen_pop (xops[0]));
2249 emit_insn (gen_rtx (SET, VOIDmode, xops[2],
2250 gen_rtx (PLUS, SImode, xops[1], xops[2])));
2251 emit_jump_insn (xops[0]);
2255 output_asm_insn ("pop%L0 %0", xops);
2256 output_asm_insn (AS2 (add%L2,%1,%2), xops);
2257 output_asm_insn ("jmp %*%0", xops);
2263 emit_jump_insn (gen_return_pop_internal (xops[1]));
2265 output_asm_insn ("ret %1", xops);
2271 emit_jump_insn (gen_return_internal ());
2273 output_asm_insn ("ret", xops);
2277 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2278 that is a valid memory address for an instruction.
2279 The MODE argument is the machine mode for the MEM expression
2280 that wants to use this address.
2282 On x86, legitimate addresses are:
2283 base movl (base),reg
2284 displacement movl disp,reg
2285 base + displacement movl disp(base),reg
2286 index + base movl (base,index),reg
2287 (index + base) + displacement movl disp(base,index),reg
2288 index*scale movl (,index,scale),reg
2289 index*scale + disp movl disp(,index,scale),reg
2290 index*scale + base movl (base,index,scale),reg
2291 (index*scale + base) + disp movl disp(base,index,scale),reg
2293 In each case, scale can be 1, 2, 4, 8. */
2295 /* This is exactly the same as print_operand_addr, except that
2296 it recognizes addresses instead of printing them.
2298 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2299 convert common non-canonical forms to canonical form so that they will
2302 #define ADDR_INVALID(msg,insn) \
2304 if (TARGET_DEBUG_ADDR) \
2306 fprintf (stderr, msg); \
2312 legitimate_pic_address_disp_p (disp)
2315 if (GET_CODE (disp) != CONST)
2317 disp = XEXP (disp, 0);
2319 if (GET_CODE (disp) == PLUS)
2321 if (GET_CODE (XEXP (disp, 1)) != CONST_INT)
2323 disp = XEXP (disp, 0);
2326 if (GET_CODE (disp) != UNSPEC
2327 || XVECLEN (disp, 0) != 1)
2330 /* Must be @GOT or @GOTOFF. */
2331 if (XINT (disp, 1) != 6
2332 && XINT (disp, 1) != 7)
2335 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2336 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
2343 legitimate_address_p (mode, addr, strict)
2344 enum machine_mode mode;
2348 rtx base = NULL_RTX;
2349 rtx indx = NULL_RTX;
2350 rtx scale = NULL_RTX;
2351 rtx disp = NULL_RTX;
2353 if (TARGET_DEBUG_ADDR)
2356 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
2357 GET_MODE_NAME (mode), strict);
2362 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
2365 else if (GET_CODE (addr) == PLUS)
2367 rtx op0 = XEXP (addr, 0);
2368 rtx op1 = XEXP (addr, 1);
2369 enum rtx_code code0 = GET_CODE (op0);
2370 enum rtx_code code1 = GET_CODE (op1);
2372 if (code0 == REG || code0 == SUBREG)
2374 if (code1 == REG || code1 == SUBREG)
2376 indx = op0; /* index + base */
2382 base = op0; /* base + displacement */
2387 else if (code0 == MULT)
2389 indx = XEXP (op0, 0);
2390 scale = XEXP (op0, 1);
2392 if (code1 == REG || code1 == SUBREG)
2393 base = op1; /* index*scale + base */
2396 disp = op1; /* index*scale + disp */
2399 else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
2401 indx = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */
2402 scale = XEXP (XEXP (op0, 0), 1);
2403 base = XEXP (op0, 1);
2407 else if (code0 == PLUS)
2409 indx = XEXP (op0, 0); /* index + base + disp */
2410 base = XEXP (op0, 1);
2416 ADDR_INVALID ("PLUS subcode is not valid.\n", op0);
2421 else if (GET_CODE (addr) == MULT)
2423 indx = XEXP (addr, 0); /* index*scale */
2424 scale = XEXP (addr, 1);
2428 disp = addr; /* displacement */
2430 /* Allow arg pointer and stack pointer as index if there is not scaling */
2431 if (base && indx && !scale
2432 && (indx == arg_pointer_rtx || indx == stack_pointer_rtx))
2439 /* Validate base register:
2441 Don't allow SUBREG's here, it can lead to spill failures when the base
2442 is one word out of a two word structure, which is represented internally
2447 if (GET_CODE (base) != REG)
2449 ADDR_INVALID ("Base is not a register.\n", base);
2453 if (GET_MODE (base) != Pmode)
2455 ADDR_INVALID ("Base is not in Pmode.\n", base);
2459 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (base))
2460 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (base)))
2462 ADDR_INVALID ("Base is not valid.\n", base);
2467 /* Validate index register:
2469 Don't allow SUBREG's here, it can lead to spill failures when the index
2470 is one word out of a two word structure, which is represented internally
2474 if (GET_CODE (indx) != REG)
2476 ADDR_INVALID ("Index is not a register.\n", indx);
2480 if (GET_MODE (indx) != Pmode)
2482 ADDR_INVALID ("Index is not in Pmode.\n", indx);
2486 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (indx))
2487 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (indx)))
2489 ADDR_INVALID ("Index is not valid.\n", indx);
2494 abort (); /* scale w/o index invalid */
2496 /* Validate scale factor: */
2499 HOST_WIDE_INT value;
2501 if (GET_CODE (scale) != CONST_INT)
2503 ADDR_INVALID ("Scale is not valid.\n", scale);
2507 value = INTVAL (scale);
2508 if (value != 1 && value != 2 && value != 4 && value != 8)
2510 ADDR_INVALID ("Scale is not a good multiplier.\n", scale);
2515 /* Validate displacement. */
2518 if (!CONSTANT_ADDRESS_P (disp))
2520 ADDR_INVALID ("Displacement is not valid.\n", disp);
2524 else if (GET_CODE (disp) == CONST_DOUBLE)
2526 ADDR_INVALID ("Displacement is a const_double.\n", disp);
2530 if (flag_pic && SYMBOLIC_CONST (disp))
2532 if (! legitimate_pic_address_disp_p (disp))
2534 ADDR_INVALID ("Displacement is an invalid PIC construct.\n",
2539 if (base != pic_offset_table_rtx
2540 && (indx != pic_offset_table_rtx || scale != NULL_RTX))
2542 ADDR_INVALID ("PIC displacement against invalid base.\n", disp);
2547 else if (HALF_PIC_P ())
2549 if (! HALF_PIC_ADDRESS_P (disp)
2550 || (base != NULL_RTX || indx != NULL_RTX))
2552 ADDR_INVALID ("Displacement is an invalid half-pic reference.\n",
2559 if (TARGET_DEBUG_ADDR)
2560 fprintf (stderr, "Address is valid.\n");
2562 /* Everything looks valid, return true */
2566 /* Return a legitimate reference for ORIG (an address) using the
2567 register REG. If REG is 0, a new pseudo is generated.
2569 There are two types of references that must be handled:
2571 1. Global data references must load the address from the GOT, via
2572 the PIC reg. An insn is emitted to do this load, and the reg is
2575 2. Static data references, constant pool addresses, and code labels
2576 compute the address as an offset from the GOT, whose base is in
2577 the PIC reg. Static data objects have SYMBOL_REF_FLAG set to
2578 differentiate them from global data objects. The returned
2579 address is the PIC reg + an unspec constant.
2581 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2582 reg also appears in the address. */
2585 legitimize_pic_address (orig, reg)
2593 if (GET_CODE (addr) == LABEL_REF
2594 || (GET_CODE (addr) == SYMBOL_REF
2595 && (CONSTANT_POOL_ADDRESS_P (addr)
2596 || SYMBOL_REF_FLAG (addr))))
2598 /* This symbol may be referenced via a displacement from the PIC
2599 base address (@GOTOFF). */
2601 current_function_uses_pic_offset_table = 1;
2602 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 7);
2603 new = gen_rtx_CONST (VOIDmode, new);
2604 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2608 emit_move_insn (reg, new);
2612 else if (GET_CODE (addr) == SYMBOL_REF)
2614 /* This symbol must be referenced via a load from the
2615 Global Offset Table (@GOT). */
2617 current_function_uses_pic_offset_table = 1;
2618 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 6);
2619 new = gen_rtx_CONST (VOIDmode, new);
2620 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2621 new = gen_rtx_MEM (Pmode, new);
2622 RTX_UNCHANGING_P (new) = 1;
2625 reg = gen_reg_rtx (Pmode);
2626 emit_move_insn (reg, new);
2631 if (GET_CODE (addr) == CONST)
2633 addr = XEXP (addr, 0);
2634 if (GET_CODE (addr) == UNSPEC)
2636 /* Check that the unspec is one of the ones we generate? */
2638 else if (GET_CODE (addr) != PLUS)
2641 if (GET_CODE (addr) == PLUS)
2643 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
2645 /* Check first to see if this is a constant offset from a @GOTOFF
2646 symbol reference. */
2647 if ((GET_CODE (op0) == LABEL_REF
2648 || (GET_CODE (op0) == SYMBOL_REF
2649 && (CONSTANT_POOL_ADDRESS_P (op0)
2650 || SYMBOL_REF_FLAG (op0))))
2651 && GET_CODE (op1) == CONST_INT)
2653 current_function_uses_pic_offset_table = 1;
2654 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, op0), 7);
2655 new = gen_rtx_PLUS (VOIDmode, new, op1);
2656 new = gen_rtx_CONST (VOIDmode, new);
2657 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2661 emit_move_insn (reg, new);
2667 base = legitimize_pic_address (XEXP (addr, 0), reg);
2668 new = legitimize_pic_address (XEXP (addr, 1),
2669 base == reg ? NULL_RTX : reg);
2671 if (GET_CODE (new) == CONST_INT)
2672 new = plus_constant (base, INTVAL (new));
2675 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
2677 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
2678 new = XEXP (new, 1);
2680 new = gen_rtx_PLUS (Pmode, base, new);
2688 /* Emit insns to move operands[1] into operands[0]. */
2691 emit_pic_move (operands, mode)
2693 enum machine_mode mode ATTRIBUTE_UNUSED;
2695 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
2697 if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
2698 operands[1] = force_reg (Pmode, operands[1]);
2700 operands[1] = legitimize_pic_address (operands[1], temp);
2703 /* Try machine-dependent ways of modifying an illegitimate address
2704 to be legitimate. If we find one, return the new, valid address.
2705 This macro is used in only one place: `memory_address' in explow.c.
2707 OLDX is the address as it was before break_out_memory_refs was called.
2708 In some cases it is useful to look at this to decide what needs to be done.
2710 MODE and WIN are passed so that this macro can use
2711 GO_IF_LEGITIMATE_ADDRESS.
2713 It is always safe for this macro to do nothing. It exists to recognize
2714 opportunities to optimize the output.
2716 For the 80386, we handle X+REG by loading X into a register R and
2717 using R+REG. R will go in a general reg and indexing will be used.
2718 However, if REG is a broken-out memory address or multiplication,
2719 nothing needs to be done because REG can certainly go in a general reg.
2721 When -fpic is used, special handling is needed for symbolic references.
2722 See comments by legitimize_pic_address in i386.c for details. */
2725 legitimize_address (x, oldx, mode)
2727 register rtx oldx ATTRIBUTE_UNUSED;
2728 enum machine_mode mode;
2733 if (TARGET_DEBUG_ADDR)
2735 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
2736 GET_MODE_NAME (mode));
2740 if (flag_pic && SYMBOLIC_CONST (x))
2741 return legitimize_pic_address (x, 0);
2743 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
2744 if (GET_CODE (x) == ASHIFT
2745 && GET_CODE (XEXP (x, 1)) == CONST_INT
2746 && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4)
2749 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
2750 GEN_INT (1 << log));
2753 if (GET_CODE (x) == PLUS)
2755 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
2757 if (GET_CODE (XEXP (x, 0)) == ASHIFT
2758 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2759 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4)
2762 XEXP (x, 0) = gen_rtx (MULT, Pmode,
2763 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
2764 GEN_INT (1 << log));
2767 if (GET_CODE (XEXP (x, 1)) == ASHIFT
2768 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2769 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4)
2772 XEXP (x, 1) = gen_rtx (MULT, Pmode,
2773 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
2774 GEN_INT (1 << log));
2777 /* Put multiply first if it isn't already. */
2778 if (GET_CODE (XEXP (x, 1)) == MULT)
2780 rtx tmp = XEXP (x, 0);
2781 XEXP (x, 0) = XEXP (x, 1);
2786 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2787 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2788 created by virtual register instantiation, register elimination, and
2789 similar optimizations. */
2790 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
2793 x = gen_rtx (PLUS, Pmode,
2794 gen_rtx (PLUS, Pmode, XEXP (x, 0),
2795 XEXP (XEXP (x, 1), 0)),
2796 XEXP (XEXP (x, 1), 1));
2800 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2801 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2802 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
2803 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2804 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
2805 && CONSTANT_P (XEXP (x, 1)))
2808 rtx other = NULL_RTX;
2810 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2812 constant = XEXP (x, 1);
2813 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
2815 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
2817 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
2818 other = XEXP (x, 1);
2826 x = gen_rtx (PLUS, Pmode,
2827 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
2828 XEXP (XEXP (XEXP (x, 0), 1), 0)),
2829 plus_constant (other, INTVAL (constant)));
2833 if (changed && legitimate_address_p (mode, x, FALSE))
2836 if (GET_CODE (XEXP (x, 0)) == MULT)
2839 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
2842 if (GET_CODE (XEXP (x, 1)) == MULT)
2845 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
2849 && GET_CODE (XEXP (x, 1)) == REG
2850 && GET_CODE (XEXP (x, 0)) == REG)
2853 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
2856 x = legitimize_pic_address (x, 0);
2859 if (changed && legitimate_address_p (mode, x, FALSE))
2862 if (GET_CODE (XEXP (x, 0)) == REG)
2864 register rtx temp = gen_reg_rtx (Pmode);
2865 register rtx val = force_operand (XEXP (x, 1), temp);
2867 emit_move_insn (temp, val);
2873 else if (GET_CODE (XEXP (x, 1)) == REG)
2875 register rtx temp = gen_reg_rtx (Pmode);
2876 register rtx val = force_operand (XEXP (x, 0), temp);
2878 emit_move_insn (temp, val);
2888 /* Print an integer constant expression in assembler syntax. Addition
2889 and subtraction are the only arithmetic that may appear in these
2890 expressions. FILE is the stdio stream to write to, X is the rtx, and
2891 CODE is the operand print code from the output string. */
2894 output_pic_addr_const (file, x, code)
2901 switch (GET_CODE (x))
2911 assemble_name (file, XSTR (x, 0));
2912 #ifdef ASM_HACK_SYMBOLREF_CODE
2913 ASM_HACK_SYMBOLREF_CODE (XSTR (x, 0), code);
2915 if (code == 'P' && ! SYMBOL_REF_FLAG (x))
2916 fputs ("@PLT", file);
2923 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
2924 assemble_name (asm_out_file, buf);
2928 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
2932 /* This used to output parentheses around the expression,
2933 but that does not work on the 386 (either ATT or BSD assembler). */
2934 output_pic_addr_const (file, XEXP (x, 0), code);
2938 if (GET_MODE (x) == VOIDmode)
2940 /* We can use %d if the number is <32 bits and positive. */
2941 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
2942 fprintf (file, "0x%lx%08lx",
2943 (unsigned long) CONST_DOUBLE_HIGH (x),
2944 (unsigned long) CONST_DOUBLE_LOW (x));
2946 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
2949 /* We can't handle floating point constants;
2950 PRINT_OPERAND must handle them. */
2951 output_operand_lossage ("floating constant misused");
2955 /* Some assemblers need integer constants to appear first. */
2956 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
2958 output_pic_addr_const (file, XEXP (x, 0), code);
2959 fprintf (file, "+");
2960 output_pic_addr_const (file, XEXP (x, 1), code);
2962 else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2964 output_pic_addr_const (file, XEXP (x, 1), code);
2965 fprintf (file, "+");
2966 output_pic_addr_const (file, XEXP (x, 0), code);
2973 output_pic_addr_const (file, XEXP (x, 0), code);
2974 fprintf (file, "-");
2975 output_pic_addr_const (file, XEXP (x, 1), code);
2979 if (XVECLEN (x, 0) != 1)
2981 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
2982 switch (XINT (x, 1))
2985 fputs ("@GOT", file);
2988 fputs ("@GOTOFF", file);
2991 fputs ("@PLT", file);
2994 output_operand_lossage ("invalid UNSPEC as operand");
3000 output_operand_lossage ("invalid expression as operand");
3005 put_jump_code (code, reverse, file)
3010 int flags = cc_prev_status.flags;
3011 int ieee = (TARGET_IEEE_FP && (flags & CC_IN_80387)
3012 && !(cc_prev_status.flags & CC_FCOMI));
3015 if (flags & CC_Z_IN_NOT_C)
3019 fputs (reverse ? "c" : "nc", file);
3023 fputs (reverse ? "nc" : "c", file);
3034 suffix = reverse ? "ae" : "b";
3039 suffix = reverse ? "ne" : "e";
3042 suffix = reverse ? "ne" : "e";
3045 suffix = reverse ? "e" : "ne";
3050 fputs (suffix, file);
3053 if (flags & CC_TEST_AX)
3055 if ((flags & CC_NO_OVERFLOW) && (code == LE || code == GT))
3058 code = reverse_condition (code);
3070 suffix = flags & CC_IN_80387 ? "a" : "g";
3078 if (flags & CC_NO_OVERFLOW)
3081 suffix = flags & CC_IN_80387 ? "b" : "l";
3089 if (flags & CC_NO_OVERFLOW)
3092 suffix = flags & CC_IN_80387 ? "ae" : "ge";
3100 suffix = flags & CC_IN_80387 ? "be" : "le";
3110 fputs (suffix, file);
3113 /* Append the correct conditional move suffix which corresponds to CODE. */
3116 put_condition_code (code, reverse_cc, mode, file)
3119 enum mode_class mode;
3122 int ieee = (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
3123 && ! (cc_prev_status.flags & CC_FCOMI));
3124 if (reverse_cc && ! ieee)
3125 code = reverse_condition (code);
3127 if (mode == MODE_INT)
3131 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
3138 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
3145 if (cc_prev_status.flags & CC_NO_OVERFLOW)
3160 if (cc_prev_status.flags & CC_NO_OVERFLOW)
3183 output_operand_lossage ("Invalid %%C operand");
3186 else if (mode == MODE_FLOAT)
3190 fputs (ieee ? (reverse_cc ? "ne" : "e") : "ne", file);
3193 fputs (ieee ? (reverse_cc ? "ne" : "e") : "e", file);
3196 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file);
3199 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file);
3202 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file);
3205 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file);
3208 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file);
3211 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file);
3214 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file);
3217 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file);
3220 output_operand_lossage ("Invalid %%C operand");
3225 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
3226 C -- print opcode suffix for set/cmov insn.
3227 c -- like C, but print reversed condition
3228 F -- print opcode suffix for fcmov insn.
3229 f -- like F, but print reversed condition
3230 D -- print the opcode suffix for a jump
3231 d -- like D, but print reversed condition
3232 R -- print the prefix for register names.
3233 z -- print the opcode suffix for the size of the current operand.
3234 * -- print a star (in certain assembler syntax)
3235 w -- print the operand as if it's a "word" (HImode) even if it isn't.
3236 J -- print the appropriate jump operand.
3237 s -- print a shift double count, followed by the assemblers argument
3239 b -- print the QImode name of the register for the indicated operand.
3240 %b0 would print %al if operands[0] is reg 0.
3241 w -- likewise, print the HImode name of the register.
3242 k -- likewise, print the SImode name of the register.
3243 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
3244 y -- print "st(0)" instead of "st" as a register.
3245 P -- print as a PIC constant
3246 _ -- output "_" if YES_UNDERSCORES */
3249 print_operand (file, x, code)
3264 #ifdef YES_UNDERSCORES
3270 PUT_OP_SIZE (code, 'l', file);
3274 PUT_OP_SIZE (code, 'w', file);
3278 PUT_OP_SIZE (code, 'b', file);
3282 PUT_OP_SIZE (code, 'l', file);
3286 PUT_OP_SIZE (code, 's', file);
3290 PUT_OP_SIZE (code, 't', file);
3294 /* 387 opcodes don't get size suffixes if the operands are
3297 if (STACK_REG_P (x))
3300 /* this is the size of op from size of operand */
3301 switch (GET_MODE_SIZE (GET_MODE (x)))
3304 #ifdef HAVE_GAS_FILDS_FISTS
3305 PUT_OP_SIZE ('W', 's', file);
3310 if (GET_MODE (x) == SFmode)
3312 PUT_OP_SIZE ('S', 's', file);
3316 PUT_OP_SIZE ('L', 'l', file);
3320 PUT_OP_SIZE ('T', 't', file);
3324 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
3326 #ifdef GAS_MNEMONICS
3327 PUT_OP_SIZE ('Q', 'q', file);
3330 PUT_OP_SIZE ('Q', 'l', file); /* Fall through */
3334 PUT_OP_SIZE ('Q', 'l', file);
3351 switch (GET_CODE (x))
3353 /* These conditions are appropriate for testing the result
3354 of an arithmetic operation, not for a compare operation.
3355 Cases GE, LT assume CC_NO_OVERFLOW true. All cases assume
3356 CC_Z_IN_NOT_C false and not floating point. */
3357 case NE: fputs ("jne", file); return;
3358 case EQ: fputs ("je", file); return;
3359 case GE: fputs ("jns", file); return;
3360 case LT: fputs ("js", file); return;
3361 case GEU: fputs ("jmp", file); return;
3362 case GTU: fputs ("jne", file); return;
3363 case LEU: fputs ("je", file); return;
3364 case LTU: fputs ("#branch never", file); return;
3366 /* no matching branches for GT nor LE */
3373 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
3375 PRINT_OPERAND (file, x, 0);
3376 fputs (AS2C (,) + 1, file);
3382 put_jump_code (GET_CODE (x), 0, file);
3386 put_jump_code (GET_CODE (x), 1, file);
3389 /* This is used by the conditional move instructions. */
3391 put_condition_code (GET_CODE (x), 0, MODE_INT, file);
3394 /* Like above, but reverse condition */
3396 put_condition_code (GET_CODE (x), 1, MODE_INT, file); return;
3399 put_condition_code (GET_CODE (x), 0, MODE_FLOAT, file);
3402 /* Like above, but reverse condition */
3404 put_condition_code (GET_CODE (x), 1, MODE_FLOAT, file);
3411 sprintf (str, "invalid operand code `%c'", code);
3412 output_operand_lossage (str);
3417 if (GET_CODE (x) == REG)
3419 PRINT_REG (x, code, file);
3422 else if (GET_CODE (x) == MEM)
3424 PRINT_PTR (x, file);
3425 if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
3428 output_pic_addr_const (file, XEXP (x, 0), code);
3430 output_addr_const (file, XEXP (x, 0));
3433 output_address (XEXP (x, 0));
3436 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
3441 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3442 REAL_VALUE_TO_TARGET_SINGLE (r, l);
3443 PRINT_IMMED_PREFIX (file);
3444 fprintf (file, "0x%lx", l);
3447 /* These float cases don't actually occur as immediate operands. */
3448 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
3453 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3454 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
3455 fprintf (file, "%s", dstr);
3458 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
3463 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3464 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
3465 fprintf (file, "%s", dstr);
3471 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3472 PRINT_IMMED_PREFIX (file);
3473 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
3474 || GET_CODE (x) == LABEL_REF)
3475 PRINT_OFFSET_PREFIX (file);
3478 output_pic_addr_const (file, x, code);
3480 output_addr_const (file, x);
3484 /* Print a memory operand whose address is ADDR. */
3487 print_operand_address (file, addr)
3491 register rtx reg1, reg2, breg, ireg;
3494 switch (GET_CODE (addr))
3497 /* ESI addressing makes instruction vector decoded on the K6. We can
3498 avoid this by ESI+0 addressing. */
3499 if (REGNO_REG_CLASS (REGNO (addr)) == SIREG
3500 && ix86_cpu == PROCESSOR_K6 && !optimize_size)
3501 output_addr_const (file, const0_rtx);
3503 fprintf (file, "%se", RP);
3504 fputs (hi_reg_name[REGNO (addr)], file);
3514 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
3516 offset = XEXP (addr, 0);
3517 addr = XEXP (addr, 1);
3519 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
3521 offset = XEXP (addr, 1);
3522 addr = XEXP (addr, 0);
3525 if (GET_CODE (addr) != PLUS)
3527 else if (GET_CODE (XEXP (addr, 0)) == MULT)
3528 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1);
3529 else if (GET_CODE (XEXP (addr, 1)) == MULT)
3530 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0);
3531 else if (GET_CODE (XEXP (addr, 0)) == REG)
3532 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1);
3533 else if (GET_CODE (XEXP (addr, 1)) == REG)
3534 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0);
3536 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
3553 if ((reg1 && GET_CODE (reg1) == MULT)
3554 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
3559 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
3565 if (ireg != 0 || breg != 0)
3572 output_pic_addr_const (file, addr, 0);
3573 else if (GET_CODE (addr) == LABEL_REF)
3574 output_asm_label (addr);
3576 output_addr_const (file, addr);
3579 if (ireg != 0 && GET_CODE (ireg) == MULT)
3581 scale = INTVAL (XEXP (ireg, 1));
3582 ireg = XEXP (ireg, 0);
3585 /* The stack pointer can only appear as a base register,
3586 never an index register, so exchange the regs if it is wrong. */
3588 if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM)
3597 /* output breg+ireg*scale */
3598 PRINT_B_I_S (breg, ireg, scale, file);
3606 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
3608 scale = INTVAL (XEXP (addr, 0));
3609 ireg = XEXP (addr, 1);
3613 scale = INTVAL (XEXP (addr, 1));
3614 ireg = XEXP (addr, 0);
3617 /* (reg,reg,) is shorter than (,reg,2). */
3620 PRINT_B_I_S (ireg, ireg, 1, file);
3624 output_addr_const (file, const0_rtx);
3625 PRINT_B_I_S (NULL_RTX, ireg, scale, file);
3631 if (GET_CODE (addr) == CONST_INT
3632 && INTVAL (addr) < 0x8000
3633 && INTVAL (addr) >= -0x8000)
3634 fprintf (file, "%d", (int) INTVAL (addr));
3638 output_pic_addr_const (file, addr, 0);
3640 output_addr_const (file, addr);
3645 /* Set the cc_status for the results of an insn whose pattern is EXP.
3646 On the 80386, we assume that only test and compare insns, as well
3647 as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, BSF, ASHIFT,
3648 ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully.
3649 Also, we assume that jumps, moves and sCOND don't affect the condition
3650 codes. All else clobbers the condition codes, by assumption.
3652 We assume that ALL integer add, minus, etc. instructions effect the
3653 condition codes. This MUST be consistent with i386.md.
3655 We don't record any float test or compare - the redundant test &
3656 compare check in final.c does not handle stack-like regs correctly. */
3659 notice_update_cc (exp)
3662 if (GET_CODE (exp) == SET)
3664 /* Jumps do not alter the cc's. */
3665 if (SET_DEST (exp) == pc_rtx)
3668 /* Moving register or memory into a register:
3669 it doesn't alter the cc's, but it might invalidate
3670 the RTX's which we remember the cc's came from.
3671 (Note that moving a constant 0 or 1 MAY set the cc's). */
3672 if (REG_P (SET_DEST (exp))
3673 && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM
3674 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'
3675 || GET_CODE (SET_SRC (exp)) == IF_THEN_ELSE))
3677 if (cc_status.value1
3678 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
3679 cc_status.value1 = 0;
3681 if (cc_status.value2
3682 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
3683 cc_status.value2 = 0;
3688 /* Moving register into memory doesn't alter the cc's.
3689 It may invalidate the RTX's which we remember the cc's came from. */
3690 if (GET_CODE (SET_DEST (exp)) == MEM
3691 && (REG_P (SET_SRC (exp))
3692 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
3694 if (cc_status.value1
3695 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
3696 cc_status.value1 = 0;
3697 if (cc_status.value2
3698 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
3699 cc_status.value2 = 0;
3704 /* Function calls clobber the cc's. */
3705 else if (GET_CODE (SET_SRC (exp)) == CALL)
3711 /* Tests and compares set the cc's in predictable ways. */
3712 else if (SET_DEST (exp) == cc0_rtx)
3715 cc_status.value1 = SET_SRC (exp);
3719 /* Certain instructions effect the condition codes. */
3720 else if (GET_MODE (SET_SRC (exp)) == SImode
3721 || GET_MODE (SET_SRC (exp)) == HImode
3722 || GET_MODE (SET_SRC (exp)) == QImode)
3723 switch (GET_CODE (SET_SRC (exp)))
3725 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
3726 /* Shifts on the 386 don't set the condition codes if the
3727 shift count is zero. */
3728 if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT)
3734 /* We assume that the CONST_INT is non-zero (this rtx would
3735 have been deleted if it were zero. */
3737 case PLUS: case MINUS: case NEG:
3738 case AND: case IOR: case XOR:
3739 cc_status.flags = CC_NO_OVERFLOW;
3740 cc_status.value1 = SET_SRC (exp);
3741 cc_status.value2 = SET_DEST (exp);
3744 /* This is the bsf pattern used by ffs. */
3746 if (XINT (SET_SRC (exp), 1) == 5)
3748 /* Only the Z flag is defined after bsf. */
3750 = CC_NOT_POSITIVE | CC_NOT_NEGATIVE | CC_NO_OVERFLOW;
3751 cc_status.value1 = XVECEXP (SET_SRC (exp), 0, 0);
3752 cc_status.value2 = 0;
3765 else if (GET_CODE (exp) == PARALLEL
3766 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
3768 if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
3770 if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
3774 if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
3776 cc_status.flags |= CC_IN_80387;
3777 if (TARGET_CMOVE && stack_regs_mentioned_p
3778 (XEXP (SET_SRC (XVECEXP (exp, 0, 0)), 1)))
3779 cc_status.flags |= CC_FCOMI;
3782 cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
3794 /* Split one or more DImode RTL references into pairs of SImode
3795 references. The RTL can be REG, offsettable MEM, integer constant, or
3796 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3797 split and "num" is its length. lo_half and hi_half are output arrays
3798 that parallel "operands". */
3801 split_di (operands, num, lo_half, hi_half)
3804 rtx lo_half[], hi_half[];
3808 rtx op = operands[num];
3809 if (! reload_completed)
3811 lo_half[num] = gen_lowpart (SImode, op);
3812 hi_half[num] = gen_highpart (SImode, op);
3814 else if (GET_CODE (op) == REG)
3816 lo_half[num] = gen_rtx_REG (SImode, REGNO (op));
3817 hi_half[num] = gen_rtx_REG (SImode, REGNO (op) + 1);
3819 else if (CONSTANT_P (op))
3820 split_double (op, &lo_half[num], &hi_half[num]);
3821 else if (offsettable_memref_p (op))
3823 rtx lo_addr = XEXP (op, 0);
3824 rtx hi_addr = XEXP (adj_offsettable_operand (op, 4), 0);
3825 lo_half[num] = change_address (op, SImode, lo_addr);
3826 hi_half[num] = change_address (op, SImode, hi_addr);
3833 /* Return 1 if this is a valid binary operation on a 387.
3834 OP is the expression matched, and MODE is its mode. */
3837 binary_387_op (op, mode)
3839 enum machine_mode mode;
3841 if (mode != VOIDmode && mode != GET_MODE (op))
3844 switch (GET_CODE (op))
3850 return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
3857 /* Return 1 if this is a valid shift or rotate operation on a 386.
3858 OP is the expression matched, and MODE is its mode. */
3863 enum machine_mode mode;
3865 rtx operand = XEXP (op, 0);
3867 if (mode != VOIDmode && mode != GET_MODE (op))
3870 if (GET_MODE (operand) != GET_MODE (op)
3871 || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
3874 return (GET_CODE (op) == ASHIFT
3875 || GET_CODE (op) == ASHIFTRT
3876 || GET_CODE (op) == LSHIFTRT
3877 || GET_CODE (op) == ROTATE
3878 || GET_CODE (op) == ROTATERT);
3881 /* Return 1 if OP is COMPARE rtx with mode VOIDmode.
3882 MODE is not used. */
3885 VOIDmode_compare_op (op, mode)
3887 enum machine_mode mode ATTRIBUTE_UNUSED;
3889 return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode;
3892 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
3893 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
3894 is the expression of the binary operation. The output may either be
3895 emitted here, or returned to the caller, like all output_* functions.
3897 There is no guarantee that the operands are the same mode, as they
3898 might be within FLOAT or FLOAT_EXTEND expressions. */
3901 output_387_binary_op (insn, operands)
3907 static char buf[100];
3909 switch (GET_CODE (operands[3]))
3931 strcpy (buf, base_op);
3933 switch (GET_CODE (operands[3]))
3937 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
3940 operands[2] = operands[1];
3944 if (GET_CODE (operands[2]) == MEM)
3945 return strcat (buf, AS1 (%z2,%2));
3947 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
3950 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
3952 if (STACK_TOP_P (operands[0]))
3953 return strcat (buf, AS2 (p,%0,%2));
3955 return strcat (buf, AS2 (p,%2,%0));
3958 if (STACK_TOP_P (operands[0]))
3959 return strcat (buf, AS2C (%y2,%0));
3961 return strcat (buf, AS2C (%2,%0));
3965 if (GET_CODE (operands[1]) == MEM)
3966 return strcat (buf, AS1 (r%z1,%1));
3968 if (GET_CODE (operands[2]) == MEM)
3969 return strcat (buf, AS1 (%z2,%2));
3971 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
3974 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
3976 if (STACK_TOP_P (operands[0]))
3977 return strcat (buf, AS2 (p,%0,%2));
3979 return strcat (buf, AS2 (rp,%2,%0));
3982 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3984 if (STACK_TOP_P (operands[0]))
3985 return strcat (buf, AS2 (rp,%0,%1));
3987 return strcat (buf, AS2 (p,%1,%0));
3990 if (STACK_TOP_P (operands[0]))
3992 if (STACK_TOP_P (operands[1]))
3993 return strcat (buf, AS2C (%y2,%0));
3995 return strcat (buf, AS2 (r,%y1,%0));
3997 else if (STACK_TOP_P (operands[1]))
3998 return strcat (buf, AS2C (%1,%0));
4000 return strcat (buf, AS2 (r,%2,%0));
4007 /* Output code for INSN to convert a float to a signed int. OPERANDS
4008 are the insn operands. The input may be SFmode, DFmode, or XFmode
4009 and the output operand may be SImode or DImode. As a special case,
4010 make sure that the 387 stack top dies if the output mode is DImode,
4011 because the hardware requires this. */
4014 output_fix_trunc (insn, operands)
4018 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
4021 if (! STACK_TOP_P (operands[1]))
4024 if (GET_MODE (operands[0]) == DImode && ! stack_top_dies)
4027 xops[0] = GEN_INT (0x0c00);
4028 xops[1] = operands[5];
4030 output_asm_insn (AS1 (fnstc%W2,%2), operands);
4031 output_asm_insn (AS2 (mov%W5,%2,%w5), operands);
4032 output_asm_insn (AS2 (or%W1,%0,%w1), xops);
4033 output_asm_insn (AS2 (mov%W3,%w5,%3), operands);
4034 output_asm_insn (AS1 (fldc%W3,%3), operands);
4036 xops[0] = NON_STACK_REG_P (operands[0]) ? operands[4] : operands[0];
4039 output_asm_insn (AS1 (fistp%z0,%y0), xops);
4041 output_asm_insn (AS1 (fist%z0,%y0), xops);
4043 if (NON_STACK_REG_P (operands[0]))
4045 if (GET_MODE (operands[0]) == SImode)
4046 output_asm_insn (AS2 (mov%L0,%4,%0), operands);
4049 xops[0] = operands[0];
4050 xops[1] = operands[4];
4051 output_asm_insn (output_move_double (xops), xops);
4055 return AS1 (fldc%W2,%2);
4058 /* Output code for INSN to extend a float. OPERANDS are the insn
4059 operands. The output may be DFmode or XFmode and the input operand
4060 may be SFmode or DFmode. Operands 2 and 3 are scratch memory and
4061 are only necessary if operands 0 or 1 are non-stack registers. */
4064 output_float_extend (insn, operands)
4068 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
4071 if (! STACK_TOP_P (operands[0]) && ! STACK_TOP_P (operands[1]))
4074 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]) && stack_top_dies)
4077 if (STACK_TOP_P (operands[0]) )
4079 if (NON_STACK_REG_P (operands[1]))
4081 if (GET_MODE (operands[1]) == SFmode)
4082 output_asm_insn (AS2 (mov%L0,%1,%2), operands);
4085 xops[0] = operands[2];
4086 xops[1] = operands[1];
4087 output_asm_insn (output_move_double (xops), xops);
4091 xops[0] = NON_STACK_REG_P (operands[1]) ? operands[2] : operands[1];
4093 output_asm_insn (AS1 (fld%z0,%y0), xops);
4097 xops[0] = NON_STACK_REG_P (operands[0]) ? operands[3] : operands[0];
4100 || (GET_CODE (xops[0]) == MEM && GET_MODE (xops[0]) == XFmode))
4102 output_asm_insn (AS1 (fstp%z0,%y0), xops);
4103 if (! stack_top_dies)
4104 output_asm_insn (AS1 (fld%z0,%y0), xops);
4107 output_asm_insn (AS1 (fst%z0,%y0), xops);
4109 if (NON_STACK_REG_P (operands[0]))
4111 xops[0] = operands[0];
4112 xops[1] = operands[3];
4113 output_asm_insn (output_move_double (xops), xops);
4118 /* Output code for INSN to compare OPERANDS. The two operands might
4119 not have the same mode: one might be within a FLOAT or FLOAT_EXTEND
4120 expression. If the compare is in mode CCFPEQmode, use an opcode that
4121 will not fault if a qNaN is present. */
4124 output_float_compare (insn, operands)
4129 rtx body = XVECEXP (PATTERN (insn), 0, 0);
4130 int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
4135 if (TARGET_CMOVE && STACK_REG_P (operands[1])
4136 && STACK_REG_P (operands[0]))
4138 cc_status.flags |= CC_FCOMI;
4139 cc_prev_status.flags &= ~CC_TEST_AX;
4142 if (! STACK_TOP_P (operands[0]))
4145 operands[0] = operands[1];
4147 cc_status.flags |= CC_REVERSED;
4150 if (! STACK_TOP_P (operands[0]))
4153 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
4155 if (STACK_REG_P (operands[1])
4157 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4158 && REGNO (operands[1]) == FIRST_STACK_REG + 1)
4160 /* If both the top of the 387 stack dies, and the other operand
4161 is also a stack register that dies, then this must be a
4162 `fcompp' float compare */
4164 if (unordered_compare)
4166 if (cc_status.flags & CC_FCOMI)
4168 output_asm_insn (AS2 (fucomip,%y1,%0), operands);
4169 output_asm_insn (AS1 (fstp, %y0), operands);
4170 if (!TARGET_IEEE_FP)
4174 output_asm_insn ("fucompp", operands);
4178 if (cc_status.flags & CC_FCOMI)
4180 output_asm_insn (AS2 (fcomip, %y1,%0), operands);
4181 output_asm_insn (AS1 (fstp, %y0), operands);
4182 if (!TARGET_IEEE_FP)
4186 output_asm_insn ("fcompp", operands);
4191 static char buf[100];
4193 /* Decide if this is a float compare or an unordered float compare. */
4195 if (unordered_compare)
4196 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fucomi" : "fucom");
4198 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fcomi" : "fcom");
4200 /* Modify the opcode if the 387 stack is to be popped. */
4205 if (cc_status.flags & CC_FCOMI)
4207 output_asm_insn (strcat (buf, AS2 (%z1,%y1,%0)), operands);
4208 if (!TARGET_IEEE_FP)
4212 output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands);
4215 /* Now retrieve the condition code. */
4218 char *r = output_fp_cc0_set (insn);
4219 if (r[0]) output_asm_insn (r, operands);
4223 /* We emit fstp instruction after integer comparsions to improve
4225 for (i = 0; i < 2 ; i++)
4227 if (STACK_REG_P (operands[i])
4228 && find_regno_note (insn, REG_DEAD, REGNO (operands[i]))
4229 && REGNO (operands[i]) != FIRST_STACK_REG
4230 && (!stack_top_dies || REGNO (operands[i]) != FIRST_STACK_REG + 1))
4233 xexp[0] = gen_rtx_REG (DFmode,
4234 REGNO (operands[i]) - (stack_top_dies != 0));
4235 output_asm_insn (AS1 (fstp, %y0), xexp);
4244 /* Output opcodes to transfer the results of FP compare or test INSN
4245 from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the
4246 result of the compare or test is unordered, no comparison operator
4247 succeeds except NE. Return an output template, if any. */
4250 output_fp_cc0_set (insn)
4257 if (!(cc_status.flags & CC_FCOMI))
4259 xops[0] = gen_rtx_REG (HImode, 0);
4260 output_asm_insn (AS1 (fnsts%W0,%0), xops);
4263 if (! TARGET_IEEE_FP)
4265 if (!(cc_status.flags & CC_REVERSED))
4267 next = next_cc0_user (insn);
4269 if (GET_CODE (PATTERN (next)) == SET
4270 && SET_DEST (PATTERN (next)) == pc_rtx
4271 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4272 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4273 else if (GET_CODE (PATTERN (next)) == SET)
4274 code = GET_CODE (SET_SRC (PATTERN (next)));
4278 if (code == GT || code == LT || code == EQ || code == NE
4279 || code == LE || code == GE)
4281 /* We will test eax directly. */
4282 cc_status.flags |= CC_TEST_AX;
4290 next = next_cc0_user (insn);
4291 if (next == NULL_RTX)
4294 if (GET_CODE (PATTERN (next)) == SET
4295 && SET_DEST (PATTERN (next)) == pc_rtx
4296 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4297 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4298 else if (GET_CODE (PATTERN (next)) == SET)
4300 if (GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4301 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4303 code = GET_CODE (SET_SRC (PATTERN (next)));
4306 else if (GET_CODE (PATTERN (next)) == PARALLEL
4307 && GET_CODE (XVECEXP (PATTERN (next), 0, 0)) == SET)
4309 if (GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0))) == IF_THEN_ELSE)
4310 code = GET_CODE (XEXP (SET_SRC (XVECEXP (PATTERN (next), 0, 0)), 0));
4312 code = GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0)));
4317 if (cc_status.flags & CC_FCOMI)
4319 /* It is very tricky. We have to do it right. */
4321 xops [0] = gen_rtx_REG (QImode, 0);
4330 output_asm_insn (AS1 (setb,%b0), xops);
4331 output_asm_insn (AS1 (setp,%h0), xops);
4332 output_asm_insn (AS2 (cmp%B0,%b0,%h0), xops);
4336 output_asm_insn (AS1 (setbe,%b0), xops);
4337 output_asm_insn (AS1 (setnp,%h0), xops);
4338 output_asm_insn (AS2 (xor%B0,%b0,%h0), xops);
4343 output_asm_insn (AS1 (setne,%b0), xops);
4344 output_asm_insn (AS1 (setp,%h0), xops);
4345 output_asm_insn (AS2 (or%B0,%b0,%h0), xops);
4358 xops[0] = gen_rtx_REG (QImode, 0);
4363 xops[1] = GEN_INT (0x45);
4364 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4369 xops[1] = GEN_INT (0x45);
4370 xops[2] = GEN_INT (0x01);
4371 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4372 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4377 xops[1] = GEN_INT (0x05);
4378 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4383 xops[1] = GEN_INT (0x45);
4384 xops[2] = GEN_INT (0x40);
4385 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4386 output_asm_insn (AS1 (dec%B0,%h0), xops);
4387 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4392 xops[1] = GEN_INT (0x45);
4393 xops[2] = GEN_INT (0x40);
4394 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4395 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4400 xops[1] = GEN_INT (0x44);
4401 xops[2] = GEN_INT (0x40);
4402 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4403 output_asm_insn (AS2 (xor%B0,%2,%h0), xops);
4419 #define MAX_386_STACK_LOCALS 2
4421 static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
4423 /* Define the structure for the machine field in struct function. */
4424 struct machine_function
4426 rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
4428 char pic_label_name[256];
4431 /* Functions to save and restore i386_stack_locals.
4432 These will be called, via pointer variables,
4433 from push_function_context and pop_function_context. */
4436 save_386_machine_status (p)
4440 = (struct machine_function *) xmalloc (sizeof (struct machine_function));
4441 bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals,
4442 sizeof i386_stack_locals);
4443 p->machine->pic_label_rtx = pic_label_rtx;
4444 bcopy (pic_label_name, p->machine->pic_label_name, 256);
4448 restore_386_machine_status (p)
4451 bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals,
4452 sizeof i386_stack_locals);
4453 pic_label_rtx = p->machine->pic_label_rtx;
4454 bcopy (p->machine->pic_label_name, pic_label_name, 256);
4459 /* Clear stack slot assignments remembered from previous functions.
4460 This is called from INIT_EXPANDERS once before RTL is emitted for each
4464 clear_386_stack_locals ()
4466 enum machine_mode mode;
4469 for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE;
4470 mode = (enum machine_mode) ((int) mode + 1))
4471 for (n = 0; n < MAX_386_STACK_LOCALS; n++)
4472 i386_stack_locals[(int) mode][n] = NULL_RTX;
4474 pic_label_rtx = NULL_RTX;
4475 bzero (pic_label_name, 256);
4476 /* Arrange to save and restore i386_stack_locals around nested functions. */
4477 save_machine_status = save_386_machine_status;
4478 restore_machine_status = restore_386_machine_status;
4481 /* Return a MEM corresponding to a stack slot with mode MODE.
4482 Allocate a new slot if necessary.
4484 The RTL for a function can have several slots available: N is
4485 which slot to use. */
4488 assign_386_stack_local (mode, n)
4489 enum machine_mode mode;
4492 if (n < 0 || n >= MAX_386_STACK_LOCALS)
4495 if (i386_stack_locals[(int) mode][n] == NULL_RTX)
4496 i386_stack_locals[(int) mode][n]
4497 = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
4499 return i386_stack_locals[(int) mode][n];
4504 enum machine_mode mode ATTRIBUTE_UNUSED;
4506 return (GET_CODE (op) == MULT);
4511 enum machine_mode mode ATTRIBUTE_UNUSED;
4513 return (GET_CODE (op) == DIV);
4517 /* Create a new copy of an rtx.
4518 Recursively copies the operands of the rtx,
4519 except for those few rtx codes that are sharable.
4520 Doesn't share CONST */
4528 register RTX_CODE code;
4529 register char *format_ptr;
4531 code = GET_CODE (orig);
4544 /* SCRATCH must be shared because they represent distinct values. */
4549 /* CONST can be shared if it contains a SYMBOL_REF. If it contains
4550 a LABEL_REF, it isn't sharable. */
4551 if (GET_CODE (XEXP (orig, 0)) == PLUS
4552 && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
4553 && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT)
4557 /* A MEM with a constant address is not sharable. The problem is that
4558 the constant address may need to be reloaded. If the mem is shared,
4559 then reloading one copy of this mem will cause all copies to appear
4560 to have been reloaded. */
4563 copy = rtx_alloc (code);
4564 PUT_MODE (copy, GET_MODE (orig));
4565 copy->in_struct = orig->in_struct;
4566 copy->volatil = orig->volatil;
4567 copy->unchanging = orig->unchanging;
4568 copy->integrated = orig->integrated;
4570 copy->is_spill_rtx = orig->is_spill_rtx;
4572 format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
4574 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
4576 switch (*format_ptr++)
4579 XEXP (copy, i) = XEXP (orig, i);
4580 if (XEXP (orig, i) != NULL)
4581 XEXP (copy, i) = copy_rtx (XEXP (orig, i));
4586 XEXP (copy, i) = XEXP (orig, i);
4591 XVEC (copy, i) = XVEC (orig, i);
4592 if (XVEC (orig, i) != NULL)
4594 XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
4595 for (j = 0; j < XVECLEN (copy, i); j++)
4596 XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j));
4601 XWINT (copy, i) = XWINT (orig, i);
4605 XINT (copy, i) = XINT (orig, i);
4610 XSTR (copy, i) = XSTR (orig, i);
4621 /* Try to rewrite a memory address to make it valid */
4624 rewrite_address (mem_rtx)
4627 rtx index_rtx, base_rtx, offset_rtx, scale_rtx, ret_rtx;
4629 int offset_adjust = 0;
4630 int was_only_offset = 0;
4631 rtx mem_addr = XEXP (mem_rtx, 0);
4632 char *storage = oballoc (0);
4634 int is_spill_rtx = 0;
4636 in_struct = MEM_IN_STRUCT_P (mem_rtx);
4637 is_spill_rtx = RTX_IS_SPILL_P (mem_rtx);
4639 if (GET_CODE (mem_addr) == PLUS
4640 && GET_CODE (XEXP (mem_addr, 1)) == PLUS
4641 && GET_CODE (XEXP (XEXP (mem_addr, 1), 0)) == REG)
4643 /* This part is utilized by the combiner. */
4645 = gen_rtx (PLUS, GET_MODE (mem_addr),
4646 gen_rtx (PLUS, GET_MODE (XEXP (mem_addr, 1)),
4647 XEXP (mem_addr, 0), XEXP (XEXP (mem_addr, 1), 0)),
4648 XEXP (XEXP (mem_addr, 1), 1));
4650 if (memory_address_p (GET_MODE (mem_rtx), ret_rtx))
4652 XEXP (mem_rtx, 0) = ret_rtx;
4653 RTX_IS_SPILL_P (ret_rtx) = is_spill_rtx;
4660 /* This part is utilized by loop.c.
4661 If the address contains PLUS (reg,const) and this pattern is invalid
4662 in this case - try to rewrite the address to make it valid. */
4663 storage = oballoc (0);
4664 index_rtx = base_rtx = offset_rtx = NULL;
4666 /* Find the base index and offset elements of the memory address. */
4667 if (GET_CODE (mem_addr) == PLUS)
4669 if (GET_CODE (XEXP (mem_addr, 0)) == REG)
4671 if (GET_CODE (XEXP (mem_addr, 1)) == REG)
4672 base_rtx = XEXP (mem_addr, 1), index_rtx = XEXP (mem_addr, 0);
4674 base_rtx = XEXP (mem_addr, 0), offset_rtx = XEXP (mem_addr, 1);
4677 else if (GET_CODE (XEXP (mem_addr, 0)) == MULT)
4679 index_rtx = XEXP (mem_addr, 0);
4680 if (GET_CODE (XEXP (mem_addr, 1)) == REG)
4681 base_rtx = XEXP (mem_addr, 1);
4683 offset_rtx = XEXP (mem_addr, 1);
4686 else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS)
4688 if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == PLUS
4689 && GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == MULT
4690 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 0))
4692 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 1))
4694 && (GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1))
4696 && GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG
4697 && GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF)
4699 index_rtx = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0);
4700 offset_rtx = XEXP (mem_addr, 1);
4701 base_rtx = XEXP (XEXP (mem_addr, 0), 1);
4702 offset_adjust = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1));
4706 offset_rtx = XEXP (mem_addr, 1);
4707 index_rtx = XEXP (XEXP (mem_addr, 0), 0);
4708 base_rtx = XEXP (XEXP (mem_addr, 0), 1);
4712 else if (GET_CODE (XEXP (mem_addr, 0)) == CONST_INT)
4714 was_only_offset = 1;
4717 offset_rtx = XEXP (mem_addr, 1);
4718 offset_adjust = INTVAL (XEXP (mem_addr, 0));
4719 if (offset_adjust == 0)
4721 XEXP (mem_rtx, 0) = offset_rtx;
4722 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4732 else if (GET_CODE (mem_addr) == MULT)
4733 index_rtx = mem_addr;
4740 if (index_rtx != 0 && GET_CODE (index_rtx) == MULT)
4742 if (GET_CODE (XEXP (index_rtx, 1)) != CONST_INT)
4748 scale_rtx = XEXP (index_rtx, 1);
4749 scale = INTVAL (scale_rtx);
4750 index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
4753 /* Now find which of the elements are invalid and try to fix them. */
4754 if (index_rtx && GET_CODE (index_rtx) == CONST_INT && base_rtx == NULL)
4756 offset_adjust = INTVAL (index_rtx) * scale;
4758 if (offset_rtx != 0 && CONSTANT_P (offset_rtx))
4759 offset_rtx = plus_constant (offset_rtx, offset_adjust);
4760 else if (offset_rtx == 0)
4761 offset_rtx = const0_rtx;
4763 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4764 XEXP (mem_rtx, 0) = offset_rtx;
4768 if (base_rtx && GET_CODE (base_rtx) == PLUS
4769 && GET_CODE (XEXP (base_rtx, 0)) == REG
4770 && GET_CODE (XEXP (base_rtx, 1)) == CONST_INT)
4772 offset_adjust += INTVAL (XEXP (base_rtx, 1));
4773 base_rtx = copy_all_rtx (XEXP (base_rtx, 0));
4776 else if (base_rtx && GET_CODE (base_rtx) == CONST_INT)
4778 offset_adjust += INTVAL (base_rtx);
4782 if (index_rtx && GET_CODE (index_rtx) == PLUS
4783 && GET_CODE (XEXP (index_rtx, 0)) == REG
4784 && GET_CODE (XEXP (index_rtx, 1)) == CONST_INT)
4786 offset_adjust += INTVAL (XEXP (index_rtx, 1)) * scale;
4787 index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
4792 if (! LEGITIMATE_INDEX_P (index_rtx)
4793 && ! (index_rtx == stack_pointer_rtx && scale == 1
4794 && base_rtx == NULL))
4803 if (! LEGITIMATE_INDEX_P (base_rtx) && GET_CODE (base_rtx) != REG)
4810 if (offset_adjust != 0)
4812 if (offset_rtx != 0 && CONSTANT_P (offset_rtx))
4813 offset_rtx = plus_constant (offset_rtx, offset_adjust);
4815 offset_rtx = const0_rtx;
4823 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx),
4824 gen_rtx (MULT, GET_MODE (index_rtx),
4825 index_rtx, scale_rtx),
4828 if (GET_CODE (offset_rtx) != CONST_INT
4829 || INTVAL (offset_rtx) != 0)
4830 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4831 ret_rtx, offset_rtx);
4835 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx),
4836 index_rtx, base_rtx);
4838 if (GET_CODE (offset_rtx) != CONST_INT
4839 || INTVAL (offset_rtx) != 0)
4840 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4841 ret_rtx, offset_rtx);
4848 ret_rtx = gen_rtx (MULT, GET_MODE (index_rtx),
4849 index_rtx, scale_rtx);
4851 if (GET_CODE (offset_rtx) != CONST_INT
4852 || INTVAL (offset_rtx) != 0)
4853 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4854 ret_rtx, offset_rtx);
4858 if (GET_CODE (offset_rtx) == CONST_INT
4859 && INTVAL (offset_rtx) == 0)
4860 ret_rtx = index_rtx;
4862 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx),
4863 index_rtx, offset_rtx);
4871 if (GET_CODE (offset_rtx) == CONST_INT
4872 && INTVAL (offset_rtx) == 0)
4875 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), base_rtx,
4878 else if (was_only_offset)
4879 ret_rtx = offset_rtx;
4887 XEXP (mem_rtx, 0) = ret_rtx;
4888 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4899 /* Return 1 if the first insn to set cc before INSN also sets the register
4900 REG_RTX; otherwise return 0. */
4902 last_to_set_cc (reg_rtx, insn)
4905 rtx prev_insn = PREV_INSN (insn);
4909 if (GET_CODE (prev_insn) == NOTE)
4912 else if (GET_CODE (prev_insn) == INSN)
4914 if (GET_CODE (PATTERN (prev_insn)) != SET)
4917 if (rtx_equal_p (SET_DEST (PATTERN (prev_insn)), reg_rtx))
4919 if (sets_condition_code (SET_SRC (PATTERN (prev_insn))))
4925 else if (! doesnt_set_condition_code (SET_SRC (PATTERN (prev_insn))))
4932 prev_insn = PREV_INSN (prev_insn);
4939 doesnt_set_condition_code (pat)
4942 switch (GET_CODE (pat))
4955 sets_condition_code (pat)
4958 switch (GET_CODE (pat))
4980 str_immediate_operand (op, mode)
4982 enum machine_mode mode ATTRIBUTE_UNUSED;
4984 if (GET_CODE (op) == CONST_INT && INTVAL (op) <= 32 && INTVAL (op) >= 0)
4994 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
4995 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
4996 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
4997 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode))
5003 /* Return 1 if the mode of the SET_DEST of insn is floating point
5004 and it is not an fld or a move from memory to memory.
5005 Otherwise return 0 */
5011 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
5012 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
5013 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
5014 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
5015 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
5016 && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FLOAT_REG
5017 && GET_CODE (SET_SRC (PATTERN (insn))) != MEM)
5023 /* Return 1 if the mode of the SET_DEST of INSN is floating point and is
5024 memory and the source is a register. */
5030 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
5031 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
5032 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
5033 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
5034 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM
5035 && GET_CODE (SET_SRC (PATTERN (insn))) == REG)
5041 /* Return 1 if DEP_INSN sets a register which INSN uses as a base
5042 or index to reference memory.
5043 otherwise return 0 */
5046 agi_dependent (insn, dep_insn)
5049 int push = 0, push_dep = 0;
5050 if (GET_CODE (dep_insn) == INSN
5051 && GET_CODE (PATTERN (dep_insn)) == SET
5052 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG
5053 && reg_mentioned_in_mem (SET_DEST (PATTERN (dep_insn)), insn))
5056 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
5057 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM
5058 && push_operand (SET_DEST (PATTERN (insn)),
5059 GET_MODE (SET_DEST (PATTERN (insn)))))
5062 if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET
5063 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == MEM
5064 && push_operand (SET_DEST (PATTERN (dep_insn)),
5065 GET_MODE (SET_DEST (PATTERN (dep_insn)))))
5068 /* CPUs contain special hardware to allow two pushes. */
5069 if (push && push_dep)
5072 /* Push operation implicitly change stack pointer causing AGI stalls. */
5073 if (push_dep && reg_mentioned_in_mem (stack_pointer_rtx, insn))
5076 /* Push also implicitly read stack pointer. */
5077 if (push && modified_in_p (stack_pointer_rtx, dep_insn))
5083 /* Return 1 if reg is used in rtl as a base or index for a memory ref
5084 otherwise return 0. */
5087 reg_mentioned_in_mem (reg, rtl)
5092 register enum rtx_code code;
5097 code = GET_CODE (rtl);
5115 if (code == MEM && reg_mentioned_p (reg, rtl))
5118 fmt = GET_RTX_FORMAT (code);
5119 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5123 for (j = XVECLEN (rtl, i) - 1; j >= 0; j--)
5124 if (reg_mentioned_in_mem (reg, XVECEXP (rtl, i, j)))
5128 else if (fmt[i] == 'e' && reg_mentioned_in_mem (reg, XEXP (rtl, i)))
5135 /* Output the appropriate insns for doing strlen if not just doing repnz; scasb
5137 operands[0] = result, initialized with the startaddress
5138 operands[1] = alignment of the address.
5139 operands[2] = scratch register, initialized with the startaddress when
5140 not aligned, otherwise undefined
5142 This is just the body. It needs the initialisations mentioned above and
5143 some address computing at the end. These things are done in i386.md. */
5146 output_strlen_unroll (operands)
5151 xops[0] = operands[0]; /* Result */
5152 /* operands[1]; * Alignment */
5153 xops[1] = operands[2]; /* Scratch */
5154 xops[2] = GEN_INT (0);
5155 xops[3] = GEN_INT (2);
5156 xops[4] = GEN_INT (3);
5157 xops[5] = GEN_INT (4);
5158 /* xops[6] = gen_label_rtx (); * label when aligned to 3-byte */
5159 /* xops[7] = gen_label_rtx (); * label when aligned to 2-byte */
5160 xops[8] = gen_label_rtx (); /* label of main loop */
5162 if (TARGET_USE_Q_REG && QI_REG_P (xops[1]))
5163 xops[9] = gen_label_rtx (); /* pentium optimisation */
5165 xops[10] = gen_label_rtx (); /* end label 2 */
5166 xops[11] = gen_label_rtx (); /* end label 1 */
5167 xops[12] = gen_label_rtx (); /* end label */
5168 /* xops[13] * Temporary used */
5169 xops[14] = GEN_INT (0xff);
5170 xops[15] = GEN_INT (0xff00);
5171 xops[16] = GEN_INT (0xff0000);
5172 xops[17] = GEN_INT (0xff000000);
5174 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
5176 /* Is there a known alignment and is it less than 4? */
5177 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) < 4)
5179 /* Is there a known alignment and is it not 2? */
5180 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
5182 xops[6] = gen_label_rtx (); /* Label when aligned to 3-byte */
5183 xops[7] = gen_label_rtx (); /* Label when aligned to 2-byte */
5185 /* Leave just the 3 lower bits.
5186 If this is a q-register, then the high part is used later
5187 therefore use andl rather than andb. */
5188 output_asm_insn (AS2 (and%L1,%4,%1), xops);
5190 /* Is aligned to 4-byte address when zero */
5191 output_asm_insn (AS1 (je,%l8), xops);
5193 /* Side-effect even Parity when %eax == 3 */
5194 output_asm_insn (AS1 (jp,%6), xops);
5196 /* Is it aligned to 2 bytes ? */
5197 if (QI_REG_P (xops[1]))
5198 output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
5200 output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
5202 output_asm_insn (AS1 (je,%7), xops);
5206 /* Since the alignment is 2, we have to check 2 or 0 bytes;
5207 check if is aligned to 4 - byte. */
5208 output_asm_insn (AS2 (and%L1,%3,%1), xops);
5210 /* Is aligned to 4-byte address when zero */
5211 output_asm_insn (AS1 (je,%l8), xops);
5214 xops[13] = gen_rtx_MEM (QImode, xops[0]);
5216 /* Now compare the bytes; compare with the high part of a q-reg
5217 gives shorter code. */
5218 if (QI_REG_P (xops[1]))
5220 /* Compare the first n unaligned byte on a byte per byte basis. */
5221 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
5223 /* When zero we reached the end. */
5224 output_asm_insn (AS1 (je,%l12), xops);
5226 /* Increment the address. */
5227 output_asm_insn (AS1 (inc%L0,%0), xops);
5229 /* Not needed with an alignment of 2 */
5230 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
5232 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5233 CODE_LABEL_NUMBER (xops[7]));
5234 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
5235 output_asm_insn (AS1 (je,%l12), xops);
5236 output_asm_insn (AS1 (inc%L0,%0), xops);
5238 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5239 CODE_LABEL_NUMBER (xops[6]));
5242 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
5246 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
5247 output_asm_insn (AS1 (je,%l12), xops);
5248 output_asm_insn (AS1 (inc%L0,%0), xops);
5250 /* Not needed with an alignment of 2 */
5251 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
5253 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5254 CODE_LABEL_NUMBER (xops[7]));
5255 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
5256 output_asm_insn (AS1 (je,%l12), xops);
5257 output_asm_insn (AS1 (inc%L0,%0), xops);
5259 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5260 CODE_LABEL_NUMBER (xops[6]));
5263 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
5266 output_asm_insn (AS1 (je,%l12), xops);
5267 output_asm_insn (AS1 (inc%L0,%0), xops);
5270 /* Generate loop to check 4 bytes at a time. It is not a good idea to
5271 align this loop. It gives only huge programs, but does not help to
5273 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[8]));
5275 xops[13] = gen_rtx_MEM (SImode, xops[0]);
5276 output_asm_insn (AS2 (mov%L1,%13,%1), xops);
5278 if (QI_REG_P (xops[1]))
5280 /* On i586 it is faster to combine the hi- and lo- part as
5281 a kind of lookahead. If anding both yields zero, then one
5282 of both *could* be zero, otherwise none of both is zero;
5283 this saves one instruction, on i486 this is slower
5284 tested with P-90, i486DX2-66, AMD486DX2-66 */
5287 output_asm_insn (AS2 (test%B1,%h1,%b1), xops);
5288 output_asm_insn (AS1 (jne,%l9), xops);
5291 /* Check first byte. */
5292 output_asm_insn (AS2 (test%B1,%b1,%b1), xops);
5293 output_asm_insn (AS1 (je,%l12), xops);
5295 /* Check second byte. */
5296 output_asm_insn (AS2 (test%B1,%h1,%h1), xops);
5297 output_asm_insn (AS1 (je,%l11), xops);
5300 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5301 CODE_LABEL_NUMBER (xops[9]));
5306 /* Check first byte. */
5307 output_asm_insn (AS2 (test%L1,%14,%1), xops);
5308 output_asm_insn (AS1 (je,%l12), xops);
5310 /* Check second byte. */
5311 output_asm_insn (AS2 (test%L1,%15,%1), xops);
5312 output_asm_insn (AS1 (je,%l11), xops);
5315 /* Check third byte. */
5316 output_asm_insn (AS2 (test%L1,%16,%1), xops);
5317 output_asm_insn (AS1 (je,%l10), xops);
5319 /* Check fourth byte and increment address. */
5320 output_asm_insn (AS2 (add%L0,%5,%0), xops);
5321 output_asm_insn (AS2 (test%L1,%17,%1), xops);
5322 output_asm_insn (AS1 (jne,%l8), xops);
5324 /* Now generate fixups when the compare stops within a 4-byte word. */
5325 output_asm_insn (AS2 (sub%L0,%4,%0), xops);
5327 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[10]));
5328 output_asm_insn (AS1 (inc%L0,%0), xops);
5330 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[11]));
5331 output_asm_insn (AS1 (inc%L0,%0), xops);
5333 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[12]));
5339 output_fp_conditional_move (which_alternative, operands)
5340 int which_alternative;
5343 enum rtx_code code = GET_CODE (operands[1]);
5345 /* This should never happen. */
5346 if (!(cc_prev_status.flags & CC_IN_80387)
5347 && (code == GT || code == LE || code == GE || code == LT))
5350 switch (which_alternative)
5353 /* r <- cond ? arg : r */
5354 output_asm_insn (AS2 (fcmov%F1,%2,%0), operands);
5358 /* r <- cond ? r : arg */
5359 output_asm_insn (AS2 (fcmov%f1,%3,%0), operands);
5370 output_int_conditional_move (which_alternative, operands)
5371 int which_alternative;
5374 enum rtx_code code = GET_CODE (operands[1]);
5376 /* This is very tricky. We have to do it right. For a code segement
5385 final_scan_insn () may delete the insn which sets CC. We have to
5386 tell final_scan_insn () if it should be reinserted. When CODE is
5387 GT or LE, we have to check the CC_NO_OVERFLOW bit and return
5388 NULL_PTR to tell final to reinsert the test insn because the
5389 conditional move cannot be handled properly without it. */
5390 if ((code == GT || code == LE)
5391 && (cc_prev_status.flags & CC_NO_OVERFLOW))
5394 switch (which_alternative)
5397 /* r <- cond ? arg : r */
5398 output_asm_insn (AS2 (cmov%C1,%2,%0), operands);
5402 /* r <- cond ? r : arg */
5403 output_asm_insn (AS2 (cmov%c1,%3,%0), operands);
5414 x86_adjust_cost (insn, link, dep_insn, cost)
5415 rtx insn, link, dep_insn;
5420 if (GET_CODE (dep_insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
5423 if (GET_CODE (dep_insn) == INSN
5424 && GET_CODE (PATTERN (dep_insn)) == SET
5425 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG
5426 && GET_CODE (insn) == INSN
5427 && GET_CODE (PATTERN (insn)) == SET
5428 && !reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
5429 SET_SRC (PATTERN (insn))))
5435 case PROCESSOR_PENTIUM:
5436 if (cost != 0 && is_fp_insn (insn) && is_fp_insn (dep_insn)
5437 && !is_fp_dest (dep_insn))
5440 if (agi_dependent (insn, dep_insn))
5441 return cost ? cost + 1 : 2;
5443 if (GET_CODE (insn) == INSN
5444 && GET_CODE (PATTERN (insn)) == SET
5445 && SET_DEST (PATTERN (insn)) == cc0_rtx
5446 && (next_inst = next_nonnote_insn (insn))
5447 && GET_CODE (next_inst) == JUMP_INSN)
5448 /* compare probably paired with jump */
5451 /* Stores stalls one cycle longer than other insns. */
5452 if (is_fp_insn (insn) && cost && is_fp_store (dep_insn))
5457 if (!is_fp_dest (dep_insn))
5459 if(!agi_dependent (insn, dep_insn))
5465 if (is_fp_store (insn) && is_fp_insn (dep_insn)
5466 && NEXT_INSN (insn) && NEXT_INSN (NEXT_INSN (insn))
5467 && NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))
5468 && (GET_CODE (NEXT_INSN (insn)) == INSN)
5469 && (GET_CODE (NEXT_INSN (NEXT_INSN (insn))) == JUMP_INSN)
5470 && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) == NOTE)
5471 && (NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn))))
5472 == NOTE_INSN_LOOP_END))
5480 /* Output assembly code for a left shift.
5482 Always use "sal" when shifting a memory operand or for a non constant
5485 When optimizing for size, we know that src == dest, and we should always
5486 use "sal". If src != dest, then copy src to dest and use "sal".
5488 Pentium and PPro (speed):
5490 When src == dest, use "add" for a shift counts of one, else use
5491 "sal". If we modeled Pentium AGI stalls and U/V pipelining better we
5492 would want to generate lea for some shifts on the Pentium.
5494 When src != dest, use "lea" for small shift counts. Otherwise,
5495 copy src to dest and use the normal shifting code. Exception for
5496 TARGET_DOUBLE_WITH_ADD. */
5499 output_ashl (insn, operands)
5500 rtx insn, *operands;
5502 /* Handle case where srcreg != dstreg. */
5503 if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
5505 if (TARGET_DOUBLE_WITH_ADD && INTVAL (operands[2]) == 1)
5506 switch (GET_MODE (operands[0]))
5509 output_asm_insn (AS2 (mov%L0,%1,%0), operands);
5510 return AS2 (add%L0,%1,%0);
5512 output_asm_insn (AS2 (mov%L0,%k1,%k0), operands);
5513 if (i386_cc_probably_useless_p (insn))
5516 return AS2 (add%L0,%k1,%k0);
5518 return AS2 (add%W0,%k1,%k0);
5520 output_asm_insn (AS2 (mov%B0,%1,%0), operands);
5521 return AS2 (add%B0,%1,%0);
5529 /* This should be extremely rare (impossible?). We can not encode a
5530 shift of the stack pointer using an lea instruction. So copy the
5531 stack pointer into the destination register and use an lea. */
5532 if (operands[1] == stack_pointer_rtx)
5534 output_asm_insn (AS2 (mov%L0,%k1,%k0), operands);
5535 operands[1] = operands[0];
5538 /* For shifts up to and including 3 bits, use lea. */
5539 operands[1] = gen_rtx_MULT (SImode,
5540 gen_rtx_REG (SImode, REGNO (operands[1])),
5541 GEN_INT (1 << INTVAL (operands[2])));
5542 return AS2 (lea%L0,%a1,%k0);
5546 /* Source and destination match. */
5548 /* Handle variable shift. */
5549 if (REG_P (operands[2]))
5550 switch (GET_MODE (operands[0]))
5553 return AS2 (sal%L0,%b2,%0);
5555 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn))
5558 return AS2 (sal%L0,%b2,%k0);
5561 return AS2 (sal%W0,%b2,%0);
5563 return AS2 (sal%B0,%b2,%0);
5568 /* Always perform shift by 1 using an add instruction. */
5569 if (REG_P (operands[0]) && operands[2] == const1_rtx)
5570 switch (GET_MODE (operands[0]))
5573 return AS2 (add%L0,%0,%0);
5575 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn))
5578 return AS2 (add%L0,%k0,%k0);
5581 return AS2 (add%W0,%0,%0);
5583 return AS2 (add%B0,%0,%0);
5589 /* ??? Currently disabled. Because our model of Pentium is far from being
5590 exact, this change will need some benchmarking. */
5591 /* Shift reg by 2 or 3 use an lea instruction for Pentium if this is
5592 insn is expected to issue into the V pipe (the insn's mode will be
5593 TImode for a U pipe, and !TImode for a V pipe instruction). */
5595 && REG_P (operands[0])
5596 && GET_CODE (operands[2]) == CONST_INT
5597 && INTVAL (operands[2]) <= 3
5598 && (int)ix86_cpu == (int)PROCESSOR_PENTIUM
5599 && GET_MODE (insn) != TImode)
5602 operands[1] = gen_rtx_MULT (SImode, gen_rtx_REG (SImode, REGNO (operands[1])),
5603 GEN_INT (1 << INTVAL (operands[2])));
5604 return AS2 (lea%L0,%a1,%0);
5608 /* Otherwise use a shift instruction. */
5609 switch (GET_MODE (operands[0]))
5612 return AS2 (sal%L0,%2,%0);
5614 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn))
5617 return AS2 (sal%L0,%2,%k0);
5620 return AS2 (sal%W0,%2,%0);
5622 return AS2 (sal%B0,%2,%0);
5628 /* Given the memory address ADDR, calculate the length of the address or
5629 the length of just the displacement (controlled by DISP_LENGTH).
5631 The length returned does not include the one-byte modrm, opcode,
5635 memory_address_info (addr, disp_length)
5639 rtx base, index, disp, scale;
5643 if (GET_CODE (addr) == PRE_DEC
5644 || GET_CODE (addr) == POST_INC)
5647 /* Register Indirect. */
5648 if (register_operand (addr, Pmode))
5650 /* Special cases: ebp and esp need the two-byte modrm form.
5652 We change [ESI] to [ESI+0] on the K6 when not optimizing
5654 if (addr == stack_pointer_rtx
5655 || addr == arg_pointer_rtx
5656 || addr == frame_pointer_rtx
5657 || (REGNO_REG_CLASS (REGNO (addr)) == SIREG
5658 && ix86_cpu == PROCESSOR_K6 && !optimize_size))
5664 /* Direct Addressing. */
5665 if (CONSTANT_P (addr))
5668 index = base = disp = scale = NULL_RTX;
5669 op0 = XEXP (addr, 0);
5670 op1 = XEXP (addr, 1);
5672 if (GET_CODE (addr) == PLUS)
5674 if (register_operand (op0, Pmode))
5676 if (register_operand (op1, Pmode))
5677 index = op0, base = op1;
5679 base = op0, disp = op1;
5681 else if (GET_CODE (op0) == MULT)
5683 index = XEXP (op0, 0);
5684 scale = XEXP (op0, 1);
5685 if (register_operand (op1, Pmode))
5690 else if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
5692 index = XEXP (XEXP (op0, 0), 0);
5693 scale = XEXP (XEXP (op0, 0), 1);
5694 base = XEXP (op0, 1);
5697 else if (GET_CODE (op0) == PLUS)
5699 index = XEXP (op0, 0);
5700 base = XEXP (op0, 1);
5706 else if (GET_CODE (addr) == MULT
5707 /* We're called for lea too, which implements ashift on occasion. */
5708 || GET_CODE (addr) == ASHIFT)
5710 index = XEXP (addr, 0);
5711 scale = XEXP (addr, 1);
5716 /* Allow arg pointer and stack pointer as index if there is not scaling */
5717 if (base && index && !scale
5718 && (index == stack_pointer_rtx
5719 || index == arg_pointer_rtx
5720 || index == frame_pointer_rtx))
5727 /* Special case: ebp cannot be encoded as a base without a displacement. */
5728 if (base == frame_pointer_rtx && !disp)
5731 /* Scaling can not be encoded without base or displacement.
5732 Except for scale == 1 where we can encode reg + reg instead of reg * 2. */
5734 && (!scale || GET_CODE (scale) != CONST_INT || (INTVAL (scale) != 1)))
5737 /* Find the length of the displacement constant. */
5741 if (GET_CODE (disp) == CONST_INT
5742 && CONST_OK_FOR_LETTER_P (INTVAL (disp), 'K'))
5748 /* An index requires the two-byte modrm form. Not important
5749 if we are computing just length of the displacement. */
5750 if (index && ! disp_length)