2 * Adaptec U320 device driver firmware for Linux and FreeBSD.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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38 * POSSIBILITY OF SUCH DAMAGES.
40 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.seq,v 1.2.2.5 2003/06/10 03:26:07 gibbs Exp $
43 VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#94 $"
44 PATCH_ARG_LIST = "struct ahd_softc *ahd"
47 #include "aic79xx.reg"
48 #include "scsi_message.h"
51 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
52 test SEQINTCODE, 0xFF jz idle_loop;
53 SET_SEQINTCODE(NO_SEQINT)
58 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
60 * Convert ERROR status into a sequencer
61 * interrupt to handle the case of an
62 * interrupt collision on the hardware
65 test ERROR, 0xFF jz no_error_set;
66 SET_SEQINTCODE(SAW_HWERR)
69 SET_MODE(M_SCSI, M_SCSI)
70 test SCSISEQ0, ENSELO|ENARBO jnz idle_loop_checkbus;
71 test SEQ_FLAGS2, SELECTOUT_QFROZEN jnz idle_loop_checkbus;
72 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je idle_loop_checkbus;
74 * ENSELO is cleared by a SELDO, so we must test for SELDO
78 test SSTAT0, SELDO jnz select_out;
83 test SSTAT0, SELDO jnz select_out;
85 test SSTAT0, SELDI jnz select_in;
86 test SCSIPHASE, ~DATA_PHASE_MASK jz idle_loop_check_nonpackreq;
87 test SCSISIGO, ATNO jz idle_loop_check_nonpackreq;
88 call unexpected_nonpkt_phase_find_ctxt;
89 idle_loop_check_nonpackreq:
90 test SSTAT2, NONPACKREQ jz . + 2;
91 call unexpected_nonpkt_phase_find_ctxt;
92 if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
93 and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
94 cmp A, FIFO0FREE|FIFO1FREE jne . + 3;
95 and SBLKCTL, ~DIAGLEDEN|DIAGLEDON;
97 or SBLKCTL, DIAGLEDEN|DIAGLEDON;
99 call idle_loop_gsfifo_in_scsi_mode;
100 call idle_loop_service_fifos;
101 call idle_loop_cchan;
106 SET_MODE(M_SCSI, M_SCSI)
107 idle_loop_gsfifo_in_scsi_mode:
108 test LQISTAT2, LQIGSAVAIL jz return;
110 * We have received good status for this transaction. There may
111 * still be data in our FIFOs draining to the host. Complete
112 * the SCB only if all data has transferred to the host.
115 bmov SCBPTR, GSFIFO, 2;
118 * If a command completed before an attempted task management
119 * function completed, notify the host after disabling any
120 * pending select-outs.
122 test SCB_TASK_MANAGEMENT, 0xFF jz gsfifo_complete_normally;
123 test SSTAT0, SELDO|SELINGO jnz . + 2;
124 and SCSISEQ0, ~ENSELO;
125 SET_SEQINTCODE(TASKMGMT_CMD_CMPLT_OKAY)
126 gsfifo_complete_normally:
127 or SCB_CONTROL, STATUS_RCVD;
130 * Since this status did not consume a FIFO, we have to
131 * be a bit more dilligent in how we check for FIFOs pertaining
132 * to this transaction. There are two states that a FIFO still
133 * transferring data may be in.
135 * 1) Configured and draining to the host, with a FIFO handler.
136 * 2) Pending cfg4data, fifo not empty.
138 * Case 1 can be detected by noticing a non-zero FIFO active
139 * count in the SCB. In this case, we allow the routine servicing
140 * the FIFO to complete the SCB.
142 * Case 2 implies either a pending or yet to occur save data
143 * pointers for this same context in the other FIFO. So, if
144 * we detect case 1, we will properly defer the post of the SCB
145 * and achieve the desired result. The pending cfg4data will
146 * notice that status has been received and complete the SCB.
148 test SCB_FIFO_USE_COUNT, 0xFF jnz idle_loop_gsfifo_in_scsi_mode;
151 jmp idle_loop_gsfifo_in_scsi_mode;
153 idle_loop_service_fifos:
154 SET_MODE(M_DFF0, M_DFF0)
155 test LONGJMP_ADDR[1], INVALID_ADDR jnz idle_loop_next_fifo;
158 SET_MODE(M_DFF1, M_DFF1)
159 test LONGJMP_ADDR[1], INVALID_ADDR jz longjmp;
164 SET_MODE(M_CCHAN, M_CCHAN)
165 test QOFF_CTLSTA, HS_MAILBOX_ACT jz hs_mailbox_empty;
166 mov LOCAL_HS_MAILBOX, HS_MAILBOX;
167 or QOFF_CTLSTA, HS_MAILBOX_ACT;
170 test CCSCBCTL, CCARREN|CCSCBEN jz scbdma_idle;
171 test CCSCBCTL, CCSCBDIR jnz fetch_new_scb_inprog;
172 test CCSCBCTL, CCSCBDONE jz return;
176 test CCSCBCTL, CCARREN jz fill_qoutfifo_dmadone;
178 * An SCB has been succesfully uploaded to the host.
179 * If the SCB was uploaded for some reason other than
180 * bad SCSI status (currently only for underruns), we
181 * queue the SCB for normal completion. Otherwise, we
182 * wait until any select-out activity has halted, and
183 * then notify the host so that the transaction can be
186 test SCB_SCSI_STATUS, 0xff jnz scbdma_notify_host;
187 and CCSCBCTL, ~(CCARREN|CCSCBEN);
188 bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
189 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
190 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
192 SET_MODE(M_SCSI, M_SCSI)
193 test SCSISEQ0, ENSELO jnz return;
194 test SSTAT0, (SELDO|SELINGO) jnz return;
195 SET_MODE(M_CCHAN, M_CCHAN)
197 * Remove SCB and notify host.
199 and CCSCBCTL, ~(CCARREN|CCSCBEN);
200 bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
201 SET_SEQINTCODE(BAD_SCB_STATUS)
203 fill_qoutfifo_dmadone:
204 and CCSCBCTL, ~(CCARREN|CCSCBEN);
205 call qoutfifo_updated;
206 mvi COMPLETE_SCB_DMAINPROG_HEAD[1], SCB_LIST_NULL;
207 bmov QOUTFIFO_NEXT_ADDR, SCBHADDR, 4;
208 test QOFF_CTLSTA, SDSCB_ROLLOVR jz return;
209 bmov QOUTFIFO_NEXT_ADDR, SHARED_DATA_ADDR, 4;
210 xor QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID_TOGGLE ret;
214 * If there are more commands waiting to be dma'ed
215 * to the host, always coalesce. Otherwise honor the
218 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne coalesce_by_count;
219 cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL jne coalesce_by_count;
220 test LOCAL_HS_MAILBOX, ENINT_COALESCE jz issue_cmdcmplt;
223 * If we have relatively few commands outstanding, don't
224 * bother waiting for another command to complete.
226 test CMDS_PENDING[1], 0xFF jnz coalesce_by_count;
227 /* Add -1 so that jnc means <= not just < */
228 add A, -1, INT_COALESCING_MINCMDS;
229 add NONE, A, CMDS_PENDING;
233 * If coalescing, only coalesce up to the limit
234 * provided by the host driver.
237 mov A, INT_COALESCING_MAXCMDS;
238 add NONE, A, INT_COALESCING_CMDCOUNT;
241 * If the timer is not currently active,
244 test INTCTL, SWTMINTMASK jz return;
245 bmov SWTIMER, INT_COALESCING_TIMER, 2;
246 mvi CLRSEQINTSTAT, CLRSEQ_SWTMRTO;
247 or INTCTL, SWTMINTEN|SWTIMER_START;
248 and INTCTL, ~SWTMINTMASK ret;
251 mvi INTSTAT, CMDCMPLT;
252 clr INT_COALESCING_CMDCOUNT;
253 or INTCTL, SWTMINTMASK ret;
256 fetch_new_scb_inprog:
257 test CCSCBCTL, ARRDONE jz return;
259 and CCSCBCTL, ~(CCARREN|CCSCBEN);
260 bmov REG0, SCBPTR, 2;
263 adc CMDS_PENDING[1], A;
264 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
266 * "Short Luns" are not placed into outgoing LQ
267 * packets in the correct byte order. Use a full
268 * sized lun field instead and fill it with the
269 * one byte of lun information we support.
271 mov SCB_PKT_LUN[6], SCB_LUN;
274 * The FIFO use count field is shared with the
275 * tag set by the host so that our SCB dma engine
276 * knows the correct location to store the SCB.
277 * Set it to zero before processing the SCB.
279 mov SCB_FIFO_USE_COUNT, ALLZEROS;
280 /* Update the next SCB address to download. */
281 bmov NEXT_QUEUED_SCB_ADDR, SCB_NEXT_SCB_BUSADDR, 4;
282 mvi SCB_NEXT[1], SCB_LIST_NULL;
283 mvi SCB_NEXT2[1], SCB_LIST_NULL;
284 /* Increment our position in the QINFIFO. */
285 mov NONE, SNSCB_QOFF;
287 * SCBs that want to send messages are always
288 * queued independently. This ensures that they
289 * are at the head of the SCB list to select out
290 * to a target and we will see the MK_MESSAGE flag.
292 test SCB_CONTROL, MK_MESSAGE jnz first_new_target_scb;
293 shr SINDEX, 3, SCB_SCSIID;
295 mvi SINDEX[1], (WAITING_SCB_TAILS >> 8);
296 bmov DINDEX, SINDEX, 2;
297 bmov SCBPTR, SINDIR, 2;
298 bmov DINDIR, REG0, 2;
299 cmp SCBPTR[1], SCB_LIST_NULL je first_new_target_scb;
300 bmov SCB_NEXT, REG0, 2 ret;
301 first_new_target_scb:
302 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je first_new_scb;
303 bmov SCBPTR, WAITING_TID_TAIL, 2;
304 bmov SCB_NEXT2, REG0, 2;
305 bmov WAITING_TID_TAIL, REG0, 2 ret;
307 bmov WAITING_TID_HEAD, REG0, 2;
308 bmov WAITING_TID_TAIL, REG0, 2 ret;
313 * Give precedence to downloading new SCBs to execute
314 * unless select-outs are currently frozen.
316 test SEQ_FLAGS2, SELECTOUT_QFROZEN jnz . + 2;
318 test QOFF_CTLSTA, NEW_SCB_AVAIL jnz fetch_new_scb;
319 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne dma_complete_scb;
320 cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL je return;
324 * Keep track of the SCBs we are dmaing just
325 * in case the DMA fails or is aborted.
327 mov A, QOUTFIFO_ENTRY_VALID_TAG;
328 bmov COMPLETE_SCB_DMAINPROG_HEAD, COMPLETE_SCB_HEAD, 2;
329 mvi CCSCBCTL, CCSCBRESET;
330 bmov SCBHADDR, QOUTFIFO_NEXT_ADDR, 4;
331 bmov SCBPTR, COMPLETE_SCB_HEAD, 2;
333 mov CCSCBRAM, SCBPTR;
334 or CCSCBRAM, A, SCBPTR[1];
335 mov NONE, SDSCB_QOFF;
336 inc INT_COALESCING_CMDCOUNT;
337 add CMDS_PENDING, -1;
338 adc CMDS_PENDING[1], -1;
339 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je fill_qoutfifo_done;
340 cmp CCSCBADDR, CCSCBADDR_MAX je fill_qoutfifo_done;
341 test QOFF_CTLSTA, SDSCB_ROLLOVR jnz fill_qoutfifo_done;
342 bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
343 jmp fill_qoutfifo_loop;
345 mov SCBHCNT, CCSCBADDR;
346 mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
347 bmov COMPLETE_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
348 mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL ret;
351 bmov SCBHADDR, NEXT_QUEUED_SCB_ADDR, 4;
352 mvi CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET jmp dma_scb;
354 bmov SCBPTR, COMPLETE_DMA_SCB_HEAD, 2;
355 bmov SCBHADDR, SCB_BUSADDR, 4;
356 mvi CCARREN|CCSCBEN|CCSCBRESET jmp dma_scb;
360 * Either post or fetch an SCB from host memory. The caller
361 * is responsible for polling for transfer completion.
363 * Prerequisits: Mode == M_CCHAN
364 * SINDEX contains CCSCBCTL flags
365 * SCBHADDR set to Host SCB address
366 * SCBPTR set to SCB src location on "push" operations
368 SET_SRC_MODE M_CCHAN;
369 SET_DST_MODE M_CCHAN;
371 mvi SCBHCNT, SCB_TRANSFER_SIZE;
372 mov CCSCBCTL, SINDEX ret;
376 bmov LONGJMP_ADDR, STACK, 2 ret;
378 bmov LONGJMP_ADDR, STACK, 2;
380 bmov STACK, LONGJMP_ADDR, 2 ret;
383 /*************************** Chip Bug Work Arounds ****************************/
385 * Must disable interrupts when setting the mode pointer
386 * register as an interrupt occurring mid update will
387 * fail to store the new mode value for restoration on
390 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
391 set_mode_work_around:
392 mvi SEQINTCTL, INTVEC1DSL;
393 mov MODE_PTR, SINDEX;
396 toggle_dff_mode_work_around:
397 mvi SEQINTCTL, INTVEC1DSL;
398 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
403 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
404 set_seqint_work_around:
405 mov SEQINTCODE, SINDEX;
406 mvi SEQINTCODE, NO_SEQINT ret;
409 /************************ Packetized LongJmp Routines *************************/
414 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
417 * Rev A hardware fails to update LAST/CURR/NEXTSCB
418 * correctly after a packetized selection in several
421 * 1) If only one command existed in the queue, the
422 * LAST/CURR/NEXTSCB are unchanged.
424 * 2) In a non QAS, protocol allowed phase change,
425 * the queue is shifted 1 too far. LASTSCB is
426 * the last SCB that was correctly processed.
428 * 3) In the QAS case, if the full list of commands
429 * was successfully sent, NEXTSCB is NULL and neither
430 * CURRSCB nor LASTSCB can be trusted. We must
431 * manually walk the list counting MAXCMDCNT elements
432 * to find the last SCB that was sent correctly.
434 * To simplify the workaround for this bug in SELDO
435 * handling, we initialize LASTSCB prior to enabling
436 * selection so we can rely on it even for case #1 above.
438 bmov LASTSCB, WAITING_TID_HEAD, 2;
440 bmov CURRSCB, WAITING_TID_HEAD, 2;
441 bmov SCBPTR, WAITING_TID_HEAD, 2;
442 shr SELOID, 4, SCB_SCSIID;
444 * If we want to send a message to the device, ensure
445 * we are selecting with atn irregardless of our packetized
446 * agreement. Since SPI4 only allows target reset or PPR
447 * messages if this is a packetized connection, the change
448 * to our negotiation table entry for this selection will
449 * be cleared when the message is acted on.
451 test SCB_CONTROL, MK_MESSAGE jz . + 3;
452 mov NEGOADDR, SELOID;
453 or NEGCONOPTS, ENAUTOATNO;
454 or SCSISEQ0, ENSELO ret;
458 * Allocate a FIFO for a non-packetized transaction.
459 * In RevA hardware, both FIFOs must be free before we
460 * can allocate a FIFO for a non-packetized transaction.
464 * Do whatever work is required to free a FIFO.
466 call idle_loop_service_fifos;
467 SET_MODE(M_SCSI, M_SCSI)
469 if ((ahd->bugs & AHD_NONPACKFIFO_BUG) != 0) {
470 and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
471 cmp A, FIFO0FREE|FIFO1FREE jne allocate_fifo_loop;
473 test DFFSTAT, FIFO1FREE jnz allocate_fifo1;
474 test DFFSTAT, FIFO0FREE jz allocate_fifo_loop;
475 mvi DFFSTAT, B_CURRFIFO_0;
476 SET_MODE(M_DFF0, M_DFF0)
477 bmov SCBPTR, ALLOCFIFO_SCBPTR, 2 ret;
482 mvi DFFSTAT, CURRFIFO_1;
483 SET_MODE(M_DFF1, M_DFF1)
484 bmov SCBPTR, ALLOCFIFO_SCBPTR, 2 ret;
487 * We have been reselected as an initiator
488 * or selected as a target.
493 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
495 * This exposes a window whereby a
496 * busfree just after a selection will
497 * be missed, but there is no other safe
498 * way to enable busfree detection if
499 * the busfreerev function is broken.
501 mvi CLRSINT1,CLRBUSFREE;
502 or SIMODE1, ENBUSFREE;
505 and SAVED_SCSIID, SELID_MASK, SELID;
508 mvi CLRSINT0, CLRSELDI;
512 * We have successfully selected out.
515 * Dequeue all SCBs sent from the waiting queue
516 * Requeue all SCBs *not* sent to the tail of the waiting queue
517 * Take Razor #494 into account for above.
519 * In Packetized Mode:
520 * Return to the idle loop. Our interrupt handler will take
521 * care of any incoming L_Qs.
523 * In Non-Packetize Mode:
524 * Continue to our normal state machine.
530 /* Clear out all SCBs that have been successfully sent. */
531 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
533 * For packetized, the LQO manager clears ENSELO on
534 * the assertion of SELDO. If we are non-packetized,
535 * LASTSCB and CURRSCB are accurate.
537 test SCSISEQ0, ENSELO jnz use_lastscb;
540 * The update is correct for LQOSTAT1 errors. All
541 * but LQOBUSFREE are handled by kernel interrupts.
542 * If we see LQOBUSFREE, return to the idle loop.
543 * Once we are out of the select_out critical section,
544 * the kernel will cleanup the LQOBUSFREE and we will
545 * eventually restart the selection if appropriate.
547 test LQOSTAT1, LQOBUSFREE jnz idle_loop;
550 * On a phase change oustside of packet boundaries,
551 * LASTSCB points to the currently active SCB context
554 test LQOSTAT2, LQOPHACHGOUTPKT jnz use_lastscb;
557 * If the hardware has traversed the whole list, NEXTSCB
558 * will be NULL, CURRSCB and LASTSCB cannot be trusted,
559 * but MAXCMDCNT is accurate. If we stop part way through
560 * the list or only had one command to issue, NEXTSCB[1] is
561 * not NULL and LASTSCB is the last command to go out.
563 cmp NEXTSCB[1], SCB_LIST_NULL jne use_lastscb;
568 bmov SCBPTR, WAITING_TID_HEAD, 2;
569 mvi SEQINTCTL, INTVEC1DSL;
570 mvi MODE_PTR, MK_MODE(M_CFG, M_CFG);
572 mvi MODE_PTR, MK_MODE(M_SCSI, M_SCSI);
576 test A, 0xFF jz found_last_sent_scb;
577 bmov SCBPTR, SCB_NEXT, 2;
578 jmp find_lastscb_loop;
580 bmov SCBPTR, LASTSCB, 2;
582 bmov CURRSCB, SCBPTR, 2;
586 * Untested - Verify with Rev B.
588 bmov SCBPTR, CURRSCB, 2;
592 * Requeue any SCBs not sent, to the tail of the waiting Q.
594 cmp SCB_NEXT[1], SCB_LIST_NULL je select_out_list_done;
597 * We know that neither the per-TID list nor the list of
598 * TIDs is empty. Use this knowledge to our advantage.
600 bmov REG0, SCB_NEXT, 2;
601 bmov SCBPTR, WAITING_TID_TAIL, 2;
602 bmov SCB_NEXT2, REG0, 2;
603 bmov WAITING_TID_TAIL, REG0, 2;
604 jmp select_out_inc_tid_q;
606 select_out_list_done:
608 * The whole list made it. Just clear our TID's tail pointer
609 * unless we were queued independently due to our need to
612 test SCB_CONTROL, MK_MESSAGE jnz select_out_inc_tid_q;
613 shr DINDEX, 3, SCB_SCSIID;
614 or DINDEX, 1; /* Want only the second byte */
615 mvi DINDEX[1], ((WAITING_SCB_TAILS) >> 8);
616 mvi DINDIR, SCB_LIST_NULL;
617 select_out_inc_tid_q:
618 bmov SCBPTR, WAITING_TID_HEAD, 2;
619 bmov WAITING_TID_HEAD, SCB_NEXT2, 2;
620 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL jne . + 2;
621 mvi WAITING_TID_TAIL[1], SCB_LIST_NULL;
622 bmov SCBPTR, CURRSCB, 2;
623 mvi CLRSINT0, CLRSELDO;
624 test LQOSTAT2, LQOPHACHGOUTPKT jnz unexpected_nonpkt_phase;
625 test LQOSTAT1, LQOPHACHGINPKT jnz unexpected_nonpkt_phase;
628 * If this is a packetized connection, return to our
629 * idle_loop and let our interrupt handler deal with
630 * any connection setup/teardown issues. The only
631 * exceptions are the case of MK_MESSAGE and task management
634 if ((ahd->bugs & AHD_LQO_ATNO_BUG) != 0) {
636 * In the A, the LQO manager transitions to LQOSTOP0 even if
637 * we have selected out with ATN asserted and the target
638 * REQs in a non-packet phase.
640 test SCB_CONTROL, MK_MESSAGE jz select_out_no_message;
641 test SCSISIGO, ATNO jnz select_out_non_packetized;
642 select_out_no_message:
644 test LQOSTAT2, LQOSTOP0 jz select_out_non_packetized;
645 test SCB_TASK_MANAGEMENT, 0xFF jz idle_loop;
646 SET_SEQINTCODE(TASKMGMT_FUNC_COMPLETE)
649 select_out_non_packetized:
650 /* Non packetized request. */
651 and SCSISEQ0, ~ENSELO;
652 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
654 * This exposes a window whereby a
655 * busfree just after a selection will
656 * be missed, but there is no other safe
657 * way to enable busfree detection if
658 * the busfreerev function is broken.
660 mvi CLRSINT1,CLRBUSFREE;
661 or SIMODE1, ENBUSFREE;
663 mov SAVED_SCSIID, SCB_SCSIID;
664 mov SAVED_LUN, SCB_LUN;
665 mvi SEQ_FLAGS, NO_CDB_SENT;
670 * As soon as we get a successful selection, the target
671 * should go into the message out phase since we have ATN
674 mvi MSG_OUT, MSG_IDENTIFYFLAG;
677 * Main loop for information transfer phases. Wait for the
678 * target to assert REQ before checking MSG, C/D and I/O for
687 test A, ~P_DATAIN_DT jz p_data;
688 cmp A,P_COMMAND je p_command;
689 cmp A,P_MESGOUT je p_mesgout;
690 cmp A,P_STATUS je p_status;
691 cmp A,P_MESGIN je p_mesgin;
693 SET_SEQINTCODE(BAD_PHASE)
694 jmp ITloop; /* Try reading the bus again. */
697 * Command phase. Set up the DMA registers and let 'er rip.
700 test SEQ_FLAGS, NOT_IDENTIFIED jz p_command_okay;
701 SET_SEQINTCODE(PROTO_VIOLATION)
703 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
704 jnz p_command_allocate_fifo;
706 * Command retry. Free our current FIFO and
707 * re-allocate a FIFO so transfer state is
712 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
713 SET_MODE(M_SCSI, M_SCSI)
714 p_command_allocate_fifo:
715 bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
719 add NONE, -17, SCB_CDB_LEN;
720 jnc p_command_embedded;
722 bmov HADDR[0], SCB_HOST_CDB_PTR, 9;
723 mvi SG_CACHE_PRE, LAST_SEG;
724 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
727 bmov SHCNT[0], SCB_CDB_LEN, 1;
728 bmov DFDAT, SCB_CDB_STORE, 16;
731 and SEQ_FLAGS, ~NO_CDB_SENT;
732 test DFCNTRL, SCSIEN jnz .;
734 * DMA Channel automatically disabled.
735 * Don't allow a data phase if the command
736 * was not fully transferred.
738 test SSTAT2, SDONE jnz ITloop;
739 or SEQ_FLAGS, NO_CDB_SENT;
744 * Status phase. Wait for the data byte to appear, then read it
745 * and store it into the SCB.
750 test SEQ_FLAGS,NOT_IDENTIFIED jnz mesgin_proto_violation;
752 mov SCB_SCSI_STATUS, SCSIDAT;
753 or SCB_CONTROL, STATUS_RCVD;
757 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
758 * indentify message sequence and send it to the target. The host may
759 * override this behavior by setting the MK_MESSAGE bit in the SCB
760 * control byte. This will cause us to interrupt the host and allow
761 * it to handle the message phase completely on its own. If the bit
762 * associated with this target is set, we will also interrupt the host,
763 * thereby allowing it to send a message on the next selection regardless
764 * of the transaction being sent.
766 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
767 * This is done to allow the host to send messages outside of an identify
768 * sequence while protecting the seqencer from testing the MK_MESSAGE bit
769 * on an SCB that might not be for the current nexus. (For example, a
770 * BDR message in responce to a bad reselection would leave us pointed to
771 * an SCB that doesn't have anything to do with the current target).
773 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
776 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
777 * in case the target decides to put us in this phase for some strange
781 /* Turn on ATN for the retry */
785 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
786 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
788 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN;
789 test SCB_CONTROL, DISCENB jnz . + 2;
790 and SINDEX, ~DISCENB;
792 * Send a tag message if TAG_ENB is set in the SCB control block.
793 * Use SCB_NONPACKET_TAG as the tag value.
796 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
797 mov SCSIDAT, SINDEX; /* Send the identify message */
799 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
800 and SCSIDAT,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
802 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
803 mov SCBPTR jmp p_mesgout_onebyte;
805 * Interrupt the driver, and allow it to handle this message
806 * phase and any required retries.
809 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
810 jmp host_message_loop;
813 mvi CLRSINT1, CLRATNO;
817 * If the next bus phase after ATN drops is message out, it means
818 * that the target is requesting that the last message(s) be resent.
821 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
824 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
825 mov LAST_MSG, MSG_OUT;
826 mvi MSG_OUT, MSG_NOOP; /* No message left */
830 * Message in phase. Bytes are read using Automatic PIO mode.
833 /* read the 1st message byte */
834 mvi ACCUM call inb_first;
836 test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
837 cmp A,MSG_DISCONNECT je mesgin_disconnect;
838 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
839 cmp ALLZEROS,A je mesgin_complete;
840 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
841 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
842 cmp A,MSG_NOOP je mesgin_done;
845 * Pushed message loop to allow the kernel to
846 * run it's own message state engine. To avoid an
847 * extra nop instruction after signaling the kernel,
848 * we perform the phase_lock before checking to see
849 * if we should exit the loop and skip the phase_lock
850 * in the ITloop. Performing back to back phase_locks
851 * shouldn't hurt, but why do it twice...
854 call phase_lock; /* Benign the first time through. */
855 SET_SEQINTCODE(HOST_MSG_LOOP)
856 cmp RETURN_1, EXIT_MSG_LOOP je ITloop;
857 cmp RETURN_1, CONT_MSG_LOOP_WRITE jne . + 3;
858 mov SCSIDAT, RETURN_2;
859 jmp host_message_loop;
860 /* Must be CONT_MSG_LOOP_READ */
861 mov NONE, SCSIDAT; /* ACK Byte */
862 jmp host_message_loop;
864 mesgin_ign_wide_residue:
865 mov SAVED_MODE, MODE_PTR;
866 SET_MODE(M_SCSI, M_SCSI)
867 shr NEGOADDR, 4, SAVED_SCSIID;
869 RESTORE_MODE(SAVED_MODE)
870 test A, WIDEXFER jz mesgin_reject;
871 /* Pull the residue byte */
872 mvi REG0 call inb_next;
873 cmp REG0, 0x01 jne mesgin_reject;
874 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
875 test SCB_TASK_ATTRIBUTE, SCB_XFERLEN_ODD jnz mesgin_done;
876 SET_SEQINTCODE(IGN_WIDE_RES)
879 mesgin_proto_violation:
880 SET_SEQINTCODE(PROTO_VIOLATION)
883 mvi MSG_MESSAGE_REJECT call mk_mesg;
885 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
888 #define INDEX_DISC_LIST(scsiid, lun) \
889 and A, 0xC0, scsiid; \
892 and SINDEX, 0x30, scsiid; \
893 shr SINDEX, 3; /* Multiply by 2 */ \
894 add SINDEX, (SCB_DISCONNECTED_LISTS & 0xFF); \
895 mvi SINDEX[1], ((SCB_DISCONNECTED_LISTS >> 8) & 0xFF)
899 * Determine whether a target is using tagged or non-tagged
900 * transactions by first looking at the transaction stored in
901 * the per-device, disconnected array. If there is no untagged
902 * transaction for this target, this must be a tagged transaction.
904 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
905 INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
906 bmov DINDEX, SINDEX, 2;
907 bmov REG0, SINDIR, 2;
908 cmp REG0[1], SCB_LIST_NULL je snoop_tag;
909 /* Untagged. Clear the busy table entry and setup the SCB. */
910 bmov DINDIR, ALLONES, 2;
911 bmov SCBPTR, REG0, 2;
915 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
916 * If we get one, we use the tag returned to find the proper
917 * SCB. After receiving the tag, look for the SCB at SCB locations tag and
921 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
924 mov NONE, SCSIDAT; /* ACK Identify MSG */
926 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
929 cmp LASTPHASE, P_MESGIN jne not_found_ITloop;
930 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
933 cmp SCSIBUS, MSG_SIMPLE_Q_TAG jne not_found;
936 mvi SCBPTR call inb_next; /* tag value */
938 test SCB_CONTROL,DISCONNECTED jz verify_other_scb;
940 cmp SCB_SCSIID, A jne verify_other_scb;
942 cmp SCB_LUN, A je setup_SCB_disconnected;
945 test SCBPTR[1], 0xFF jnz verify_scb;
949 * Ensure that the SCB the tag points to is for
950 * an SCB transaction to the reconnecting target.
953 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
956 test SCB_CONTROL,DISCONNECTED jz not_found;
957 setup_SCB_disconnected:
958 and SCB_CONTROL,~DISCONNECTED;
959 clr SEQ_FLAGS; /* make note of IDENTIFY */
960 test SCB_SGPTR, SG_LIST_NULL jnz . + 3;
961 bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
963 /* See if the host wants to send a message upon reconnection */
964 test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
965 mvi HOST_MSG call mk_mesg;
969 SET_SEQINTCODE(NO_MATCH)
973 SET_SEQINTCODE(NO_MATCH)
977 * We received a "command complete" message. Put the SCB on the complete
978 * queue and trigger a completion interrupt via the idle loop. Before doing
979 * so, check to see if there
980 * is a residual or the status byte is something other than STATUS_GOOD (0).
981 * In either of these conditions, we upload the SCB back to the host so it can
982 * process this information. In the case of a non zero status byte, we
983 * additionally interrupt the kernel driver synchronously, allowing it to
984 * decide if sense should be retrieved. If the kernel driver wishes to request
985 * sense, it will fill the kernel SCB with a request sense command, requeue
986 * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting
987 * RETURN_1 to SEND_SENSE.
992 * If ATN is raised, we still want to give the target a message.
993 * Perhaps there was a parity error on this last message byte.
994 * Either way, the target should take us to message out phase
995 * and then attempt to complete the command again. We should use a
996 * critical section here to guard against a timeout triggering
997 * for this command and setting ATN while we are still processing
999 test SCSISIGI, ATNI jnz mesgin_done;
1003 * If we are identified and have successfully sent the CDB,
1004 * any status will do. Optimize this fast path.
1006 test SCB_CONTROL, STATUS_RCVD jz mesgin_proto_violation;
1007 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz complete_accepted;
1010 * If the target never sent an identify message but instead went
1011 * to mesgin to give an invalid message, let the host abort us.
1013 test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
1016 * If we recevied good status but never successfully sent the
1017 * cdb, abort the command.
1019 test SCB_SCSI_STATUS,0xff jnz complete_accepted;
1020 test SEQ_FLAGS, NO_CDB_SENT jnz mesgin_proto_violation;
1024 * See if we attempted to deliver a message but the target ingnored us.
1026 test SCB_CONTROL, MK_MESSAGE jz complete_nomsg;
1027 SET_SEQINTCODE(MKMSG_FAILED)
1029 call queue_scb_completion;
1033 /* Cancel any pending select-out. */
1034 test SSTAT0, SELDO|SELINGO jnz . + 2;
1035 and SCSISEQ0, ~ENSELO;
1038 add QFREEZE_COUNT, 1;
1039 adc QFREEZE_COUNT[1], A;
1040 or SEQ_FLAGS2, SELECTOUT_QFROZEN;
1041 mov A, ACCUM_SAVE ret;
1044 * Complete the current FIFO's SCB if data for this same
1045 * SCB is not transferring in the other FIFO.
1047 SET_SRC_MODE M_DFF1;
1048 SET_DST_MODE M_DFF1;
1049 pkt_complete_scb_if_fifos_idle:
1050 bmov ARG_1, SCBPTR, 2;
1051 mvi DFFSXFRCTL, CLRCHN;
1052 SET_MODE(M_SCSI, M_SCSI)
1053 bmov SCBPTR, ARG_1, 2;
1054 test SCB_FIFO_USE_COUNT, 0xFF jnz return;
1055 queue_scb_completion:
1056 test SCB_SCSI_STATUS,0xff jnz bad_status;
1058 * Check for residuals
1060 test SCB_SGPTR, SG_LIST_NULL jnz complete; /* No xfer */
1061 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
1062 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
1064 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
1065 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
1067 cmp SCB_SCSI_STATUS, STATUS_PKT_SENSE je upload_scb;
1071 * Restore SCB TAG since we reuse this field
1072 * in the sequencer. We don't want to corrupt
1075 bmov SCB_TAG, SCBPTR, 2;
1076 bmov SCB_NEXT_COMPLETE, COMPLETE_DMA_SCB_HEAD, 2;
1077 bmov COMPLETE_DMA_SCB_HEAD, SCBPTR, 2;
1078 or SCB_SGPTR, SG_STATUS_VALID ret;
1081 * Is it a disconnect message? Set a flag in the SCB to remind us
1082 * and await the bus going free. If this is an untagged transaction
1083 * store the SCB id for it in our untagged target table for lookup on
1088 * If ATN is raised, we still want to give the target a message.
1089 * Perhaps there was a parity error on this last message byte
1090 * or we want to abort this command. Either way, the target
1091 * should take us to message out phase and then attempt to
1093 * XXX - Wait for more testing.
1094 test SCSISIGI, ATNI jnz mesgin_done;
1096 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT
1097 jnz mesgin_proto_violation;
1098 or SCB_CONTROL,DISCONNECTED;
1099 test SCB_CONTROL, TAG_ENB jnz await_busfree;
1101 bmov REG0, SCBPTR, 2;
1102 INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
1103 bmov DINDEX, SINDEX, 2;
1104 bmov DINDIR, REG0, 2;
1105 bmov SCBPTR, REG0, 2;
1108 and SIMODE1, ~ENBUSFREE;
1109 if ((ahd->bugs & AHD_BUSFREEREV_BUG) == 0) {
1111 * In the BUSFREEREV_BUG case, the
1112 * busfree status was cleared at the
1113 * beginning of the connection.
1115 mvi CLRSINT1,CLRBUSFREE;
1117 mov NONE, SCSIDAT; /* Ack the last byte */
1118 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1119 jnz await_busfree_not_m_dff;
1120 SET_SRC_MODE M_DFF1;
1121 SET_DST_MODE M_DFF1;
1122 await_busfree_clrchn:
1123 mvi DFFSXFRCTL, CLRCHN;
1124 await_busfree_not_m_dff:
1125 call clear_target_state;
1126 test SSTAT1,REQINIT|BUSFREE jz .;
1127 test SSTAT1, BUSFREE jnz idle_loop;
1128 SET_SEQINTCODE(MISSED_BUSFREE)
1132 * Save data pointers message:
1133 * Copying RAM values back to SCB, for Save Data Pointers message, but
1134 * only if we've actually been into a data phase to change them. This
1135 * protects against bogus data in scratch ram and the residual counts
1136 * since they are only initialized when we go into data_in or data_out.
1137 * Ack the message as soon as possible.
1139 SET_SRC_MODE M_DFF1;
1140 SET_DST_MODE M_DFF1;
1142 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1143 test SEQ_FLAGS, DPHASE jz ITloop;
1149 * If we are asked to save our position at the end of the
1150 * transfer, just mark us at the end rather than perform a
1153 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz save_pointers_full;
1154 or SCB_SGPTR, SG_LIST_NULL ret;
1158 * The SCB_DATAPTR becomes the current SHADDR.
1159 * All other information comes directly from our residual
1162 bmov SCB_DATAPTR, SHADDR, 8;
1163 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8 ret;
1166 * Restore pointers message? Data pointers are recopied from the
1167 * SCB anytime we enter a data phase for the first time, so all
1168 * we need to do is clear the DPHASE flag and let the data phase
1169 * code do the rest. We also reset/reallocate the FIFO to make
1170 * sure we have a clean start for the next data or command phase.
1173 and SEQ_FLAGS, ~DPHASE;
1174 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1)) jnz msgin_rdptrs_get_fifo;
1175 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1176 SET_MODE(M_SCSI, M_SCSI)
1177 msgin_rdptrs_get_fifo:
1182 mvi LASTPHASE, P_BUSFREE;
1183 /* clear target specific flags */
1184 mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT ret;
1187 if ((ahd->bugs & AHD_EARLY_REQ_BUG) != 0) {
1189 * Don't ignore persistent REQ assertions just because
1190 * they were asserted within the bus settle delay window.
1191 * This allows us to tolerate devices like the GEM318
1192 * that violate the SCSI spec. We are careful not to
1193 * count REQ while we are waiting for it to fall during
1194 * an async phase due to our asserted ACK. Each
1195 * sequencer instruction takes ~25ns, so the REQ must
1196 * last at least 100ns in order to be counted as a true
1199 test SCSIPHASE, 0xFF jnz phase_locked;
1200 test SCSISIGI, ACKI jnz phase_lock;
1201 test SCSISIGI, REQI jz phase_lock;
1202 test SCSIPHASE, 0xFF jnz phase_locked;
1203 test SCSISIGI, ACKI jnz phase_lock;
1204 test SCSISIGI, REQI jz phase_lock;
1207 test SCSIPHASE, 0xFF jz .;
1209 test SSTAT1, SCSIPERR jnz phase_lock;
1210 phase_lock_latch_phase:
1211 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
1214 * Functions to read data in Automatic PIO mode.
1216 * An ACK is not sent on input from the target until SCSIDATL is read from.
1217 * So we wait until SCSIDATL is latched (the usual way), then read the data
1218 * byte directly off the bus using SCSIBUSL. When we have pulled the ATN
1219 * line, or we just want to acknowledge the byte, then we do a dummy read
1220 * from SCISDATL. The SCSI spec guarantees that the target will hold the
1221 * data byte on the bus until we send our ACK.
1223 * The assumption here is that these are called in a particular sequence,
1224 * and that REQ is already set when inb_first is called. inb_{first,next}
1225 * use the same calling convention as inb.
1228 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1231 * If there is a parity error, wait for the kernel to
1232 * see the interrupt and prepare our message response
1233 * before continuing.
1235 test SCSIPHASE, 0xFF jz .;
1236 test SSTAT1, SCSIPERR jnz inb_next_wait;
1237 inb_next_check_phase:
1238 and LASTPHASE, PHASE_MASK, SCSISIGI;
1239 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1243 mov DINDIR,SCSIBUS ret; /*read byte directly from bus*/
1245 mov NONE,SCSIDAT ret; /*dummy read from latch to ACK*/
1249 mov MSG_OUT,SINDEX ret;
1251 SET_SRC_MODE M_DFF1;
1252 SET_DST_MODE M_DFF1;
1254 test SG_STATE, FETCH_INPROG jz disable_ccsgen_fetch_done;
1256 disable_ccsgen_fetch_done:
1261 * Do we have any prefetch left???
1263 test SG_STATE, SEGS_AVAIL jnz idle_sg_avail;
1266 * Can this FIFO have access to the S/G cache yet?
1268 test CCSGCTL, SG_CACHE_AVAIL jz return;
1270 /* Did we just finish fetching segs? */
1271 test CCSGCTL, CCSGDONE jnz idle_sgfetch_complete;
1273 /* Are we actively fetching segments? */
1274 test CCSGCTL, CCSGENACK jnz return;
1277 * We fetch a "cacheline aligned" and sized amount of data
1278 * so we don't end up referencing a non-existant page.
1279 * Cacheline aligned is in quotes because the kernel will
1280 * set the prefetch amount to a reasonable level if the
1281 * cacheline size is unknown.
1283 bmov SGHADDR, SCB_RESIDUAL_SGPTR, 4;
1284 mvi SGHCNT, SG_PREFETCH_CNT;
1285 if ((ahd->bugs & AHD_REG_SLOW_SETTLE_BUG) != 0) {
1287 * Need two instruction between "touches" of SGHADDR.
1291 and SGHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
1292 mvi CCSGCTL, CCSGEN|CCSGRESET;
1293 or SG_STATE, FETCH_INPROG ret;
1294 idle_sgfetch_complete:
1296 * Guard against SG_CACHE_AVAIL activating during sg fetch
1297 * request in the other FIFO.
1299 test SG_STATE, FETCH_INPROG jz return;
1301 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
1302 mvi SG_STATE, SEGS_AVAIL|LOADING_NEEDED;
1304 /* Does the hardware have space for another SG entry? */
1305 test DFSTATUS, PRELOAD_AVAIL jz return;
1307 * On the A, preloading a segment before HDMAENACK
1308 * comes true can clobber the shaddow address of the
1309 * first segment in the S/G FIFO. Wait until it is
1312 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) == 0) {
1313 test DFCNTRL, HDMAENACK jz return;
1315 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1316 bmov HADDR, CCSGRAM, 8;
1318 bmov HADDR, CCSGRAM, 4;
1320 bmov HCNT, CCSGRAM, 3;
1321 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
1322 if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
1323 and HADDR[4], SG_HIGH_ADDR_BITS, SCB_RESIDUAL_DATACNT[3];
1325 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1326 /* Skip 4 bytes of pad. */
1330 clr A; /* add sizeof(struct scatter) */
1331 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
1332 adc SCB_RESIDUAL_SGPTR[1],A;
1333 adc SCB_RESIDUAL_SGPTR[2],A;
1334 adc SCB_RESIDUAL_SGPTR[3],A;
1335 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
1336 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 3;
1337 or SINDEX, LAST_SEG;
1339 mov SG_CACHE_PRE, SINDEX;
1340 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
1342 * Use SCSIENWRDIS so that SCSIEN is never
1343 * modified by this operation.
1345 or DFCNTRL, PRELOADEN|HDMAEN|SCSIENWRDIS;
1347 or DFCNTRL, PRELOADEN|HDMAEN;
1350 * Do we have another segment in the cache?
1352 add NONE, SG_PREFETCH_CNT_LIMIT, CCSGADDR;
1354 and SG_STATE, ~SEGS_AVAIL ret;
1357 * Initialize the DMA address and counter from the SCB.
1360 bmov HADDR, SCB_DATAPTR, 11;
1361 and REG_ISR, ~SG_FULL_RESID, SCB_SGPTR[0];
1362 test SCB_DATACNT[3], SG_LAST_SEG jz . + 2;
1363 or REG_ISR, LAST_SEG;
1364 mov SG_CACHE_PRE, REG_ISR;
1365 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1367 * Since we've are entering a data phase, we will
1368 * rely on the SCB_RESID* fields. Initialize the
1369 * residual and clear the full residual flag.
1371 and SCB_SGPTR[0], ~SG_FULL_RESID;
1372 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
1373 /* If we need more S/G elements, tell the idle loop */
1374 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz . + 2;
1375 mvi SG_STATE, LOADING_NEEDED ret;
1380 test SG_STATE, LOADING_NEEDED jnz service_fifo;
1381 p_data_clear_handler:
1382 or LONGJMP_ADDR[1], INVALID_ADDR ret;
1385 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed;
1386 SET_SEQINTCODE(PROTO_VIOLATION)
1389 test SEQ_FLAGS, DPHASE jz data_phase_initialize;
1392 * If we re-enter the data phase after going through another
1393 * phase, our transfer location has almost certainly been
1394 * corrupted by the interveining, non-data, transfers. Ask
1395 * the host driver to fix us up based on the transfer residual
1396 * unless we already know that we should be bitbucketing.
1398 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1399 SET_SEQINTCODE(PDATA_REINIT)
1400 jmp data_phase_inbounds;
1404 * Turn on `Bit Bucket' mode, wait until the target takes
1405 * us to another phase, and then notify the host.
1407 mov SAVED_MODE, MODE_PTR;
1408 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1409 jnz bitbucket_not_m_dff;
1411 * Ensure that any FIFO contents are cleared out and the
1412 * FIFO free'd prior to starting the BITBUCKET. BITBUCKET
1413 * doesn't discard data already in the FIFO.
1415 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1416 SET_MODE(M_SCSI, M_SCSI)
1417 bitbucket_not_m_dff:
1418 or SXFRCTL1,BITBUCKET;
1419 /* Wait for non-data phase. */
1420 test SCSIPHASE, ~DATA_PHASE_MASK jz .;
1421 and SXFRCTL1, ~BITBUCKET;
1422 RESTORE_MODE(SAVED_MODE)
1423 SET_SRC_MODE M_DFF1;
1424 SET_DST_MODE M_DFF1;
1425 SET_SEQINTCODE(DATA_OVERRUN)
1428 data_phase_initialize:
1429 test SCB_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1430 call load_first_seg;
1431 data_phase_inbounds:
1432 /* We have seen a data phase at least once. */
1433 or SEQ_FLAGS, DPHASE;
1434 mov SAVED_MODE, MODE_PTR;
1435 test SG_STATE, LOADING_NEEDED jz data_group_dma_loop;
1436 call p_data_handle_xfer;
1437 data_group_dma_loop:
1439 * The transfer is complete if either the last segment
1440 * completes or the target changes phase. Both conditions
1441 * will clear SCSIEN.
1443 call idle_loop_service_fifos;
1444 call idle_loop_cchan;
1445 call idle_loop_gsfifo;
1446 RESTORE_MODE(SAVED_MODE)
1447 test DFCNTRL, SCSIEN jnz data_group_dma_loop;
1449 data_group_dmafinish:
1451 * The transfer has terminated either due to a phase
1452 * change, and/or the completion of the last segment.
1453 * We have two goals here. Do as much other work
1454 * as possible while the data fifo drains on a read
1455 * and respond as quickly as possible to the standard
1456 * messages (save data pointers/disconnect and command
1457 * complete) that usually follow a data phase.
1462 * Go ahead and shut down the DMA engine now.
1464 test DFCNTRL, DIRECTION jnz data_phase_finish;
1465 data_group_fifoflush:
1466 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1467 or DFCNTRL, FIFOFLUSH;
1470 * We have enabled the auto-ack feature. This means
1471 * that the controller may have already transferred
1472 * some overrun bytes into the data FIFO and acked them
1473 * on the bus. The only way to detect this situation is
1474 * to wait for LAST_SEG_DONE to come true on a completed
1475 * transfer and then test to see if the data FIFO is
1476 * non-empty. We know there is more data yet to transfer
1477 * if SG_LIST_NULL is not yet set, thus there cannot be
1480 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_finish;
1481 test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
1482 test DFSTATUS, FIFOEMP jnz data_phase_finish;
1487 * If the target has left us in data phase, loop through
1488 * the dma code again. We will only loop if there is a
1491 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1492 test SSTAT0, TARGET jnz data_phase_done;
1494 if ((ahd->flags & AHD_INITIATORROLE) != 0) {
1495 test SSTAT1, REQINIT jz .;
1496 test SCSIPHASE, DATA_PHASE_MASK jnz p_data;
1500 /* Kill off any pending prefetch */
1501 call disable_ccsgen;
1502 or LONGJMP_ADDR[1], INVALID_ADDR;
1504 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1505 test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
1507 and SEQ_FLAGS, ~DPHASE_PENDING;
1508 * For data-in phases, wait for any pending acks from the
1509 * initiator before changing phase. We only need to
1510 * send Ignore Wide Residue messages for data-in phases.
1511 test DFCNTRL, DIRECTION jz target_ITloop;
1512 test SSTAT1, REQINIT jnz .;
1513 test SCB_TASK_ATTRIBUTE, SCB_XFERLEN_ODD jz target_ITloop;
1514 SET_MODE(M_SCSI, M_SCSI)
1515 test NEGCONOPTS, WIDEXFER jz target_ITloop;
1518 * Issue an Ignore Wide Residue Message.
1519 mvi P_MESGIN|BSYO call change_phase;
1520 mvi MSG_IGN_WIDE_RESIDUE call target_outb;
1521 mvi 1 call target_outb;
1529 * We assume that, even though data may still be
1530 * transferring to the host, that the SCSI side of
1531 * the DMA engine is now in a static state. This
1532 * allows us to update our notion of where we are
1535 * If, by chance, we stopped before being able
1536 * to fetch additional segments for this transfer,
1537 * yet the last S/G was completely exhausted,
1538 * call our idle loop until it is able to load
1539 * another segment. This will allow us to immediately
1540 * pickup on the next segment on the next data phase.
1542 * If we happened to stop on the last segment, then
1543 * our residual information is still correct from
1544 * the idle loop and there is no need to perform
1547 residual_before_last_seg:
1548 test MDFFSTAT, SHVALID jnz sgptr_fixup;
1550 * Can never happen from an interrupt as the packetized
1551 * hardware will only interrupt us once SHVALID or
1554 call idle_loop_service_fifos;
1555 RESTORE_MODE(SAVED_MODE)
1558 test SG_CACHE_SHADOW, LAST_SEG jz residual_before_last_seg;
1559 /* Record if we've consumed all S/G entries */
1560 test MDFFSTAT, SHVALID jz . + 2;
1561 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1562 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL ret;
1566 * Fixup the residual next S/G pointer. The S/G preload
1567 * feature of the chip allows us to load two elements
1568 * in addition to the currently active element. We
1569 * store the bottom byte of the next S/G pointer in
1570 * the SG_CACHE_PTR register so we can restore the
1571 * correct value when the DMA completes. If the next
1572 * sg ptr value has advanced to the point where higher
1573 * bytes in the address have been affected, fix them
1576 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
1577 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
1578 add SCB_RESIDUAL_SGPTR[1], -1;
1579 adc SCB_RESIDUAL_SGPTR[2], -1;
1580 adc SCB_RESIDUAL_SGPTR[3], -1;
1582 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
1583 clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */
1584 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1587 call issue_cmdcmplt;
1588 mvi CLRSEQINTSTAT, CLRSEQ_SWTMRTO;
1589 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
1591 * In H2A4, the mode pointer is not saved
1592 * for intvec2, but is restored on iret.
1593 * This can lead to the restoration of a
1594 * bogus mode ptr. Manually clear the
1595 * intmask bits and do a normal return
1598 and SEQINTCTL, ~(INTMASK2|INTMASK1) ret;
1600 or SEQINTCTL, IRET ret;
1604 if ((ahd->features & AHD_RTI) == 0) {
1606 * On RevA Silicon, if the target returns us to data-out
1607 * after we have already trained for data-out, it is
1608 * possible for us to transition the free running clock to
1609 * data-valid before the required 100ns P1 setup time (8 P1
1610 * assertions in fast-160 mode). This will only happen if
1611 * this L-Q is a continuation of a data transfer for which
1612 * we have already prefetched data into our FIFO (LQ/Data
1613 * followed by LQ/Data for the same write transaction).
1614 * This can cause some target implementations to miss the
1615 * first few data transfers on the bus. We detect this
1616 * situation by noticing that this is the first data transfer
1617 * after an LQ (LQIWORKONLQ true), that the data transfer is
1618 * a continuation of a transfer already setup in our FIFO
1619 * (SAVEPTRS interrupt), and that the transaction is a write
1620 * (DIRECTION set in DFCNTRL). The delay is performed by
1621 * disabling SCSIEN until we see the first REQ from the
1624 * First instruction in an ISR cannot be a branch on
1625 * Rev A. Snapshot LQISTAT2 so the status is not missed
1626 * and deffer the test by one instruction.
1628 mov REG_ISR, LQISTAT2;
1629 test REG_ISR, LQIWORKONLQ jz main_isr;
1630 test SEQINTSRC, SAVEPTRS jz main_isr;
1631 test LONGJMP_ADDR[1], INVALID_ADDR jz saveptr_active_fifo;
1633 * Switch to the active FIFO after clearing the snapshot
1634 * savepointer in the current FIFO. We do this so that
1635 * a pending CTXTDONE or SAVEPTR is visible in the active
1636 * FIFO. This status is the only way we can detect if we
1637 * have lost the race (e.g. host paused us) and our attepts
1638 * to disable the channel occurred after all REQs were
1639 * already seen and acked (REQINIT never comes true).
1641 mvi DFFSXFRCTL, CLRCHN;
1642 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1643 test DFCNTRL, DIRECTION jz interrupt_return;
1644 and DFCNTRL, ~SCSIEN;
1645 snapshot_wait_data_valid:
1646 test SEQINTSRC, (CTXTDONE|SAVEPTRS) jnz snapshot_data_valid;
1647 test SSTAT1, REQINIT jz snapshot_wait_data_valid;
1648 snapshot_data_valid:
1650 or SEQINTCTL, IRET ret;
1652 mvi DFFSXFRCTL, CLRCHN;
1653 or SEQINTCTL, IRET ret;
1656 test SEQINTSRC, CFG4DATA jnz cfg4data_intr;
1657 test SEQINTSRC, CFG4ISTAT jnz cfg4istat_intr;
1658 test SEQINTSRC, SAVEPTRS jnz saveptr_intr;
1659 test SEQINTSRC, CFG4ICMD jnz cfg4icmd_intr;
1660 SET_SEQINTCODE(INVALID_SEQINT)
1663 * There are two types of save pointers interrupts:
1664 * The first is a snapshot save pointers where the current FIFO is not
1665 * active and contains a snapshot of the current poniter information.
1666 * This happens between packets in a stream for a single L_Q. Since we
1667 * are not performing a pointer save, we can safely clear the channel
1668 * so it can be used for other transactions. On RTI capable controllers,
1669 * where snapshots can, and are, disabled, the code to handle this type
1670 * of snapshot is not active.
1672 * The second case is a save pointers on an active FIFO which occurs
1673 * if the target changes to a new L_Q or busfrees/QASes and the transfer
1674 * has a residual. This should occur coincident with a ctxtdone. We
1675 * disable the interrupt and allow our active routine to handle the
1679 if ((ahd->features & AHD_RTI) == 0) {
1680 test LONGJMP_ADDR[1], INVALID_ADDR jnz snapshot_saveptr;
1682 saveptr_active_fifo:
1683 and SEQIMODE, ~ENSAVEPTRS;
1684 or SEQINTCTL, IRET ret;
1687 test SCB_SGPTR[0], SG_LIST_NULL jnz pkt_handle_overrun_inc_use_count;
1688 call load_first_seg;
1689 call pkt_handle_xfer;
1690 inc SCB_FIFO_USE_COUNT;
1692 or SEQINTCTL, IRET ret;
1696 add NONE, -13, SCB_CDB_LEN;
1697 jnc cfg4istat_have_sense_addr;
1698 test SCB_CDB_LEN, SCB_CDB_LEN_PTR jnz cfg4istat_have_sense_addr;
1700 * Host sets up address/count and enables transfer.
1702 SET_SEQINTCODE(CFG4ISTAT_INTR)
1703 jmp cfg4istat_setup_handler;
1704 cfg4istat_have_sense_addr:
1705 bmov HADDR, SCB_SENSE_BUSADDR, 4;
1706 mvi HCNT[1], (AHD_SENSE_BUFSIZE >> 8);
1707 mvi SG_CACHE_PRE, LAST_SEG;
1708 mvi DFCNTRL, PRELOADEN|SCSIEN|HDMAEN;
1709 cfg4istat_setup_handler:
1711 * Status pkt is transferring to host.
1712 * Wait in idle loop for transfer to complete.
1713 * If a command completed before an attempted
1714 * task management function completed, notify the host.
1716 test SCB_TASK_MANAGEMENT, 0xFF jz cfg4istat_no_taskmgmt_func;
1717 SET_SEQINTCODE(TASKMGMT_CMD_CMPLT_OKAY)
1718 cfg4istat_no_taskmgmt_func:
1719 call pkt_handle_status;
1720 or SEQINTCTL, IRET ret;
1724 * In the case of DMAing a CDB from the host, the normal
1725 * CDB buffer is formatted with an 8 byte address followed
1726 * by a 1 byte count.
1728 bmov HADDR[0], SCB_HOST_CDB_PTR, 9;
1729 mvi SG_CACHE_PRE, LAST_SEG;
1730 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1731 call pkt_handle_cdb;
1732 or SEQINTCTL, IRET ret;
1735 * See if the target has gone on in this context creating an
1736 * overrun condition. For the write case, the hardware cannot
1737 * ack bytes until data are provided. So, if the target begins
1738 * another packet without changing contexts, implying we are
1739 * not sitting on a packet boundary, we are in an overrun
1740 * situation. For the read case, the hardware will continue to
1741 * ack bytes into the FIFO, and may even ack the last overrun packet
1742 * into the FIFO. If the FIFO should become non-empty, we are in
1743 * a read overrun case.
1745 #define check_overrun \
1746 /* Not on a packet boundary. */ \
1747 test MDFFSTAT, DLZERO jz pkt_handle_overrun; \
1748 test DFSTATUS, FIFOEMP jz pkt_handle_overrun
1751 test SG_STATE, LOADING_NEEDED jz pkt_last_seg;
1753 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1754 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1755 test SCSISIGO, ATNO jnz . + 2;
1756 test SSTAT2, NONPACKREQ jz pkt_service_fifo;
1758 * Defer handling of this NONPACKREQ until we
1759 * can be sure it pertains to this FIFO. SAVEPTRS
1760 * will not be asserted if the NONPACKREQ is for us,
1761 * so we must simulate it if shaddow is valid. If
1762 * shaddow is not valid, keep running this FIFO until we
1763 * have satisfied the transfer by loading segments and
1764 * waiting for either shaddow valid or last_seg_done.
1766 test MDFFSTAT, SHVALID jnz pkt_saveptrs;
1768 test SG_STATE, LOADING_NEEDED jnz service_fifo;
1771 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1772 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_last_seg_done;
1773 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1774 test SCSISIGO, ATNO jnz . + 2;
1775 test SSTAT2, NONPACKREQ jz return;
1776 test MDFFSTAT, SHVALID jz return;
1780 * Either a SAVEPTRS interrupt condition is pending for this FIFO
1781 * or we have a pending NONPACKREQ for this FIFO. We differentiate
1782 * between the two by capturing the state of the SAVEPTRS interrupt
1783 * prior to clearing this status and executing the common code for
1788 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1789 or DFCNTRL, FIFOFLUSH;
1791 mov REG0, SEQINTSRC;
1794 mvi CLRSEQINTSRC, CLRSAVEPTRS;
1795 call disable_ccsgen;
1796 or SEQIMODE, ENSAVEPTRS;
1797 test DFCNTRL, DIRECTION jnz pkt_saveptrs_check_status;
1798 test DFSTATUS, FIFOEMP jnz pkt_saveptrs_check_status;
1800 * Keep a handler around for this FIFO until it drains
1801 * to the host to guarantee that we don't complete the
1802 * command to the host before the data arrives.
1804 pkt_saveptrs_wait_fifoemp:
1806 test DFSTATUS, FIFOEMP jz return;
1807 pkt_saveptrs_check_status:
1808 or LONGJMP_ADDR[1], INVALID_ADDR;
1809 test REG0, SAVEPTRS jz unexpected_nonpkt_phase;
1810 dec SCB_FIFO_USE_COUNT;
1811 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
1812 mvi DFFSXFRCTL, CLRCHN ret;
1816 * LAST_SEG_DONE status has been seen in the current FIFO.
1817 * This indicates that all of the allowed data for this
1818 * command has transferred across the SCSI and host buses.
1819 * Check for overrun and see if we can complete this command.
1824 * Mark transfer as completed.
1826 or SCB_SGPTR, SG_LIST_NULL;
1829 * Wait for the current context to finish to verify that
1830 * no overrun condition has occurred.
1832 test SEQINTSRC, CTXTDONE jnz pkt_ctxt_done;
1834 pkt_wait_ctxt_done_loop:
1835 test SEQINTSRC, CTXTDONE jnz pkt_ctxt_done;
1837 * A sufficiently large overrun or a NONPACKREQ may
1838 * prevent CTXTDONE from ever asserting, so we must
1839 * poll for these statuses too.
1842 test SSTAT2, NONPACKREQ jz return;
1843 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
1848 or LONGJMP_ADDR[1], INVALID_ADDR;
1850 * If status has been received, it is safe to skip
1851 * the check to see if another FIFO is active because
1852 * LAST_SEG_DONE has been observed. However, we check
1853 * the FIFO anyway since it costs us only one extra
1854 * instruction to leverage common code to perform the
1857 dec SCB_FIFO_USE_COUNT;
1858 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
1859 mvi DFFSXFRCTL, CLRCHN ret;
1863 * Must wait until CDB xfer is over before issuing the
1868 test SG_CACHE_SHADOW, LAST_SEG_DONE jz return;
1869 or LONGJMP_ADDR[1], INVALID_ADDR;
1870 mvi DFFSXFRCTL, CLRCHN ret;
1873 * Watch over the status transfer. Our host sense buffer is
1874 * large enough to take the maximum allowed status packet.
1875 * None-the-less, we must still catch and report overruns to
1876 * the host. Additionally, properly catch unexpected non-packet
1877 * phases that are typically caused by CRC errors in status packet
1882 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_status_check_overrun;
1883 test SEQINTSRC, CTXTDONE jz pkt_status_check_nonpackreq;
1884 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_status_check_overrun;
1886 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1887 or DFCNTRL, FIFOFLUSH;
1889 test DFSTATUS, FIFOEMP jz return;
1891 or LONGJMP_ADDR[1], INVALID_ADDR;
1892 mvi SCB_SCSI_STATUS, STATUS_PKT_SENSE;
1893 or SCB_CONTROL, STATUS_RCVD;
1894 jmp pkt_complete_scb_if_fifos_idle;
1896 pkt_status_check_overrun:
1898 * Status PKT overruns are uncerimoniously recovered with a
1899 * bus reset. If we've overrun, let the host know so that
1900 * recovery can be performed.
1902 * LAST_SEG_DONE has been observed. If either CTXTDONE or
1903 * a NONPACKREQ phase change have occurred and the FIFO is
1904 * empty, there is no overrun.
1906 test DFSTATUS, FIFOEMP jz pkt_status_report_overrun;
1907 test SEQINTSRC, CTXTDONE jz . + 2;
1908 test DFSTATUS, FIFOEMP jnz pkt_status_IU_done;
1909 test SCSIPHASE, ~DATA_PHASE_MASK jz return;
1910 test DFSTATUS, FIFOEMP jnz pkt_status_check_nonpackreq;
1911 pkt_status_report_overrun:
1912 SET_SEQINTCODE(STATUS_OVERRUN)
1913 /* SEQUENCER RESTARTED */
1914 pkt_status_check_nonpackreq:
1916 * CTXTDONE may be held off if a NONPACKREQ is associated with
1917 * the current context. If a NONPACKREQ is observed, decide
1918 * if it is for the current context. If it is for the current
1919 * context, we must defer NONPACKREQ processing until all data
1920 * has transferred to the host.
1922 test SCSIPHASE, ~DATA_PHASE_MASK jz return;
1923 test SCSISIGO, ATNO jnz . + 2;
1924 test SSTAT2, NONPACKREQ jz return;
1925 test SEQINTSRC, CTXTDONE jnz pkt_status_IU_done;
1926 test DFSTATUS, FIFOEMP jz return;
1928 * The unexpected nonpkt phase handler assumes that any
1929 * data channel use will have a FIFO reference count. It
1930 * turns out that the status handler doesn't need a refernce
1931 * count since the status received flag, and thus completion
1932 * processing, cannot be set until the handler is finished.
1933 * We increment the count here to make the nonpkt handler
1936 inc SCB_FIFO_USE_COUNT;
1940 * Nonpackreq is a polled status. It can come true in three situations:
1941 * we have received an L_Q, we have sent one or more L_Qs, or there is no
1942 * L_Q context associated with this REQ (REQ occurs immediately after a
1943 * (re)selection). Routines that know that the context responsible for this
1944 * nonpackreq call directly into unexpected_nonpkt_phase. In the case of the
1945 * top level idle loop, we exhaust all active contexts prior to determining that
1946 * we simply do not have the full I_T_L_Q for this phase.
1948 unexpected_nonpkt_phase_find_ctxt:
1950 * This nonpackreq is most likely associated with one of the tags
1951 * in a FIFO or an outgoing LQ. Only treat it as an I_T only
1952 * nonpackreq if we've cleared out the FIFOs and handled any
1955 SET_SRC_MODE M_SCSI;
1956 SET_DST_MODE M_SCSI;
1957 and A, FIFO1FREE|FIFO0FREE, DFFSTAT;
1958 cmp A, FIFO1FREE|FIFO0FREE jne return;
1959 test SSTAT0, SELDO jnz return;
1960 mvi SCBPTR[1], SCB_LIST_NULL;
1961 unexpected_nonpkt_phase:
1962 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1)) jnz . + 3;
1963 SET_SRC_MODE M_DFF0;
1964 SET_DST_MODE M_DFF0;
1965 or LONGJMP_ADDR[1], INVALID_ADDR;
1966 dec SCB_FIFO_USE_COUNT;
1967 mvi DFFSXFRCTL, CLRCHN;
1968 mvi CLRSINT2, CLRNONPACKREQ;
1969 test SCSIPHASE, ~(MSG_IN_PHASE|MSG_OUT_PHASE) jnz illegal_phase;
1970 SET_SEQINTCODE(ENTERING_NONPACK)
1974 SET_SEQINTCODE(ILLEGAL_PHASE)
1978 * We have entered an overrun situation. If we have working
1979 * BITBUCKET, flip that on and let the hardware eat any overrun
1980 * data. Otherwise use an overrun buffer in the host to simulate
1983 pkt_handle_overrun_inc_use_count:
1984 inc SCB_FIFO_USE_COUNT;
1986 SET_SEQINTCODE(CFG4OVERRUN)
1988 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) == 0) {
1989 or DFFSXFRCTL, DFFBITBUCKET;
1990 SET_SRC_MODE M_DFF1;
1991 SET_DST_MODE M_DFF1;
1993 call load_overrun_buf;
1994 mvi DFCNTRL, (HDMAEN|SCSIEN|PRELOADEN);
1997 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
1998 test DFSTATUS, PRELOAD_AVAIL jz overrun_load_done;
1999 call load_overrun_buf;
2000 or DFCNTRL, PRELOADEN;
2002 test SEQINTSRC, CTXTDONE jnz pkt_overrun_end;
2004 test DFFSXFRCTL, DFFBITBUCKET jz pkt_overrun_end;
2006 test SSTAT2, NONPACKREQ jz return;
2008 or SCB_RESIDUAL_SGPTR, SG_OVERRUN_RESID;
2009 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
2010 dec SCB_FIFO_USE_COUNT;
2011 or LONGJMP_ADDR[1], INVALID_ADDR;
2012 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
2013 mvi DFFSXFRCTL, CLRCHN ret;
2015 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
2018 * Load a dummy segment if preload space is available.
2020 mov HADDR[0], SHARED_DATA_ADDR;
2021 add HADDR[1], PKT_OVERRUN_BUFOFFSET, SHARED_DATA_ADDR[1];
2024 adc HADDR[2], A, SHARED_DATA_ADDR[2];
2025 adc HADDR[3], A, SHARED_DATA_ADDR[3];
2027 bmov HADDR[4], ALLZEROS, 4;
2028 /* PKT_OVERRUN_BUFSIZE is a multiple of 256 */
2030 mvi HCNT[1], ((PKT_OVERRUN_BUFSIZE >> 8) & 0xFF);