sys/dev/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <drm/drm_edid.h>
  32 #include <drm/drmP.h>
  33 #include "intel_drv.h"
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include <drm/drm_dp_helper.h>
  38 #include <drm/drm_crtc_helper.h>
  39
  40 static void intel_increase_pllclock(struct drm_crtc *crtc);
  41 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  42
  43 typedef struct {
  44         int     min, max;
  45 } intel_range_t;
  46
  47 typedef struct {
  48         int     dot_limit;
  49         int     p2_slow, p2_fast;
  50 } intel_p2_t;
  51
  52 #define INTEL_P2_NUM                  2
  53 typedef struct intel_limit intel_limit_t;
  54 struct intel_limit {
  55         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  56         intel_p2_t          p2;
  57 };
  58
  59 /* FDI */
  60 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  61
  62 int
  63 intel_pch_rawclk(struct drm_device *dev)
  64 {
  65         struct drm_i915_private *dev_priv = dev->dev_private;
  66
  67         WARN_ON(!HAS_PCH_SPLIT(dev));
  68
  69         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  70 }
  71
  72 static inline u32 /* units of 100MHz */
  73 intel_fdi_link_freq(struct drm_device *dev)
  74 {
  75         if (IS_GEN5(dev)) {
  76                 struct drm_i915_private *dev_priv = dev->dev_private;
  77                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  78         } else
  79                 return 27;
  80 }
  81
  82 static const intel_limit_t intel_limits_i8xx_dvo = {
  83         .dot = { .min = 25000, .max = 350000 },
  84         .vco = { .min = 930000, .max = 1400000 },
  85         .n = { .min = 3, .max = 16 },
  86         .m = { .min = 96, .max = 140 },
  87         .m1 = { .min = 18, .max = 26 },
  88         .m2 = { .min = 6, .max = 16 },
  89         .p = { .min = 4, .max = 128 },
  90         .p1 = { .min = 2, .max = 33 },
  91         .p2 = { .dot_limit = 165000,
  92                 .p2_slow = 4, .p2_fast = 2 },
  93 };
  94
  95 static const intel_limit_t intel_limits_i8xx_lvds = {
  96         .dot = { .min = 25000, .max = 350000 },
  97         .vco = { .min = 930000, .max = 1400000 },
  98         .n = { .min = 3, .max = 16 },
  99         .m = { .min = 96, .max = 140 },
 100         .m1 = { .min = 18, .max = 26 },
 101         .m2 = { .min = 6, .max = 16 },
 102         .p = { .min = 4, .max = 128 },
 103         .p1 = { .min = 1, .max = 6 },
 104         .p2 = { .dot_limit = 165000,
 105                 .p2_slow = 14, .p2_fast = 7 },
 106 };
 107
 108 static const intel_limit_t intel_limits_i9xx_sdvo = {
 109         .dot = { .min = 20000, .max = 400000 },
 110         .vco = { .min = 1400000, .max = 2800000 },
 111         .n = { .min = 1, .max = 6 },
 112         .m = { .min = 70, .max = 120 },
 113         .m1 = { .min = 8, .max = 18 },
 114         .m2 = { .min = 3, .max = 7 },
 115         .p = { .min = 5, .max = 80 },
 116         .p1 = { .min = 1, .max = 8 },
 117         .p2 = { .dot_limit = 200000,
 118                 .p2_slow = 10, .p2_fast = 5 },
 119 };
 120
 121 static const intel_limit_t intel_limits_i9xx_lvds = {
 122         .dot = { .min = 20000, .max = 400000 },
 123         .vco = { .min = 1400000, .max = 2800000 },
 124         .n = { .min = 1, .max = 6 },
 125         .m = { .min = 70, .max = 120 },
 126         .m1 = { .min = 8, .max = 18 },
 127         .m2 = { .min = 3, .max = 7 },
 128         .p = { .min = 7, .max = 98 },
 129         .p1 = { .min = 1, .max = 8 },
 130         .p2 = { .dot_limit = 112000,
 131                 .p2_slow = 14, .p2_fast = 7 },
 132 };
 133
 134
 135 static const intel_limit_t intel_limits_g4x_sdvo = {
 136         .dot = { .min = 25000, .max = 270000 },
 137         .vco = { .min = 1750000, .max = 3500000},
 138         .n = { .min = 1, .max = 4 },
 139         .m = { .min = 104, .max = 138 },
 140         .m1 = { .min = 17, .max = 23 },
 141         .m2 = { .min = 5, .max = 11 },
 142         .p = { .min = 10, .max = 30 },
 143         .p1 = { .min = 1, .max = 3},
 144         .p2 = { .dot_limit = 270000,
 145                 .p2_slow = 10,
 146                 .p2_fast = 10
 147         },
 148 };
 149
 150 static const intel_limit_t intel_limits_g4x_hdmi = {
 151         .dot = { .min = 22000, .max = 400000 },
 152         .vco = { .min = 1750000, .max = 3500000},
 153         .n = { .min = 1, .max = 4 },
 154         .m = { .min = 104, .max = 138 },
 155         .m1 = { .min = 16, .max = 23 },
 156         .m2 = { .min = 5, .max = 11 },
 157         .p = { .min = 5, .max = 80 },
 158         .p1 = { .min = 1, .max = 8},
 159         .p2 = { .dot_limit = 165000,
 160                 .p2_slow = 10, .p2_fast = 5 },
 161 };
 162
 163 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 164         .dot = { .min = 20000, .max = 115000 },
 165         .vco = { .min = 1750000, .max = 3500000 },
 166         .n = { .min = 1, .max = 3 },
 167         .m = { .min = 104, .max = 138 },
 168         .m1 = { .min = 17, .max = 23 },
 169         .m2 = { .min = 5, .max = 11 },
 170         .p = { .min = 28, .max = 112 },
 171         .p1 = { .min = 2, .max = 8 },
 172         .p2 = { .dot_limit = 0,
 173                 .p2_slow = 14, .p2_fast = 14
 174         },
 175 };
 176
 177 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 178         .dot = { .min = 80000, .max = 224000 },
 179         .vco = { .min = 1750000, .max = 3500000 },
 180         .n = { .min = 1, .max = 3 },
 181         .m = { .min = 104, .max = 138 },
 182         .m1 = { .min = 17, .max = 23 },
 183         .m2 = { .min = 5, .max = 11 },
 184         .p = { .min = 14, .max = 42 },
 185         .p1 = { .min = 2, .max = 6 },
 186         .p2 = { .dot_limit = 0,
 187                 .p2_slow = 7, .p2_fast = 7
 188         },
 189 };
 190
 191 static const intel_limit_t intel_limits_pineview_sdvo = {
 192         .dot = { .min = 20000, .max = 400000},
 193         .vco = { .min = 1700000, .max = 3500000 },
 194         /* Pineview's Ncounter is a ring counter */
 195         .n = { .min = 3, .max = 6 },
 196         .m = { .min = 2, .max = 256 },
 197         /* Pineview only has one combined m divider, which we treat as m2. */
 198         .m1 = { .min = 0, .max = 0 },
 199         .m2 = { .min = 0, .max = 254 },
 200         .p = { .min = 5, .max = 80 },
 201         .p1 = { .min = 1, .max = 8 },
 202         .p2 = { .dot_limit = 200000,
 203                 .p2_slow = 10, .p2_fast = 5 },
 204 };
 205
 206 static const intel_limit_t intel_limits_pineview_lvds = {
 207         .dot = { .min = 20000, .max = 400000 },
 208         .vco = { .min = 1700000, .max = 3500000 },
 209         .n = { .min = 3, .max = 6 },
 210         .m = { .min = 2, .max = 256 },
 211         .m1 = { .min = 0, .max = 0 },
 212         .m2 = { .min = 0, .max = 254 },
 213         .p = { .min = 7, .max = 112 },
 214         .p1 = { .min = 1, .max = 8 },
 215         .p2 = { .dot_limit = 112000,
 216                 .p2_slow = 14, .p2_fast = 14 },
 217 };
 218
 219 /* Ironlake / Sandybridge
 220  *
 221  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 222  * the range value for them is (actual_value - 2).
 223  */
 224 static const intel_limit_t intel_limits_ironlake_dac = {
 225         .dot = { .min = 25000, .max = 350000 },
 226         .vco = { .min = 1760000, .max = 3510000 },
 227         .n = { .min = 1, .max = 5 },
 228         .m = { .min = 79, .max = 127 },
 229         .m1 = { .min = 12, .max = 22 },
 230         .m2 = { .min = 5, .max = 9 },
 231         .p = { .min = 5, .max = 80 },
 232         .p1 = { .min = 1, .max = 8 },
 233         .p2 = { .dot_limit = 225000,
 234                 .p2_slow = 10, .p2_fast = 5 },
 235 };
 236
 237 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 238         .dot = { .min = 25000, .max = 350000 },
 239         .vco = { .min = 1760000, .max = 3510000 },
 240         .n = { .min = 1, .max = 3 },
 241         .m = { .min = 79, .max = 118 },
 242         .m1 = { .min = 12, .max = 22 },
 243         .m2 = { .min = 5, .max = 9 },
 244         .p = { .min = 28, .max = 112 },
 245         .p1 = { .min = 2, .max = 8 },
 246         .p2 = { .dot_limit = 225000,
 247                 .p2_slow = 14, .p2_fast = 14 },
 248 };
 249
 250 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 251         .dot = { .min = 25000, .max = 350000 },
 252         .vco = { .min = 1760000, .max = 3510000 },
 253         .n = { .min = 1, .max = 3 },
 254         .m = { .min = 79, .max = 127 },
 255         .m1 = { .min = 12, .max = 22 },
 256         .m2 = { .min = 5, .max = 9 },
 257         .p = { .min = 14, .max = 56 },
 258         .p1 = { .min = 2, .max = 8 },
 259         .p2 = { .dot_limit = 225000,
 260                 .p2_slow = 7, .p2_fast = 7 },
 261 };
 262
 263 /* LVDS 100mhz refclk limits. */
 264 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 265         .dot = { .min = 25000, .max = 350000 },
 266         .vco = { .min = 1760000, .max = 3510000 },
 267         .n = { .min = 1, .max = 2 },
 268         .m = { .min = 79, .max = 126 },
 269         .m1 = { .min = 12, .max = 22 },
 270         .m2 = { .min = 5, .max = 9 },
 271         .p = { .min = 28, .max = 112 },
 272         .p1 = { .min = 2, .max = 8 },
 273         .p2 = { .dot_limit = 225000,
 274                 .p2_slow = 14, .p2_fast = 14 },
 275 };
 276
 277 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 1760000, .max = 3510000 },
 280         .n = { .min = 1, .max = 3 },
 281         .m = { .min = 79, .max = 126 },
 282         .m1 = { .min = 12, .max = 22 },
 283         .m2 = { .min = 5, .max = 9 },
 284         .p = { .min = 14, .max = 42 },
 285         .p1 = { .min = 2, .max = 6 },
 286         .p2 = { .dot_limit = 225000,
 287                 .p2_slow = 7, .p2_fast = 7 },
 288 };
 289
 290 static const intel_limit_t intel_limits_vlv_dac = {
 291         .dot = { .min = 25000, .max = 270000 },
 292         .vco = { .min = 4000000, .max = 6000000 },
 293         .n = { .min = 1, .max = 7 },
 294         .m = { .min = 22, .max = 450 }, /* guess */
 295         .m1 = { .min = 2, .max = 3 },
 296         .m2 = { .min = 11, .max = 156 },
 297         .p = { .min = 10, .max = 30 },
 298         .p1 = { .min = 1, .max = 3 },
 299         .p2 = { .dot_limit = 270000,
 300                 .p2_slow = 2, .p2_fast = 20 },
 301 };
 302
 303 static const intel_limit_t intel_limits_vlv_hdmi = {
 304         .dot = { .min = 25000, .max = 270000 },
 305         .vco = { .min = 4000000, .max = 6000000 },
 306         .n = { .min = 1, .max = 7 },
 307         .m = { .min = 60, .max = 300 }, /* guess */
 308         .m1 = { .min = 2, .max = 3 },
 309         .m2 = { .min = 11, .max = 156 },
 310         .p = { .min = 10, .max = 30 },
 311         .p1 = { .min = 2, .max = 3 },
 312         .p2 = { .dot_limit = 270000,
 313                 .p2_slow = 2, .p2_fast = 20 },
 314 };
 315
 316 static const intel_limit_t intel_limits_vlv_dp = {
 317         .dot = { .min = 25000, .max = 270000 },
 318         .vco = { .min = 4000000, .max = 6000000 },
 319         .n = { .min = 1, .max = 7 },
 320         .m = { .min = 22, .max = 450 },
 321         .m1 = { .min = 2, .max = 3 },
 322         .m2 = { .min = 11, .max = 156 },
 323         .p = { .min = 10, .max = 30 },
 324         .p1 = { .min = 1, .max = 3 },
 325         .p2 = { .dot_limit = 270000,
 326                 .p2_slow = 2, .p2_fast = 20 },
 327 };
 328
 329 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 330                                                 int refclk)
 331 {
 332         struct drm_device *dev = crtc->dev;
 333         const intel_limit_t *limit;
 334
 335         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 336                 if (intel_is_dual_link_lvds(dev)) {
 337                         if (refclk == 100000)
 338                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 339                         else
 340                                 limit = &intel_limits_ironlake_dual_lvds;
 341                 } else {
 342                         if (refclk == 100000)
 343                                 limit = &intel_limits_ironlake_single_lvds_100m;
 344                         else
 345                                 limit = &intel_limits_ironlake_single_lvds;
 346                 }
 347         } else
 348                 limit = &intel_limits_ironlake_dac;
 349
 350         return limit;
 351 }
 352
 353 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 354 {
 355         struct drm_device *dev = crtc->dev;
 356         const intel_limit_t *limit;
 357
 358         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 359                 if (intel_is_dual_link_lvds(dev))
 360                         limit = &intel_limits_g4x_dual_channel_lvds;
 361                 else
 362                         limit = &intel_limits_g4x_single_channel_lvds;
 363         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 364                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 365                 limit = &intel_limits_g4x_hdmi;
 366         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 367                 limit = &intel_limits_g4x_sdvo;
 368         } else /* The option is for other outputs */
 369                 limit = &intel_limits_i9xx_sdvo;
 370
 371         return limit;
 372 }
 373
 374 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 375 {
 376         struct drm_device *dev = crtc->dev;
 377         const intel_limit_t *limit;
 378
 379         if (HAS_PCH_SPLIT(dev))
 380                 limit = intel_ironlake_limit(crtc, refclk);
 381         else if (IS_G4X(dev)) {
 382                 limit = intel_g4x_limit(crtc);
 383         } else if (IS_PINEVIEW(dev)) {
 384                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 385                         limit = &intel_limits_pineview_lvds;
 386                 else
 387                         limit = &intel_limits_pineview_sdvo;
 388         } else if (IS_VALLEYVIEW(dev)) {
 389                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 390                         limit = &intel_limits_vlv_dac;
 391                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 392                         limit = &intel_limits_vlv_hdmi;
 393                 else
 394                         limit = &intel_limits_vlv_dp;
 395         } else if (!IS_GEN2(dev)) {
 396                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 397                         limit = &intel_limits_i9xx_lvds;
 398                 else
 399                         limit = &intel_limits_i9xx_sdvo;
 400         } else {
 401                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 402                         limit = &intel_limits_i8xx_lvds;
 403                 else
 404                         limit = &intel_limits_i8xx_dvo;
 405         }
 406         return limit;
 407 }
 408
 409 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 410 static void pineview_clock(int refclk, intel_clock_t *clock)
 411 {
 412         clock->m = clock->m2 + 2;
 413         clock->p = clock->p1 * clock->p2;
 414         clock->vco = refclk * clock->m / clock->n;
 415         clock->dot = clock->vco / clock->p;
 416 }
 417
 418 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 419 {
 420         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 421 }
 422
 423 static void i9xx_clock(int refclk, intel_clock_t *clock)
 424 {
 425         clock->m = i9xx_dpll_compute_m(clock);
 426         clock->p = clock->p1 * clock->p2;
 427         clock->vco = refclk * clock->m / (clock->n + 2);
 428         clock->dot = clock->vco / clock->p;
 429 }
 430
 431 /**
 432  * Returns whether any output on the specified pipe is of the specified type
 433  */
 434 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 435 {
 436         struct drm_device *dev = crtc->dev;
 437         struct intel_encoder *encoder;
 438
 439         for_each_encoder_on_crtc(dev, crtc, encoder)
 440                 if (encoder->type == type)
 441                         return true;
 442
 443         return false;
 444 }
 445
 446 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 447 /**
 448  * Returns whether the given set of divisors are valid for a given refclk with
 449  * the given connectors.
 450  */
 451
 452 static bool intel_PLL_is_valid(struct drm_device *dev,
 453                                const intel_limit_t *limit,
 454                                const intel_clock_t *clock)
 455 {
 456         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 457                 INTELPllInvalid("p1 out of range\n");
 458         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 459                 INTELPllInvalid("p out of range\n");
 460         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 461                 INTELPllInvalid("m2 out of range\n");
 462         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 463                 INTELPllInvalid("m1 out of range\n");
 464         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 465                 INTELPllInvalid("m1 <= m2\n");
 466         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 467                 INTELPllInvalid("m out of range\n");
 468         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 469                 INTELPllInvalid("n out of range\n");
 470         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 471                 INTELPllInvalid("vco out of range\n");
 472         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 473          * connector, etc., rather than just a single range.
 474          */
 475         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 476                 INTELPllInvalid("dot out of range\n");
 477
 478         return true;
 479 }
 480
 481 static bool
 482 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 483                     int target, int refclk, intel_clock_t *match_clock,
 484                     intel_clock_t *best_clock)
 485 {
 486         struct drm_device *dev = crtc->dev;
 487         intel_clock_t clock;
 488         int err = target;
 489
 490         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 491                 /*
 492                  * For LVDS just rely on its current settings for dual-channel.
 493                  * We haven't figured out how to reliably set up different
 494                  * single/dual channel state, if we even can.
 495                  */
 496                 if (intel_is_dual_link_lvds(dev))
 497                         clock.p2 = limit->p2.p2_fast;
 498                 else
 499                         clock.p2 = limit->p2.p2_slow;
 500         } else {
 501                 if (target < limit->p2.dot_limit)
 502                         clock.p2 = limit->p2.p2_slow;
 503                 else
 504                         clock.p2 = limit->p2.p2_fast;
 505         }
 506
 507         memset(best_clock, 0, sizeof(*best_clock));
 508
 509         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 510              clock.m1++) {
 511                 for (clock.m2 = limit->m2.min;
 512                      clock.m2 <= limit->m2.max; clock.m2++) {
 513                         if (clock.m2 >= clock.m1)
 514                                 break;
 515                         for (clock.n = limit->n.min;
 516                              clock.n <= limit->n.max; clock.n++) {
 517                                 for (clock.p1 = limit->p1.min;
 518                                         clock.p1 <= limit->p1.max; clock.p1++) {
 519                                         int this_err;
 520
 521                                         i9xx_clock(refclk, &clock);
 522                                         if (!intel_PLL_is_valid(dev, limit,
 523                                                                 &clock))
 524                                                 continue;
 525                                         if (match_clock &&
 526                                             clock.p != match_clock->p)
 527                                                 continue;
 528
 529                                         this_err = abs(clock.dot - target);
 530                                         if (this_err < err) {
 531                                                 *best_clock = clock;
 532                                                 err = this_err;
 533                                         }
 534                                 }
 535                         }
 536                 }
 537         }
 538
 539         return (err != target);
 540 }
 541
 542 static bool
 543 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 544                    int target, int refclk, intel_clock_t *match_clock,
 545                    intel_clock_t *best_clock)
 546 {
 547         struct drm_device *dev = crtc->dev;
 548         intel_clock_t clock;
 549         int err = target;
 550
 551         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 552                 /*
 553                  * For LVDS just rely on its current settings for dual-channel.
 554                  * We haven't figured out how to reliably set up different
 555                  * single/dual channel state, if we even can.
 556                  */
 557                 if (intel_is_dual_link_lvds(dev))
 558                         clock.p2 = limit->p2.p2_fast;
 559                 else
 560                         clock.p2 = limit->p2.p2_slow;
 561         } else {
 562                 if (target < limit->p2.dot_limit)
 563                         clock.p2 = limit->p2.p2_slow;
 564                 else
 565                         clock.p2 = limit->p2.p2_fast;
 566         }
 567
 568         memset(best_clock, 0, sizeof(*best_clock));
 569
 570         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 571              clock.m1++) {
 572                 for (clock.m2 = limit->m2.min;
 573                      clock.m2 <= limit->m2.max; clock.m2++) {
 574                         for (clock.n = limit->n.min;
 575                              clock.n <= limit->n.max; clock.n++) {
 576                                 for (clock.p1 = limit->p1.min;
 577                                         clock.p1 <= limit->p1.max; clock.p1++) {
 578                                         int this_err;
 579
 580                                         pineview_clock(refclk, &clock);
 581                                         if (!intel_PLL_is_valid(dev, limit,
 582                                                                 &clock))
 583                                                 continue;
 584                                         if (match_clock &&
 585                                             clock.p != match_clock->p)
 586                                                 continue;
 587
 588                                         this_err = abs(clock.dot - target);
 589                                         if (this_err < err) {
 590                                                 *best_clock = clock;
 591                                                 err = this_err;
 592                                         }
 593                                 }
 594                         }
 595                 }
 596         }
 597
 598         return (err != target);
 599 }
 600
 601 static bool
 602 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 603                    int target, int refclk, intel_clock_t *match_clock,
 604                    intel_clock_t *best_clock)
 605 {
 606         struct drm_device *dev = crtc->dev;
 607         intel_clock_t clock;
 608         int max_n;
 609         bool found;
 610         /* approximately equals target * 0.00585 */
 611         int err_most = (target >> 8) + (target >> 9);
 612         found = false;
 613
 614         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 615                 if (intel_is_dual_link_lvds(dev))
 616                         clock.p2 = limit->p2.p2_fast;
 617                 else
 618                         clock.p2 = limit->p2.p2_slow;
 619         } else {
 620                 if (target < limit->p2.dot_limit)
 621                         clock.p2 = limit->p2.p2_slow;
 622                 else
 623                         clock.p2 = limit->p2.p2_fast;
 624         }
 625
 626         memset(best_clock, 0, sizeof(*best_clock));
 627         max_n = limit->n.max;
 628         /* based on hardware requirement, prefer smaller n to precision */
 629         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 630                 /* based on hardware requirement, prefere larger m1,m2 */
 631                 for (clock.m1 = limit->m1.max;
 632                      clock.m1 >= limit->m1.min; clock.m1--) {
 633                         for (clock.m2 = limit->m2.max;
 634                              clock.m2 >= limit->m2.min; clock.m2--) {
 635                                 for (clock.p1 = limit->p1.max;
 636                                      clock.p1 >= limit->p1.min; clock.p1--) {
 637                                         int this_err;
 638
 639                                         i9xx_clock(refclk, &clock);
 640                                         if (!intel_PLL_is_valid(dev, limit,
 641                                                                 &clock))
 642                                                 continue;
 643
 644                                         this_err = abs(clock.dot - target);
 645                                         if (this_err < err_most) {
 646                                                 *best_clock = clock;
 647                                                 err_most = this_err;
 648                                                 max_n = clock.n;
 649                                                 found = true;
 650                                         }
 651                                 }
 652                         }
 653                 }
 654         }
 655         return found;
 656 }
 657
 658 static bool
 659 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 660                    int target, int refclk, intel_clock_t *match_clock,
 661                    intel_clock_t *best_clock)
 662 {
 663         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 664         u32 m, n, fastclk;
 665         u32 updrate, minupdate, fracbits, p;
 666         unsigned long bestppm, ppm, absppm;
 667         int dotclk, flag;
 668
 669         flag = 0;
 670         dotclk = target * 1000;
 671         bestppm = 1000000;
 672         ppm = absppm = 0;
 673         fastclk = dotclk / (2*100);
 674         updrate = 0;
 675         minupdate = 19200;
 676         fracbits = 1;
 677         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 678         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 679
 680         /* based on hardware requirement, prefer smaller n to precision */
 681         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 682                 updrate = refclk / n;
 683                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 684                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 685                                 if (p2 > 10)
 686                                         p2 = p2 - 1;
 687                                 p = p1 * p2;
 688                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 689                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 690                                         m2 = (((2*(fastclk * p * n / m1 )) +
 691                                                refclk) / (2*refclk));
 692                                         m = m1 * m2;
 693                                         vco = updrate * m;
 694                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 695                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 696                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 697                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 698                                                         bestppm = 0;
 699                                                         flag = 1;
 700                                                 }
 701                                                 if (absppm < bestppm - 10) {
 702                                                         bestppm = absppm;
 703                                                         flag = 1;
 704                                                 }
 705                                                 if (flag) {
 706                                                         bestn = n;
 707                                                         bestm1 = m1;
 708                                                         bestm2 = m2;
 709                                                         bestp1 = p1;
 710                                                         bestp2 = p2;
 711                                                         flag = 0;
 712                                                 }
 713                                         }
 714                                 }
 715                         }
 716                 }
 717         }
 718         best_clock->n = bestn;
 719         best_clock->m1 = bestm1;
 720         best_clock->m2 = bestm2;
 721         best_clock->p1 = bestp1;
 722         best_clock->p2 = bestp2;
 723
 724         return true;
 725 }
 726
 727 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 728                                              enum i915_pipe pipe)
 729 {
 730         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 732
 733         return intel_crtc->config.cpu_transcoder;
 734 }
 735
 736 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 737 {
 738         struct drm_i915_private *dev_priv = dev->dev_private;
 739         u32 frame, frame_reg = PIPEFRAME(pipe);
 740
 741         frame = I915_READ(frame_reg);
 742
 743         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 744                 DRM_DEBUG_KMS("vblank wait timed out\n");
 745 }
 746
 747 /**
 748  * intel_wait_for_vblank - wait for vblank on a given pipe
 749  * @dev: drm device
 750  * @pipe: pipe to wait for
 751  *
 752  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 753  * mode setting code.
 754  */
 755 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 756 {
 757         struct drm_i915_private *dev_priv = dev->dev_private;
 758         int pipestat_reg = PIPESTAT(pipe);
 759
 760         if (INTEL_INFO(dev)->gen >= 5) {
 761                 ironlake_wait_for_vblank(dev, pipe);
 762                 return;
 763         }
 764
 765         /* Clear existing vblank status. Note this will clear any other
 766          * sticky status fields as well.
 767          *
 768          * This races with i915_driver_irq_handler() with the result
 769          * that either function could miss a vblank event.  Here it is not
 770          * fatal, as we will either wait upon the next vblank interrupt or
 771          * timeout.  Generally speaking intel_wait_for_vblank() is only
 772          * called during modeset at which time the GPU should be idle and
 773          * should *not* be performing page flips and thus not waiting on
 774          * vblanks...
 775          * Currently, the result of us stealing a vblank from the irq
 776          * handler is that a single frame will be skipped during swapbuffers.
 777          */
 778         I915_WRITE(pipestat_reg,
 779                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 780
 781         /* Wait for vblank interrupt bit to set */
 782         if (wait_for(I915_READ(pipestat_reg) &
 783                      PIPE_VBLANK_INTERRUPT_STATUS,
 784                      50))
 785                 DRM_DEBUG_KMS("vblank wait timed out\n");
 786 }
 787
 788 /*
 789  * intel_wait_for_pipe_off - wait for pipe to turn off
 790  * @dev: drm device
 791  * @pipe: pipe to wait for
 792  *
 793  * After disabling a pipe, we can't wait for vblank in the usual way,
 794  * spinning on the vblank interrupt status bit, since we won't actually
 795  * see an interrupt when the pipe is disabled.
 796  *
 797  * On Gen4 and above:
 798  *   wait for the pipe register state bit to turn off
 799  *
 800  * Otherwise:
 801  *   wait for the display line value to settle (it usually
 802  *   ends up stopping at the start of the next frame).
 803  *
 804  */
 805 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 806 {
 807         struct drm_i915_private *dev_priv = dev->dev_private;
 808         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 809                                                                       pipe);
 810
 811         if (INTEL_INFO(dev)->gen >= 4) {
 812                 int reg = PIPECONF(cpu_transcoder);
 813
 814                 /* Wait for the Pipe State to go off */
 815                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 816                              100))
 817                         WARN(1, "pipe_off wait timed out\n");
 818         } else {
 819                 u32 last_line, line_mask;
 820                 int reg = PIPEDSL(pipe);
 821                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 822
 823                 if (IS_GEN2(dev))
 824                         line_mask = DSL_LINEMASK_GEN2;
 825                 else
 826                         line_mask = DSL_LINEMASK_GEN3;
 827
 828                 /* Wait for the display line to settle */
 829                 do {
 830                         last_line = I915_READ(reg) & line_mask;
 831                         mdelay(5);
 832                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 833                          time_after(timeout, jiffies));
 834                 if (time_after(jiffies, timeout))
 835                         WARN(1, "pipe_off wait timed out\n");
 836         }
 837 }
 838
 839 /*
 840  * ibx_digital_port_connected - is the specified port connected?
 841  * @dev_priv: i915 private structure
 842  * @port: the port to test
 843  *
 844  * Returns true if @port is connected, false otherwise.
 845  */
 846 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 847                                 struct intel_digital_port *port)
 848 {
 849         u32 bit;
 850
 851         if (HAS_PCH_IBX(dev_priv->dev)) {
 852                 switch(port->port) {
 853                 case PORT_B:
 854                         bit = SDE_PORTB_HOTPLUG;
 855                         break;
 856                 case PORT_C:
 857                         bit = SDE_PORTC_HOTPLUG;
 858                         break;
 859                 case PORT_D:
 860                         bit = SDE_PORTD_HOTPLUG;
 861                         break;
 862                 default:
 863                         return true;
 864                 }
 865         } else {
 866                 switch(port->port) {
 867                 case PORT_B:
 868                         bit = SDE_PORTB_HOTPLUG_CPT;
 869                         break;
 870                 case PORT_C:
 871                         bit = SDE_PORTC_HOTPLUG_CPT;
 872                         break;
 873                 case PORT_D:
 874                         bit = SDE_PORTD_HOTPLUG_CPT;
 875                         break;
 876                 default:
 877                         return true;
 878                 }
 879         }
 880
 881         return I915_READ(SDEISR) & bit;
 882 }
 883
 884 static const char *state_string(bool enabled)
 885 {
 886         return enabled ? "on" : "off";
 887 }
 888
 889 /* Only for pre-ILK configs */
 890 static void assert_pll(struct drm_i915_private *dev_priv,
 891                        enum i915_pipe pipe, bool state)
 892 {
 893         int reg;
 894         u32 val;
 895         bool cur_state;
 896
 897         reg = DPLL(pipe);
 898         val = I915_READ(reg);
 899         cur_state = !!(val & DPLL_VCO_ENABLE);
 900         WARN(cur_state != state,
 901              "PLL state assertion failure (expected %s, current %s)\n",
 902              state_string(state), state_string(cur_state));
 903 }
 904 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 905 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 906
 907 static struct intel_shared_dpll *
 908 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 909 {
 910         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 911
 912         if (crtc->config.shared_dpll < 0)
 913                 return NULL;
 914
 915         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 916 }
 917
 918 /* For ILK+ */
 919 static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 920                                struct intel_shared_dpll *pll,
 921                                bool state)
 922 {
 923         bool cur_state;
 924         struct intel_dpll_hw_state hw_state;
 925
 926         if (HAS_PCH_LPT(dev_priv->dev)) {
 927                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 928                 return;
 929         }
 930
 931         if (WARN (!pll,
 932                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 933                 return;
 934
 935         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 936         WARN(cur_state != state,
 937              "%s assertion failure (expected %s, current %s)\n",
 938              pll->name, state_string(state), state_string(cur_state));
 939 }
 940 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 941 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 942
 943 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 944                           enum i915_pipe pipe, bool state)
 945 {
 946         int reg;
 947         u32 val;
 948         bool cur_state;
 949         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 950                                                                       pipe);
 951
 952         if (HAS_DDI(dev_priv->dev)) {
 953                 /* DDI does not have a specific FDI_TX register */
 954                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 955                 val = I915_READ(reg);
 956                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 957         } else {
 958                 reg = FDI_TX_CTL(pipe);
 959                 val = I915_READ(reg);
 960                 cur_state = !!(val & FDI_TX_ENABLE);
 961         }
 962         WARN(cur_state != state,
 963              "FDI TX state assertion failure (expected %s, current %s)\n",
 964              state_string(state), state_string(cur_state));
 965 }
 966 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 967 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 968
 969 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 970                           enum i915_pipe pipe, bool state)
 971 {
 972         int reg;
 973         u32 val;
 974         bool cur_state;
 975
 976         reg = FDI_RX_CTL(pipe);
 977         val = I915_READ(reg);
 978         cur_state = !!(val & FDI_RX_ENABLE);
 979         WARN(cur_state != state,
 980              "FDI RX state assertion failure (expected %s, current %s)\n",
 981              state_string(state), state_string(cur_state));
 982 }
 983 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 984 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 985
 986 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 987                                       enum i915_pipe pipe)
 988 {
 989         int reg;
 990         u32 val;
 991
 992         /* ILK FDI PLL is always enabled */
 993         if (dev_priv->info->gen == 5)
 994                 return;
 995
 996         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
 997         if (HAS_DDI(dev_priv->dev))
 998                 return;
 999
1000         reg = FDI_TX_CTL(pipe);
1001         val = I915_READ(reg);
1002         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1003 }
1004
1005 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1006                                       enum i915_pipe pipe)
1007 {
1008         int reg;
1009         u32 val;
1010
1011         reg = FDI_RX_CTL(pipe);
1012         val = I915_READ(reg);
1013         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1014 }
1015
1016 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1017                                   enum i915_pipe pipe)
1018 {
1019         int pp_reg, lvds_reg;
1020         u32 val;
1021         enum i915_pipe panel_pipe = PIPE_A;
1022         bool locked = true;
1023
1024         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1025                 pp_reg = PCH_PP_CONTROL;
1026                 lvds_reg = PCH_LVDS;
1027         } else {
1028                 pp_reg = PP_CONTROL;
1029                 lvds_reg = LVDS;
1030         }
1031
1032         val = I915_READ(pp_reg);
1033         if (!(val & PANEL_POWER_ON) ||
1034             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1035                 locked = false;
1036
1037         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1038                 panel_pipe = PIPE_B;
1039
1040         WARN(panel_pipe == pipe && locked,
1041              "panel assertion failure, pipe %c regs locked\n",
1042              pipe_name(pipe));
1043 }
1044
1045 void assert_pipe(struct drm_i915_private *dev_priv,
1046                  enum i915_pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1052                                                                       pipe);
1053
1054         /* if we need the pipe A quirk it must be always on */
1055         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1056                 state = true;
1057
1058         if (!intel_display_power_enabled(dev_priv->dev,
1059                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1060                 cur_state = false;
1061         } else {
1062                 reg = PIPECONF(cpu_transcoder);
1063                 val = I915_READ(reg);
1064                 cur_state = !!(val & PIPECONF_ENABLE);
1065         }
1066
1067         WARN(cur_state != state,
1068              "pipe %c assertion failure (expected %s, current %s)\n",
1069              pipe_name(pipe), state_string(state), state_string(cur_state));
1070 }
1071
1072 static void assert_plane(struct drm_i915_private *dev_priv,
1073                          enum plane plane, bool state)
1074 {
1075         int reg;
1076         u32 val;
1077         bool cur_state;
1078
1079         reg = DSPCNTR(plane);
1080         val = I915_READ(reg);
1081         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1082         WARN(cur_state != state,
1083              "plane %c assertion failure (expected %s, current %s)\n",
1084              plane_name(plane), state_string(state), state_string(cur_state));
1085 }
1086
1087 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1088 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1089
1090 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1091                                    enum i915_pipe pipe)
1092 {
1093         struct drm_device *dev = dev_priv->dev;
1094         int reg, i;
1095         u32 val;
1096         int cur_pipe;
1097
1098         /* Primary planes are fixed to pipes on gen4+ */
1099         if (INTEL_INFO(dev)->gen >= 4) {
1100                 reg = DSPCNTR(pipe);
1101                 val = I915_READ(reg);
1102                 WARN((val & DISPLAY_PLANE_ENABLE),
1103                      "plane %c assertion failure, should be disabled but not\n",
1104                      plane_name(pipe));
1105                 return;
1106         }
1107
1108         /* Need to check both planes against the pipe */
1109         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1110                 reg = DSPCNTR(i);
1111                 val = I915_READ(reg);
1112                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1113                         DISPPLANE_SEL_PIPE_SHIFT;
1114                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1115                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1116                      plane_name(i), pipe_name(pipe));
1117         }
1118 }
1119
1120 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1121                                     enum i915_pipe pipe)
1122 {
1123         struct drm_device *dev = dev_priv->dev;
1124         int reg, i;
1125         u32 val;
1126
1127         if (IS_VALLEYVIEW(dev)) {
1128                 for (i = 0; i < dev_priv->num_plane; i++) {
1129                         reg = SPCNTR(pipe, i);
1130                         val = I915_READ(reg);
1131                         WARN((val & SP_ENABLE),
1132                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1133                              sprite_name(pipe, i), pipe_name(pipe));
1134                 }
1135         } else if (INTEL_INFO(dev)->gen >= 7) {
1136                 reg = SPRCTL(pipe);
1137                 val = I915_READ(reg);
1138                 WARN((val & SPRITE_ENABLE),
1139                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1140                      plane_name(pipe), pipe_name(pipe));
1141         } else if (INTEL_INFO(dev)->gen >= 5) {
1142                 reg = DVSCNTR(pipe);
1143                 val = I915_READ(reg);
1144                 WARN((val & DVS_ENABLE),
1145                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1146                      plane_name(pipe), pipe_name(pipe));
1147         }
1148 }
1149
1150 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1151 {
1152         u32 val;
1153         bool enabled;
1154
1155         if (HAS_PCH_LPT(dev_priv->dev)) {
1156                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1157                 return;
1158         }
1159
1160         val = I915_READ(PCH_DREF_CONTROL);
1161         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1162                             DREF_SUPERSPREAD_SOURCE_MASK));
1163         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1164 }
1165
1166 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1167                                            enum i915_pipe pipe)
1168 {
1169         int reg;
1170         u32 val;
1171         bool enabled;
1172
1173         reg = PCH_TRANSCONF(pipe);
1174         val = I915_READ(reg);
1175         enabled = !!(val & TRANS_ENABLE);
1176         WARN(enabled,
1177              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1178              pipe_name(pipe));
1179 }
1180
1181 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1182                             enum i915_pipe pipe, u32 port_sel, u32 val)
1183 {
1184         if ((val & DP_PORT_EN) == 0)
1185                 return false;
1186
1187         if (HAS_PCH_CPT(dev_priv->dev)) {
1188                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1189                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1190                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1191                         return false;
1192         } else {
1193                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1194                         return false;
1195         }
1196         return true;
1197 }
1198
1199 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1200                               enum i915_pipe pipe, u32 val)
1201 {
1202         if ((val & SDVO_ENABLE) == 0)
1203                 return false;
1204
1205         if (HAS_PCH_CPT(dev_priv->dev)) {
1206                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1207                         return false;
1208         } else {
1209                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1210                         return false;
1211         }
1212         return true;
1213 }
1214
1215 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1216                               enum i915_pipe pipe, u32 val)
1217 {
1218         if ((val & LVDS_PORT_EN) == 0)
1219                 return false;
1220
1221         if (HAS_PCH_CPT(dev_priv->dev)) {
1222                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1223                         return false;
1224         } else {
1225                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1226                         return false;
1227         }
1228         return true;
1229 }
1230
1231 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1232                               enum i915_pipe pipe, u32 val)
1233 {
1234         if ((val & ADPA_DAC_ENABLE) == 0)
1235                 return false;
1236         if (HAS_PCH_CPT(dev_priv->dev)) {
1237                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1238                         return false;
1239         } else {
1240                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1241                         return false;
1242         }
1243         return true;
1244 }
1245
1246 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1247                                    enum i915_pipe pipe, int reg, u32 port_sel)
1248 {
1249         u32 val = I915_READ(reg);
1250         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1251              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1252              reg, pipe_name(pipe));
1253
1254         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1255              && (val & DP_PIPEB_SELECT),
1256              "IBX PCH dp port still using transcoder B\n");
1257 }
1258
1259 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1260                                      enum i915_pipe pipe, int reg)
1261 {
1262         u32 val = I915_READ(reg);
1263         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1264              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1265              reg, pipe_name(pipe));
1266
1267         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1268              && (val & SDVO_PIPE_B_SELECT),
1269              "IBX PCH hdmi port still using transcoder B\n");
1270 }
1271
1272 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1273                                       enum i915_pipe pipe)
1274 {
1275         int reg;
1276         u32 val;
1277
1278         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1279         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1280         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1281
1282         reg = PCH_ADPA;
1283         val = I915_READ(reg);
1284         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1285              "PCH VGA enabled on transcoder %c, should be disabled\n",
1286              pipe_name(pipe));
1287
1288         reg = PCH_LVDS;
1289         val = I915_READ(reg);
1290         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1291              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1292              pipe_name(pipe));
1293
1294         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1295         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1296         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1297 }
1298
1299 /**
1300  * intel_enable_pll - enable a PLL
1301  * @dev_priv: i915 private structure
1302  * @pipe: pipe PLL to enable
1303  *
1304  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1305  * make sure the PLL reg is writable first though, since the panel write
1306  * protect mechanism may be enabled.
1307  *
1308  * Note!  This is for pre-ILK only.
1309  *
1310  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1311  */
1312 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
1313 {
1314         int reg;
1315         u32 val;
1316
1317         assert_pipe_disabled(dev_priv, pipe);
1318
1319         /* No really, not for ILK+ */
1320         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1321
1322         /* PLL is protected by panel, make sure we can write it */
1323         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1324                 assert_panel_unlocked(dev_priv, pipe);
1325
1326         reg = DPLL(pipe);
1327         val = I915_READ(reg);
1328         val |= DPLL_VCO_ENABLE;
1329
1330         /* We do this three times for luck */
1331         I915_WRITE(reg, val);
1332         POSTING_READ(reg);
1333         udelay(150); /* wait for warmup */
1334         I915_WRITE(reg, val);
1335         POSTING_READ(reg);
1336         udelay(150); /* wait for warmup */
1337         I915_WRITE(reg, val);
1338         POSTING_READ(reg);
1339         udelay(150); /* wait for warmup */
1340 }
1341
1342 /**
1343  * intel_disable_pll - disable a PLL
1344  * @dev_priv: i915 private structure
1345  * @pipe: pipe PLL to disable
1346  *
1347  * Disable the PLL for @pipe, making sure the pipe is off first.
1348  *
1349  * Note!  This is for pre-ILK only.
1350  */
1351 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
1352 {
1353         int reg;
1354         u32 val;
1355
1356         /* Don't disable pipe A or pipe A PLLs if needed */
1357         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1358                 return;
1359
1360         /* Make sure the pipe isn't still relying on us */
1361         assert_pipe_disabled(dev_priv, pipe);
1362
1363         reg = DPLL(pipe);
1364         val = I915_READ(reg);
1365         val &= ~DPLL_VCO_ENABLE;
1366         I915_WRITE(reg, val);
1367         POSTING_READ(reg);
1368 }
1369
1370 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1371 {
1372         u32 port_mask;
1373
1374         if (!port)
1375                 port_mask = DPLL_PORTB_READY_MASK;
1376         else
1377                 port_mask = DPLL_PORTC_READY_MASK;
1378
1379         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1380                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1381                      'B' + port, I915_READ(DPLL(0)));
1382 }
1383
1384 /**
1385  * ironlake_enable_shared_dpll - enable PCH PLL
1386  * @dev_priv: i915 private structure
1387  * @pipe: pipe PLL to enable
1388  *
1389  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1390  * drives the transcoder clock.
1391  */
1392 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1393 {
1394         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1395         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1396
1397         /* PCH PLLs only available on ILK, SNB and IVB */
1398         BUG_ON(dev_priv->info->gen < 5);
1399         if (WARN_ON(pll == NULL))
1400                 return;
1401
1402         if (WARN_ON(pll->refcount == 0))
1403                 return;
1404
1405         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1406                       pll->name, pll->active, pll->on,
1407                       crtc->base.base.id);
1408
1409         if (pll->active++) {
1410                 WARN_ON(!pll->on);
1411                 assert_shared_dpll_enabled(dev_priv, pll);
1412                 return;
1413         }
1414         WARN_ON(pll->on);
1415
1416         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1417         pll->enable(dev_priv, pll);
1418         pll->on = true;
1419 }
1420
1421 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1422 {
1423         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1424         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1425
1426         /* PCH only available on ILK+ */
1427         BUG_ON(dev_priv->info->gen < 5);
1428         if (WARN_ON(pll == NULL))
1429                return;
1430
1431         if (WARN_ON(pll->refcount == 0))
1432                 return;
1433
1434         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1435                       pll->name, pll->active, pll->on,
1436                       crtc->base.base.id);
1437
1438         if (WARN_ON(pll->active == 0)) {
1439                 assert_shared_dpll_disabled(dev_priv, pll);
1440                 return;
1441         }
1442
1443         assert_shared_dpll_enabled(dev_priv, pll);
1444         WARN_ON(!pll->on);
1445         if (--pll->active)
1446                 return;
1447
1448         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1449         pll->disable(dev_priv, pll);
1450         pll->on = false;
1451 }
1452
1453 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1454                                            enum i915_pipe pipe)
1455 {
1456         struct drm_device *dev = dev_priv->dev;
1457         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1459         uint32_t reg, val, pipeconf_val;
1460
1461         /* PCH only available on ILK+ */
1462         BUG_ON(dev_priv->info->gen < 5);
1463
1464         /* Make sure PCH DPLL is enabled */
1465         assert_shared_dpll_enabled(dev_priv,
1466                                    intel_crtc_to_shared_dpll(intel_crtc));
1467
1468         /* FDI must be feeding us bits for PCH ports */
1469         assert_fdi_tx_enabled(dev_priv, pipe);
1470         assert_fdi_rx_enabled(dev_priv, pipe);
1471
1472         if (HAS_PCH_CPT(dev)) {
1473                 /* Workaround: Set the timing override bit before enabling the
1474                  * pch transcoder. */
1475                 reg = TRANS_CHICKEN2(pipe);
1476                 val = I915_READ(reg);
1477                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1478                 I915_WRITE(reg, val);
1479         }
1480
1481         reg = PCH_TRANSCONF(pipe);
1482         val = I915_READ(reg);
1483         pipeconf_val = I915_READ(PIPECONF(pipe));
1484
1485         if (HAS_PCH_IBX(dev_priv->dev)) {
1486                 /*
1487                  * make the BPC in transcoder be consistent with
1488                  * that in pipeconf reg.
1489                  */
1490                 val &= ~PIPECONF_BPC_MASK;
1491                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1492         }
1493
1494         val &= ~TRANS_INTERLACE_MASK;
1495         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1496                 if (HAS_PCH_IBX(dev_priv->dev) &&
1497                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1498                         val |= TRANS_LEGACY_INTERLACED_ILK;
1499                 else
1500                         val |= TRANS_INTERLACED;
1501         else
1502                 val |= TRANS_PROGRESSIVE;
1503
1504         I915_WRITE(reg, val | TRANS_ENABLE);
1505         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1506                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1507 }
1508
1509 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1510                                       enum transcoder cpu_transcoder)
1511 {
1512         u32 val, pipeconf_val;
1513
1514         /* PCH only available on ILK+ */
1515         BUG_ON(dev_priv->info->gen < 5);
1516
1517         /* FDI must be feeding us bits for PCH ports */
1518         assert_fdi_tx_enabled(dev_priv, (enum i915_pipe) cpu_transcoder);
1519         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1520
1521         /* Workaround: set timing override bit. */
1522         val = I915_READ(_TRANSA_CHICKEN2);
1523         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1524         I915_WRITE(_TRANSA_CHICKEN2, val);
1525
1526         val = TRANS_ENABLE;
1527         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1528
1529         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1530             PIPECONF_INTERLACED_ILK)
1531                 val |= TRANS_INTERLACED;
1532         else
1533                 val |= TRANS_PROGRESSIVE;
1534
1535         I915_WRITE(LPT_TRANSCONF, val);
1536         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1537                 DRM_ERROR("Failed to enable PCH transcoder\n");
1538 }
1539
1540 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1541                                             enum i915_pipe pipe)
1542 {
1543         struct drm_device *dev = dev_priv->dev;
1544         uint32_t reg, val;
1545
1546         /* FDI relies on the transcoder */
1547         assert_fdi_tx_disabled(dev_priv, pipe);
1548         assert_fdi_rx_disabled(dev_priv, pipe);
1549
1550         /* Ports must be off as well */
1551         assert_pch_ports_disabled(dev_priv, pipe);
1552
1553         reg = PCH_TRANSCONF(pipe);
1554         val = I915_READ(reg);
1555         val &= ~TRANS_ENABLE;
1556         I915_WRITE(reg, val);
1557         /* wait for PCH transcoder off, transcoder state */
1558         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1559                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1560
1561         if (!HAS_PCH_IBX(dev)) {
1562                 /* Workaround: Clear the timing override chicken bit again. */
1563                 reg = TRANS_CHICKEN2(pipe);
1564                 val = I915_READ(reg);
1565                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1566                 I915_WRITE(reg, val);
1567         }
1568 }
1569
1570 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1571 {
1572         u32 val;
1573
1574         val = I915_READ(LPT_TRANSCONF);
1575         val &= ~TRANS_ENABLE;
1576         I915_WRITE(LPT_TRANSCONF, val);
1577         /* wait for PCH transcoder off, transcoder state */
1578         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1579                 DRM_ERROR("Failed to disable PCH transcoder\n");
1580
1581         /* Workaround: clear timing override bit. */
1582         val = I915_READ(_TRANSA_CHICKEN2);
1583         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1584         I915_WRITE(_TRANSA_CHICKEN2, val);
1585 }
1586
1587 /**
1588  * intel_enable_pipe - enable a pipe, asserting requirements
1589  * @dev_priv: i915 private structure
1590  * @pipe: pipe to enable
1591  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1592  *
1593  * Enable @pipe, making sure that various hardware specific requirements
1594  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1595  *
1596  * @pipe should be %PIPE_A or %PIPE_B.
1597  *
1598  * Will wait until the pipe is actually running (i.e. first vblank) before
1599  * returning.
1600  */
1601 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
1602                               bool pch_port)
1603 {
1604         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1605                                                                       pipe);
1606         enum i915_pipe pch_transcoder;
1607         int reg;
1608         u32 val;
1609
1610         assert_planes_disabled(dev_priv, pipe);
1611         assert_sprites_disabled(dev_priv, pipe);
1612
1613         if (HAS_PCH_LPT(dev_priv->dev))
1614                 pch_transcoder = TRANSCODER_A;
1615         else
1616                 pch_transcoder = pipe;
1617
1618         /*
1619          * A pipe without a PLL won't actually be able to drive bits from
1620          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1621          * need the check.
1622          */
1623         if (!HAS_PCH_SPLIT(dev_priv->dev))
1624                 assert_pll_enabled(dev_priv, pipe);
1625         else {
1626                 if (pch_port) {
1627                         /* if driving the PCH, we need FDI enabled */
1628                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1629                         assert_fdi_tx_pll_enabled(dev_priv,
1630                                                   (enum i915_pipe) cpu_transcoder);
1631                 }
1632                 /* FIXME: assert CPU port conditions for SNB+ */
1633         }
1634
1635         reg = PIPECONF(cpu_transcoder);
1636         val = I915_READ(reg);
1637         if (val & PIPECONF_ENABLE)
1638                 return;
1639
1640         I915_WRITE(reg, val | PIPECONF_ENABLE);
1641         intel_wait_for_vblank(dev_priv->dev, pipe);
1642 }
1643
1644 /**
1645  * intel_disable_pipe - disable a pipe, asserting requirements
1646  * @dev_priv: i915 private structure
1647  * @pipe: pipe to disable
1648  *
1649  * Disable @pipe, making sure that various hardware specific requirements
1650  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1651  *
1652  * @pipe should be %PIPE_A or %PIPE_B.
1653  *
1654  * Will wait until the pipe has shut down before returning.
1655  */
1656 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1657                                enum i915_pipe pipe)
1658 {
1659         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1660                                                                       pipe);
1661         int reg;
1662         u32 val;
1663
1664         /*
1665          * Make sure planes won't keep trying to pump pixels to us,
1666          * or we might hang the display.
1667          */
1668         assert_planes_disabled(dev_priv, pipe);
1669         assert_sprites_disabled(dev_priv, pipe);
1670
1671         /* Don't disable pipe A or pipe A PLLs if needed */
1672         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1673                 return;
1674
1675         reg = PIPECONF(cpu_transcoder);
1676         val = I915_READ(reg);
1677         if ((val & PIPECONF_ENABLE) == 0)
1678                 return;
1679
1680         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1681         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1682 }
1683
1684 /*
1685  * Plane regs are double buffered, going from enabled->disabled needs a
1686  * trigger in order to latch.  The display address reg provides this.
1687  */
1688 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1689                                       enum plane plane)
1690 {
1691         if (dev_priv->info->gen >= 4)
1692                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1693         else
1694                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1695 }
1696
1697 /**
1698  * intel_enable_plane - enable a display plane on a given pipe
1699  * @dev_priv: i915 private structure
1700  * @plane: plane to enable
1701  * @pipe: pipe being fed
1702  *
1703  * Enable @plane on @pipe, making sure that @pipe is running first.
1704  */
1705 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1706                                enum plane plane, enum i915_pipe pipe)
1707 {
1708         int reg;
1709         u32 val;
1710
1711         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1712         assert_pipe_enabled(dev_priv, pipe);
1713
1714         reg = DSPCNTR(plane);
1715         val = I915_READ(reg);
1716         if (val & DISPLAY_PLANE_ENABLE)
1717                 return;
1718
1719         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1720         intel_flush_display_plane(dev_priv, plane);
1721         intel_wait_for_vblank(dev_priv->dev, pipe);
1722 }
1723
1724 /**
1725  * intel_disable_plane - disable a display plane
1726  * @dev_priv: i915 private structure
1727  * @plane: plane to disable
1728  * @pipe: pipe consuming the data
1729  *
1730  * Disable @plane; should be an independent operation.
1731  */
1732 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1733                                 enum plane plane, enum i915_pipe pipe)
1734 {
1735         int reg;
1736         u32 val;
1737
1738         reg = DSPCNTR(plane);
1739         val = I915_READ(reg);
1740         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1741                 return;
1742
1743         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1744         intel_flush_display_plane(dev_priv, plane);
1745         intel_wait_for_vblank(dev_priv->dev, pipe);
1746 }
1747
1748 static bool need_vtd_wa(struct drm_device *dev)
1749 {
1750 #ifdef CONFIG_INTEL_IOMMU
1751         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1752                 return true;
1753 #endif
1754         return false;
1755 }
1756
1757 int
1758 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1759                            struct drm_i915_gem_object *obj,
1760                            struct intel_ring_buffer *pipelined)
1761 {
1762         struct drm_i915_private *dev_priv = dev->dev_private;
1763         u32 alignment;
1764         int ret;
1765
1766         switch (obj->tiling_mode) {
1767         case I915_TILING_NONE:
1768                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1769                         alignment = 128 * 1024;
1770                 else if (INTEL_INFO(dev)->gen >= 4)
1771                         alignment = 4 * 1024;
1772                 else
1773                         alignment = 64 * 1024;
1774                 break;
1775         case I915_TILING_X:
1776                 /* pin() will align the object as required by fence */
1777                 alignment = 0;
1778                 break;
1779         case I915_TILING_Y:
1780                 /* Despite that we check this in framebuffer_init userspace can
1781                  * screw us over and change the tiling after the fact. Only
1782                  * pinned buffers can't change their tiling. */
1783                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1784                 return -EINVAL;
1785         default:
1786                 BUG();
1787         }
1788
1789         /* Note that the w/a also requires 64 PTE of padding following the
1790          * bo. We currently fill all unused PTE with the shadow page and so
1791          * we should always have valid PTE following the scanout preventing
1792          * the VT-d warning.
1793          */
1794         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1795                 alignment = 256 * 1024;
1796
1797         dev_priv->mm.interruptible = false;
1798         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1799         if (ret)
1800                 goto err_interruptible;
1801
1802         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1803          * fence, whereas 965+ only requires a fence if using
1804          * framebuffer compression.  For simplicity, we always install
1805          * a fence as the cost is not that onerous.
1806          */
1807         ret = i915_gem_object_get_fence(obj);
1808         if (ret)
1809                 goto err_unpin;
1810
1811         i915_gem_object_pin_fence(obj);
1812
1813         dev_priv->mm.interruptible = true;
1814         return 0;
1815
1816 err_unpin:
1817         i915_gem_object_unpin(obj);
1818 err_interruptible:
1819         dev_priv->mm.interruptible = true;
1820         return ret;
1821 }
1822
1823 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1824 {
1825         i915_gem_object_unpin_fence(obj);
1826         i915_gem_object_unpin(obj);
1827 }
1828
1829 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1830  * is assumed to be a power-of-two. */
1831 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1832                                              unsigned int tiling_mode,
1833                                              unsigned int cpp,
1834                                              unsigned int pitch)
1835 {
1836         if (tiling_mode != I915_TILING_NONE) {
1837                 unsigned int tile_rows, tiles;
1838
1839                 tile_rows = *y / 8;
1840                 *y %= 8;
1841
1842                 tiles = *x / (512/cpp);
1843                 *x %= 512/cpp;
1844
1845                 return tile_rows * pitch * 8 + tiles * 4096;
1846         } else {
1847                 unsigned int offset;
1848
1849                 offset = *y * pitch + *x * cpp;
1850                 *y = 0;
1851                 *x = (offset & 4095) / cpp;
1852                 return offset & -4096;
1853         }
1854 }
1855
1856 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1857                              int x, int y)
1858 {
1859         struct drm_device *dev = crtc->dev;
1860         struct drm_i915_private *dev_priv = dev->dev_private;
1861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1862         struct intel_framebuffer *intel_fb;
1863         struct drm_i915_gem_object *obj;
1864         int plane = intel_crtc->plane;
1865         unsigned long linear_offset;
1866         u32 dspcntr;
1867         u32 reg;
1868
1869         switch (plane) {
1870         case 0:
1871         case 1:
1872                 break;
1873         default:
1874                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1875                 return -EINVAL;
1876         }
1877
1878         intel_fb = to_intel_framebuffer(fb);
1879         obj = intel_fb->obj;
1880
1881         reg = DSPCNTR(plane);
1882         dspcntr = I915_READ(reg);
1883         /* Mask out pixel format bits in case we change it */
1884         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1885         switch (fb->pixel_format) {
1886         case DRM_FORMAT_C8:
1887                 dspcntr |= DISPPLANE_8BPP;
1888                 break;
1889         case DRM_FORMAT_XRGB1555:
1890         case DRM_FORMAT_ARGB1555:
1891                 dspcntr |= DISPPLANE_BGRX555;
1892                 break;
1893         case DRM_FORMAT_RGB565:
1894                 dspcntr |= DISPPLANE_BGRX565;
1895                 break;
1896         case DRM_FORMAT_XRGB8888:
1897         case DRM_FORMAT_ARGB8888:
1898                 dspcntr |= DISPPLANE_BGRX888;
1899                 break;
1900         case DRM_FORMAT_XBGR8888:
1901         case DRM_FORMAT_ABGR8888:
1902                 dspcntr |= DISPPLANE_RGBX888;
1903                 break;
1904         case DRM_FORMAT_XRGB2101010:
1905         case DRM_FORMAT_ARGB2101010:
1906                 dspcntr |= DISPPLANE_BGRX101010;
1907                 break;
1908         case DRM_FORMAT_XBGR2101010:
1909         case DRM_FORMAT_ABGR2101010:
1910                 dspcntr |= DISPPLANE_RGBX101010;
1911                 break;
1912         default:
1913                 BUG();
1914         }
1915
1916         if (INTEL_INFO(dev)->gen >= 4) {
1917                 if (obj->tiling_mode != I915_TILING_NONE)
1918                         dspcntr |= DISPPLANE_TILED;
1919                 else
1920                         dspcntr &= ~DISPPLANE_TILED;
1921         }
1922
1923         if (IS_G4X(dev))
1924                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1925
1926         I915_WRITE(reg, dspcntr);
1927
1928         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1929
1930         if (INTEL_INFO(dev)->gen >= 4) {
1931                 intel_crtc->dspaddr_offset =
1932                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1933                                                        fb->bits_per_pixel / 8,
1934                                                        fb->pitches[0]);
1935                 linear_offset -= intel_crtc->dspaddr_offset;
1936         } else {
1937                 intel_crtc->dspaddr_offset = linear_offset;
1938         }
1939
1940         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1941                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1942         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1943         if (INTEL_INFO(dev)->gen >= 4) {
1944                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1945                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1946                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1947                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1948         } else
1949                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1950         POSTING_READ(reg);
1951
1952         return 0;
1953 }
1954
1955 static int ironlake_update_plane(struct drm_crtc *crtc,
1956                                  struct drm_framebuffer *fb, int x, int y)
1957 {
1958         struct drm_device *dev = crtc->dev;
1959         struct drm_i915_private *dev_priv = dev->dev_private;
1960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1961         struct intel_framebuffer *intel_fb;
1962         struct drm_i915_gem_object *obj;
1963         int plane = intel_crtc->plane;
1964         unsigned long linear_offset;
1965         u32 dspcntr;
1966         u32 reg;
1967
1968         switch (plane) {
1969         case 0:
1970         case 1:
1971         case 2:
1972                 break;
1973         default:
1974                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1975                 return -EINVAL;
1976         }
1977
1978         intel_fb = to_intel_framebuffer(fb);
1979         obj = intel_fb->obj;
1980
1981         reg = DSPCNTR(plane);
1982         dspcntr = I915_READ(reg);
1983         /* Mask out pixel format bits in case we change it */
1984         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1985         switch (fb->pixel_format) {
1986         case DRM_FORMAT_C8:
1987                 dspcntr |= DISPPLANE_8BPP;
1988                 break;
1989         case DRM_FORMAT_RGB565:
1990                 dspcntr |= DISPPLANE_BGRX565;
1991                 break;
1992         case DRM_FORMAT_XRGB8888:
1993         case DRM_FORMAT_ARGB8888:
1994                 dspcntr |= DISPPLANE_BGRX888;
1995                 break;
1996         case DRM_FORMAT_XBGR8888:
1997         case DRM_FORMAT_ABGR8888:
1998                 dspcntr |= DISPPLANE_RGBX888;
1999                 break;
2000         case DRM_FORMAT_XRGB2101010:
2001         case DRM_FORMAT_ARGB2101010:
2002                 dspcntr |= DISPPLANE_BGRX101010;
2003                 break;
2004         case DRM_FORMAT_XBGR2101010:
2005         case DRM_FORMAT_ABGR2101010:
2006                 dspcntr |= DISPPLANE_RGBX101010;
2007                 break;
2008         default:
2009                 BUG();
2010         }
2011
2012         if (obj->tiling_mode != I915_TILING_NONE)
2013                 dspcntr |= DISPPLANE_TILED;
2014         else
2015                 dspcntr &= ~DISPPLANE_TILED;
2016
2017         /* must disable */
2018         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2019
2020         I915_WRITE(reg, dspcntr);
2021
2022         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2023         intel_crtc->dspaddr_offset =
2024                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2025                                                fb->bits_per_pixel / 8,
2026                                                fb->pitches[0]);
2027         linear_offset -= intel_crtc->dspaddr_offset;
2028
2029         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2030                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2031         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2032         I915_MODIFY_DISPBASE(DSPSURF(plane),
2033                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2034         if (IS_HASWELL(dev)) {
2035                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2036         } else {
2037                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2038                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2039         }
2040         POSTING_READ(reg);
2041
2042         return 0;
2043 }
2044
2045 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2046 static int
2047 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2048                            int x, int y, enum mode_set_atomic state)
2049 {
2050         struct drm_device *dev = crtc->dev;
2051         struct drm_i915_private *dev_priv = dev->dev_private;
2052
2053         if (dev_priv->display.disable_fbc)
2054                 dev_priv->display.disable_fbc(dev);
2055         intel_increase_pllclock(crtc);
2056
2057         return dev_priv->display.update_plane(crtc, fb, x, y);
2058 }
2059
2060 void intel_display_handle_reset(struct drm_device *dev)
2061 {
2062         struct drm_i915_private *dev_priv = dev->dev_private;
2063         struct drm_crtc *crtc;
2064
2065         /*
2066          * Flips in the rings have been nuked by the reset,
2067          * so complete all pending flips so that user space
2068          * will get its events and not get stuck.
2069          *
2070          * Also update the base address of all primary
2071          * planes to the the last fb to make sure we're
2072          * showing the correct fb after a reset.
2073          *
2074          * Need to make two loops over the crtcs so that we
2075          * don't try to grab a crtc mutex before the
2076          * pending_flip_queue really got woken up.
2077          */
2078
2079         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2080                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2081                 enum plane plane = intel_crtc->plane;
2082
2083                 intel_prepare_page_flip(dev, plane);
2084                 intel_finish_page_flip_plane(dev, plane);
2085         }
2086
2087         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2088                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2089
2090                 mutex_lock(&crtc->mutex);
2091                 if (intel_crtc->active)
2092                         dev_priv->display.update_plane(crtc, crtc->fb,
2093                                                        crtc->x, crtc->y);
2094                 mutex_unlock(&crtc->mutex);
2095         }
2096 }
2097
2098 static int
2099 intel_finish_fb(struct drm_framebuffer *old_fb)
2100 {
2101         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2102         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2103         bool was_interruptible = dev_priv->mm.interruptible;
2104         int ret;
2105
2106         /* Big Hammer, we also need to ensure that any pending
2107          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2108          * current scanout is retired before unpinning the old
2109          * framebuffer.
2110          *
2111          * This should only fail upon a hung GPU, in which case we
2112          * can safely continue.
2113          */
2114         dev_priv->mm.interruptible = false;
2115         ret = i915_gem_object_finish_gpu(obj);
2116         dev_priv->mm.interruptible = was_interruptible;
2117
2118         return ret;
2119 }
2120
2121 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2122 {
2123         struct drm_device *dev = crtc->dev;
2124 #if 0
2125         struct drm_i915_master_private *master_priv;
2126 #else
2127         drm_i915_private_t *dev_priv = dev->dev_private;
2128 #endif
2129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2130
2131 #if 0
2132         if (!dev->primary->master)
2133                 return;
2134
2135         master_priv = dev->primary->master->driver_priv;
2136         if (!master_priv->sarea_priv)
2137                 return;
2138 #else
2139         if (!dev_priv->sarea_priv)
2140                 return;
2141 #endif
2142
2143         switch (intel_crtc->pipe) {
2144         case 0:
2145 #if 0
2146                 master_priv->sarea_priv->pipeA_x = x;
2147                 master_priv->sarea_priv->pipeA_y = y;
2148 #else
2149                 dev_priv->sarea_priv->planeA_x = x;
2150                 dev_priv->sarea_priv->planeA_y = y;
2151 #endif
2152                 break;
2153         case 1:
2154 #if 0
2155                 master_priv->sarea_priv->pipeB_x = x;
2156                 master_priv->sarea_priv->pipeB_y = y;
2157 #else
2158                 dev_priv->sarea_priv->planeB_x = x;
2159                 dev_priv->sarea_priv->planeB_y = y;
2160 #endif
2161                 break;
2162         default:
2163                 break;
2164         }
2165 }
2166
2167 static int
2168 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2169                     struct drm_framebuffer *fb)
2170 {
2171         struct drm_device *dev = crtc->dev;
2172         struct drm_i915_private *dev_priv = dev->dev_private;
2173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2174         struct drm_framebuffer *old_fb;
2175         int ret;
2176
2177         /* no fb bound */
2178         if (!fb) {
2179                 DRM_ERROR("No FB bound\n");
2180                 return 0;
2181         }
2182
2183         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2184                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2185                           plane_name(intel_crtc->plane),
2186                           INTEL_INFO(dev)->num_pipes);
2187                 return -EINVAL;
2188         }
2189
2190         mutex_lock(&dev->struct_mutex);
2191         ret = intel_pin_and_fence_fb_obj(dev,
2192                                          to_intel_framebuffer(fb)->obj,
2193                                          NULL);
2194         if (ret != 0) {
2195                 mutex_unlock(&dev->struct_mutex);
2196                 DRM_ERROR("pin & fence failed\n");
2197                 return ret;
2198         }
2199
2200         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2201         if (ret) {
2202                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2203                 mutex_unlock(&dev->struct_mutex);
2204                 DRM_ERROR("failed to update base address\n");
2205                 return ret;
2206         }
2207
2208         old_fb = crtc->fb;
2209         crtc->fb = fb;
2210         crtc->x = x;
2211         crtc->y = y;
2212
2213         if (old_fb) {
2214                 if (intel_crtc->active && old_fb != fb)
2215                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2216                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2217         }
2218
2219         intel_update_fbc(dev);
2220         mutex_unlock(&dev->struct_mutex);
2221
2222         intel_crtc_update_sarea_pos(crtc, x, y);
2223
2224         return 0;
2225 }
2226
2227 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2228 {
2229         struct drm_device *dev = crtc->dev;
2230         struct drm_i915_private *dev_priv = dev->dev_private;
2231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2232         int pipe = intel_crtc->pipe;
2233         u32 reg, temp;
2234
2235         /* enable normal train */
2236         reg = FDI_TX_CTL(pipe);
2237         temp = I915_READ(reg);
2238         if (IS_IVYBRIDGE(dev)) {
2239                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2240                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2241         } else {
2242                 temp &= ~FDI_LINK_TRAIN_NONE;
2243                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2244         }
2245         I915_WRITE(reg, temp);
2246
2247         reg = FDI_RX_CTL(pipe);
2248         temp = I915_READ(reg);
2249         if (HAS_PCH_CPT(dev)) {
2250                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2251                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2252         } else {
2253                 temp &= ~FDI_LINK_TRAIN_NONE;
2254                 temp |= FDI_LINK_TRAIN_NONE;
2255         }
2256         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2257
2258         /* wait one idle pattern time */
2259         POSTING_READ(reg);
2260         udelay(1000);
2261
2262         /* IVB wants error correction enabled */
2263         if (IS_IVYBRIDGE(dev))
2264                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2265                            FDI_FE_ERRC_ENABLE);
2266 }
2267
2268 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2269 {
2270         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2271 }
2272
2273 static void ivb_modeset_global_resources(struct drm_device *dev)
2274 {
2275         struct drm_i915_private *dev_priv = dev->dev_private;
2276         struct intel_crtc *pipe_B_crtc =
2277                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2278         struct intel_crtc *pipe_C_crtc =
2279                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2280         uint32_t temp;
2281
2282         /*
2283          * When everything is off disable fdi C so that we could enable fdi B
2284          * with all lanes. Note that we don't care about enabled pipes without
2285          * an enabled pch encoder.
2286          */
2287         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2288             !pipe_has_enabled_pch(pipe_C_crtc)) {
2289                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2290                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2291
2292                 temp = I915_READ(SOUTH_CHICKEN1);
2293                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2294                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2295                 I915_WRITE(SOUTH_CHICKEN1, temp);
2296         }
2297 }
2298
2299 /* The FDI link training functions for ILK/Ibexpeak. */
2300 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2301 {
2302         struct drm_device *dev = crtc->dev;
2303         struct drm_i915_private *dev_priv = dev->dev_private;
2304         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2305         int pipe = intel_crtc->pipe;
2306         int plane = intel_crtc->plane;
2307         u32 reg, temp, tries;
2308
2309         /* FDI needs bits from pipe & plane first */
2310         assert_pipe_enabled(dev_priv, pipe);
2311         assert_plane_enabled(dev_priv, plane);
2312
2313         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2314            for train result */
2315         reg = FDI_RX_IMR(pipe);
2316         temp = I915_READ(reg);
2317         temp &= ~FDI_RX_SYMBOL_LOCK;
2318         temp &= ~FDI_RX_BIT_LOCK;
2319         I915_WRITE(reg, temp);
2320         I915_READ(reg);
2321         udelay(150);
2322
2323         /* enable CPU FDI TX and PCH FDI RX */
2324         reg = FDI_TX_CTL(pipe);
2325         temp = I915_READ(reg);
2326         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2327         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2328         temp &= ~FDI_LINK_TRAIN_NONE;
2329         temp |= FDI_LINK_TRAIN_PATTERN_1;
2330         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2331
2332         reg = FDI_RX_CTL(pipe);
2333         temp = I915_READ(reg);
2334         temp &= ~FDI_LINK_TRAIN_NONE;
2335         temp |= FDI_LINK_TRAIN_PATTERN_1;
2336         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2337
2338         POSTING_READ(reg);
2339         udelay(150);
2340
2341         /* Ironlake workaround, enable clock pointer after FDI enable*/
2342         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2343         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2344                    FDI_RX_PHASE_SYNC_POINTER_EN);
2345
2346         reg = FDI_RX_IIR(pipe);
2347         for (tries = 0; tries < 5; tries++) {
2348                 temp = I915_READ(reg);
2349                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2350
2351                 if ((temp & FDI_RX_BIT_LOCK)) {
2352                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2353                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2354                         break;
2355                 }
2356         }
2357         if (tries == 5)
2358                 DRM_ERROR("FDI train 1 fail!\n");
2359
2360         /* Train 2 */
2361         reg = FDI_TX_CTL(pipe);
2362         temp = I915_READ(reg);
2363         temp &= ~FDI_LINK_TRAIN_NONE;
2364         temp |= FDI_LINK_TRAIN_PATTERN_2;
2365         I915_WRITE(reg, temp);
2366
2367         reg = FDI_RX_CTL(pipe);
2368         temp = I915_READ(reg);
2369         temp &= ~FDI_LINK_TRAIN_NONE;
2370         temp |= FDI_LINK_TRAIN_PATTERN_2;
2371         I915_WRITE(reg, temp);
2372
2373         POSTING_READ(reg);
2374         udelay(150);
2375
2376         reg = FDI_RX_IIR(pipe);
2377         for (tries = 0; tries < 5; tries++) {
2378                 temp = I915_READ(reg);
2379                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2380
2381                 if (temp & FDI_RX_SYMBOL_LOCK) {
2382                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2383                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2384                         break;
2385                 }
2386         }
2387         if (tries == 5)
2388                 DRM_ERROR("FDI train 2 fail!\n");
2389
2390         DRM_DEBUG_KMS("FDI train done\n");
2391
2392 }
2393
2394 static const int snb_b_fdi_train_param[] = {
2395         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2396         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2397         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2398         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2399 };
2400
2401 /* The FDI link training functions for SNB/Cougarpoint. */
2402 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2403 {
2404         struct drm_device *dev = crtc->dev;
2405         struct drm_i915_private *dev_priv = dev->dev_private;
2406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2407         int pipe = intel_crtc->pipe;
2408         u32 reg, temp, i, retry;
2409
2410         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2411            for train result */
2412         reg = FDI_RX_IMR(pipe);
2413         temp = I915_READ(reg);
2414         temp &= ~FDI_RX_SYMBOL_LOCK;
2415         temp &= ~FDI_RX_BIT_LOCK;
2416         I915_WRITE(reg, temp);
2417
2418         POSTING_READ(reg);
2419         udelay(150);
2420
2421         /* enable CPU FDI TX and PCH FDI RX */
2422         reg = FDI_TX_CTL(pipe);
2423         temp = I915_READ(reg);
2424         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2425         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2426         temp &= ~FDI_LINK_TRAIN_NONE;
2427         temp |= FDI_LINK_TRAIN_PATTERN_1;
2428         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2429         /* SNB-B */
2430         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2431         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2432
2433         I915_WRITE(FDI_RX_MISC(pipe),
2434                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2435
2436         reg = FDI_RX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         if (HAS_PCH_CPT(dev)) {
2439                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2440                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2441         } else {
2442                 temp &= ~FDI_LINK_TRAIN_NONE;
2443                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2444         }
2445         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2446
2447         POSTING_READ(reg);
2448         udelay(150);
2449
2450         for (i = 0; i < 4; i++) {
2451                 reg = FDI_TX_CTL(pipe);
2452                 temp = I915_READ(reg);
2453                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2454                 temp |= snb_b_fdi_train_param[i];
2455                 I915_WRITE(reg, temp);
2456
2457                 POSTING_READ(reg);
2458                 udelay(500);
2459
2460                 for (retry = 0; retry < 5; retry++) {
2461                         reg = FDI_RX_IIR(pipe);
2462                         temp = I915_READ(reg);
2463                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2464                         if (temp & FDI_RX_BIT_LOCK) {
2465                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2466                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2467                                 break;
2468                         }
2469                         udelay(50);
2470                 }
2471                 if (retry < 5)
2472                         break;
2473         }
2474         if (i == 4)
2475                 DRM_ERROR("FDI train 1 fail!\n");
2476
2477         /* Train 2 */
2478         reg = FDI_TX_CTL(pipe);
2479         temp = I915_READ(reg);
2480         temp &= ~FDI_LINK_TRAIN_NONE;
2481         temp |= FDI_LINK_TRAIN_PATTERN_2;
2482         if (IS_GEN6(dev)) {
2483                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2484                 /* SNB-B */
2485                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2486         }
2487         I915_WRITE(reg, temp);
2488
2489         reg = FDI_RX_CTL(pipe);
2490         temp = I915_READ(reg);
2491         if (HAS_PCH_CPT(dev)) {
2492                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2493                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2494         } else {
2495                 temp &= ~FDI_LINK_TRAIN_NONE;
2496                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2497         }
2498         I915_WRITE(reg, temp);
2499
2500         POSTING_READ(reg);
2501         udelay(150);
2502
2503         for (i = 0; i < 4; i++) {
2504                 reg = FDI_TX_CTL(pipe);
2505                 temp = I915_READ(reg);
2506                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2507                 temp |= snb_b_fdi_train_param[i];
2508                 I915_WRITE(reg, temp);
2509
2510                 POSTING_READ(reg);
2511                 udelay(500);
2512
2513                 for (retry = 0; retry < 5; retry++) {
2514                         reg = FDI_RX_IIR(pipe);
2515                         temp = I915_READ(reg);
2516                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2517                         if (temp & FDI_RX_SYMBOL_LOCK) {
2518                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2519                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2520                                 break;
2521                         }
2522                         udelay(50);
2523                 }
2524                 if (retry < 5)
2525                         break;
2526         }
2527         if (i == 4)
2528                 DRM_ERROR("FDI train 2 fail!\n");
2529
2530         DRM_DEBUG_KMS("FDI train done.\n");
2531 }
2532
2533 /* Manual link training for Ivy Bridge A0 parts */
2534 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2535 {
2536         struct drm_device *dev = crtc->dev;
2537         struct drm_i915_private *dev_priv = dev->dev_private;
2538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2539         int pipe = intel_crtc->pipe;
2540         u32 reg, temp, i;
2541
2542         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2543            for train result */
2544         reg = FDI_RX_IMR(pipe);
2545         temp = I915_READ(reg);
2546         temp &= ~FDI_RX_SYMBOL_LOCK;
2547         temp &= ~FDI_RX_BIT_LOCK;
2548         I915_WRITE(reg, temp);
2549
2550         POSTING_READ(reg);
2551         udelay(150);
2552
2553         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2554                       I915_READ(FDI_RX_IIR(pipe)));
2555
2556         /* enable CPU FDI TX and PCH FDI RX */
2557         reg = FDI_TX_CTL(pipe);
2558         temp = I915_READ(reg);
2559         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2560         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2561         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2562         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2563         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2564         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2565         temp |= FDI_COMPOSITE_SYNC;
2566         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2567
2568         I915_WRITE(FDI_RX_MISC(pipe),
2569                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2570
2571         reg = FDI_RX_CTL(pipe);
2572         temp = I915_READ(reg);
2573         temp &= ~FDI_LINK_TRAIN_AUTO;
2574         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2575         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2576         temp |= FDI_COMPOSITE_SYNC;
2577         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2578
2579         POSTING_READ(reg);
2580         udelay(150);
2581
2582         for (i = 0; i < 4; i++) {
2583                 reg = FDI_TX_CTL(pipe);
2584                 temp = I915_READ(reg);
2585                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586                 temp |= snb_b_fdi_train_param[i];
2587                 I915_WRITE(reg, temp);
2588
2589                 POSTING_READ(reg);
2590                 udelay(500);
2591
2592                 reg = FDI_RX_IIR(pipe);
2593                 temp = I915_READ(reg);
2594                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2595
2596                 if (temp & FDI_RX_BIT_LOCK ||
2597                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2598                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2599                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2600                         break;
2601                 }
2602         }
2603         if (i == 4)
2604                 DRM_ERROR("FDI train 1 fail!\n");
2605
2606         /* Train 2 */
2607         reg = FDI_TX_CTL(pipe);
2608         temp = I915_READ(reg);
2609         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2610         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2611         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2612         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2613         I915_WRITE(reg, temp);
2614
2615         reg = FDI_RX_CTL(pipe);
2616         temp = I915_READ(reg);
2617         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2618         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2619         I915_WRITE(reg, temp);
2620
2621         POSTING_READ(reg);
2622         udelay(150);
2623
2624         for (i = 0; i < 4; i++) {
2625                 reg = FDI_TX_CTL(pipe);
2626                 temp = I915_READ(reg);
2627                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2628                 temp |= snb_b_fdi_train_param[i];
2629                 I915_WRITE(reg, temp);
2630
2631                 POSTING_READ(reg);
2632                 udelay(500);
2633
2634                 reg = FDI_RX_IIR(pipe);
2635                 temp = I915_READ(reg);
2636                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2637
2638                 if (temp & FDI_RX_SYMBOL_LOCK) {
2639                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2640                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2641                         break;
2642                 }
2643         }
2644         if (i == 4)
2645                 DRM_ERROR("FDI train 2 fail!\n");
2646
2647         DRM_DEBUG_KMS("FDI train done.\n");
2648 }
2649
2650 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2651 {
2652         struct drm_device *dev = intel_crtc->base.dev;
2653         struct drm_i915_private *dev_priv = dev->dev_private;
2654         int pipe = intel_crtc->pipe;
2655         u32 reg, temp;
2656
2657
2658         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2659         reg = FDI_RX_CTL(pipe);
2660         temp = I915_READ(reg);
2661         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2662         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2663         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2664         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2665
2666         POSTING_READ(reg);
2667         udelay(200);
2668
2669         /* Switch from Rawclk to PCDclk */
2670         temp = I915_READ(reg);
2671         I915_WRITE(reg, temp | FDI_PCDCLK);
2672
2673         POSTING_READ(reg);
2674         udelay(200);
2675
2676         /* Enable CPU FDI TX PLL, always on for Ironlake */
2677         reg = FDI_TX_CTL(pipe);
2678         temp = I915_READ(reg);
2679         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2680                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2681
2682                 POSTING_READ(reg);
2683                 udelay(100);
2684         }
2685 }
2686
2687 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2688 {
2689         struct drm_device *dev = intel_crtc->base.dev;
2690         struct drm_i915_private *dev_priv = dev->dev_private;
2691         int pipe = intel_crtc->pipe;
2692         u32 reg, temp;
2693
2694         /* Switch from PCDclk to Rawclk */
2695         reg = FDI_RX_CTL(pipe);
2696         temp = I915_READ(reg);
2697         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2698
2699         /* Disable CPU FDI TX PLL */
2700         reg = FDI_TX_CTL(pipe);
2701         temp = I915_READ(reg);
2702         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2703
2704         POSTING_READ(reg);
2705         udelay(100);
2706
2707         reg = FDI_RX_CTL(pipe);
2708         temp = I915_READ(reg);
2709         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2710
2711         /* Wait for the clocks to turn off. */
2712         POSTING_READ(reg);
2713         udelay(100);
2714 }
2715
2716 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2717 {
2718         struct drm_device *dev = crtc->dev;
2719         struct drm_i915_private *dev_priv = dev->dev_private;
2720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2721         int pipe = intel_crtc->pipe;
2722         u32 reg, temp;
2723
2724         /* disable CPU FDI tx and PCH FDI rx */
2725         reg = FDI_TX_CTL(pipe);
2726         temp = I915_READ(reg);
2727         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2728         POSTING_READ(reg);
2729
2730         reg = FDI_RX_CTL(pipe);
2731         temp = I915_READ(reg);
2732         temp &= ~(0x7 << 16);
2733         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2734         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2735
2736         POSTING_READ(reg);
2737         udelay(100);
2738
2739         /* Ironlake workaround, disable clock pointer after downing FDI */
2740         if (HAS_PCH_IBX(dev)) {
2741                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2742         }
2743
2744         /* still set train pattern 1 */
2745         reg = FDI_TX_CTL(pipe);
2746         temp = I915_READ(reg);
2747         temp &= ~FDI_LINK_TRAIN_NONE;
2748         temp |= FDI_LINK_TRAIN_PATTERN_1;
2749         I915_WRITE(reg, temp);
2750
2751         reg = FDI_RX_CTL(pipe);
2752         temp = I915_READ(reg);
2753         if (HAS_PCH_CPT(dev)) {
2754                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2755                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2756         } else {
2757                 temp &= ~FDI_LINK_TRAIN_NONE;
2758                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2759         }
2760         /* BPC in FDI rx is consistent with that in PIPECONF */
2761         temp &= ~(0x07 << 16);
2762         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2763         I915_WRITE(reg, temp);
2764
2765         POSTING_READ(reg);
2766         udelay(100);
2767 }
2768
2769 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2770 {
2771         struct drm_device *dev = crtc->dev;
2772         struct drm_i915_private *dev_priv = dev->dev_private;
2773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2774         bool pending;
2775
2776         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2777             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2778                 return false;
2779
2780         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
2781         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2782         lockmgr(&dev->event_lock, LK_RELEASE);
2783
2784         return pending;
2785 }
2786
2787 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2788 {
2789         struct drm_device *dev = crtc->dev;
2790         struct drm_i915_private *dev_priv = dev->dev_private;
2791
2792         if (crtc->fb == NULL)
2793                 return;
2794
2795         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2796
2797         wait_event(dev_priv->pending_flip_queue,
2798                    !intel_crtc_has_pending_flip(crtc));
2799
2800         mutex_lock(&dev->struct_mutex);
2801         intel_finish_fb(crtc->fb);
2802         mutex_unlock(&dev->struct_mutex);
2803 }
2804
2805 /* Program iCLKIP clock to the desired frequency */
2806 static void lpt_program_iclkip(struct drm_crtc *crtc)
2807 {
2808         struct drm_device *dev = crtc->dev;
2809         struct drm_i915_private *dev_priv = dev->dev_private;
2810         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2811         u32 temp;
2812
2813         mutex_lock(&dev_priv->dpio_lock);
2814
2815         /* It is necessary to ungate the pixclk gate prior to programming
2816          * the divisors, and gate it back when it is done.
2817          */
2818         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2819
2820         /* Disable SSCCTL */
2821         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2822                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2823                                 SBI_SSCCTL_DISABLE,
2824                         SBI_ICLK);
2825
2826         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2827         if (crtc->mode.clock == 20000) {
2828                 auxdiv = 1;
2829                 divsel = 0x41;
2830                 phaseinc = 0x20;
2831         } else {
2832                 /* The iCLK virtual clock root frequency is in MHz,
2833                  * but the crtc->mode.clock in in KHz. To get the divisors,
2834                  * it is necessary to divide one by another, so we
2835                  * convert the virtual clock precision to KHz here for higher
2836                  * precision.
2837                  */
2838                 u32 iclk_virtual_root_freq = 172800 * 1000;
2839                 u32 iclk_pi_range = 64;
2840                 u32 desired_divisor, msb_divisor_value, pi_value;
2841
2842                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2843                 msb_divisor_value = desired_divisor / iclk_pi_range;
2844                 pi_value = desired_divisor % iclk_pi_range;
2845
2846                 auxdiv = 0;
2847                 divsel = msb_divisor_value - 2;
2848                 phaseinc = pi_value;
2849         }
2850
2851         /* This should not happen with any sane values */
2852         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2853                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2854         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2855                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2856
2857         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2858                         crtc->mode.clock,
2859                         auxdiv,
2860                         divsel,
2861                         phasedir,
2862                         phaseinc);
2863
2864         /* Program SSCDIVINTPHASE6 */
2865         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2866         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2867         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2868         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2869         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2870         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2871         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2872         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2873
2874         /* Program SSCAUXDIV */
2875         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2876         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2877         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2878         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2879
2880         /* Enable modulator and associated divider */
2881         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2882         temp &= ~SBI_SSCCTL_DISABLE;
2883         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2884
2885         /* Wait for initialization time */
2886         udelay(24);
2887
2888         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2889
2890         mutex_unlock(&dev_priv->dpio_lock);
2891 }
2892
2893 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2894                                                 enum i915_pipe pch_transcoder)
2895 {
2896         struct drm_device *dev = crtc->base.dev;
2897         struct drm_i915_private *dev_priv = dev->dev_private;
2898         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2899
2900         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2901                    I915_READ(HTOTAL(cpu_transcoder)));
2902         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2903                    I915_READ(HBLANK(cpu_transcoder)));
2904         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2905                    I915_READ(HSYNC(cpu_transcoder)));
2906
2907         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2908                    I915_READ(VTOTAL(cpu_transcoder)));
2909         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2910                    I915_READ(VBLANK(cpu_transcoder)));
2911         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2912                    I915_READ(VSYNC(cpu_transcoder)));
2913         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2914                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2915 }
2916
2917 /*
2918  * Enable PCH resources required for PCH ports:
2919  *   - PCH PLLs
2920  *   - FDI training & RX/TX
2921  *   - update transcoder timings
2922  *   - DP transcoding bits
2923  *   - transcoder
2924  */
2925 static void ironlake_pch_enable(struct drm_crtc *crtc)
2926 {
2927         struct drm_device *dev = crtc->dev;
2928         struct drm_i915_private *dev_priv = dev->dev_private;
2929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2930         int pipe = intel_crtc->pipe;
2931         u32 reg, temp;
2932
2933         assert_pch_transcoder_disabled(dev_priv, pipe);
2934
2935         /* Write the TU size bits before fdi link training, so that error
2936          * detection works. */
2937         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2938                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2939
2940         /* For PCH output, training FDI link */
2941         dev_priv->display.fdi_link_train(crtc);
2942
2943         /* XXX: pch pll's can be enabled any time before we enable the PCH
2944          * transcoder, and we actually should do this to not upset any PCH
2945          * transcoder that already use the clock when we share it.
2946          *
2947          * Note that enable_shared_dpll tries to do the right thing, but
2948          * get_shared_dpll unconditionally resets the pll - we need that to have
2949          * the right LVDS enable sequence. */
2950         ironlake_enable_shared_dpll(intel_crtc);
2951
2952         if (HAS_PCH_CPT(dev)) {
2953                 u32 sel;
2954
2955                 temp = I915_READ(PCH_DPLL_SEL);
2956                 temp |= TRANS_DPLL_ENABLE(pipe);
2957                 sel = TRANS_DPLLB_SEL(pipe);
2958                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
2959                         temp |= sel;
2960                 else
2961                         temp &= ~sel;
2962                 I915_WRITE(PCH_DPLL_SEL, temp);
2963         }
2964
2965         /* set transcoder timing, panel must allow it */
2966         assert_panel_unlocked(dev_priv, pipe);
2967         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2968
2969         intel_fdi_normal_train(crtc);
2970
2971         /* For PCH DP, enable TRANS_DP_CTL */
2972         if (HAS_PCH_CPT(dev) &&
2973             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2974              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2975                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2976                 reg = TRANS_DP_CTL(pipe);
2977                 temp = I915_READ(reg);
2978                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2979                           TRANS_DP_SYNC_MASK |
2980                           TRANS_DP_BPC_MASK);
2981                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2982                          TRANS_DP_ENH_FRAMING);
2983                 temp |= bpc << 9; /* same format but at 11:9 */
2984
2985                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2986                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2987                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2988                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2989
2990                 switch (intel_trans_dp_port_sel(crtc)) {
2991                 case PCH_DP_B:
2992                         temp |= TRANS_DP_PORT_SEL_B;
2993                         break;
2994                 case PCH_DP_C:
2995                         temp |= TRANS_DP_PORT_SEL_C;
2996                         break;
2997                 case PCH_DP_D:
2998                         temp |= TRANS_DP_PORT_SEL_D;
2999                         break;
3000                 default:
3001                         BUG();
3002                 }
3003
3004                 I915_WRITE(reg, temp);
3005         }
3006
3007         ironlake_enable_pch_transcoder(dev_priv, pipe);
3008 }
3009
3010 static void lpt_pch_enable(struct drm_crtc *crtc)
3011 {
3012         struct drm_device *dev = crtc->dev;
3013         struct drm_i915_private *dev_priv = dev->dev_private;
3014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3015         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3016
3017         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3018
3019         lpt_program_iclkip(crtc);
3020
3021         /* Set transcoder timing. */
3022         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3023
3024         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3025 }
3026
3027 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3028 {
3029         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3030
3031         if (pll == NULL)
3032                 return;
3033
3034         if (pll->refcount == 0) {
3035                 WARN(1, "bad %s refcount\n", pll->name);
3036                 return;
3037         }
3038
3039         if (--pll->refcount == 0) {
3040                 WARN_ON(pll->on);
3041                 WARN_ON(pll->active);
3042         }
3043
3044         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3045 }
3046
3047 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
3048 {
3049         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3050         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3051         enum intel_dpll_id i;
3052
3053         if (pll) {
3054                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3055                               crtc->base.base.id, pll->name);
3056                 intel_put_shared_dpll(crtc);
3057         }
3058
3059         if (HAS_PCH_IBX(dev_priv->dev)) {
3060                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3061                 i = crtc->pipe;
3062                 pll = &dev_priv->shared_dplls[i];
3063
3064                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3065                               crtc->base.base.id, pll->name);
3066
3067                 goto found;
3068         }
3069
3070         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3071                 pll = &dev_priv->shared_dplls[i];
3072
3073                 /* Only want to check enabled timings first */
3074                 if (pll->refcount == 0)
3075                         continue;
3076
3077                 if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3078                     fp == I915_READ(PCH_FP0(pll->id))) {
3079                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3080                                       crtc->base.base.id,
3081                                       pll->name, pll->refcount, pll->active);
3082
3083                         goto found;
3084                 }
3085         }
3086
3087         /* Ok no matching timings, maybe there's a free one? */
3088         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3089                 pll = &dev_priv->shared_dplls[i];
3090                 if (pll->refcount == 0) {
3091                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3092                                       crtc->base.base.id, pll->name);
3093                         goto found;
3094                 }
3095         }
3096
3097         return NULL;
3098
3099 found:
3100         crtc->config.shared_dpll = i;
3101         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3102                          pipe_name(crtc->pipe));
3103
3104         if (pll->active == 0) {
3105                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3106                        sizeof(pll->hw_state));
3107
3108                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3109                 WARN_ON(pll->on);
3110                 assert_shared_dpll_disabled(dev_priv, pll);
3111
3112                 /* Wait for the clocks to stabilize before rewriting the regs */
3113                 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3114                 POSTING_READ(PCH_DPLL(pll->id));
3115                 udelay(150);
3116
3117                 I915_WRITE(PCH_FP0(pll->id), fp);
3118                 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3119         }
3120         pll->refcount++;
3121
3122         return pll;
3123 }
3124
3125 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3126 {
3127         struct drm_i915_private *dev_priv = dev->dev_private;
3128         int dslreg = PIPEDSL(pipe);
3129         u32 temp;
3130
3131         temp = I915_READ(dslreg);
3132         udelay(500);
3133         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3134                 if (wait_for(I915_READ(dslreg) != temp, 5))
3135                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3136         }
3137 }
3138
3139 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3140 {
3141         struct drm_device *dev = crtc->base.dev;
3142         struct drm_i915_private *dev_priv = dev->dev_private;
3143         int pipe = crtc->pipe;
3144
3145         if (crtc->config.pch_pfit.size) {
3146                 /* Force use of hard-coded filter coefficients
3147                  * as some pre-programmed values are broken,
3148                  * e.g. x201.
3149                  */
3150                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3151                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3152                                                  PF_PIPE_SEL_IVB(pipe));
3153                 else
3154                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3155                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3156                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3157         }
3158 }
3159
3160 static void intel_enable_planes(struct drm_crtc *crtc)
3161 {
3162         struct drm_device *dev = crtc->dev;
3163         enum i915_pipe pipe = to_intel_crtc(crtc)->pipe;
3164         struct intel_plane *intel_plane;
3165
3166         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3167                 if (intel_plane->pipe == pipe)
3168                         intel_plane_restore(&intel_plane->base);
3169 }
3170
3171 static void intel_disable_planes(struct drm_crtc *crtc)
3172 {
3173         struct drm_device *dev = crtc->dev;
3174         enum i915_pipe pipe = to_intel_crtc(crtc)->pipe;
3175         struct intel_plane *intel_plane;
3176
3177         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3178                 if (intel_plane->pipe == pipe)
3179                         intel_plane_disable(&intel_plane->base);
3180 }
3181
3182 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3183 {
3184         struct drm_device *dev = crtc->dev;
3185         struct drm_i915_private *dev_priv = dev->dev_private;
3186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3187         struct intel_encoder *encoder;
3188         int pipe = intel_crtc->pipe;
3189         int plane = intel_crtc->plane;
3190         u32 temp;
3191
3192         WARN_ON(!crtc->enabled);
3193
3194         if (intel_crtc->active)
3195                 return;
3196
3197         intel_crtc->active = true;
3198
3199         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3200         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3201
3202         intel_update_watermarks(dev);
3203
3204         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3205                 temp = I915_READ(PCH_LVDS);
3206                 if ((temp & LVDS_PORT_EN) == 0)
3207                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3208         }
3209
3210
3211         if (intel_crtc->config.has_pch_encoder) {
3212                 /* Note: FDI PLL enabling _must_ be done before we enable the
3213                  * cpu pipes, hence this is separate from all the other fdi/pch
3214                  * enabling. */
3215                 ironlake_fdi_pll_enable(intel_crtc);
3216         } else {
3217                 assert_fdi_tx_disabled(dev_priv, pipe);
3218                 assert_fdi_rx_disabled(dev_priv, pipe);
3219         }
3220
3221         for_each_encoder_on_crtc(dev, crtc, encoder)
3222                 if (encoder->pre_enable)
3223                         encoder->pre_enable(encoder);
3224
3225         ironlake_pfit_enable(intel_crtc);
3226
3227         /*
3228          * On ILK+ LUT must be loaded before the pipe is running but with
3229          * clocks enabled
3230          */
3231         intel_crtc_load_lut(crtc);
3232
3233         intel_enable_pipe(dev_priv, pipe,
3234                           intel_crtc->config.has_pch_encoder);
3235         intel_enable_plane(dev_priv, plane, pipe);
3236         intel_enable_planes(crtc);
3237         intel_crtc_update_cursor(crtc, true);
3238
3239         if (intel_crtc->config.has_pch_encoder)
3240                 ironlake_pch_enable(crtc);
3241
3242         mutex_lock(&dev->struct_mutex);
3243         intel_update_fbc(dev);
3244         mutex_unlock(&dev->struct_mutex);
3245
3246         for_each_encoder_on_crtc(dev, crtc, encoder)
3247                 encoder->enable(encoder);
3248
3249         if (HAS_PCH_CPT(dev))
3250                 cpt_verify_modeset(dev, intel_crtc->pipe);
3251
3252         /*
3253          * There seems to be a race in PCH platform hw (at least on some
3254          * outputs) where an enabled pipe still completes any pageflip right
3255          * away (as if the pipe is off) instead of waiting for vblank. As soon
3256          * as the first vblank happend, everything works as expected. Hence just
3257          * wait for one vblank before returning to avoid strange things
3258          * happening.
3259          */
3260         intel_wait_for_vblank(dev, intel_crtc->pipe);
3261 }
3262
3263 /* IPS only exists on ULT machines and is tied to pipe A. */
3264 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3265 {
3266         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3267 }
3268
3269 static void hsw_enable_ips(struct intel_crtc *crtc)
3270 {
3271         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3272
3273         if (!crtc->config.ips_enabled)
3274                 return;
3275
3276         /* We can only enable IPS after we enable a plane and wait for a vblank.
3277          * We guarantee that the plane is enabled by calling intel_enable_ips
3278          * only after intel_enable_plane. And intel_enable_plane already waits
3279          * for a vblank, so all we need to do here is to enable the IPS bit. */
3280         assert_plane_enabled(dev_priv, crtc->plane);
3281         I915_WRITE(IPS_CTL, IPS_ENABLE);
3282 }
3283
3284 static void hsw_disable_ips(struct intel_crtc *crtc)
3285 {
3286         struct drm_device *dev = crtc->base.dev;
3287         struct drm_i915_private *dev_priv = dev->dev_private;
3288
3289         if (!crtc->config.ips_enabled)
3290                 return;
3291
3292         assert_plane_enabled(dev_priv, crtc->plane);
3293         I915_WRITE(IPS_CTL, 0);
3294
3295         /* We need to wait for a vblank before we can disable the plane. */
3296         intel_wait_for_vblank(dev, crtc->pipe);
3297 }
3298
3299 static void haswell_crtc_enable(struct drm_crtc *crtc)
3300 {
3301         struct drm_device *dev = crtc->dev;
3302         struct drm_i915_private *dev_priv = dev->dev_private;
3303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3304         struct intel_encoder *encoder;
3305         int pipe = intel_crtc->pipe;
3306         int plane = intel_crtc->plane;
3307
3308         WARN_ON(!crtc->enabled);
3309
3310         if (intel_crtc->active)
3311                 return;
3312
3313         intel_crtc->active = true;
3314
3315         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3316         if (intel_crtc->config.has_pch_encoder)
3317                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3318
3319         intel_update_watermarks(dev);
3320
3321         if (intel_crtc->config.has_pch_encoder)
3322                 dev_priv->display.fdi_link_train(crtc);
3323
3324         for_each_encoder_on_crtc(dev, crtc, encoder)
3325                 if (encoder->pre_enable)
3326                         encoder->pre_enable(encoder);
3327
3328         intel_ddi_enable_pipe_clock(intel_crtc);
3329
3330         ironlake_pfit_enable(intel_crtc);
3331
3332         /*
3333          * On ILK+ LUT must be loaded before the pipe is running but with
3334          * clocks enabled
3335          */
3336         intel_crtc_load_lut(crtc);
3337
3338         intel_ddi_set_pipe_settings(crtc);
3339         intel_ddi_enable_transcoder_func(crtc);
3340
3341         intel_enable_pipe(dev_priv, pipe,
3342                           intel_crtc->config.has_pch_encoder);
3343         intel_enable_plane(dev_priv, plane, pipe);
3344         intel_enable_planes(crtc);
3345         intel_crtc_update_cursor(crtc, true);
3346
3347         hsw_enable_ips(intel_crtc);
3348
3349         if (intel_crtc->config.has_pch_encoder)
3350                 lpt_pch_enable(crtc);
3351
3352         mutex_lock(&dev->struct_mutex);
3353         intel_update_fbc(dev);
3354         mutex_unlock(&dev->struct_mutex);
3355
3356         for_each_encoder_on_crtc(dev, crtc, encoder)
3357                 encoder->enable(encoder);
3358
3359         /*
3360          * There seems to be a race in PCH platform hw (at least on some
3361          * outputs) where an enabled pipe still completes any pageflip right
3362          * away (as if the pipe is off) instead of waiting for vblank. As soon
3363          * as the first vblank happend, everything works as expected. Hence just
3364          * wait for one vblank before returning to avoid strange things
3365          * happening.
3366          */
3367         intel_wait_for_vblank(dev, intel_crtc->pipe);
3368 }
3369
3370 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3371 {
3372         struct drm_device *dev = crtc->base.dev;
3373         struct drm_i915_private *dev_priv = dev->dev_private;
3374         int pipe = crtc->pipe;
3375
3376         /* To avoid upsetting the power well on haswell only disable the pfit if
3377          * it's in use. The hw state code will make sure we get this right. */
3378         if (crtc->config.pch_pfit.size) {
3379                 I915_WRITE(PF_CTL(pipe), 0);
3380                 I915_WRITE(PF_WIN_POS(pipe), 0);
3381                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3382         }
3383 }
3384
3385 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3386 {
3387         struct drm_device *dev = crtc->dev;
3388         struct drm_i915_private *dev_priv = dev->dev_private;
3389         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3390         struct intel_encoder *encoder;
3391         int pipe = intel_crtc->pipe;
3392         int plane = intel_crtc->plane;
3393         u32 reg, temp;
3394
3395
3396         if (!intel_crtc->active)
3397                 return;
3398
3399         for_each_encoder_on_crtc(dev, crtc, encoder)
3400                 encoder->disable(encoder);
3401
3402         intel_crtc_wait_for_pending_flips(crtc);
3403         drm_vblank_off(dev, pipe);
3404
3405         if (dev_priv->cfb_plane == plane)
3406                 intel_disable_fbc(dev);
3407
3408         intel_crtc_update_cursor(crtc, false);
3409         intel_disable_planes(crtc);
3410         intel_disable_plane(dev_priv, plane, pipe);
3411
3412         if (intel_crtc->config.has_pch_encoder)
3413                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3414
3415         intel_disable_pipe(dev_priv, pipe);
3416
3417         ironlake_pfit_disable(intel_crtc);
3418
3419         for_each_encoder_on_crtc(dev, crtc, encoder)
3420                 if (encoder->post_disable)
3421                         encoder->post_disable(encoder);
3422
3423         if (intel_crtc->config.has_pch_encoder) {
3424                 ironlake_fdi_disable(crtc);
3425
3426                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3427                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3428
3429                 if (HAS_PCH_CPT(dev)) {
3430                         /* disable TRANS_DP_CTL */
3431                         reg = TRANS_DP_CTL(pipe);
3432                         temp = I915_READ(reg);
3433                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3434                                   TRANS_DP_PORT_SEL_MASK);
3435                         temp |= TRANS_DP_PORT_SEL_NONE;
3436                         I915_WRITE(reg, temp);
3437
3438                         /* disable DPLL_SEL */
3439                         temp = I915_READ(PCH_DPLL_SEL);
3440                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3441                         I915_WRITE(PCH_DPLL_SEL, temp);
3442                 }
3443
3444                 /* disable PCH DPLL */
3445                 intel_disable_shared_dpll(intel_crtc);
3446
3447                 ironlake_fdi_pll_disable(intel_crtc);
3448         }
3449
3450         intel_crtc->active = false;
3451         intel_update_watermarks(dev);
3452
3453         mutex_lock(&dev->struct_mutex);
3454         intel_update_fbc(dev);
3455         mutex_unlock(&dev->struct_mutex);
3456 }
3457
3458 static void haswell_crtc_disable(struct drm_crtc *crtc)
3459 {
3460         struct drm_device *dev = crtc->dev;
3461         struct drm_i915_private *dev_priv = dev->dev_private;
3462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3463         struct intel_encoder *encoder;
3464         int pipe = intel_crtc->pipe;
3465         int plane = intel_crtc->plane;
3466         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3467
3468         if (!intel_crtc->active)
3469                 return;
3470
3471         for_each_encoder_on_crtc(dev, crtc, encoder)
3472                 encoder->disable(encoder);
3473
3474         intel_crtc_wait_for_pending_flips(crtc);
3475         drm_vblank_off(dev, pipe);
3476
3477         /* FBC must be disabled before disabling the plane on HSW. */
3478         if (dev_priv->cfb_plane == plane)
3479                 intel_disable_fbc(dev);
3480
3481         hsw_disable_ips(intel_crtc);
3482
3483         intel_crtc_update_cursor(crtc, false);
3484         intel_disable_planes(crtc);
3485         intel_disable_plane(dev_priv, plane, pipe);
3486
3487         if (intel_crtc->config.has_pch_encoder)
3488                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3489         intel_disable_pipe(dev_priv, pipe);
3490
3491         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3492
3493         ironlake_pfit_disable(intel_crtc);
3494
3495         intel_ddi_disable_pipe_clock(intel_crtc);
3496
3497         for_each_encoder_on_crtc(dev, crtc, encoder)
3498                 if (encoder->post_disable)
3499                         encoder->post_disable(encoder);
3500
3501         if (intel_crtc->config.has_pch_encoder) {
3502                 lpt_disable_pch_transcoder(dev_priv);
3503                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3504                 intel_ddi_fdi_disable(crtc);
3505         }
3506
3507         intel_crtc->active = false;
3508         intel_update_watermarks(dev);
3509
3510         mutex_lock(&dev->struct_mutex);
3511         intel_update_fbc(dev);
3512         mutex_unlock(&dev->struct_mutex);
3513 }
3514
3515 static void ironlake_crtc_off(struct drm_crtc *crtc)
3516 {
3517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3518         intel_put_shared_dpll(intel_crtc);
3519 }
3520
3521 static void haswell_crtc_off(struct drm_crtc *crtc)
3522 {
3523         intel_ddi_put_crtc_pll(crtc);
3524 }
3525
3526 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3527 {
3528         if (!enable && intel_crtc->overlay) {
3529                 struct drm_device *dev = intel_crtc->base.dev;
3530                 struct drm_i915_private *dev_priv = dev->dev_private;
3531
3532                 mutex_lock(&dev->struct_mutex);
3533                 dev_priv->mm.interruptible = false;
3534                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3535                 dev_priv->mm.interruptible = true;
3536                 mutex_unlock(&dev->struct_mutex);
3537         }
3538
3539         /* Let userspace switch the overlay on again. In most cases userspace
3540          * has to recompute where to put it anyway.
3541          */
3542 }
3543
3544 /**
3545  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3546  * cursor plane briefly if not already running after enabling the display
3547  * plane.
3548  * This workaround avoids occasional blank screens when self refresh is
3549  * enabled.
3550  */
3551 static void
3552 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
3553 {
3554         u32 cntl = I915_READ(CURCNTR(pipe));
3555
3556         if ((cntl & CURSOR_MODE) == 0) {
3557                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3558
3559                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3560                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3561                 intel_wait_for_vblank(dev_priv->dev, pipe);
3562                 I915_WRITE(CURCNTR(pipe), cntl);
3563                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3564                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3565         }
3566 }
3567
3568 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3569 {
3570         struct drm_device *dev = crtc->base.dev;
3571         struct drm_i915_private *dev_priv = dev->dev_private;
3572         struct intel_crtc_config *pipe_config = &crtc->config;
3573
3574         if (!crtc->config.gmch_pfit.control)
3575                 return;
3576
3577         /*
3578          * The panel fitter should only be adjusted whilst the pipe is disabled,
3579          * according to register description and PRM.
3580          */
3581         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3582         assert_pipe_disabled(dev_priv, crtc->pipe);
3583
3584         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3585         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3586
3587         /* Border color in case we don't scale up to the full screen. Black by
3588          * default, change to something else for debugging. */
3589         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3590 }
3591
3592 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3593 {
3594         struct drm_device *dev = crtc->dev;
3595         struct drm_i915_private *dev_priv = dev->dev_private;
3596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597         struct intel_encoder *encoder;
3598         int pipe = intel_crtc->pipe;
3599         int plane = intel_crtc->plane;
3600
3601         WARN_ON(!crtc->enabled);
3602
3603         if (intel_crtc->active)
3604                 return;
3605
3606         intel_crtc->active = true;
3607         intel_update_watermarks(dev);
3608
3609         mutex_lock(&dev_priv->dpio_lock);
3610
3611         for_each_encoder_on_crtc(dev, crtc, encoder)
3612                 if (encoder->pre_pll_enable)
3613                         encoder->pre_pll_enable(encoder);
3614
3615         intel_enable_pll(dev_priv, pipe);
3616
3617         for_each_encoder_on_crtc(dev, crtc, encoder)
3618                 if (encoder->pre_enable)
3619                         encoder->pre_enable(encoder);
3620
3621         /* VLV wants encoder enabling _before_ the pipe is up. */
3622         for_each_encoder_on_crtc(dev, crtc, encoder)
3623                 encoder->enable(encoder);
3624
3625         i9xx_pfit_enable(intel_crtc);
3626
3627         intel_crtc_load_lut(crtc);
3628
3629         intel_enable_pipe(dev_priv, pipe, false);
3630         intel_enable_plane(dev_priv, plane, pipe);
3631         intel_enable_planes(crtc);
3632         intel_crtc_update_cursor(crtc, true);
3633
3634         intel_update_fbc(dev);
3635
3636         mutex_unlock(&dev_priv->dpio_lock);
3637 }
3638
3639 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3640 {
3641         struct drm_device *dev = crtc->dev;
3642         struct drm_i915_private *dev_priv = dev->dev_private;
3643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644         struct intel_encoder *encoder;
3645         int pipe = intel_crtc->pipe;
3646         int plane = intel_crtc->plane;
3647
3648         WARN_ON(!crtc->enabled);
3649
3650         if (intel_crtc->active)
3651                 return;
3652
3653         intel_crtc->active = true;
3654         intel_update_watermarks(dev);
3655
3656         intel_enable_pll(dev_priv, pipe);
3657
3658         for_each_encoder_on_crtc(dev, crtc, encoder)
3659                 if (encoder->pre_enable)
3660                         encoder->pre_enable(encoder);
3661
3662         i9xx_pfit_enable(intel_crtc);
3663
3664         intel_crtc_load_lut(crtc);
3665
3666         intel_enable_pipe(dev_priv, pipe, false);
3667         intel_enable_plane(dev_priv, plane, pipe);
3668         intel_enable_planes(crtc);
3669         /* The fixup needs to happen before cursor is enabled */
3670         if (IS_G4X(dev))
3671                 g4x_fixup_plane(dev_priv, pipe);
3672         intel_crtc_update_cursor(crtc, true);
3673
3674         /* Give the overlay scaler a chance to enable if it's on this pipe */
3675         intel_crtc_dpms_overlay(intel_crtc, true);
3676
3677         intel_update_fbc(dev);
3678
3679         for_each_encoder_on_crtc(dev, crtc, encoder)
3680                 encoder->enable(encoder);
3681 }
3682
3683 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3684 {
3685         struct drm_device *dev = crtc->base.dev;
3686         struct drm_i915_private *dev_priv = dev->dev_private;
3687
3688         if (!crtc->config.gmch_pfit.control)
3689                 return;
3690
3691         assert_pipe_disabled(dev_priv, crtc->pipe);
3692
3693         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3694                          I915_READ(PFIT_CONTROL));
3695         I915_WRITE(PFIT_CONTROL, 0);
3696 }
3697
3698 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3699 {
3700         struct drm_device *dev = crtc->dev;
3701         struct drm_i915_private *dev_priv = dev->dev_private;
3702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3703         struct intel_encoder *encoder;
3704         int pipe = intel_crtc->pipe;
3705         int plane = intel_crtc->plane;
3706
3707         if (!intel_crtc->active)
3708                 return;
3709
3710         for_each_encoder_on_crtc(dev, crtc, encoder)
3711                 encoder->disable(encoder);
3712
3713         /* Give the overlay scaler a chance to disable if it's on this pipe */
3714         intel_crtc_wait_for_pending_flips(crtc);
3715         drm_vblank_off(dev, pipe);
3716
3717         if (dev_priv->cfb_plane == plane)
3718                 intel_disable_fbc(dev);
3719
3720         intel_crtc_dpms_overlay(intel_crtc, false);
3721         intel_crtc_update_cursor(crtc, false);
3722         intel_disable_planes(crtc);
3723         intel_disable_plane(dev_priv, plane, pipe);
3724
3725         intel_disable_pipe(dev_priv, pipe);
3726
3727         i9xx_pfit_disable(intel_crtc);
3728
3729         for_each_encoder_on_crtc(dev, crtc, encoder)
3730                 if (encoder->post_disable)
3731                         encoder->post_disable(encoder);
3732
3733         intel_disable_pll(dev_priv, pipe);
3734
3735         intel_crtc->active = false;
3736         intel_update_fbc(dev);
3737         intel_update_watermarks(dev);
3738 }
3739
3740 static void i9xx_crtc_off(struct drm_crtc *crtc)
3741 {
3742 }
3743
3744 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3745                                     bool enabled)
3746 {
3747         struct drm_device *dev = crtc->dev;
3748         struct drm_i915_private *dev_priv = dev->dev_private;
3749 #if 0
3750         struct drm_i915_master_private *master_priv;
3751 #endif
3752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3753         int pipe = intel_crtc->pipe;
3754
3755 #if 0
3756         if (!dev->primary->master)
3757                 return;
3758
3759         master_priv = dev->primary->master->driver_priv;
3760         if (!master_priv->sarea_priv)
3761                 return;
3762 #else
3763         if (!dev_priv->sarea_priv)
3764                 return;
3765 #endif
3766
3767         switch (pipe) {
3768         case 0:
3769 #if 0
3770                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3771                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3772 #else
3773                 dev_priv->sarea_priv->planeA_w = enabled ? crtc->mode.hdisplay : 0;
3774                 dev_priv->sarea_priv->planeA_h = enabled ? crtc->mode.vdisplay : 0;
3775 #endif
3776                 break;
3777         case 1:
3778 #if 0
3779                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3780                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3781 #else
3782                 dev_priv->sarea_priv->planeB_w = enabled ? crtc->mode.hdisplay : 0;
3783                 dev_priv->sarea_priv->planeB_h = enabled ? crtc->mode.vdisplay : 0;
3784 #endif
3785                 break;
3786         default:
3787                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3788                 break;
3789         }
3790 }
3791
3792 /**
3793  * Sets the power management mode of the pipe and plane.
3794  */
3795 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3796 {
3797         struct drm_device *dev = crtc->dev;
3798         struct drm_i915_private *dev_priv = dev->dev_private;
3799         struct intel_encoder *intel_encoder;
3800         bool enable = false;
3801
3802         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3803                 enable |= intel_encoder->connectors_active;
3804
3805         if (enable)
3806                 dev_priv->display.crtc_enable(crtc);
3807         else
3808                 dev_priv->display.crtc_disable(crtc);
3809
3810         intel_crtc_update_sarea(crtc, enable);
3811 }
3812
3813 static void intel_crtc_disable(struct drm_crtc *crtc)
3814 {
3815         struct drm_device *dev = crtc->dev;
3816         struct drm_connector *connector;
3817         struct drm_i915_private *dev_priv = dev->dev_private;
3818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3819
3820         /* crtc should still be enabled when we disable it. */
3821         WARN_ON(!crtc->enabled);
3822
3823         dev_priv->display.crtc_disable(crtc);
3824         intel_crtc->eld_vld = false;
3825         intel_crtc_update_sarea(crtc, false);
3826         dev_priv->display.off(crtc);
3827
3828         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3829         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3830
3831         if (crtc->fb) {
3832                 mutex_lock(&dev->struct_mutex);
3833                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3834                 mutex_unlock(&dev->struct_mutex);
3835                 crtc->fb = NULL;
3836         }
3837
3838         /* Update computed state. */
3839         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3840                 if (!connector->encoder || !connector->encoder->crtc)
3841                         continue;
3842
3843                 if (connector->encoder->crtc != crtc)
3844                         continue;
3845
3846                 connector->dpms = DRM_MODE_DPMS_OFF;
3847                 to_intel_encoder(connector->encoder)->connectors_active = false;
3848         }
3849 }
3850
3851 void intel_modeset_disable(struct drm_device *dev)
3852 {
3853         struct drm_crtc *crtc;
3854
3855         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3856                 if (crtc->enabled)
3857                         intel_crtc_disable(crtc);
3858         }
3859 }
3860
3861 void intel_encoder_destroy(struct drm_encoder *encoder)
3862 {
3863         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3864
3865         drm_encoder_cleanup(encoder);
3866         kfree(intel_encoder);
3867 }
3868
3869 /* Simple dpms helper for encodres with just one connector, no cloning and only
3870  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3871  * state of the entire output pipe. */
3872 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3873 {
3874         if (mode == DRM_MODE_DPMS_ON) {
3875                 encoder->connectors_active = true;
3876
3877                 intel_crtc_update_dpms(encoder->base.crtc);
3878         } else {
3879                 encoder->connectors_active = false;
3880
3881                 intel_crtc_update_dpms(encoder->base.crtc);
3882         }
3883 }
3884
3885 /* Cross check the actual hw state with our own modeset state tracking (and it's
3886  * internal consistency). */
3887 static void intel_connector_check_state(struct intel_connector *connector)
3888 {
3889         if (connector->get_hw_state(connector)) {
3890                 struct intel_encoder *encoder = connector->encoder;
3891                 struct drm_crtc *crtc;
3892                 bool encoder_enabled;
3893                 enum i915_pipe pipe;
3894
3895                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3896                               connector->base.base.id,
3897                               drm_get_connector_name(&connector->base));
3898
3899                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3900                      "wrong connector dpms state\n");
3901                 WARN(connector->base.encoder != &encoder->base,
3902                      "active connector not linked to encoder\n");
3903                 WARN(!encoder->connectors_active,
3904                      "encoder->connectors_active not set\n");
3905
3906                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3907                 WARN(!encoder_enabled, "encoder not enabled\n");
3908                 if (WARN_ON(!encoder->base.crtc))
3909                         return;
3910
3911                 crtc = encoder->base.crtc;
3912
3913                 WARN(!crtc->enabled, "crtc not enabled\n");
3914                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3915                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3916                      "encoder active on the wrong pipe\n");
3917         }
3918 }
3919
3920 /* Even simpler default implementation, if there's really no special case to
3921  * consider. */
3922 void intel_connector_dpms(struct drm_connector *connector, int mode)
3923 {
3924         struct intel_encoder *encoder = intel_attached_encoder(connector);
3925
3926         /* All the simple cases only support two dpms states. */
3927         if (mode != DRM_MODE_DPMS_ON)
3928                 mode = DRM_MODE_DPMS_OFF;
3929
3930         if (mode == connector->dpms)
3931                 return;
3932
3933         connector->dpms = mode;
3934
3935         /* Only need to change hw state when actually enabled */
3936         if (encoder->base.crtc)
3937                 intel_encoder_dpms(encoder, mode);
3938         else
3939                 WARN_ON(encoder->connectors_active != false);
3940
3941         intel_modeset_check_state(connector->dev);
3942 }
3943
3944 /* Simple connector->get_hw_state implementation for encoders that support only
3945  * one connector and no cloning and hence the encoder state determines the state
3946  * of the connector. */
3947 bool intel_connector_get_hw_state(struct intel_connector *connector)
3948 {
3949         enum i915_pipe pipe = 0;
3950         struct intel_encoder *encoder = connector->encoder;
3951
3952         return encoder->get_hw_state(encoder, &pipe);
3953 }
3954
3955 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum i915_pipe pipe,
3956                                      struct intel_crtc_config *pipe_config)
3957 {
3958         struct drm_i915_private *dev_priv = dev->dev_private;
3959         struct intel_crtc *pipe_B_crtc =
3960                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3961
3962         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3963                       pipe_name(pipe), pipe_config->fdi_lanes);
3964         if (pipe_config->fdi_lanes > 4) {
3965                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3966                               pipe_name(pipe), pipe_config->fdi_lanes);
3967                 return false;
3968         }
3969
3970         if (IS_HASWELL(dev)) {
3971                 if (pipe_config->fdi_lanes > 2) {
3972                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3973                                       pipe_config->fdi_lanes);
3974                         return false;
3975                 } else {
3976                         return true;
3977                 }
3978         }
3979
3980         if (INTEL_INFO(dev)->num_pipes == 2)
3981                 return true;
3982
3983         /* Ivybridge 3 pipe is really complicated */
3984         switch (pipe) {
3985         case PIPE_A:
3986                 return true;
3987         case PIPE_B:
3988                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3989                     pipe_config->fdi_lanes > 2) {
3990                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3991                                       pipe_name(pipe), pipe_config->fdi_lanes);
3992                         return false;
3993                 }
3994                 return true;
3995         case PIPE_C:
3996                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3997                     pipe_B_crtc->config.fdi_lanes <= 2) {
3998                         if (pipe_config->fdi_lanes > 2) {
3999                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4000                                               pipe_name(pipe), pipe_config->fdi_lanes);
4001                                 return false;
4002                         }
4003                 } else {
4004                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4005                         return false;
4006                 }
4007                 return true;
4008         default:
4009                 BUG();
4010         }
4011 }
4012
4013 #define RETRY 1
4014 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4015                                        struct intel_crtc_config *pipe_config)
4016 {
4017         struct drm_device *dev = intel_crtc->base.dev;
4018         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4019         int lane, link_bw, fdi_dotclock;
4020         bool setup_ok, needs_recompute = false;
4021
4022 retry:
4023         /* FDI is a binary signal running at ~2.7GHz, encoding
4024          * each output octet as 10 bits. The actual frequency
4025          * is stored as a divider into a 100MHz clock, and the
4026          * mode pixel clock is stored in units of 1KHz.
4027          * Hence the bw of each lane in terms of the mode signal
4028          * is:
4029          */
4030         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4031
4032         fdi_dotclock = adjusted_mode->clock;
4033         fdi_dotclock /= pipe_config->pixel_multiplier;
4034
4035         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4036                                            pipe_config->pipe_bpp);
4037
4038         pipe_config->fdi_lanes = lane;
4039
4040         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4041                                link_bw, &pipe_config->fdi_m_n);
4042
4043         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4044                                             intel_crtc->pipe, pipe_config);
4045         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4046                 pipe_config->pipe_bpp -= 2*3;
4047                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4048                               pipe_config->pipe_bpp);
4049                 needs_recompute = true;
4050                 pipe_config->bw_constrained = true;
4051
4052                 goto retry;
4053         }
4054
4055         if (needs_recompute)
4056                 return RETRY;
4057
4058         return setup_ok ? 0 : -EINVAL;
4059 }
4060
4061 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4062                                    struct intel_crtc_config *pipe_config)
4063 {
4064         pipe_config->ips_enabled = i915_enable_ips &&
4065                                    hsw_crtc_supports_ips(crtc) &&
4066                                    pipe_config->pipe_bpp == 24;
4067 }
4068
4069 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4070                                      struct intel_crtc_config *pipe_config)
4071 {
4072         struct drm_device *dev = crtc->base.dev;
4073         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4074
4075         if (HAS_PCH_SPLIT(dev)) {
4076                 /* FDI link clock is fixed at 2.7G */
4077                 if (pipe_config->requested_mode.clock * 3
4078                     > IRONLAKE_FDI_FREQ * 4)
4079                         return -EINVAL;
4080         }
4081
4082         /* All interlaced capable intel hw wants timings in frames. Note though
4083          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4084          * timings, so we need to be careful not to clobber these.*/
4085         if (!pipe_config->timings_set)
4086                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4087
4088         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4089          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4090          */
4091         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4092                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4093                 return -EINVAL;
4094
4095         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4096                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4097         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4098                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4099                  * for lvds. */
4100                 pipe_config->pipe_bpp = 8*3;
4101         }
4102
4103         if (HAS_IPS(dev))
4104                 hsw_compute_ips_config(crtc, pipe_config);
4105
4106         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4107          * clock survives for now. */
4108         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4109                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4110
4111         if (pipe_config->has_pch_encoder)
4112                 return ironlake_fdi_compute_config(crtc, pipe_config);
4113
4114         return 0;
4115 }
4116
4117 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4118 {
4119         return 400000; /* FIXME */
4120 }
4121
4122 static int i945_get_display_clock_speed(struct drm_device *dev)
4123 {
4124         return 400000;
4125 }
4126
4127 static int i915_get_display_clock_speed(struct drm_device *dev)
4128 {
4129         return 333000;
4130 }
4131
4132 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4133 {
4134         return 200000;
4135 }
4136
4137 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4138 {
4139         u16 gcfgc = 0;
4140
4141         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4142
4143         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4144                 return 133000;
4145         else {
4146                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4147                 case GC_DISPLAY_CLOCK_333_MHZ:
4148                         return 333000;
4149                 default:
4150                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4151                         return 190000;
4152                 }
4153         }
4154 }
4155
4156 static int i865_get_display_clock_speed(struct drm_device *dev)
4157 {
4158         return 266000;
4159 }
4160
4161 static int i855_get_display_clock_speed(struct drm_device *dev)
4162 {
4163         u16 hpllcc = 0;
4164         /* Assume that the hardware is in the high speed state.  This
4165          * should be the default.
4166          */
4167         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4168         case GC_CLOCK_133_200:
4169         case GC_CLOCK_100_200:
4170                 return 200000;
4171         case GC_CLOCK_166_250:
4172                 return 250000;
4173         case GC_CLOCK_100_133:
4174                 return 133000;
4175         }
4176
4177         /* Shouldn't happen */
4178         return 0;
4179 }
4180
4181 static int i830_get_display_clock_speed(struct drm_device *dev)
4182 {
4183         return 133000;
4184 }
4185
4186 static void
4187 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4188 {
4189         while (*num > DATA_LINK_M_N_MASK ||
4190                *den > DATA_LINK_M_N_MASK) {
4191                 *num >>= 1;
4192                 *den >>= 1;
4193         }
4194 }
4195
4196 static void compute_m_n(unsigned int m, unsigned int n,
4197                         uint32_t *ret_m, uint32_t *ret_n)
4198 {
4199         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4200         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4201         intel_reduce_m_n_ratio(ret_m, ret_n);
4202 }
4203
4204 void
4205 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4206                        int pixel_clock, int link_clock,
4207                        struct intel_link_m_n *m_n)
4208 {
4209         m_n->tu = 64;
4210
4211         compute_m_n(bits_per_pixel * pixel_clock,
4212                     link_clock * nlanes * 8,
4213                     &m_n->gmch_m, &m_n->gmch_n);
4214
4215         compute_m_n(pixel_clock, link_clock,
4216                     &m_n->link_m, &m_n->link_n);
4217 }
4218
4219 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4220 {
4221         if (i915_panel_use_ssc >= 0)
4222                 return i915_panel_use_ssc != 0;
4223         return dev_priv->vbt.lvds_use_ssc
4224                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4225 }
4226
4227 static int vlv_get_refclk(struct drm_crtc *crtc)
4228 {
4229         struct drm_device *dev = crtc->dev;
4230         struct drm_i915_private *dev_priv = dev->dev_private;
4231         int refclk = 27000; /* for DP & HDMI */
4232
4233         return 100000; /* only one validated so far */
4234
4235         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4236                 refclk = 96000;
4237         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4238                 if (intel_panel_use_ssc(dev_priv))
4239                         refclk = 100000;
4240                 else
4241                         refclk = 96000;
4242         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4243                 refclk = 100000;
4244         }
4245
4246         return refclk;
4247 }
4248
4249 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4250 {
4251         struct drm_device *dev = crtc->dev;
4252         struct drm_i915_private *dev_priv = dev->dev_private;
4253         int refclk;
4254
4255         if (IS_VALLEYVIEW(dev)) {
4256                 refclk = vlv_get_refclk(crtc);
4257         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4258             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4259                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4260                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4261                               refclk / 1000);
4262         } else if (!IS_GEN2(dev)) {
4263                 refclk = 96000;
4264         } else {
4265                 refclk = 48000;
4266         }
4267
4268         return refclk;
4269 }
4270
4271 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4272 {
4273         return (1 << dpll->n) << 16 | dpll->m2;
4274 }
4275
4276 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4277 {
4278         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4279 }
4280
4281 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4282                                      intel_clock_t *reduced_clock)
4283 {
4284         struct drm_device *dev = crtc->base.dev;
4285         struct drm_i915_private *dev_priv = dev->dev_private;
4286         int pipe = crtc->pipe;
4287         u32 fp, fp2 = 0;
4288
4289         if (IS_PINEVIEW(dev)) {
4290                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4291                 if (reduced_clock)
4292                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4293         } else {
4294                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4295                 if (reduced_clock)
4296                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4297         }
4298
4299         I915_WRITE(FP0(pipe), fp);
4300
4301         crtc->lowfreq_avail = false;
4302         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4303             reduced_clock && i915_powersave) {
4304                 I915_WRITE(FP1(pipe), fp2);
4305                 crtc->lowfreq_avail = true;
4306         } else {
4307                 I915_WRITE(FP1(pipe), fp);
4308         }
4309 }
4310
4311 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4312 {
4313         u32 reg_val;
4314
4315         /*
4316          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4317          * and set it to a reasonable value instead.
4318          */
4319         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4320         reg_val &= 0xffffff00;
4321         reg_val |= 0x00000030;
4322         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4323
4324         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4325         reg_val &= 0x8cffffff;
4326         reg_val = 0x8c000000;
4327         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4328
4329         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4330         reg_val &= 0xffffff00;
4331         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4332
4333         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4334         reg_val &= 0x00ffffff;
4335         reg_val |= 0xb0000000;
4336         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4337 }
4338
4339 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4340                                          struct intel_link_m_n *m_n)
4341 {
4342         struct drm_device *dev = crtc->base.dev;
4343         struct drm_i915_private *dev_priv = dev->dev_private;
4344         int pipe = crtc->pipe;
4345
4346         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4347         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4348         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4349         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4350 }
4351
4352 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4353                                          struct intel_link_m_n *m_n)
4354 {
4355         struct drm_device *dev = crtc->base.dev;
4356         struct drm_i915_private *dev_priv = dev->dev_private;
4357         int pipe = crtc->pipe;
4358         enum transcoder transcoder = crtc->config.cpu_transcoder;
4359
4360         if (INTEL_INFO(dev)->gen >= 5) {
4361                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4362                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4363                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4364                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4365         } else {
4366                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4367                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4368                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4369                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4370         }
4371 }
4372
4373 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4374 {
4375         if (crtc->config.has_pch_encoder)
4376                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4377         else
4378                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4379 }
4380
4381 static void vlv_update_pll(struct intel_crtc *crtc)
4382 {
4383         struct drm_device *dev = crtc->base.dev;
4384         struct drm_i915_private *dev_priv = dev->dev_private;
4385         struct intel_encoder *encoder;
4386         int pipe = crtc->pipe;
4387         u32 dpll, mdiv;
4388         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4389         bool is_hdmi;
4390         u32 coreclk, reg_val, dpll_md;
4391
4392         mutex_lock(&dev_priv->dpio_lock);
4393
4394         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4395
4396         bestn = crtc->config.dpll.n;
4397         bestm1 = crtc->config.dpll.m1;
4398         bestm2 = crtc->config.dpll.m2;
4399         bestp1 = crtc->config.dpll.p1;
4400         bestp2 = crtc->config.dpll.p2;
4401
4402         /* See eDP HDMI DPIO driver vbios notes doc */
4403
4404         /* PLL B needs special handling */
4405         if (pipe)
4406                 vlv_pllb_recal_opamp(dev_priv);
4407
4408         /* Set up Tx target for periodic Rcomp update */
4409         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4410
4411         /* Disable target IRef on PLL */
4412         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4413         reg_val &= 0x00ffffff;
4414         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4415
4416         /* Disable fast lock */
4417         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4418
4419         /* Set idtafcrecal before PLL is enabled */
4420         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4421         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4422         mdiv |= ((bestn << DPIO_N_SHIFT));
4423         mdiv |= (1 << DPIO_K_SHIFT);
4424
4425         /*
4426          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4427          * but we don't support that).
4428          * Note: don't use the DAC post divider as it seems unstable.
4429          */
4430         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4431         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4432
4433         mdiv |= DPIO_ENABLE_CALIBRATION;
4434         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4435
4436         /* Set HBR and RBR LPF coefficients */
4437         if (crtc->config.port_clock == 162000 ||
4438             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4439             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4440                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4441                                  0x005f0021);
4442         else
4443                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4444                                  0x00d0000f);
4445
4446         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4447             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4448                 /* Use SSC source */
4449                 if (!pipe)
4450                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4451                                          0x0df40000);
4452                 else
4453                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4454                                          0x0df70000);
4455         } else { /* HDMI or VGA */
4456                 /* Use bend source */
4457                 if (!pipe)
4458                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4459                                          0x0df70000);
4460                 else
4461                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4462                                          0x0df40000);
4463         }
4464
4465         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4466         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4467         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4468             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4469                 coreclk |= 0x01000000;
4470         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4471
4472         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4473
4474         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4475                 if (encoder->pre_pll_enable)
4476                         encoder->pre_pll_enable(encoder);
4477
4478         /* Enable DPIO clock input */
4479         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4480                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4481         if (pipe)
4482                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4483
4484         dpll |= DPLL_VCO_ENABLE;
4485         I915_WRITE(DPLL(pipe), dpll);
4486         POSTING_READ(DPLL(pipe));
4487         udelay(150);
4488
4489         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4490                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4491
4492         dpll_md = (crtc->config.pixel_multiplier - 1)
4493                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4494         I915_WRITE(DPLL_MD(pipe), dpll_md);
4495         POSTING_READ(DPLL_MD(pipe));
4496
4497         if (crtc->config.has_dp_encoder)
4498                 intel_dp_set_m_n(crtc);
4499
4500         mutex_unlock(&dev_priv->dpio_lock);
4501 }
4502
4503 static void i9xx_update_pll(struct intel_crtc *crtc,
4504                             intel_clock_t *reduced_clock,
4505                             int num_connectors)
4506 {
4507         struct drm_device *dev = crtc->base.dev;
4508         struct drm_i915_private *dev_priv = dev->dev_private;
4509         struct intel_encoder *encoder;
4510         int pipe = crtc->pipe;
4511         u32 dpll;
4512         bool is_sdvo;
4513         struct dpll *clock = &crtc->config.dpll;
4514
4515         i9xx_update_pll_dividers(crtc, reduced_clock);
4516
4517         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4518                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4519
4520         dpll = DPLL_VGA_MODE_DIS;
4521
4522         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4523                 dpll |= DPLLB_MODE_LVDS;
4524         else
4525                 dpll |= DPLLB_MODE_DAC_SERIAL;
4526
4527         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4528                 dpll |= (crtc->config.pixel_multiplier - 1)
4529                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4530         }
4531
4532         if (is_sdvo)
4533                 dpll |= DPLL_DVO_HIGH_SPEED;
4534
4535         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4536                 dpll |= DPLL_DVO_HIGH_SPEED;
4537
4538         /* compute bitmask from p1 value */
4539         if (IS_PINEVIEW(dev))
4540                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4541         else {
4542                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4543                 if (IS_G4X(dev) && reduced_clock)
4544                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4545         }
4546         switch (clock->p2) {
4547         case 5:
4548                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4549                 break;
4550         case 7:
4551                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4552                 break;
4553         case 10:
4554                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4555                 break;
4556         case 14:
4557                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4558                 break;
4559         }
4560         if (INTEL_INFO(dev)->gen >= 4)
4561                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4562
4563         if (crtc->config.sdvo_tv_clock)
4564                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4565         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4566                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4567                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4568         else
4569                 dpll |= PLL_REF_INPUT_DREFCLK;
4570
4571         dpll |= DPLL_VCO_ENABLE;
4572         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4573         POSTING_READ(DPLL(pipe));
4574         udelay(150);
4575
4576         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4577                 if (encoder->pre_pll_enable)
4578                         encoder->pre_pll_enable(encoder);
4579
4580         if (crtc->config.has_dp_encoder)
4581                 intel_dp_set_m_n(crtc);
4582
4583         I915_WRITE(DPLL(pipe), dpll);
4584
4585         /* Wait for the clocks to stabilize. */
4586         POSTING_READ(DPLL(pipe));
4587         udelay(150);
4588
4589         if (INTEL_INFO(dev)->gen >= 4) {
4590                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4591                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4592                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4593         } else {
4594                 /* The pixel multiplier can only be updated once the
4595                  * DPLL is enabled and the clocks are stable.
4596                  *
4597                  * So write it again.
4598                  */
4599                 I915_WRITE(DPLL(pipe), dpll);
4600         }
4601 }
4602
4603 static void i8xx_update_pll(struct intel_crtc *crtc,
4604                             intel_clock_t *reduced_clock,
4605                             int num_connectors)
4606 {
4607         struct drm_device *dev = crtc->base.dev;
4608         struct drm_i915_private *dev_priv = dev->dev_private;
4609         struct intel_encoder *encoder;
4610         int pipe = crtc->pipe;
4611         u32 dpll;
4612         struct dpll *clock = &crtc->config.dpll;
4613
4614         i9xx_update_pll_dividers(crtc, reduced_clock);
4615
4616         dpll = DPLL_VGA_MODE_DIS;
4617
4618         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4619                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4620         } else {
4621                 if (clock->p1 == 2)
4622                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4623                 else
4624                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4625                 if (clock->p2 == 4)
4626                         dpll |= PLL_P2_DIVIDE_BY_4;
4627         }
4628
4629         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4630                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4631                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4632         else
4633                 dpll |= PLL_REF_INPUT_DREFCLK;
4634
4635         dpll |= DPLL_VCO_ENABLE;
4636         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4637         POSTING_READ(DPLL(pipe));
4638         udelay(150);
4639
4640         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4641                 if (encoder->pre_pll_enable)
4642                         encoder->pre_pll_enable(encoder);
4643
4644         I915_WRITE(DPLL(pipe), dpll);
4645
4646         /* Wait for the clocks to stabilize. */
4647         POSTING_READ(DPLL(pipe));
4648         udelay(150);
4649
4650         /* The pixel multiplier can only be updated once the
4651          * DPLL is enabled and the clocks are stable.
4652          *
4653          * So write it again.
4654          */
4655         I915_WRITE(DPLL(pipe), dpll);
4656 }
4657
4658 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4659 {
4660         struct drm_device *dev = intel_crtc->base.dev;
4661         struct drm_i915_private *dev_priv = dev->dev_private;
4662         enum i915_pipe pipe = intel_crtc->pipe;
4663         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4664         struct drm_display_mode *adjusted_mode =
4665                 &intel_crtc->config.adjusted_mode;
4666         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4667         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4668
4669         /* We need to be careful not to changed the adjusted mode, for otherwise
4670          * the hw state checker will get angry at the mismatch. */
4671         crtc_vtotal = adjusted_mode->crtc_vtotal;
4672         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4673
4674         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4675                 /* the chip adds 2 halflines automatically */
4676                 crtc_vtotal -= 1;
4677                 crtc_vblank_end -= 1;
4678                 vsyncshift = adjusted_mode->crtc_hsync_start
4679                              - adjusted_mode->crtc_htotal / 2;
4680         } else {
4681                 vsyncshift = 0;
4682         }
4683
4684         if (INTEL_INFO(dev)->gen > 3)
4685                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4686
4687         I915_WRITE(HTOTAL(cpu_transcoder),
4688                    (adjusted_mode->crtc_hdisplay - 1) |
4689                    ((adjusted_mode->crtc_htotal - 1) << 16));
4690         I915_WRITE(HBLANK(cpu_transcoder),
4691                    (adjusted_mode->crtc_hblank_start - 1) |
4692                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4693         I915_WRITE(HSYNC(cpu_transcoder),
4694                    (adjusted_mode->crtc_hsync_start - 1) |
4695                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4696
4697         I915_WRITE(VTOTAL(cpu_transcoder),
4698                    (adjusted_mode->crtc_vdisplay - 1) |
4699                    ((crtc_vtotal - 1) << 16));
4700         I915_WRITE(VBLANK(cpu_transcoder),
4701                    (adjusted_mode->crtc_vblank_start - 1) |
4702                    ((crtc_vblank_end - 1) << 16));
4703         I915_WRITE(VSYNC(cpu_transcoder),
4704                    (adjusted_mode->crtc_vsync_start - 1) |
4705                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4706
4707         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4708          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4709          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4710          * bits. */
4711         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4712             (pipe == PIPE_B || pipe == PIPE_C))
4713                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4714
4715         /* pipesrc controls the size that is scaled from, which should
4716          * always be the user's requested size.
4717          */
4718         I915_WRITE(PIPESRC(pipe),
4719                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4720 }
4721
4722 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4723                                    struct intel_crtc_config *pipe_config)
4724 {
4725         struct drm_device *dev = crtc->base.dev;
4726         struct drm_i915_private *dev_priv = dev->dev_private;
4727         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4728         uint32_t tmp;
4729
4730         tmp = I915_READ(HTOTAL(cpu_transcoder));
4731         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4732         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4733         tmp = I915_READ(HBLANK(cpu_transcoder));
4734         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4735         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4736         tmp = I915_READ(HSYNC(cpu_transcoder));
4737         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4738         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4739
4740         tmp = I915_READ(VTOTAL(cpu_transcoder));
4741         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4742         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4743         tmp = I915_READ(VBLANK(cpu_transcoder));
4744         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4745         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4746         tmp = I915_READ(VSYNC(cpu_transcoder));
4747         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4748         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4749
4750         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4751                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4752                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4753                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4754         }
4755
4756         tmp = I915_READ(PIPESRC(crtc->pipe));
4757         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4758         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4759 }
4760
4761 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4762 {
4763         struct drm_device *dev = intel_crtc->base.dev;
4764         struct drm_i915_private *dev_priv = dev->dev_private;
4765         uint32_t pipeconf;
4766
4767         pipeconf = 0;
4768
4769         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4770                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4771                  * core speed.
4772                  *
4773                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4774                  * pipe == 0 check?
4775                  */
4776                 if (intel_crtc->config.requested_mode.clock >
4777                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4778                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4779         }
4780
4781         /* only g4x and later have fancy bpc/dither controls */
4782         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4783                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4784                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4785                         pipeconf |= PIPECONF_DITHER_EN |
4786                                     PIPECONF_DITHER_TYPE_SP;
4787
4788                 switch (intel_crtc->config.pipe_bpp) {
4789                 case 18:
4790                         pipeconf |= PIPECONF_6BPC;
4791                         break;
4792                 case 24:
4793                         pipeconf |= PIPECONF_8BPC;
4794                         break;
4795                 case 30:
4796                         pipeconf |= PIPECONF_10BPC;
4797                         break;
4798                 default:
4799                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4800                         BUG();
4801                 }
4802         }
4803
4804         if (HAS_PIPE_CXSR(dev)) {
4805                 if (intel_crtc->lowfreq_avail) {
4806                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4807                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4808                 } else {
4809                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4810                 }
4811         }
4812
4813         if (!IS_GEN2(dev) &&
4814             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4815                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4816         else
4817                 pipeconf |= PIPECONF_PROGRESSIVE;
4818
4819         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4820                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4821
4822         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4823         POSTING_READ(PIPECONF(intel_crtc->pipe));
4824 }
4825
4826 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4827                               int x, int y,
4828                               struct drm_framebuffer *fb)
4829 {
4830         struct drm_device *dev = crtc->dev;
4831         struct drm_i915_private *dev_priv = dev->dev_private;
4832         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4833         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4834         int pipe = intel_crtc->pipe;
4835         int plane = intel_crtc->plane;
4836         int refclk, num_connectors = 0;
4837         intel_clock_t clock, reduced_clock;
4838         u32 dspcntr;
4839         bool ok, has_reduced_clock = false;
4840         bool is_lvds = false;
4841         struct intel_encoder *encoder;
4842         const intel_limit_t *limit;
4843         int ret;
4844
4845         for_each_encoder_on_crtc(dev, crtc, encoder) {
4846                 switch (encoder->type) {
4847                 case INTEL_OUTPUT_LVDS:
4848                         is_lvds = true;
4849                         break;
4850                 }
4851
4852                 num_connectors++;
4853         }
4854
4855         refclk = i9xx_get_refclk(crtc, num_connectors);
4856
4857         /*
4858          * Returns a set of divisors for the desired target clock with the given
4859          * refclk, or FALSE.  The returned values represent the clock equation:
4860          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4861          */
4862         limit = intel_limit(crtc, refclk);
4863         ok = dev_priv->display.find_dpll(limit, crtc,
4864                                          intel_crtc->config.port_clock,
4865                                          refclk, NULL, &clock);
4866         if (!ok && !intel_crtc->config.clock_set) {
4867                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4868                 return -EINVAL;
4869         }
4870
4871         /* Ensure that the cursor is valid for the new mode before changing... */
4872         intel_crtc_update_cursor(crtc, true);
4873
4874         if (is_lvds && dev_priv->lvds_downclock_avail) {
4875                 /*
4876                  * Ensure we match the reduced clock's P to the target clock.
4877                  * If the clocks don't match, we can't switch the display clock
4878                  * by using the FP0/FP1. In such case we will disable the LVDS
4879                  * downclock feature.
4880                 */
4881                 has_reduced_clock =
4882                         dev_priv->display.find_dpll(limit, crtc,
4883                                                     dev_priv->lvds_downclock,
4884                                                     refclk, &clock,
4885                                                     &reduced_clock);
4886         }
4887         /* Compat-code for transition, will disappear. */
4888         if (!intel_crtc->config.clock_set) {
4889                 intel_crtc->config.dpll.n = clock.n;
4890                 intel_crtc->config.dpll.m1 = clock.m1;
4891                 intel_crtc->config.dpll.m2 = clock.m2;
4892                 intel_crtc->config.dpll.p1 = clock.p1;
4893                 intel_crtc->config.dpll.p2 = clock.p2;
4894         }
4895
4896         if (IS_GEN2(dev))
4897                 i8xx_update_pll(intel_crtc,
4898                                 has_reduced_clock ? &reduced_clock : NULL,
4899                                 num_connectors);
4900         else if (IS_VALLEYVIEW(dev))
4901                 vlv_update_pll(intel_crtc);
4902         else
4903                 i9xx_update_pll(intel_crtc,
4904                                 has_reduced_clock ? &reduced_clock : NULL,
4905                                 num_connectors);
4906
4907         /* Set up the display plane register */
4908         dspcntr = DISPPLANE_GAMMA_ENABLE;
4909
4910         if (!IS_VALLEYVIEW(dev)) {
4911                 if (pipe == 0)
4912                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4913                 else
4914                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4915         }
4916
4917         intel_set_pipe_timings(intel_crtc);
4918
4919         /* pipesrc and dspsize control the size that is scaled from,
4920          * which should always be the user's requested size.
4921          */
4922         I915_WRITE(DSPSIZE(plane),
4923                    ((mode->vdisplay - 1) << 16) |
4924                    (mode->hdisplay - 1));
4925         I915_WRITE(DSPPOS(plane), 0);
4926
4927         i9xx_set_pipeconf(intel_crtc);
4928
4929         I915_WRITE(DSPCNTR(plane), dspcntr);
4930         POSTING_READ(DSPCNTR(plane));
4931
4932         ret = intel_pipe_set_base(crtc, x, y, fb);
4933
4934         intel_update_watermarks(dev);
4935
4936         return ret;
4937 }
4938
4939 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4940                                  struct intel_crtc_config *pipe_config)
4941 {
4942         struct drm_device *dev = crtc->base.dev;
4943         struct drm_i915_private *dev_priv = dev->dev_private;
4944         uint32_t tmp;
4945
4946         tmp = I915_READ(PFIT_CONTROL);
4947         if (!(tmp & PFIT_ENABLE))
4948                 return;
4949
4950         /* Check whether the pfit is attached to our pipe. */
4951         if (INTEL_INFO(dev)->gen < 4) {
4952                 if (crtc->pipe != PIPE_B)
4953                         return;
4954         } else {
4955                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4956                         return;
4957         }
4958
4959         pipe_config->gmch_pfit.control = tmp;
4960         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4961         if (INTEL_INFO(dev)->gen < 5)
4962                 pipe_config->gmch_pfit.lvds_border_bits =
4963                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4964 }
4965
4966 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4967                                  struct intel_crtc_config *pipe_config)
4968 {
4969         struct drm_device *dev = crtc->base.dev;
4970         struct drm_i915_private *dev_priv = dev->dev_private;
4971         uint32_t tmp;
4972
4973         pipe_config->cpu_transcoder = crtc->pipe;
4974         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4975
4976         tmp = I915_READ(PIPECONF(crtc->pipe));
4977         if (!(tmp & PIPECONF_ENABLE))
4978                 return false;
4979
4980         intel_get_pipe_timings(crtc, pipe_config);
4981
4982         i9xx_get_pfit_config(crtc, pipe_config);
4983
4984         if (INTEL_INFO(dev)->gen >= 4) {
4985                 tmp = I915_READ(DPLL_MD(crtc->pipe));
4986                 pipe_config->pixel_multiplier =
4987                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4988                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4989         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4990                 tmp = I915_READ(DPLL(crtc->pipe));
4991                 pipe_config->pixel_multiplier =
4992                         ((tmp & SDVO_MULTIPLIER_MASK)
4993                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4994         } else {
4995                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4996                  * port and will be fixed up in the encoder->get_config
4997                  * function. */
4998                 pipe_config->pixel_multiplier = 1;
4999         }
5000
5001         return true;
5002 }
5003
5004 static void ironlake_init_pch_refclk(struct drm_device *dev)
5005 {
5006         struct drm_i915_private *dev_priv = dev->dev_private;
5007         struct drm_mode_config *mode_config = &dev->mode_config;
5008         struct intel_encoder *encoder;
5009         u32 val, final;
5010         bool has_lvds = false;
5011         bool has_cpu_edp = false;
5012         bool has_panel = false;
5013         bool has_ck505 = false;
5014         bool can_ssc = false;
5015
5016         /* We need to take the global config into account */
5017         list_for_each_entry(encoder, &mode_config->encoder_list,
5018                             base.head) {
5019                 switch (encoder->type) {
5020                 case INTEL_OUTPUT_LVDS:
5021                         has_panel = true;
5022                         has_lvds = true;
5023                         break;
5024                 case INTEL_OUTPUT_EDP:
5025                         has_panel = true;
5026                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5027                                 has_cpu_edp = true;
5028                         break;
5029                 }
5030         }
5031
5032         if (HAS_PCH_IBX(dev)) {
5033                 has_ck505 = dev_priv->vbt.display_clock_mode;
5034                 can_ssc = has_ck505;
5035         } else {
5036                 has_ck505 = false;
5037                 can_ssc = true;
5038         }
5039
5040         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5041                       has_panel, has_lvds, has_ck505);
5042
5043         /* Ironlake: try to setup display ref clock before DPLL
5044          * enabling. This is only under driver's control after
5045          * PCH B stepping, previous chipset stepping should be
5046          * ignoring this setting.
5047          */
5048         val = I915_READ(PCH_DREF_CONTROL);
5049
5050         /* As we must carefully and slowly disable/enable each source in turn,
5051          * compute the final state we want first and check if we need to
5052          * make any changes at all.
5053          */
5054         final = val;
5055         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5056         if (has_ck505)
5057                 final |= DREF_NONSPREAD_CK505_ENABLE;
5058         else
5059                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5060
5061         final &= ~DREF_SSC_SOURCE_MASK;
5062         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5063         final &= ~DREF_SSC1_ENABLE;
5064
5065         if (has_panel) {
5066                 final |= DREF_SSC_SOURCE_ENABLE;
5067
5068                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5069                         final |= DREF_SSC1_ENABLE;
5070
5071                 if (has_cpu_edp) {
5072                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5073                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5074                         else
5075                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5076                 } else
5077                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5078         } else {
5079                 final |= DREF_SSC_SOURCE_DISABLE;
5080                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5081         }
5082
5083         if (final == val)
5084                 return;
5085
5086         /* Always enable nonspread source */
5087         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5088
5089         if (has_ck505)
5090                 val |= DREF_NONSPREAD_CK505_ENABLE;
5091         else
5092                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5093
5094         if (has_panel) {
5095                 val &= ~DREF_SSC_SOURCE_MASK;
5096                 val |= DREF_SSC_SOURCE_ENABLE;
5097
5098                 /* SSC must be turned on before enabling the CPU output  */
5099                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5100                         DRM_DEBUG_KMS("Using SSC on panel\n");
5101                         val |= DREF_SSC1_ENABLE;
5102                 } else
5103                         val &= ~DREF_SSC1_ENABLE;
5104
5105                 /* Get SSC going before enabling the outputs */
5106                 I915_WRITE(PCH_DREF_CONTROL, val);
5107                 POSTING_READ(PCH_DREF_CONTROL);
5108                 udelay(200);
5109
5110                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5111
5112                 /* Enable CPU source on CPU attached eDP */
5113                 if (has_cpu_edp) {
5114                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5115                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5116                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5117                         }
5118                         else
5119                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5120                 } else
5121                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5122
5123                 I915_WRITE(PCH_DREF_CONTROL, val);
5124                 POSTING_READ(PCH_DREF_CONTROL);
5125                 udelay(200);
5126         } else {
5127                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5128
5129                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5130
5131                 /* Turn off CPU output */
5132                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5133
5134                 I915_WRITE(PCH_DREF_CONTROL, val);
5135                 POSTING_READ(PCH_DREF_CONTROL);
5136                 udelay(200);
5137
5138                 /* Turn off the SSC source */
5139                 val &= ~DREF_SSC_SOURCE_MASK;
5140                 val |= DREF_SSC_SOURCE_DISABLE;
5141
5142                 /* Turn off SSC1 */
5143                 val &= ~DREF_SSC1_ENABLE;
5144
5145                 I915_WRITE(PCH_DREF_CONTROL, val);
5146                 POSTING_READ(PCH_DREF_CONTROL);
5147                 udelay(200);
5148         }
5149
5150         BUG_ON(val != final);
5151 }
5152
5153 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5154 static void lpt_init_pch_refclk(struct drm_device *dev)
5155 {
5156         struct drm_i915_private *dev_priv = dev->dev_private;
5157         struct drm_mode_config *mode_config = &dev->mode_config;
5158         struct intel_encoder *encoder;
5159         bool has_vga = false;
5160         bool is_sdv = false;
5161         u32 tmp;
5162
5163         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5164                 switch (encoder->type) {
5165                 case INTEL_OUTPUT_ANALOG:
5166                         has_vga = true;
5167                         break;
5168                 }
5169         }
5170
5171         if (!has_vga)
5172                 return;
5173
5174         mutex_lock(&dev_priv->dpio_lock);
5175
5176         /* XXX: Rip out SDV support once Haswell ships for real. */
5177         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5178                 is_sdv = true;
5179
5180         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5181         tmp &= ~SBI_SSCCTL_DISABLE;
5182         tmp |= SBI_SSCCTL_PATHALT;
5183         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5184
5185         udelay(24);
5186
5187         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5188         tmp &= ~SBI_SSCCTL_PATHALT;
5189         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5190
5191         if (!is_sdv) {
5192                 tmp = I915_READ(SOUTH_CHICKEN2);
5193                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5194                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5195
5196                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5197                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5198                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5199
5200                 tmp = I915_READ(SOUTH_CHICKEN2);
5201                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5202                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5203
5204                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5205                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5206                                        100))
5207                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5208         }
5209
5210         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5211         tmp &= ~(0xFF << 24);
5212         tmp |= (0x12 << 24);
5213         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5214
5215         if (is_sdv) {
5216                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5217                 tmp |= 0x7FFF;
5218                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5219         }
5220
5221         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5222         tmp |= (1 << 11);
5223         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5224
5225         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5226         tmp |= (1 << 11);
5227         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5228
5229         if (is_sdv) {
5230                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5231                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5232                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5233
5234                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5235                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5236                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5237
5238                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5239                 tmp |= (0x3F << 8);
5240                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5241
5242                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5243                 tmp |= (0x3F << 8);
5244                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5245         }
5246
5247         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5248         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5249         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5250
5251         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5252         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5253         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5254
5255         if (!is_sdv) {
5256                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5257                 tmp &= ~(7 << 13);
5258                 tmp |= (5 << 13);
5259                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5260
5261                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5262                 tmp &= ~(7 << 13);
5263                 tmp |= (5 << 13);
5264                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5265         }
5266
5267         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5268         tmp &= ~0xFF;
5269         tmp |= 0x1C;
5270         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5271
5272         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5273         tmp &= ~0xFF;
5274         tmp |= 0x1C;
5275         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5276
5277         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5278         tmp &= ~(0xFF << 16);
5279         tmp |= (0x1C << 16);
5280         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5281
5282         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5283         tmp &= ~(0xFF << 16);
5284         tmp |= (0x1C << 16);
5285         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5286
5287         if (!is_sdv) {
5288                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5289                 tmp |= (1 << 27);
5290                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5291
5292                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5293                 tmp |= (1 << 27);
5294                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5295
5296                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5297                 tmp &= ~(0xF << 28);
5298                 tmp |= (4 << 28);
5299                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5300
5301                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5302                 tmp &= ~(0xF << 28);
5303                 tmp |= (4 << 28);
5304                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5305         }
5306
5307         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5308         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5309         tmp |= SBI_DBUFF0_ENABLE;
5310         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5311
5312         mutex_unlock(&dev_priv->dpio_lock);
5313 }
5314
5315 /*
5316  * Initialize reference clocks when the driver loads
5317  */
5318 void intel_init_pch_refclk(struct drm_device *dev)
5319 {
5320         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5321                 ironlake_init_pch_refclk(dev);
5322         else if (HAS_PCH_LPT(dev))
5323                 lpt_init_pch_refclk(dev);
5324 }
5325
5326 static int ironlake_get_refclk(struct drm_crtc *crtc)
5327 {
5328         struct drm_device *dev = crtc->dev;
5329         struct drm_i915_private *dev_priv = dev->dev_private;
5330         struct intel_encoder *encoder;
5331         int num_connectors = 0;
5332         bool is_lvds = false;
5333
5334         for_each_encoder_on_crtc(dev, crtc, encoder) {
5335                 switch (encoder->type) {
5336                 case INTEL_OUTPUT_LVDS:
5337                         is_lvds = true;
5338                         break;
5339                 }
5340                 num_connectors++;
5341         }
5342
5343         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5344                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5345                               dev_priv->vbt.lvds_ssc_freq);
5346                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5347         }
5348
5349         return 120000;
5350 }
5351
5352 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5353 {
5354         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5356         int pipe = intel_crtc->pipe;
5357         uint32_t val;
5358
5359         val = 0;
5360
5361         switch (intel_crtc->config.pipe_bpp) {
5362         case 18:
5363                 val |= PIPECONF_6BPC;
5364                 break;
5365         case 24:
5366                 val |= PIPECONF_8BPC;
5367                 break;
5368         case 30:
5369                 val |= PIPECONF_10BPC;
5370                 break;
5371         case 36:
5372                 val |= PIPECONF_12BPC;
5373                 break;
5374         default:
5375                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5376                 BUG();
5377         }
5378
5379         if (intel_crtc->config.dither)
5380                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5381
5382         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5383                 val |= PIPECONF_INTERLACED_ILK;
5384         else
5385                 val |= PIPECONF_PROGRESSIVE;
5386
5387         if (intel_crtc->config.limited_color_range)
5388                 val |= PIPECONF_COLOR_RANGE_SELECT;
5389
5390         I915_WRITE(PIPECONF(pipe), val);
5391         POSTING_READ(PIPECONF(pipe));
5392 }
5393
5394 /*
5395  * Set up the pipe CSC unit.
5396  *
5397  * Currently only full range RGB to limited range RGB conversion
5398  * is supported, but eventually this should handle various
5399  * RGB<->YCbCr scenarios as well.
5400  */
5401 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5402 {
5403         struct drm_device *dev = crtc->dev;
5404         struct drm_i915_private *dev_priv = dev->dev_private;
5405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5406         int pipe = intel_crtc->pipe;
5407         uint16_t coeff = 0x7800; /* 1.0 */
5408
5409         /*
5410          * TODO: Check what kind of values actually come out of the pipe
5411          * with these coeff/postoff values and adjust to get the best
5412          * accuracy. Perhaps we even need to take the bpc value into
5413          * consideration.
5414          */
5415
5416         if (intel_crtc->config.limited_color_range)
5417                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5418
5419         /*
5420          * GY/GU and RY/RU should be the other way around according
5421          * to BSpec, but reality doesn't agree. Just set them up in
5422          * a way that results in the correct picture.
5423          */
5424         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5425         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5426
5427         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5428         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5429
5430         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5431         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5432
5433         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5434         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5435         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5436
5437         if (INTEL_INFO(dev)->gen > 6) {
5438                 uint16_t postoff = 0;
5439
5440                 if (intel_crtc->config.limited_color_range)
5441                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5442
5443                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5444                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5445                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5446
5447                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5448         } else {
5449                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5450
5451                 if (intel_crtc->config.limited_color_range)
5452                         mode |= CSC_BLACK_SCREEN_OFFSET;
5453
5454                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5455         }
5456 }
5457
5458 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5459 {
5460         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5461         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5462         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5463         uint32_t val;
5464
5465         val = 0;
5466
5467         if (intel_crtc->config.dither)
5468                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5469
5470         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5471                 val |= PIPECONF_INTERLACED_ILK;
5472         else
5473                 val |= PIPECONF_PROGRESSIVE;
5474
5475         I915_WRITE(PIPECONF(cpu_transcoder), val);
5476         POSTING_READ(PIPECONF(cpu_transcoder));
5477
5478         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5479         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5480 }
5481
5482 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5483                                     intel_clock_t *clock,
5484                                     bool *has_reduced_clock,
5485                                     intel_clock_t *reduced_clock)
5486 {
5487         struct drm_device *dev = crtc->dev;
5488         struct drm_i915_private *dev_priv = dev->dev_private;
5489         struct intel_encoder *intel_encoder;
5490         int refclk;
5491         const intel_limit_t *limit;
5492         bool ret, is_lvds = false;
5493
5494         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5495                 switch (intel_encoder->type) {
5496                 case INTEL_OUTPUT_LVDS:
5497                         is_lvds = true;
5498                         break;
5499                 }
5500         }
5501
5502         refclk = ironlake_get_refclk(crtc);
5503
5504         /*
5505          * Returns a set of divisors for the desired target clock with the given
5506          * refclk, or FALSE.  The returned values represent the clock equation:
5507          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5508          */
5509         limit = intel_limit(crtc, refclk);
5510         ret = dev_priv->display.find_dpll(limit, crtc,
5511                                           to_intel_crtc(crtc)->config.port_clock,
5512                                           refclk, NULL, clock);
5513         if (!ret)
5514                 return false;
5515
5516         if (is_lvds && dev_priv->lvds_downclock_avail) {
5517                 /*
5518                  * Ensure we match the reduced clock's P to the target clock.
5519                  * If the clocks don't match, we can't switch the display clock
5520                  * by using the FP0/FP1. In such case we will disable the LVDS
5521                  * downclock feature.
5522                 */
5523                 *has_reduced_clock =
5524                         dev_priv->display.find_dpll(limit, crtc,
5525                                                     dev_priv->lvds_downclock,
5526                                                     refclk, clock,
5527                                                     reduced_clock);
5528         }
5529
5530         return true;
5531 }
5532
5533 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5534 {
5535         struct drm_i915_private *dev_priv = dev->dev_private;
5536         uint32_t temp;
5537
5538         temp = I915_READ(SOUTH_CHICKEN1);
5539         if (temp & FDI_BC_BIFURCATION_SELECT)
5540                 return;
5541
5542         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5543         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5544
5545         temp |= FDI_BC_BIFURCATION_SELECT;
5546         DRM_DEBUG_KMS("enabling fdi C rx\n");
5547         I915_WRITE(SOUTH_CHICKEN1, temp);
5548         POSTING_READ(SOUTH_CHICKEN1);
5549 }
5550
5551 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5552 {
5553         struct drm_device *dev = intel_crtc->base.dev;
5554         struct drm_i915_private *dev_priv = dev->dev_private;
5555
5556         switch (intel_crtc->pipe) {
5557         case PIPE_A:
5558                 break;
5559         case PIPE_B:
5560                 if (intel_crtc->config.fdi_lanes > 2)
5561                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5562                 else
5563                         cpt_enable_fdi_bc_bifurcation(dev);
5564
5565                 break;
5566         case PIPE_C:
5567                 cpt_enable_fdi_bc_bifurcation(dev);
5568
5569                 break;
5570         default:
5571                 BUG();
5572         }
5573 }
5574
5575 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5576 {
5577         /*
5578          * Account for spread spectrum to avoid
5579          * oversubscribing the link. Max center spread
5580          * is 2.5%; use 5% for safety's sake.
5581          */
5582         u32 bps = target_clock * bpp * 21 / 20;
5583         return bps / (link_bw * 8) + 1;
5584 }
5585
5586 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5587 {
5588         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5589 }
5590
5591 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5592                                       u32 *fp,
5593                                       intel_clock_t *reduced_clock, u32 *fp2)
5594 {
5595         struct drm_crtc *crtc = &intel_crtc->base;
5596         struct drm_device *dev = crtc->dev;
5597         struct drm_i915_private *dev_priv = dev->dev_private;
5598         struct intel_encoder *intel_encoder;
5599         uint32_t dpll;
5600         int factor, num_connectors = 0;
5601         bool is_lvds = false, is_sdvo = false;
5602
5603         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5604                 switch (intel_encoder->type) {
5605                 case INTEL_OUTPUT_LVDS:
5606                         is_lvds = true;
5607                         break;
5608                 case INTEL_OUTPUT_SDVO:
5609                 case INTEL_OUTPUT_HDMI:
5610                         is_sdvo = true;
5611                         break;
5612                 }
5613
5614                 num_connectors++;
5615         }
5616
5617         /* Enable autotuning of the PLL clock (if permissible) */
5618         factor = 21;
5619         if (is_lvds) {
5620                 if ((intel_panel_use_ssc(dev_priv) &&
5621                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5622                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5623                         factor = 25;
5624         } else if (intel_crtc->config.sdvo_tv_clock)
5625                 factor = 20;
5626
5627         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5628                 *fp |= FP_CB_TUNE;
5629
5630         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5631                 *fp2 |= FP_CB_TUNE;
5632
5633         dpll = 0;
5634
5635         if (is_lvds)
5636                 dpll |= DPLLB_MODE_LVDS;
5637         else
5638                 dpll |= DPLLB_MODE_DAC_SERIAL;
5639
5640         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5641                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5642
5643         if (is_sdvo)
5644                 dpll |= DPLL_DVO_HIGH_SPEED;
5645         if (intel_crtc->config.has_dp_encoder)
5646                 dpll |= DPLL_DVO_HIGH_SPEED;
5647
5648         /* compute bitmask from p1 value */
5649         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5650         /* also FPA1 */
5651         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5652
5653         switch (intel_crtc->config.dpll.p2) {
5654         case 5:
5655                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5656                 break;
5657         case 7:
5658                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5659                 break;
5660         case 10:
5661                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5662                 break;
5663         case 14:
5664                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5665                 break;
5666         }
5667
5668         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5669                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5670         else
5671                 dpll |= PLL_REF_INPUT_DREFCLK;
5672
5673         return dpll | DPLL_VCO_ENABLE;
5674 }
5675
5676 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5677                                   int x, int y,
5678                                   struct drm_framebuffer *fb)
5679 {
5680         struct drm_device *dev = crtc->dev;
5681         struct drm_i915_private *dev_priv = dev->dev_private;
5682         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5683         int pipe = intel_crtc->pipe;
5684         int plane = intel_crtc->plane;
5685         int num_connectors = 0;
5686         intel_clock_t clock, reduced_clock;
5687         u32 dpll = 0, fp = 0, fp2 = 0;
5688         bool ok, has_reduced_clock = false;
5689         bool is_lvds = false;
5690         struct intel_encoder *encoder;
5691         struct intel_shared_dpll *pll;
5692         int ret;
5693
5694         for_each_encoder_on_crtc(dev, crtc, encoder) {
5695                 switch (encoder->type) {
5696                 case INTEL_OUTPUT_LVDS:
5697                         is_lvds = true;
5698                         break;
5699                 }
5700
5701                 num_connectors++;
5702         }
5703
5704         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5705              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5706
5707         ok = ironlake_compute_clocks(crtc, &clock,
5708                                      &has_reduced_clock, &reduced_clock);
5709         if (!ok && !intel_crtc->config.clock_set) {
5710                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5711                 return -EINVAL;
5712         }
5713         /* Compat-code for transition, will disappear. */
5714         if (!intel_crtc->config.clock_set) {
5715                 intel_crtc->config.dpll.n = clock.n;
5716                 intel_crtc->config.dpll.m1 = clock.m1;
5717                 intel_crtc->config.dpll.m2 = clock.m2;
5718                 intel_crtc->config.dpll.p1 = clock.p1;
5719                 intel_crtc->config.dpll.p2 = clock.p2;
5720         }
5721
5722         /* Ensure that the cursor is valid for the new mode before changing... */
5723         intel_crtc_update_cursor(crtc, true);
5724
5725         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5726         if (intel_crtc->config.has_pch_encoder) {
5727                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5728                 if (has_reduced_clock)
5729                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5730
5731                 dpll = ironlake_compute_dpll(intel_crtc,
5732                                              &fp, &reduced_clock,
5733                                              has_reduced_clock ? &fp2 : NULL);
5734
5735                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5736                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5737                 if (has_reduced_clock)
5738                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5739                 else
5740                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5741
5742                 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
5743                 if (pll == NULL) {
5744                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5745                                          pipe_name(pipe));
5746                         return -EINVAL;
5747                 }
5748         } else
5749                 intel_put_shared_dpll(intel_crtc);
5750
5751         if (intel_crtc->config.has_dp_encoder)
5752                 intel_dp_set_m_n(intel_crtc);
5753
5754         for_each_encoder_on_crtc(dev, crtc, encoder)
5755                 if (encoder->pre_pll_enable)
5756                         encoder->pre_pll_enable(encoder);
5757
5758         if (is_lvds && has_reduced_clock && i915_powersave)
5759                 intel_crtc->lowfreq_avail = true;
5760         else
5761                 intel_crtc->lowfreq_avail = false;
5762
5763         if (intel_crtc->config.has_pch_encoder) {
5764                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5765
5766                 I915_WRITE(PCH_DPLL(pll->id), dpll);
5767
5768                 /* Wait for the clocks to stabilize. */
5769                 POSTING_READ(PCH_DPLL(pll->id));
5770                 udelay(150);
5771
5772                 /* The pixel multiplier can only be updated once the
5773                  * DPLL is enabled and the clocks are stable.
5774                  *
5775                  * So write it again.
5776                  */
5777                 I915_WRITE(PCH_DPLL(pll->id), dpll);
5778
5779                 if (has_reduced_clock)
5780                         I915_WRITE(PCH_FP1(pll->id), fp2);
5781                 else
5782                         I915_WRITE(PCH_FP1(pll->id), fp);
5783         }
5784
5785         intel_set_pipe_timings(intel_crtc);
5786
5787         if (intel_crtc->config.has_pch_encoder) {
5788                 intel_cpu_transcoder_set_m_n(intel_crtc,
5789                                              &intel_crtc->config.fdi_m_n);
5790         }
5791
5792         if (IS_IVYBRIDGE(dev))
5793                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5794
5795         ironlake_set_pipeconf(crtc);
5796
5797         /* Set up the display plane register */
5798         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5799         POSTING_READ(DSPCNTR(plane));
5800
5801         ret = intel_pipe_set_base(crtc, x, y, fb);
5802
5803         intel_update_watermarks(dev);
5804
5805         return ret;
5806 }
5807
5808 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5809                                         struct intel_crtc_config *pipe_config)
5810 {
5811         struct drm_device *dev = crtc->base.dev;
5812         struct drm_i915_private *dev_priv = dev->dev_private;
5813         enum transcoder transcoder = pipe_config->cpu_transcoder;
5814
5815         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5816         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5817         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5818                                         & ~TU_SIZE_MASK;
5819         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5820         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5821                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5822 }
5823
5824 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5825                                      struct intel_crtc_config *pipe_config)
5826 {
5827         struct drm_device *dev = crtc->base.dev;
5828         struct drm_i915_private *dev_priv = dev->dev_private;
5829         uint32_t tmp;
5830
5831         tmp = I915_READ(PF_CTL(crtc->pipe));
5832
5833         if (tmp & PF_ENABLE) {
5834                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5835                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5836
5837                 /* We currently do not free assignements of panel fitters on
5838                  * ivb/hsw (since we don't use the higher upscaling modes which
5839                  * differentiates them) so just WARN about this case for now. */
5840                 if (IS_GEN7(dev)) {
5841                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5842                                 PF_PIPE_SEL_IVB(crtc->pipe));
5843                 }
5844         }
5845 }
5846
5847 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5848                                      struct intel_crtc_config *pipe_config)
5849 {
5850         struct drm_device *dev = crtc->base.dev;
5851         struct drm_i915_private *dev_priv = dev->dev_private;
5852         uint32_t tmp;
5853
5854         pipe_config->cpu_transcoder = crtc->pipe;
5855         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5856
5857         tmp = I915_READ(PIPECONF(crtc->pipe));
5858         if (!(tmp & PIPECONF_ENABLE))
5859                 return false;
5860
5861         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5862                 struct intel_shared_dpll *pll;
5863
5864                 pipe_config->has_pch_encoder = true;
5865
5866                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5867                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5868                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5869
5870                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5871
5872                 /* XXX: Can't properly read out the pch dpll pixel multiplier
5873                  * since we don't have state tracking for pch clocks yet. */
5874                 pipe_config->pixel_multiplier = 1;
5875
5876                 if (HAS_PCH_IBX(dev_priv->dev)) {
5877                         pipe_config->shared_dpll = crtc->pipe;
5878                 } else {
5879                         tmp = I915_READ(PCH_DPLL_SEL);
5880                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5881                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5882                         else
5883                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5884                 }
5885
5886                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5887
5888                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5889                                            &pipe_config->dpll_hw_state));
5890         } else {
5891                 pipe_config->pixel_multiplier = 1;
5892         }
5893
5894         intel_get_pipe_timings(crtc, pipe_config);
5895
5896         ironlake_get_pfit_config(crtc, pipe_config);
5897
5898         return true;
5899 }
5900
5901 static void haswell_modeset_global_resources(struct drm_device *dev)
5902 {
5903         bool enable = false;
5904         struct intel_crtc *crtc;
5905
5906         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5907                 if (!crtc->base.enabled)
5908                         continue;
5909
5910                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5911                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5912                         enable = true;
5913         }
5914
5915         intel_set_power_well(dev, enable);
5916 }
5917
5918 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5919                                  int x, int y,
5920                                  struct drm_framebuffer *fb)
5921 {
5922         struct drm_device *dev = crtc->dev;
5923         struct drm_i915_private *dev_priv = dev->dev_private;
5924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5925         int plane = intel_crtc->plane;
5926         int ret;
5927
5928         if (!intel_ddi_pll_mode_set(crtc))
5929                 return -EINVAL;
5930
5931         /* Ensure that the cursor is valid for the new mode before changing... */
5932         intel_crtc_update_cursor(crtc, true);
5933
5934         if (intel_crtc->config.has_dp_encoder)
5935                 intel_dp_set_m_n(intel_crtc);
5936
5937         intel_crtc->lowfreq_avail = false;
5938
5939         intel_set_pipe_timings(intel_crtc);
5940
5941         if (intel_crtc->config.has_pch_encoder) {
5942                 intel_cpu_transcoder_set_m_n(intel_crtc,
5943                                              &intel_crtc->config.fdi_m_n);
5944         }
5945
5946         haswell_set_pipeconf(crtc);
5947
5948         intel_set_pipe_csc(crtc);
5949
5950         /* Set up the display plane register */
5951         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5952         POSTING_READ(DSPCNTR(plane));
5953
5954         ret = intel_pipe_set_base(crtc, x, y, fb);
5955
5956         intel_update_watermarks(dev);
5957
5958         return ret;
5959 }
5960
5961 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5962                                     struct intel_crtc_config *pipe_config)
5963 {
5964         struct drm_device *dev = crtc->base.dev;
5965         struct drm_i915_private *dev_priv = dev->dev_private;
5966         enum intel_display_power_domain pfit_domain;
5967         uint32_t tmp;
5968
5969         pipe_config->cpu_transcoder = crtc->pipe;
5970         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5971
5972         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5973         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5974                 enum i915_pipe trans_edp_pipe;
5975                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5976                 default:
5977                         WARN(1, "unknown pipe linked to edp transcoder\n");
5978                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5979                 case TRANS_DDI_EDP_INPUT_A_ON:
5980                         trans_edp_pipe = PIPE_A;
5981                         break;
5982                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5983                         trans_edp_pipe = PIPE_B;
5984                         break;
5985                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5986                         trans_edp_pipe = PIPE_C;
5987                         break;
5988                 }
5989
5990                 if (trans_edp_pipe == crtc->pipe)
5991                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5992         }
5993
5994         if (!intel_display_power_enabled(dev,
5995                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5996                 return false;
5997
5998         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5999         if (!(tmp & PIPECONF_ENABLE))
6000                 return false;
6001
6002         /*
6003          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6004          * DDI E. So just check whether this pipe is wired to DDI E and whether
6005          * the PCH transcoder is on.
6006          */
6007         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6008         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6009             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6010                 pipe_config->has_pch_encoder = true;
6011
6012                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6013                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6014                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6015
6016                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6017         }
6018
6019         intel_get_pipe_timings(crtc, pipe_config);
6020
6021         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6022         if (intel_display_power_enabled(dev, pfit_domain))
6023                 ironlake_get_pfit_config(crtc, pipe_config);
6024
6025         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6026                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6027
6028         pipe_config->pixel_multiplier = 1;
6029
6030         return true;
6031 }
6032
6033 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6034                                int x, int y,
6035                                struct drm_framebuffer *fb)
6036 {
6037         struct drm_device *dev = crtc->dev;
6038         struct drm_i915_private *dev_priv = dev->dev_private;
6039         struct drm_encoder_helper_funcs *encoder_funcs;
6040         struct intel_encoder *encoder;
6041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6042         struct drm_display_mode *adjusted_mode =
6043                 &intel_crtc->config.adjusted_mode;
6044         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6045         int pipe = intel_crtc->pipe;
6046         int ret;
6047
6048         drm_vblank_pre_modeset(dev, pipe);
6049
6050         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6051
6052         drm_vblank_post_modeset(dev, pipe);
6053
6054         if (ret != 0)
6055                 return ret;
6056
6057         for_each_encoder_on_crtc(dev, crtc, encoder) {
6058                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6059                         encoder->base.base.id,
6060                         drm_get_encoder_name(&encoder->base),
6061                         mode->base.id, mode->name);
6062                 if (encoder->mode_set) {
6063                         encoder->mode_set(encoder);
6064                 } else {
6065                         encoder_funcs = encoder->base.helper_private;
6066                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6067                 }
6068         }
6069
6070         return 0;
6071 }
6072
6073 static bool intel_eld_uptodate(struct drm_connector *connector,
6074                                int reg_eldv, uint32_t bits_eldv,
6075                                int reg_elda, uint32_t bits_elda,
6076                                int reg_edid)
6077 {
6078         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6079         uint8_t *eld = connector->eld;
6080         uint32_t i;
6081
6082         i = I915_READ(reg_eldv);
6083         i &= bits_eldv;
6084
6085         if (!eld[0])
6086                 return !i;
6087
6088         if (!i)
6089                 return false;
6090
6091         i = I915_READ(reg_elda);
6092         i &= ~bits_elda;
6093         I915_WRITE(reg_elda, i);
6094
6095         for (i = 0; i < eld[2]; i++)
6096                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6097                         return false;
6098
6099         return true;
6100 }
6101
6102 static void g4x_write_eld(struct drm_connector *connector,
6103                           struct drm_crtc *crtc)
6104 {
6105         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6106         uint8_t *eld = connector->eld;
6107         uint32_t eldv;
6108         uint32_t len;
6109         uint32_t i;
6110
6111         i = I915_READ(G4X_AUD_VID_DID);
6112
6113         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6114                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6115         else
6116                 eldv = G4X_ELDV_DEVCTG;
6117
6118         if (intel_eld_uptodate(connector,
6119                                G4X_AUD_CNTL_ST, eldv,
6120                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6121                                G4X_HDMIW_HDMIEDID))
6122                 return;
6123
6124         i = I915_READ(G4X_AUD_CNTL_ST);
6125         i &= ~(eldv | G4X_ELD_ADDR);
6126         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6127         I915_WRITE(G4X_AUD_CNTL_ST, i);
6128
6129         if (!eld[0])
6130                 return;
6131
6132         len = min_t(uint8_t, eld[2], len);
6133         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6134         for (i = 0; i < len; i++)
6135                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6136
6137         i = I915_READ(G4X_AUD_CNTL_ST);
6138         i |= eldv;
6139         I915_WRITE(G4X_AUD_CNTL_ST, i);
6140 }
6141
6142 static void haswell_write_eld(struct drm_connector *connector,
6143                                      struct drm_crtc *crtc)
6144 {
6145         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6146         uint8_t *eld = connector->eld;
6147         struct drm_device *dev = crtc->dev;
6148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6149         uint32_t eldv;
6150         uint32_t i;
6151         int len;
6152         int pipe = to_intel_crtc(crtc)->pipe;
6153         int tmp;
6154
6155         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6156         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6157         int aud_config = HSW_AUD_CFG(pipe);
6158         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6159
6160
6161         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6162
6163         /* Audio output enable */
6164         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6165         tmp = I915_READ(aud_cntrl_st2);
6166         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6167         I915_WRITE(aud_cntrl_st2, tmp);
6168
6169         /* Wait for 1 vertical blank */
6170         intel_wait_for_vblank(dev, pipe);
6171
6172         /* Set ELD valid state */
6173         tmp = I915_READ(aud_cntrl_st2);
6174         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6175         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6176         I915_WRITE(aud_cntrl_st2, tmp);
6177         tmp = I915_READ(aud_cntrl_st2);
6178         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6179
6180         /* Enable HDMI mode */
6181         tmp = I915_READ(aud_config);
6182         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6183         /* clear N_programing_enable and N_value_index */
6184         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6185         I915_WRITE(aud_config, tmp);
6186
6187         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6188
6189         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6190         intel_crtc->eld_vld = true;
6191
6192         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6193                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6194                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6195                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6196         } else
6197                 I915_WRITE(aud_config, 0);
6198
6199         if (intel_eld_uptodate(connector,
6200                                aud_cntrl_st2, eldv,
6201                                aud_cntl_st, IBX_ELD_ADDRESS,
6202                                hdmiw_hdmiedid))
6203                 return;
6204
6205         i = I915_READ(aud_cntrl_st2);
6206         i &= ~eldv;
6207         I915_WRITE(aud_cntrl_st2, i);
6208
6209         if (!eld[0])
6210                 return;
6211
6212         i = I915_READ(aud_cntl_st);
6213         i &= ~IBX_ELD_ADDRESS;
6214         I915_WRITE(aud_cntl_st, i);
6215         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6216         DRM_DEBUG_DRIVER("port num:%d\n", i);
6217
6218         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6219         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6220         for (i = 0; i < len; i++)
6221                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6222
6223         i = I915_READ(aud_cntrl_st2);
6224         i |= eldv;
6225         I915_WRITE(aud_cntrl_st2, i);
6226
6227 }
6228
6229 static void ironlake_write_eld(struct drm_connector *connector,
6230                                      struct drm_crtc *crtc)
6231 {
6232         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6233         uint8_t *eld = connector->eld;
6234         uint32_t eldv;
6235         uint32_t i;
6236         int len;
6237         int hdmiw_hdmiedid;
6238         int aud_config;
6239         int aud_cntl_st;
6240         int aud_cntrl_st2;
6241         int pipe = to_intel_crtc(crtc)->pipe;
6242
6243         if (HAS_PCH_IBX(connector->dev)) {
6244                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6245                 aud_config = IBX_AUD_CFG(pipe);
6246                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6247                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6248         } else {
6249                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6250                 aud_config = CPT_AUD_CFG(pipe);
6251                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6252                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6253         }
6254
6255         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6256
6257         i = I915_READ(aud_cntl_st);
6258         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6259         if (!i) {
6260                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6261                 /* operate blindly on all ports */
6262                 eldv = IBX_ELD_VALIDB;
6263                 eldv |= IBX_ELD_VALIDB << 4;
6264                 eldv |= IBX_ELD_VALIDB << 8;
6265         } else {
6266                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6267                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6268         }
6269
6270         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6271                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6272                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6273                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6274         } else
6275                 I915_WRITE(aud_config, 0);
6276
6277         if (intel_eld_uptodate(connector,
6278                                aud_cntrl_st2, eldv,
6279                                aud_cntl_st, IBX_ELD_ADDRESS,
6280                                hdmiw_hdmiedid))
6281                 return;
6282
6283         i = I915_READ(aud_cntrl_st2);
6284         i &= ~eldv;
6285         I915_WRITE(aud_cntrl_st2, i);
6286
6287         if (!eld[0])
6288                 return;
6289
6290         i = I915_READ(aud_cntl_st);
6291         i &= ~IBX_ELD_ADDRESS;
6292         I915_WRITE(aud_cntl_st, i);
6293
6294         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6295         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6296         for (i = 0; i < len; i++)
6297                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6298
6299         i = I915_READ(aud_cntrl_st2);
6300         i |= eldv;
6301         I915_WRITE(aud_cntrl_st2, i);
6302 }
6303
6304 void intel_write_eld(struct drm_encoder *encoder,
6305                      struct drm_display_mode *mode)
6306 {
6307         struct drm_crtc *crtc = encoder->crtc;
6308         struct drm_connector *connector;
6309         struct drm_device *dev = encoder->dev;
6310         struct drm_i915_private *dev_priv = dev->dev_private;
6311
6312         connector = drm_select_eld(encoder, mode);
6313         if (!connector)
6314                 return;
6315
6316         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6317                          connector->base.id,
6318                          drm_get_connector_name(connector),
6319                          connector->encoder->base.id,
6320                          drm_get_encoder_name(connector->encoder));
6321
6322         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6323
6324         if (dev_priv->display.write_eld)
6325                 dev_priv->display.write_eld(connector, crtc);
6326 }
6327
6328 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6329 void intel_crtc_load_lut(struct drm_crtc *crtc)
6330 {
6331         struct drm_device *dev = crtc->dev;
6332         struct drm_i915_private *dev_priv = dev->dev_private;
6333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6334         enum i915_pipe pipe = intel_crtc->pipe;
6335         int palreg = PALETTE(pipe);
6336         int i;
6337         bool reenable_ips = false;
6338
6339         /* The clocks have to be on to load the palette. */
6340         if (!crtc->enabled || !intel_crtc->active)
6341                 return;
6342
6343         if (!HAS_PCH_SPLIT(dev_priv->dev))
6344                 assert_pll_enabled(dev_priv, pipe);
6345
6346         /* use legacy palette for Ironlake */
6347         if (HAS_PCH_SPLIT(dev))
6348                 palreg = LGC_PALETTE(pipe);
6349
6350         /* Workaround : Do not read or write the pipe palette/gamma data while
6351          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6352          */
6353         if (intel_crtc->config.ips_enabled &&
6354             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6355              GAMMA_MODE_MODE_SPLIT)) {
6356                 hsw_disable_ips(intel_crtc);
6357                 reenable_ips = true;
6358         }
6359
6360         for (i = 0; i < 256; i++) {
6361                 I915_WRITE(palreg + 4 * i,
6362                            (intel_crtc->lut_r[i] << 16) |
6363                            (intel_crtc->lut_g[i] << 8) |
6364                            intel_crtc->lut_b[i]);
6365         }
6366
6367         if (reenable_ips)
6368                 hsw_enable_ips(intel_crtc);
6369 }
6370
6371 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6372 {
6373         struct drm_device *dev = crtc->dev;
6374         struct drm_i915_private *dev_priv = dev->dev_private;
6375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6376         bool visible = base != 0;
6377         u32 cntl;
6378
6379         if (intel_crtc->cursor_visible == visible)
6380                 return;
6381
6382         cntl = I915_READ(_CURACNTR);
6383         if (visible) {
6384                 /* On these chipsets we can only modify the base whilst
6385                  * the cursor is disabled.
6386                  */
6387                 I915_WRITE(_CURABASE, base);
6388
6389                 cntl &= ~(CURSOR_FORMAT_MASK);
6390                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6391                 cntl |= CURSOR_ENABLE |
6392                         CURSOR_GAMMA_ENABLE |
6393                         CURSOR_FORMAT_ARGB;
6394         } else
6395                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6396         I915_WRITE(_CURACNTR, cntl);
6397
6398         intel_crtc->cursor_visible = visible;
6399 }
6400
6401 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6402 {
6403         struct drm_device *dev = crtc->dev;
6404         struct drm_i915_private *dev_priv = dev->dev_private;
6405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6406         int pipe = intel_crtc->pipe;
6407         bool visible = base != 0;
6408
6409         if (intel_crtc->cursor_visible != visible) {
6410                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6411                 if (base) {
6412                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6413                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6414                         cntl |= pipe << 28; /* Connect to correct pipe */
6415                 } else {
6416                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6417                         cntl |= CURSOR_MODE_DISABLE;
6418                 }
6419                 I915_WRITE(CURCNTR(pipe), cntl);
6420
6421                 intel_crtc->cursor_visible = visible;
6422         }
6423         /* and commit changes on next vblank */
6424         I915_WRITE(CURBASE(pipe), base);
6425 }
6426
6427 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6428 {
6429         struct drm_device *dev = crtc->dev;
6430         struct drm_i915_private *dev_priv = dev->dev_private;
6431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6432         int pipe = intel_crtc->pipe;
6433         bool visible = base != 0;
6434
6435         if (intel_crtc->cursor_visible != visible) {
6436                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6437                 if (base) {
6438                         cntl &= ~CURSOR_MODE;
6439                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6440                 } else {
6441                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6442                         cntl |= CURSOR_MODE_DISABLE;
6443                 }
6444                 if (IS_HASWELL(dev))
6445                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6446                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6447
6448                 intel_crtc->cursor_visible = visible;
6449         }
6450         /* and commit changes on next vblank */
6451         I915_WRITE(CURBASE_IVB(pipe), base);
6452 }
6453
6454 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6455 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6456                                      bool on)
6457 {
6458         struct drm_device *dev = crtc->dev;
6459         struct drm_i915_private *dev_priv = dev->dev_private;
6460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6461         int pipe = intel_crtc->pipe;
6462         int x = intel_crtc->cursor_x;
6463         int y = intel_crtc->cursor_y;
6464         u32 base, pos;
6465         bool visible;
6466
6467         pos = 0;
6468
6469         if (on && crtc->enabled && crtc->fb) {
6470                 base = intel_crtc->cursor_addr;
6471                 if (x > (int) crtc->fb->width)
6472                         base = 0;
6473
6474                 if (y > (int) crtc->fb->height)
6475                         base = 0;
6476         } else
6477                 base = 0;
6478
6479         if (x < 0) {
6480                 if (x + intel_crtc->cursor_width < 0)
6481                         base = 0;
6482
6483                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6484                 x = -x;
6485         }
6486         pos |= x << CURSOR_X_SHIFT;
6487
6488         if (y < 0) {
6489                 if (y + intel_crtc->cursor_height < 0)
6490                         base = 0;
6491
6492                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6493                 y = -y;
6494         }
6495         pos |= y << CURSOR_Y_SHIFT;
6496
6497         visible = base != 0;
6498         if (!visible && !intel_crtc->cursor_visible)
6499                 return;
6500
6501         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6502                 I915_WRITE(CURPOS_IVB(pipe), pos);
6503                 ivb_update_cursor(crtc, base);
6504         } else {
6505                 I915_WRITE(CURPOS(pipe), pos);
6506                 if (IS_845G(dev) || IS_I865G(dev))
6507                         i845_update_cursor(crtc, base);
6508                 else
6509                         i9xx_update_cursor(crtc, base);
6510         }
6511 }
6512
6513 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6514                                  struct drm_file *file,
6515                                  uint32_t handle,
6516                                  uint32_t width, uint32_t height)
6517 {
6518         struct drm_device *dev = crtc->dev;
6519         struct drm_i915_private *dev_priv = dev->dev_private;
6520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6521         struct drm_i915_gem_object *obj;
6522         uint32_t addr;
6523         int ret;
6524
6525         /* if we want to turn off the cursor ignore width and height */
6526         if (!handle) {
6527                 DRM_DEBUG_KMS("cursor off\n");
6528                 addr = 0;
6529                 obj = NULL;
6530                 mutex_lock(&dev->struct_mutex);
6531                 goto finish;
6532         }
6533
6534         /* Currently we only support 64x64 cursors */
6535         if (width != 64 || height != 64) {
6536                 DRM_ERROR("we currently only support 64x64 cursors\n");
6537                 return -EINVAL;
6538         }
6539
6540         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6541         if (&obj->base == NULL)
6542                 return -ENOENT;
6543
6544         if (obj->base.size < width * height * 4) {
6545                 DRM_ERROR("buffer is to small\n");
6546                 ret = -ENOMEM;
6547                 goto fail;
6548         }
6549
6550         /* we only need to pin inside GTT if cursor is non-phy */
6551         mutex_lock(&dev->struct_mutex);
6552         if (!dev_priv->info->cursor_needs_physical) {
6553                 unsigned alignment;
6554
6555                 if (obj->tiling_mode) {
6556                         DRM_ERROR("cursor cannot be tiled\n");
6557                         ret = -EINVAL;
6558                         goto fail_locked;
6559                 }
6560
6561                 /* Note that the w/a also requires 2 PTE of padding following
6562                  * the bo. We currently fill all unused PTE with the shadow
6563                  * page and so we should always have valid PTE following the
6564                  * cursor preventing the VT-d warning.
6565                  */
6566                 alignment = 0;
6567                 if (need_vtd_wa(dev))
6568                         alignment = 64*1024;
6569
6570                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6571                 if (ret) {
6572                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6573                         goto fail_locked;
6574                 }
6575
6576                 ret = i915_gem_object_put_fence(obj);
6577                 if (ret) {
6578                         DRM_ERROR("failed to release fence for cursor");
6579                         goto fail_unpin;
6580                 }
6581
6582                 addr = obj->gtt_offset;
6583         } else {
6584                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6585                 ret = i915_gem_attach_phys_object(dev, obj,
6586                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6587                                                   align);
6588                 if (ret) {
6589                         DRM_ERROR("failed to attach phys object\n");
6590                         goto fail_locked;
6591                 }
6592                 addr = obj->phys_obj->handle->busaddr;
6593         }
6594
6595         if (IS_GEN2(dev))
6596                 I915_WRITE(CURSIZE, (height << 12) | width);
6597
6598  finish:
6599         if (intel_crtc->cursor_bo) {
6600                 if (dev_priv->info->cursor_needs_physical) {
6601                         if (intel_crtc->cursor_bo != obj)
6602                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6603                 } else
6604                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6605                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6606         }
6607
6608         mutex_unlock(&dev->struct_mutex);
6609
6610         intel_crtc->cursor_addr = addr;
6611         intel_crtc->cursor_bo = obj;
6612         intel_crtc->cursor_width = width;
6613         intel_crtc->cursor_height = height;
6614
6615         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6616
6617         return 0;
6618 fail_unpin:
6619         i915_gem_object_unpin(obj);
6620 fail_locked:
6621         mutex_unlock(&dev->struct_mutex);
6622 fail:
6623         drm_gem_object_unreference_unlocked(&obj->base);
6624         return ret;
6625 }
6626
6627 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6628 {
6629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6630
6631         intel_crtc->cursor_x = x;
6632         intel_crtc->cursor_y = y;
6633
6634         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6635
6636         return 0;
6637 }
6638
6639 /** Sets the color ramps on behalf of RandR */
6640 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6641                                  u16 blue, int regno)
6642 {
6643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6644
6645         intel_crtc->lut_r[regno] = red >> 8;
6646         intel_crtc->lut_g[regno] = green >> 8;
6647         intel_crtc->lut_b[regno] = blue >> 8;
6648 }
6649
6650 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6651                              u16 *blue, int regno)
6652 {
6653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6654
6655         *red = intel_crtc->lut_r[regno] << 8;
6656         *green = intel_crtc->lut_g[regno] << 8;
6657         *blue = intel_crtc->lut_b[regno] << 8;
6658 }
6659
6660 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6661                                  u16 *blue, uint32_t start, uint32_t size)
6662 {
6663         int end = (start + size > 256) ? 256 : start + size, i;
6664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6665
6666         for (i = start; i < end; i++) {
6667                 intel_crtc->lut_r[i] = red[i] >> 8;
6668                 intel_crtc->lut_g[i] = green[i] >> 8;
6669                 intel_crtc->lut_b[i] = blue[i] >> 8;
6670         }
6671
6672         intel_crtc_load_lut(crtc);
6673 }
6674
6675 /* VESA 640x480x72Hz mode to set on the pipe */
6676 static struct drm_display_mode load_detect_mode = {
6677         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6678                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6679 };
6680
6681 static struct drm_framebuffer *
6682 intel_framebuffer_create(struct drm_device *dev,
6683                          struct drm_mode_fb_cmd2 *mode_cmd,
6684                          struct drm_i915_gem_object *obj)
6685 {
6686         struct intel_framebuffer *intel_fb;
6687         int ret;
6688
6689         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6690         if (!intel_fb) {
6691                 drm_gem_object_unreference_unlocked(&obj->base);
6692                 return ERR_PTR(-ENOMEM);
6693         }
6694
6695         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6696         if (ret) {
6697                 drm_gem_object_unreference_unlocked(&obj->base);
6698                 kfree(intel_fb);
6699                 return ERR_PTR(ret);
6700         }
6701
6702         return &intel_fb->base;
6703 }
6704
6705 static u32
6706 intel_framebuffer_pitch_for_width(int width, int bpp)
6707 {
6708         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6709         return ALIGN(pitch, 64);
6710 }
6711
6712 static u32
6713 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6714 {
6715         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6716         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6717 }
6718
6719 static struct drm_framebuffer *
6720 intel_framebuffer_create_for_mode(struct drm_device *dev,
6721                                   struct drm_display_mode *mode,
6722                                   int depth, int bpp)
6723 {
6724         struct drm_i915_gem_object *obj;
6725         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6726
6727         obj = i915_gem_alloc_object(dev,
6728                                     intel_framebuffer_size_for_mode(mode, bpp));
6729         if (obj == NULL)
6730                 return ERR_PTR(-ENOMEM);
6731
6732         mode_cmd.width = mode->hdisplay;
6733         mode_cmd.height = mode->vdisplay;
6734         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6735                                                                 bpp);
6736         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6737
6738         return intel_framebuffer_create(dev, &mode_cmd, obj);
6739 }
6740
6741 static struct drm_framebuffer *
6742 mode_fits_in_fbdev(struct drm_device *dev,
6743                    struct drm_display_mode *mode)
6744 {
6745         struct drm_i915_private *dev_priv = dev->dev_private;
6746         struct drm_i915_gem_object *obj;
6747         struct drm_framebuffer *fb;
6748
6749         if (dev_priv->fbdev == NULL)
6750                 return NULL;
6751
6752         obj = dev_priv->fbdev->ifb.obj;
6753         if (obj == NULL)
6754                 return NULL;
6755
6756         fb = &dev_priv->fbdev->ifb.base;
6757         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6758                                                                fb->bits_per_pixel))
6759                 return NULL;
6760
6761         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6762                 return NULL;
6763
6764         return fb;
6765 }
6766
6767 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6768                                 struct drm_display_mode *mode,
6769                                 struct intel_load_detect_pipe *old)
6770 {
6771         struct intel_crtc *intel_crtc;
6772         struct intel_encoder *intel_encoder =
6773                 intel_attached_encoder(connector);
6774         struct drm_crtc *possible_crtc;
6775         struct drm_encoder *encoder = &intel_encoder->base;
6776         struct drm_crtc *crtc = NULL;
6777         struct drm_device *dev = encoder->dev;
6778         struct drm_framebuffer *fb;
6779         int i = -1;
6780
6781         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6782                       connector->base.id, drm_get_connector_name(connector),
6783                       encoder->base.id, drm_get_encoder_name(encoder));
6784
6785         /*
6786          * Algorithm gets a little messy:
6787          *
6788          *   - if the connector already has an assigned crtc, use it (but make
6789          *     sure it's on first)
6790          *
6791          *   - try to find the first unused crtc that can drive this connector,
6792          *     and use that if we find one
6793          */
6794
6795         /* See if we already have a CRTC for this connector */
6796         if (encoder->crtc) {
6797                 crtc = encoder->crtc;
6798
6799                 mutex_lock(&crtc->mutex);
6800
6801                 old->dpms_mode = connector->dpms;
6802                 old->load_detect_temp = false;
6803
6804                 /* Make sure the crtc and connector are running */
6805                 if (connector->dpms != DRM_MODE_DPMS_ON)
6806                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6807
6808                 return true;
6809         }
6810
6811         /* Find an unused one (if possible) */
6812         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6813                 i++;
6814                 if (!(encoder->possible_crtcs & (1 << i)))
6815                         continue;
6816                 if (!possible_crtc->enabled) {
6817                         crtc = possible_crtc;
6818                         break;
6819                 }
6820         }
6821
6822         /*
6823          * If we didn't find an unused CRTC, don't use any.
6824          */
6825         if (!crtc) {
6826                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6827                 return false;
6828         }
6829
6830         mutex_lock(&crtc->mutex);
6831         intel_encoder->new_crtc = to_intel_crtc(crtc);
6832         to_intel_connector(connector)->new_encoder = intel_encoder;
6833
6834         intel_crtc = to_intel_crtc(crtc);
6835         old->dpms_mode = connector->dpms;
6836         old->load_detect_temp = true;
6837         old->release_fb = NULL;
6838
6839         if (!mode)
6840                 mode = &load_detect_mode;
6841
6842         /* We need a framebuffer large enough to accommodate all accesses
6843          * that the plane may generate whilst we perform load detection.
6844          * We can not rely on the fbcon either being present (we get called
6845          * during its initialisation to detect all boot displays, or it may
6846          * not even exist) or that it is large enough to satisfy the
6847          * requested mode.
6848          */
6849         fb = mode_fits_in_fbdev(dev, mode);
6850         if (fb == NULL) {
6851                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6852                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6853                 old->release_fb = fb;
6854         } else
6855                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6856         if (IS_ERR(fb)) {
6857                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6858                 mutex_unlock(&crtc->mutex);
6859                 return false;
6860         }
6861
6862         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6863                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6864                 if (old->release_fb)
6865                         old->release_fb->funcs->destroy(old->release_fb);
6866                 mutex_unlock(&crtc->mutex);
6867                 return false;
6868         }
6869
6870         /* let the connector get through one full cycle before testing */
6871         intel_wait_for_vblank(dev, intel_crtc->pipe);
6872         return true;
6873 }
6874
6875 void intel_release_load_detect_pipe(struct drm_connector *connector,
6876                                     struct intel_load_detect_pipe *old)
6877 {
6878         struct intel_encoder *intel_encoder =
6879                 intel_attached_encoder(connector);
6880         struct drm_encoder *encoder = &intel_encoder->base;
6881         struct drm_crtc *crtc = encoder->crtc;
6882
6883         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6884                       connector->base.id, drm_get_connector_name(connector),
6885                       encoder->base.id, drm_get_encoder_name(encoder));
6886
6887         if (old->load_detect_temp) {
6888                 to_intel_connector(connector)->new_encoder = NULL;
6889                 intel_encoder->new_crtc = NULL;
6890                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6891
6892                 if (old->release_fb) {
6893                         drm_framebuffer_unregister_private(old->release_fb);
6894                         drm_framebuffer_unreference(old->release_fb);
6895                 }
6896
6897                 mutex_unlock(&crtc->mutex);
6898                 return;
6899         }
6900
6901         /* Switch crtc and encoder back off if necessary */
6902         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6903                 connector->funcs->dpms(connector, old->dpms_mode);
6904
6905         mutex_unlock(&crtc->mutex);
6906 }
6907
6908 /* Returns the clock of the currently programmed mode of the given pipe. */
6909 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6910 {
6911         struct drm_i915_private *dev_priv = dev->dev_private;
6912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6913         int pipe = intel_crtc->pipe;
6914         u32 dpll = I915_READ(DPLL(pipe));
6915         u32 fp;
6916         intel_clock_t clock;
6917
6918         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6919                 fp = I915_READ(FP0(pipe));
6920         else
6921                 fp = I915_READ(FP1(pipe));
6922
6923         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6924         if (IS_PINEVIEW(dev)) {
6925                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6926                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6927         } else {
6928                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6929                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6930         }
6931
6932         if (!IS_GEN2(dev)) {
6933                 if (IS_PINEVIEW(dev))
6934                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6935                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6936                 else
6937                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6938                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6939
6940                 switch (dpll & DPLL_MODE_MASK) {
6941                 case DPLLB_MODE_DAC_SERIAL:
6942                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6943                                 5 : 10;
6944                         break;
6945                 case DPLLB_MODE_LVDS:
6946                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6947                                 7 : 14;
6948                         break;
6949                 default:
6950                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6951                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6952                         return 0;
6953                 }
6954
6955                 if (IS_PINEVIEW(dev))
6956                         pineview_clock(96000, &clock);
6957                 else
6958                         i9xx_clock(96000, &clock);
6959         } else {
6960                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6961
6962                 if (is_lvds) {
6963                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6964                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6965                         clock.p2 = 14;
6966
6967                         if ((dpll & PLL_REF_INPUT_MASK) ==
6968                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6969                                 /* XXX: might not be 66MHz */
6970                                 i9xx_clock(66000, &clock);
6971                         } else
6972                                 i9xx_clock(48000, &clock);
6973                 } else {
6974                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6975                                 clock.p1 = 2;
6976                         else {
6977                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6978                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6979                         }
6980                         if (dpll & PLL_P2_DIVIDE_BY_4)
6981                                 clock.p2 = 4;
6982                         else
6983                                 clock.p2 = 2;
6984
6985                         i9xx_clock(48000, &clock);
6986                 }
6987         }
6988
6989         /* XXX: It would be nice to validate the clocks, but we can't reuse
6990          * i830PllIsValid() because it relies on the xf86_config connector
6991          * configuration being accurate, which it isn't necessarily.
6992          */
6993
6994         return clock.dot;
6995 }
6996
6997 /** Returns the currently programmed mode of the given pipe. */
6998 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6999                                              struct drm_crtc *crtc)
7000 {
7001         struct drm_i915_private *dev_priv = dev->dev_private;
7002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7003         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7004         struct drm_display_mode *mode;
7005         int htot = I915_READ(HTOTAL(cpu_transcoder));
7006         int hsync = I915_READ(HSYNC(cpu_transcoder));
7007         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7008         int vsync = I915_READ(VSYNC(cpu_transcoder));
7009
7010         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7011         if (!mode)
7012                 return NULL;
7013
7014         mode->clock = intel_crtc_clock_get(dev, crtc);
7015         mode->hdisplay = (htot & 0xffff) + 1;
7016         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7017         mode->hsync_start = (hsync & 0xffff) + 1;
7018         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7019         mode->vdisplay = (vtot & 0xffff) + 1;
7020         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7021         mode->vsync_start = (vsync & 0xffff) + 1;
7022         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7023
7024         drm_mode_set_name(mode);
7025
7026         return mode;
7027 }
7028
7029 static void intel_increase_pllclock(struct drm_crtc *crtc)
7030 {
7031         struct drm_device *dev = crtc->dev;
7032         drm_i915_private_t *dev_priv = dev->dev_private;
7033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7034         int pipe = intel_crtc->pipe;
7035         int dpll_reg = DPLL(pipe);
7036         int dpll;
7037
7038         if (HAS_PCH_SPLIT(dev))
7039                 return;
7040
7041         if (!dev_priv->lvds_downclock_avail)
7042                 return;
7043
7044         dpll = I915_READ(dpll_reg);
7045         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7046                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7047
7048                 assert_panel_unlocked(dev_priv, pipe);
7049
7050                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7051                 I915_WRITE(dpll_reg, dpll);
7052                 intel_wait_for_vblank(dev, pipe);
7053
7054                 dpll = I915_READ(dpll_reg);
7055                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7056                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7057         }
7058 }
7059
7060 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7061 {
7062         struct drm_device *dev = crtc->dev;
7063         drm_i915_private_t *dev_priv = dev->dev_private;
7064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7065
7066         if (HAS_PCH_SPLIT(dev))
7067                 return;
7068
7069         if (!dev_priv->lvds_downclock_avail)
7070                 return;
7071
7072         /*
7073          * Since this is called by a timer, we should never get here in
7074          * the manual case.
7075          */
7076         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7077                 int pipe = intel_crtc->pipe;
7078                 int dpll_reg = DPLL(pipe);
7079                 int dpll;
7080
7081                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7082
7083                 assert_panel_unlocked(dev_priv, pipe);
7084
7085                 dpll = I915_READ(dpll_reg);
7086                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7087                 I915_WRITE(dpll_reg, dpll);
7088                 intel_wait_for_vblank(dev, pipe);
7089                 dpll = I915_READ(dpll_reg);
7090                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7091                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7092         }
7093
7094 }
7095
7096 void intel_mark_busy(struct drm_device *dev)
7097 {
7098         i915_update_gfx_val(dev->dev_private);
7099 }
7100
7101 void intel_mark_idle(struct drm_device *dev)
7102 {
7103         struct drm_crtc *crtc;
7104
7105         if (!i915_powersave)
7106                 return;
7107
7108         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7109                 if (!crtc->fb)
7110                         continue;
7111
7112                 intel_decrease_pllclock(crtc);
7113         }
7114 }
7115
7116 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7117                         struct intel_ring_buffer *ring)
7118 {
7119         struct drm_device *dev = obj->base.dev;
7120         struct drm_crtc *crtc;
7121
7122         if (!i915_powersave)
7123                 return;
7124
7125         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7126                 if (!crtc->fb)
7127                         continue;
7128
7129                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7130                         continue;
7131
7132                 intel_increase_pllclock(crtc);
7133                 if (ring && intel_fbc_enabled(dev))
7134                         ring->fbc_dirty = true;
7135         }
7136 }
7137
7138 static void intel_crtc_destroy(struct drm_crtc *crtc)
7139 {
7140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7141         struct drm_device *dev = crtc->dev;
7142         struct intel_unpin_work *work;
7143
7144         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
7145         work = intel_crtc->unpin_work;
7146         intel_crtc->unpin_work = NULL;
7147         lockmgr(&dev->event_lock, LK_RELEASE);
7148
7149         if (work) {
7150                 cancel_work_sync(&work->work);
7151                 kfree(work);
7152         }
7153
7154         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7155
7156         drm_crtc_cleanup(crtc);
7157
7158         kfree(intel_crtc);
7159 }
7160
7161 static void intel_unpin_work_fn(struct work_struct *__work)
7162 {
7163         struct intel_unpin_work *work =
7164                 container_of(__work, struct intel_unpin_work, work);
7165         struct drm_device *dev = work->crtc->dev;
7166
7167         mutex_lock(&dev->struct_mutex);
7168         intel_unpin_fb_obj(work->old_fb_obj);
7169         drm_gem_object_unreference(&work->pending_flip_obj->base);
7170         drm_gem_object_unreference(&work->old_fb_obj->base);
7171
7172         intel_update_fbc(dev);
7173         mutex_unlock(&dev->struct_mutex);
7174
7175         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7176         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7177
7178         kfree(work);
7179 }
7180
7181 static void do_intel_finish_page_flip(struct drm_device *dev,
7182                                       struct drm_crtc *crtc)
7183 {
7184         drm_i915_private_t *dev_priv = dev->dev_private;
7185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7186         struct intel_unpin_work *work;
7187
7188         /* Ignore early vblank irqs */
7189         if (intel_crtc == NULL)
7190                 return;
7191
7192         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
7193         work = intel_crtc->unpin_work;
7194
7195         /* Ensure we don't miss a work->pending update ... */
7196         cpu_lfence();
7197
7198         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7199                 lockmgr(&dev->event_lock, LK_RELEASE);
7200                 return;
7201         }
7202
7203         /* and that the unpin work is consistent wrt ->pending. */
7204         cpu_lfence();
7205
7206         intel_crtc->unpin_work = NULL;
7207
7208         if (work->event)
7209                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7210
7211         drm_vblank_put(dev, intel_crtc->pipe);
7212
7213         lockmgr(&dev->event_lock, LK_RELEASE);
7214
7215         wake_up_all(&dev_priv->pending_flip_queue);
7216
7217         queue_work(dev_priv->wq, &work->work);
7218
7219         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7220 }
7221
7222 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7223 {
7224         drm_i915_private_t *dev_priv = dev->dev_private;
7225         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7226
7227         do_intel_finish_page_flip(dev, crtc);
7228 }
7229
7230 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7231 {
7232         drm_i915_private_t *dev_priv = dev->dev_private;
7233         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7234
7235         do_intel_finish_page_flip(dev, crtc);
7236 }
7237
7238 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7239 {
7240         drm_i915_private_t *dev_priv = dev->dev_private;
7241         struct intel_crtc *intel_crtc =
7242                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7243
7244         /* NB: An MMIO update of the plane base pointer will also
7245          * generate a page-flip completion irq, i.e. every modeset
7246          * is also accompanied by a spurious intel_prepare_page_flip().
7247          */
7248         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
7249         if (intel_crtc->unpin_work)
7250                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7251         lockmgr(&dev->event_lock, LK_RELEASE);
7252 }
7253
7254 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7255 {
7256         /* Ensure that the work item is consistent when activating it ... */
7257         cpu_sfence();
7258         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7259         /* and that it is marked active as soon as the irq could fire. */
7260         cpu_sfence();
7261 }
7262
7263 static int intel_gen2_queue_flip(struct drm_device *dev,
7264                                  struct drm_crtc *crtc,
7265                                  struct drm_framebuffer *fb,
7266                                  struct drm_i915_gem_object *obj)
7267 {
7268         struct drm_i915_private *dev_priv = dev->dev_private;
7269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7270         u32 flip_mask;
7271         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7272         int ret;
7273
7274         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7275         if (ret)
7276                 goto err;
7277
7278         ret = intel_ring_begin(ring, 6);
7279         if (ret)
7280                 goto err_unpin;
7281
7282         /* Can't queue multiple flips, so wait for the previous
7283          * one to finish before executing the next.
7284          */
7285         if (intel_crtc->plane)
7286                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7287         else
7288                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7289         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7290         intel_ring_emit(ring, MI_NOOP);
7291         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7292                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7293         intel_ring_emit(ring, fb->pitches[0]);
7294         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7295         intel_ring_emit(ring, 0); /* aux display base address, unused */
7296
7297         intel_mark_page_flip_active(intel_crtc);
7298         intel_ring_advance(ring);
7299         return 0;
7300
7301 err_unpin:
7302         intel_unpin_fb_obj(obj);
7303 err:
7304         return ret;
7305 }
7306
7307 static int intel_gen3_queue_flip(struct drm_device *dev,
7308                                  struct drm_crtc *crtc,
7309                                  struct drm_framebuffer *fb,
7310                                  struct drm_i915_gem_object *obj)
7311 {
7312         struct drm_i915_private *dev_priv = dev->dev_private;
7313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7314         u32 flip_mask;
7315         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7316         int ret;
7317
7318         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7319         if (ret)
7320                 goto err;
7321
7322         ret = intel_ring_begin(ring, 6);
7323         if (ret)
7324                 goto err_unpin;
7325
7326         if (intel_crtc->plane)
7327                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7328         else
7329                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7330         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7331         intel_ring_emit(ring, MI_NOOP);
7332         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7333                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7334         intel_ring_emit(ring, fb->pitches[0]);
7335         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7336         intel_ring_emit(ring, MI_NOOP);
7337
7338         intel_mark_page_flip_active(intel_crtc);
7339         intel_ring_advance(ring);
7340         return 0;
7341
7342 err_unpin:
7343         intel_unpin_fb_obj(obj);
7344 err:
7345         return ret;
7346 }
7347
7348 static int intel_gen4_queue_flip(struct drm_device *dev,
7349                                  struct drm_crtc *crtc,
7350                                  struct drm_framebuffer *fb,
7351                                  struct drm_i915_gem_object *obj)
7352 {
7353         struct drm_i915_private *dev_priv = dev->dev_private;
7354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7355         uint32_t pf, pipesrc;
7356         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7357         int ret;
7358
7359         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7360         if (ret)
7361                 goto err;
7362
7363         ret = intel_ring_begin(ring, 4);
7364         if (ret)
7365                 goto err_unpin;
7366
7367         /* i965+ uses the linear or tiled offsets from the
7368          * Display Registers (which do not change across a page-flip)
7369          * so we need only reprogram the base address.
7370          */
7371         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7372                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7373         intel_ring_emit(ring, fb->pitches[0]);
7374         intel_ring_emit(ring,
7375                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7376                         obj->tiling_mode);
7377
7378         /* XXX Enabling the panel-fitter across page-flip is so far
7379          * untested on non-native modes, so ignore it for now.
7380          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7381          */
7382         pf = 0;
7383         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7384         intel_ring_emit(ring, pf | pipesrc);
7385
7386         intel_mark_page_flip_active(intel_crtc);
7387         intel_ring_advance(ring);
7388         return 0;
7389
7390 err_unpin:
7391         intel_unpin_fb_obj(obj);
7392 err:
7393         return ret;
7394 }
7395
7396 static int intel_gen6_queue_flip(struct drm_device *dev,
7397                                  struct drm_crtc *crtc,
7398                                  struct drm_framebuffer *fb,
7399                                  struct drm_i915_gem_object *obj)
7400 {
7401         struct drm_i915_private *dev_priv = dev->dev_private;
7402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7403         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7404         uint32_t pf, pipesrc;
7405         int ret;
7406
7407         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7408         if (ret)
7409                 goto err;
7410
7411         ret = intel_ring_begin(ring, 4);
7412         if (ret)
7413                 goto err_unpin;
7414
7415         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7416                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7417         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7418         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7419
7420         /* Contrary to the suggestions in the documentation,
7421          * "Enable Panel Fitter" does not seem to be required when page
7422          * flipping with a non-native mode, and worse causes a normal
7423          * modeset to fail.
7424          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7425          */
7426         pf = 0;
7427         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7428         intel_ring_emit(ring, pf | pipesrc);
7429
7430         intel_mark_page_flip_active(intel_crtc);
7431         intel_ring_advance(ring);
7432         return 0;
7433
7434 err_unpin:
7435         intel_unpin_fb_obj(obj);
7436 err:
7437         return ret;
7438 }
7439
7440 /*
7441  * On gen7 we currently use the blit ring because (in early silicon at least)
7442  * the render ring doesn't give us interrpts for page flip completion, which
7443  * means clients will hang after the first flip is queued.  Fortunately the
7444  * blit ring generates interrupts properly, so use it instead.
7445  */
7446 static int intel_gen7_queue_flip(struct drm_device *dev,
7447                                  struct drm_crtc *crtc,
7448                                  struct drm_framebuffer *fb,
7449                                  struct drm_i915_gem_object *obj)
7450 {
7451         struct drm_i915_private *dev_priv = dev->dev_private;
7452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7453         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7454         uint32_t plane_bit = 0;
7455         int ret;
7456
7457         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7458         if (ret)
7459                 goto err;
7460
7461         switch(intel_crtc->plane) {
7462         case PLANE_A:
7463                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7464                 break;
7465         case PLANE_B:
7466                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7467                 break;
7468         case PLANE_C:
7469                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7470                 break;
7471         default:
7472                 WARN_ONCE(1, "unknown plane in flip command\n");
7473                 ret = -ENODEV;
7474                 goto err_unpin;
7475         }
7476
7477         ret = intel_ring_begin(ring, 4);
7478         if (ret)
7479                 goto err_unpin;
7480
7481         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7482         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7483         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7484         intel_ring_emit(ring, (MI_NOOP));
7485
7486         intel_mark_page_flip_active(intel_crtc);
7487         intel_ring_advance(ring);
7488         return 0;
7489
7490 err_unpin:
7491         intel_unpin_fb_obj(obj);
7492 err:
7493         return ret;
7494 }
7495
7496 static int intel_default_queue_flip(struct drm_device *dev,
7497                                     struct drm_crtc *crtc,
7498                                     struct drm_framebuffer *fb,
7499                                     struct drm_i915_gem_object *obj)
7500 {
7501         return -ENODEV;
7502 }
7503
7504 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7505                                 struct drm_framebuffer *fb,
7506                                 struct drm_pending_vblank_event *event)
7507 {
7508         struct drm_device *dev = crtc->dev;
7509         struct drm_i915_private *dev_priv = dev->dev_private;
7510         struct drm_framebuffer *old_fb = crtc->fb;
7511         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7513         struct intel_unpin_work *work;
7514         int ret;
7515
7516         /* Can't change pixel format via MI display flips. */
7517         if (fb->pixel_format != crtc->fb->pixel_format)
7518                 return -EINVAL;
7519
7520         /*
7521          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7522          * Note that pitch changes could also affect these register.
7523          */
7524         if (INTEL_INFO(dev)->gen > 3 &&
7525             (fb->offsets[0] != crtc->fb->offsets[0] ||
7526              fb->pitches[0] != crtc->fb->pitches[0]))
7527                 return -EINVAL;
7528
7529         work = kzalloc(sizeof *work, GFP_KERNEL);
7530         if (work == NULL)
7531                 return -ENOMEM;
7532
7533         work->event = event;
7534         work->crtc = crtc;
7535         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7536         INIT_WORK(&work->work, intel_unpin_work_fn);
7537
7538         ret = drm_vblank_get(dev, intel_crtc->pipe);
7539         if (ret)
7540                 goto free_work;
7541
7542         /* We borrow the event spin lock for protecting unpin_work */
7543         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
7544         if (intel_crtc->unpin_work) {
7545                 lockmgr(&dev->event_lock, LK_RELEASE);
7546                 kfree(work);
7547                 drm_vblank_put(dev, intel_crtc->pipe);
7548
7549                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7550                 return -EBUSY;
7551         }
7552         intel_crtc->unpin_work = work;
7553         lockmgr(&dev->event_lock, LK_RELEASE);
7554
7555         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7556                 flush_workqueue(dev_priv->wq);
7557
7558         ret = i915_mutex_lock_interruptible(dev);
7559         if (ret)
7560                 goto cleanup;
7561
7562         /* Reference the objects for the scheduled work. */
7563         drm_gem_object_reference(&work->old_fb_obj->base);
7564         drm_gem_object_reference(&obj->base);
7565
7566         crtc->fb = fb;
7567
7568         work->pending_flip_obj = obj;
7569
7570         work->enable_stall_check = true;
7571
7572         atomic_inc(&intel_crtc->unpin_work_count);
7573         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7574
7575         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7576         if (ret)
7577                 goto cleanup_pending;
7578
7579         intel_disable_fbc(dev);
7580         intel_mark_fb_busy(obj, NULL);
7581         mutex_unlock(&dev->struct_mutex);
7582
7583         trace_i915_flip_request(intel_crtc->plane, obj);
7584
7585         return 0;
7586
7587 cleanup_pending:
7588         atomic_dec(&intel_crtc->unpin_work_count);
7589         crtc->fb = old_fb;
7590         drm_gem_object_unreference(&work->old_fb_obj->base);
7591         drm_gem_object_unreference(&obj->base);
7592         mutex_unlock(&dev->struct_mutex);
7593
7594 cleanup:
7595         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
7596         intel_crtc->unpin_work = NULL;
7597         lockmgr(&dev->event_lock, LK_RELEASE);
7598
7599         drm_vblank_put(dev, intel_crtc->pipe);
7600 free_work:
7601         kfree(work);
7602
7603         return ret;
7604 }
7605
7606 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7607         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7608         .load_lut = intel_crtc_load_lut,
7609 };
7610
7611 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7612                                   struct drm_crtc *crtc)
7613 {
7614         struct drm_device *dev;
7615         struct drm_crtc *tmp;
7616         int crtc_mask = 1;
7617
7618         WARN(!crtc, "checking null crtc?\n");
7619         /* profmakx: this is to prevent the kernel from panicing */
7620         if(!crtc) {
7621                 return false;
7622         }
7623
7624         dev = crtc->dev;
7625
7626         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7627                 if (tmp == crtc)
7628                         break;
7629                 crtc_mask <<= 1;
7630         }
7631
7632         if (encoder->possible_crtcs & crtc_mask)
7633                 return true;
7634         return false;
7635 }
7636
7637 /**
7638  * intel_modeset_update_staged_output_state
7639  *
7640  * Updates the staged output configuration state, e.g. after we've read out the
7641  * current hw state.
7642  */
7643 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7644 {
7645         struct intel_encoder *encoder;
7646         struct intel_connector *connector;
7647
7648         list_for_each_entry(connector, &dev->mode_config.connector_list,
7649                             base.head) {
7650                 connector->new_encoder =
7651                         to_intel_encoder(connector->base.encoder);
7652         }
7653
7654         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7655                             base.head) {
7656                 encoder->new_crtc =
7657                         to_intel_crtc(encoder->base.crtc);
7658         }
7659 }
7660
7661 /**
7662  * intel_modeset_commit_output_state
7663  *
7664  * This function copies the stage display pipe configuration to the real one.
7665  */
7666 static void intel_modeset_commit_output_state(struct drm_device *dev)
7667 {
7668         struct intel_encoder *encoder;
7669         struct intel_connector *connector;
7670
7671         list_for_each_entry(connector, &dev->mode_config.connector_list,
7672                             base.head) {
7673                 connector->base.encoder = &connector->new_encoder->base;
7674         }
7675
7676         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7677                             base.head) {
7678                 encoder->base.crtc = &encoder->new_crtc->base;
7679         }
7680 }
7681
7682 static void
7683 connected_sink_compute_bpp(struct intel_connector * connector,
7684                            struct intel_crtc_config *pipe_config)
7685 {
7686         int bpp = pipe_config->pipe_bpp;
7687
7688         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7689                 connector->base.base.id,
7690                 drm_get_connector_name(&connector->base));
7691
7692         /* Don't use an invalid EDID bpc value */
7693         if (connector->base.display_info.bpc &&
7694             connector->base.display_info.bpc * 3 < bpp) {
7695                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7696                               bpp, connector->base.display_info.bpc*3);
7697                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7698         }
7699
7700         /* Clamp bpp to 8 on screens without EDID 1.4 */
7701         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7702                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7703                               bpp);
7704                 pipe_config->pipe_bpp = 24;
7705         }
7706 }
7707
7708 static int
7709 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7710                           struct drm_framebuffer *fb,
7711                           struct intel_crtc_config *pipe_config)
7712 {
7713         struct drm_device *dev = crtc->base.dev;
7714         struct intel_connector *connector;
7715         int bpp;
7716
7717         switch (fb->pixel_format) {
7718         case DRM_FORMAT_C8:
7719                 bpp = 8*3; /* since we go through a colormap */
7720                 break;
7721         case DRM_FORMAT_XRGB1555:
7722         case DRM_FORMAT_ARGB1555:
7723                 /* checked in intel_framebuffer_init already */
7724                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7725                         return -EINVAL;
7726         case DRM_FORMAT_RGB565:
7727                 bpp = 6*3; /* min is 18bpp */
7728                 break;
7729         case DRM_FORMAT_XBGR8888:
7730         case DRM_FORMAT_ABGR8888:
7731                 /* checked in intel_framebuffer_init already */
7732                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7733                         return -EINVAL;
7734         case DRM_FORMAT_XRGB8888:
7735         case DRM_FORMAT_ARGB8888:
7736                 bpp = 8*3;
7737                 break;
7738         case DRM_FORMAT_XRGB2101010:
7739         case DRM_FORMAT_ARGB2101010:
7740         case DRM_FORMAT_XBGR2101010:
7741         case DRM_FORMAT_ABGR2101010:
7742                 /* checked in intel_framebuffer_init already */
7743                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7744                         return -EINVAL;
7745                 bpp = 10*3;
7746                 break;
7747         /* TODO: gen4+ supports 16 bpc floating point, too. */
7748         default:
7749                 DRM_DEBUG_KMS("unsupported depth\n");
7750                 return -EINVAL;
7751         }
7752
7753         pipe_config->pipe_bpp = bpp;
7754
7755         /* Clamp display bpp to EDID value */
7756         list_for_each_entry(connector, &dev->mode_config.connector_list,
7757                             base.head) {
7758                 if (!connector->new_encoder ||
7759                     connector->new_encoder->new_crtc != crtc)
7760                         continue;
7761
7762                 connected_sink_compute_bpp(connector, pipe_config);
7763         }
7764
7765         return bpp;
7766 }
7767
7768 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7769                                    struct intel_crtc_config *pipe_config,
7770                                    const char *context)
7771 {
7772         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7773                       context, pipe_name(crtc->pipe));
7774
7775         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7776         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7777                       pipe_config->pipe_bpp, pipe_config->dither);
7778         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7779                       pipe_config->has_pch_encoder,
7780                       pipe_config->fdi_lanes,
7781                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7782                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7783                       pipe_config->fdi_m_n.tu);
7784         DRM_DEBUG_KMS("requested mode:\n");
7785         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7786         DRM_DEBUG_KMS("adjusted mode:\n");
7787         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7788         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7789                       pipe_config->gmch_pfit.control,
7790                       pipe_config->gmch_pfit.pgm_ratios,
7791                       pipe_config->gmch_pfit.lvds_border_bits);
7792         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7793                       pipe_config->pch_pfit.pos,
7794                       pipe_config->pch_pfit.size);
7795         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7796 }
7797
7798 static bool check_encoder_cloning(struct drm_crtc *crtc)
7799 {
7800         int num_encoders = 0;
7801         bool uncloneable_encoders = false;
7802         struct intel_encoder *encoder;
7803
7804         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7805                             base.head) {
7806                 if (&encoder->new_crtc->base != crtc)
7807                         continue;
7808
7809                 num_encoders++;
7810                 if (!encoder->cloneable)
7811                         uncloneable_encoders = true;
7812         }
7813
7814         return !(num_encoders > 1 && uncloneable_encoders);
7815 }
7816
7817 static struct intel_crtc_config *
7818 intel_modeset_pipe_config(struct drm_crtc *crtc,
7819                           struct drm_framebuffer *fb,
7820                           struct drm_display_mode *mode)
7821 {
7822         struct drm_device *dev = crtc->dev;
7823         struct drm_encoder_helper_funcs *encoder_funcs;
7824         struct intel_encoder *encoder;
7825         struct intel_crtc_config *pipe_config;
7826         int plane_bpp, ret = -EINVAL;
7827         bool retry = true;
7828
7829         if (!check_encoder_cloning(crtc)) {
7830                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7831                 return ERR_PTR(-EINVAL);
7832         }
7833
7834         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7835         if (!pipe_config)
7836                 return ERR_PTR(-ENOMEM);
7837
7838         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7839         drm_mode_copy(&pipe_config->requested_mode, mode);
7840         pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7841         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7842
7843         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7844          * plane pixel format and any sink constraints into account. Returns the
7845          * source plane bpp so that dithering can be selected on mismatches
7846          * after encoders and crtc also have had their say. */
7847         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7848                                               fb, pipe_config);
7849         if (plane_bpp < 0)
7850                 goto fail;
7851
7852 encoder_retry:
7853         /* Ensure the port clock defaults are reset when retrying. */
7854         pipe_config->port_clock = 0;
7855         pipe_config->pixel_multiplier = 1;
7856
7857         /* Pass our mode to the connectors and the CRTC to give them a chance to
7858          * adjust it according to limitations or connector properties, and also
7859          * a chance to reject the mode entirely.
7860          */
7861         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7862                             base.head) {
7863
7864                 if (&encoder->new_crtc->base != crtc)
7865                         continue;
7866
7867                 if (encoder->compute_config) {
7868                         if (!(encoder->compute_config(encoder, pipe_config))) {
7869                                 DRM_DEBUG_KMS("Encoder config failure\n");
7870                                 goto fail;
7871                         }
7872
7873                         continue;
7874                 }
7875
7876                 encoder_funcs = encoder->base.helper_private;
7877                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7878                                                 &pipe_config->requested_mode,
7879                                                 &pipe_config->adjusted_mode))) {
7880                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7881                         goto fail;
7882                 }
7883         }
7884
7885         /* Set default port clock if not overwritten by the encoder. Needs to be
7886          * done afterwards in case the encoder adjusts the mode. */
7887         if (!pipe_config->port_clock)
7888                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7889
7890         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7891         if (ret < 0) {
7892                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7893                 goto fail;
7894         }
7895
7896         if (ret == RETRY) {
7897                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7898                         ret = -EINVAL;
7899                         goto fail;
7900                 }
7901
7902                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7903                 retry = false;
7904                 goto encoder_retry;
7905         }
7906
7907         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7908         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7909                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7910
7911         return pipe_config;
7912 fail:
7913         kfree(pipe_config);
7914         return ERR_PTR(ret);
7915 }
7916
7917 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7918  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7919 static void
7920 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7921                              unsigned *prepare_pipes, unsigned *disable_pipes)
7922 {
7923         struct intel_crtc *intel_crtc;
7924         struct drm_device *dev = crtc->dev;
7925         struct intel_encoder *encoder;
7926         struct intel_connector *connector;
7927         struct drm_crtc *tmp_crtc;
7928
7929         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7930
7931         /* Check which crtcs have changed outputs connected to them, these need
7932          * to be part of the prepare_pipes mask. We don't (yet) support global
7933          * modeset across multiple crtcs, so modeset_pipes will only have one
7934          * bit set at most. */
7935         list_for_each_entry(connector, &dev->mode_config.connector_list,
7936                             base.head) {
7937                 if (connector->base.encoder == &connector->new_encoder->base)
7938                         continue;
7939
7940                 if (connector->base.encoder) {
7941                         tmp_crtc = connector->base.encoder->crtc;
7942
7943                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7944                 }
7945
7946                 if (connector->new_encoder)
7947                         *prepare_pipes |=
7948                                 1 << connector->new_encoder->new_crtc->pipe;
7949         }
7950
7951         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7952                             base.head) {
7953                 if (encoder->base.crtc == &encoder->new_crtc->base)
7954                         continue;
7955
7956                 if (encoder->base.crtc) {
7957                         tmp_crtc = encoder->base.crtc;
7958
7959                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7960                 }
7961
7962                 if (encoder->new_crtc)
7963                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7964         }
7965
7966         /* Check for any pipes that will be fully disabled ... */
7967         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7968                             base.head) {
7969                 bool used = false;
7970
7971                 /* Don't try to disable disabled crtcs. */
7972                 if (!intel_crtc->base.enabled)
7973                         continue;
7974
7975                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7976                                     base.head) {
7977                         if (encoder->new_crtc == intel_crtc)
7978                                 used = true;
7979                 }
7980
7981                 if (!used)
7982                         *disable_pipes |= 1 << intel_crtc->pipe;
7983         }
7984
7985
7986         /* set_mode is also used to update properties on life display pipes. */
7987         intel_crtc = to_intel_crtc(crtc);
7988         if (crtc->enabled)
7989                 *prepare_pipes |= 1 << intel_crtc->pipe;
7990
7991         /*
7992          * For simplicity do a full modeset on any pipe where the output routing
7993          * changed. We could be more clever, but that would require us to be
7994          * more careful with calling the relevant encoder->mode_set functions.
7995          */
7996         if (*prepare_pipes)
7997                 *modeset_pipes = *prepare_pipes;
7998
7999         /* ... and mask these out. */
8000         *modeset_pipes &= ~(*disable_pipes);
8001         *prepare_pipes &= ~(*disable_pipes);
8002
8003         /*
8004          * HACK: We don't (yet) fully support global modesets. intel_set_config
8005          * obies this rule, but the modeset restore mode of
8006          * intel_modeset_setup_hw_state does not.
8007          */
8008         *modeset_pipes &= 1 << intel_crtc->pipe;
8009         *prepare_pipes &= 1 << intel_crtc->pipe;
8010
8011         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8012                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8013 }
8014
8015 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8016 {
8017         struct drm_encoder *encoder;
8018         struct drm_device *dev = crtc->dev;
8019
8020         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8021                 if (encoder->crtc == crtc)
8022                         return true;
8023
8024         return false;
8025 }
8026
8027 static void
8028 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8029 {
8030         struct intel_encoder *intel_encoder;
8031         struct intel_crtc *intel_crtc;
8032         struct drm_connector *connector;
8033
8034         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8035                             base.head) {
8036                 if (!intel_encoder->base.crtc)
8037                         continue;
8038
8039                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8040
8041                 if (prepare_pipes & (1 << intel_crtc->pipe))
8042                         intel_encoder->connectors_active = false;
8043         }
8044
8045         intel_modeset_commit_output_state(dev);
8046
8047         /* Update computed state. */
8048         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8049                             base.head) {
8050                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8051         }
8052
8053         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8054                 if (!connector->encoder || !connector->encoder->crtc)
8055                         continue;
8056
8057                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8058
8059                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8060                         struct drm_property *dpms_property =
8061                                 dev->mode_config.dpms_property;
8062
8063                         connector->dpms = DRM_MODE_DPMS_ON;
8064                         drm_object_property_set_value(&connector->base,
8065                                                          dpms_property,
8066                                                          DRM_MODE_DPMS_ON);
8067
8068                         intel_encoder = to_intel_encoder(connector->encoder);
8069                         intel_encoder->connectors_active = true;
8070                 }
8071         }
8072
8073 }
8074
8075 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8076         list_for_each_entry((intel_crtc), \
8077                             &(dev)->mode_config.crtc_list, \
8078                             base.head) \
8079                 if (mask & (1 <<(intel_crtc)->pipe))
8080
8081 static bool
8082 intel_pipe_config_compare(struct drm_device *dev,
8083                           struct intel_crtc_config *current_config,
8084                           struct intel_crtc_config *pipe_config)
8085 {
8086 #define PIPE_CONF_CHECK_X(name) \
8087         if (current_config->name != pipe_config->name) { \
8088                 DRM_ERROR("mismatch in " #name " " \
8089                           "(expected 0x%08x, found 0x%08x)\n", \
8090                           current_config->name, \
8091                           pipe_config->name); \
8092                 return false; \
8093         }
8094
8095 #define PIPE_CONF_CHECK_I(name) \
8096         if (current_config->name != pipe_config->name) { \
8097                 DRM_ERROR("mismatch in " #name " " \
8098                           "(expected %i, found %i)\n", \
8099                           current_config->name, \
8100                           pipe_config->name); \
8101                 return false; \
8102         }
8103
8104 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8105         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8106                 DRM_ERROR("mismatch in " #name " " \
8107                           "(expected %i, found %i)\n", \
8108                           current_config->name & (mask), \
8109                           pipe_config->name & (mask)); \
8110                 return false; \
8111         }
8112
8113 #define PIPE_CONF_QUIRK(quirk)  \
8114         ((current_config->quirks | pipe_config->quirks) & (quirk))
8115
8116         PIPE_CONF_CHECK_I(cpu_transcoder);
8117
8118         PIPE_CONF_CHECK_I(has_pch_encoder);
8119         PIPE_CONF_CHECK_I(fdi_lanes);
8120         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8121         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8122         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8123         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8124         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8125
8126         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8127         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8128         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8129         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8130         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8131         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8132
8133         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8134         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8135         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8136         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8137         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8138         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8139
8140         if (!HAS_PCH_SPLIT(dev))
8141                 PIPE_CONF_CHECK_I(pixel_multiplier);
8142
8143         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8144                               DRM_MODE_FLAG_INTERLACE);
8145
8146         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8147                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8148                                       DRM_MODE_FLAG_PHSYNC);
8149                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8150                                       DRM_MODE_FLAG_NHSYNC);
8151                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8152                                       DRM_MODE_FLAG_PVSYNC);
8153                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8154                                       DRM_MODE_FLAG_NVSYNC);
8155         }
8156
8157         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8158         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8159
8160         PIPE_CONF_CHECK_I(gmch_pfit.control);
8161         /* pfit ratios are autocomputed by the hw on gen4+ */
8162         if (INTEL_INFO(dev)->gen < 4)
8163                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8164         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8165         PIPE_CONF_CHECK_I(pch_pfit.pos);
8166         PIPE_CONF_CHECK_I(pch_pfit.size);
8167
8168         PIPE_CONF_CHECK_I(ips_enabled);
8169
8170         PIPE_CONF_CHECK_I(shared_dpll);
8171         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8172         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8173         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8174
8175 #undef PIPE_CONF_CHECK_X
8176 #undef PIPE_CONF_CHECK_I
8177 #undef PIPE_CONF_CHECK_FLAGS
8178 #undef PIPE_CONF_QUIRK
8179
8180         return true;
8181 }
8182
8183 static void
8184 check_connector_state(struct drm_device *dev)
8185 {
8186         struct intel_connector *connector;
8187
8188         list_for_each_entry(connector, &dev->mode_config.connector_list,
8189                             base.head) {
8190                 /* This also checks the encoder/connector hw state with the
8191                  * ->get_hw_state callbacks. */
8192                 intel_connector_check_state(connector);
8193
8194                 WARN(&connector->new_encoder->base != connector->base.encoder,
8195                      "connector's staged encoder doesn't match current encoder\n");
8196         }
8197 }
8198
8199 static void
8200 check_encoder_state(struct drm_device *dev)
8201 {
8202         struct intel_encoder *encoder;
8203         struct intel_connector *connector;
8204
8205         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8206                             base.head) {
8207                 bool enabled = false;
8208                 bool active = false;
8209                 enum i915_pipe pipe, tracked_pipe;
8210
8211                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8212                               encoder->base.base.id,
8213                               drm_get_encoder_name(&encoder->base));
8214
8215                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8216                      "encoder's stage crtc doesn't match current crtc\n");
8217                 WARN(encoder->connectors_active && !encoder->base.crtc,
8218                      "encoder's active_connectors set, but no crtc\n");
8219
8220                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8221                                     base.head) {
8222                         if (connector->base.encoder != &encoder->base)
8223                                 continue;
8224                         enabled = true;
8225                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8226                                 active = true;
8227                 }
8228                 WARN(!!encoder->base.crtc != enabled,
8229                      "encoder's enabled state mismatch "
8230                      "(expected %i, found %i)\n",
8231                      !!encoder->base.crtc, enabled);
8232                 WARN(active && !encoder->base.crtc,
8233                      "active encoder with no crtc\n");
8234
8235                 WARN(encoder->connectors_active != active,
8236                      "encoder's computed active state doesn't match tracked active state "
8237                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8238
8239                 active = encoder->get_hw_state(encoder, &pipe);
8240                 WARN(active != encoder->connectors_active,
8241                      "encoder's hw state doesn't match sw tracking "
8242                      "(expected %i, found %i)\n",
8243                      encoder->connectors_active, active);
8244
8245                 if (!encoder->base.crtc)
8246                         continue;
8247
8248                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8249                 WARN(active && pipe != tracked_pipe,
8250                      "active encoder's pipe doesn't match"
8251                      "(expected %i, found %i)\n",
8252                      tracked_pipe, pipe);
8253
8254         }
8255 }
8256
8257 static void
8258 check_crtc_state(struct drm_device *dev)
8259 {
8260         drm_i915_private_t *dev_priv = dev->dev_private;
8261         struct intel_crtc *crtc;
8262         struct intel_encoder *encoder;
8263         struct intel_crtc_config pipe_config;
8264
8265         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8266                             base.head) {
8267                 bool enabled = false;
8268                 bool active = false;
8269
8270                 memset(&pipe_config, 0, sizeof(pipe_config));
8271
8272                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8273                               crtc->base.base.id);
8274
8275                 WARN(crtc->active && !crtc->base.enabled,
8276                      "active crtc, but not enabled in sw tracking\n");
8277
8278                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8279                                     base.head) {
8280                         if (encoder->base.crtc != &crtc->base)
8281                                 continue;
8282                         enabled = true;
8283                         if (encoder->connectors_active)
8284                                 active = true;
8285                 }
8286
8287                 WARN(active != crtc->active,
8288                      "crtc's computed active state doesn't match tracked active state "
8289                      "(expected %i, found %i)\n", active, crtc->active);
8290                 WARN(enabled != crtc->base.enabled,
8291                      "crtc's computed enabled state doesn't match tracked enabled state "
8292                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8293
8294                 active = dev_priv->display.get_pipe_config(crtc,
8295                                                            &pipe_config);
8296
8297                 /* hw state is inconsistent with the pipe A quirk */
8298                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8299                         active = crtc->active;
8300
8301                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8302                                     base.head) {
8303                         enum i915_pipe pipe;
8304                         if (encoder->base.crtc != &crtc->base)
8305                                 continue;
8306                         if (encoder->get_config &&
8307                             encoder->get_hw_state(encoder, &pipe))
8308                                 encoder->get_config(encoder, &pipe_config);
8309                 }
8310
8311                 WARN(crtc->active != active,
8312                      "crtc active state doesn't match with hw state "
8313                      "(expected %i, found %i)\n", crtc->active, active);
8314
8315                 if (active &&
8316                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8317                         WARN(1, "pipe state doesn't match!\n");
8318                         intel_dump_pipe_config(crtc, &pipe_config,
8319                                                "[hw state]");
8320                         intel_dump_pipe_config(crtc, &crtc->config,
8321                                                "[sw state]");
8322                 }
8323         }
8324 }
8325
8326 static void
8327 check_shared_dpll_state(struct drm_device *dev)
8328 {
8329         drm_i915_private_t *dev_priv = dev->dev_private;
8330         struct intel_crtc *crtc;
8331         struct intel_dpll_hw_state dpll_hw_state;
8332         int i;
8333
8334         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8335                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8336                 int enabled_crtcs = 0, active_crtcs = 0;
8337                 bool active;
8338
8339                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8340
8341                 DRM_DEBUG_KMS("%s\n", pll->name);
8342
8343                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8344
8345                 WARN(pll->active > pll->refcount,
8346                      "more active pll users than references: %i vs %i\n",
8347                      pll->active, pll->refcount);
8348                 WARN(pll->active && !pll->on,
8349                      "pll in active use but not on in sw tracking\n");
8350                 WARN(pll->on && !pll->active,
8351                      "pll in on but not on in use in sw tracking\n");
8352                 WARN(pll->on != active,
8353                      "pll on state mismatch (expected %i, found %i)\n",
8354                      pll->on, active);
8355
8356                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8357                                     base.head) {
8358                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8359                                 enabled_crtcs++;
8360                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8361                                 active_crtcs++;
8362                 }
8363                 WARN(pll->active != active_crtcs,
8364                      "pll active crtcs mismatch (expected %i, found %i)\n",
8365                      pll->active, active_crtcs);
8366                 WARN(pll->refcount != enabled_crtcs,
8367                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8368                      pll->refcount, enabled_crtcs);
8369
8370                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8371                                        sizeof(dpll_hw_state)),
8372                      "pll hw state mismatch\n");
8373         }
8374 }
8375
8376 void
8377 intel_modeset_check_state(struct drm_device *dev)
8378 {
8379         check_connector_state(dev);
8380         check_encoder_state(dev);
8381         check_crtc_state(dev);
8382         check_shared_dpll_state(dev);
8383 }
8384
8385 static int __intel_set_mode(struct drm_crtc *crtc,
8386                             struct drm_display_mode *mode,
8387                             int x, int y, struct drm_framebuffer *fb)
8388 {
8389         struct drm_device *dev = crtc->dev;
8390         drm_i915_private_t *dev_priv = dev->dev_private;
8391         struct drm_display_mode *saved_mode, *saved_hwmode;
8392         struct intel_crtc_config *pipe_config = NULL;
8393         struct intel_crtc *intel_crtc;
8394         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8395         int ret = 0;
8396
8397         saved_mode = kmalloc(2 * sizeof(*saved_mode), M_DRM, M_WAITOK);
8398         if (!saved_mode)
8399                 return -ENOMEM;
8400         saved_hwmode = saved_mode + 1;
8401
8402         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8403                                      &prepare_pipes, &disable_pipes);
8404
8405         *saved_hwmode = crtc->hwmode;
8406         *saved_mode = crtc->mode;
8407
8408         /* Hack: Because we don't (yet) support global modeset on multiple
8409          * crtcs, we don't keep track of the new mode for more than one crtc.
8410          * Hence simply check whether any bit is set in modeset_pipes in all the
8411          * pieces of code that are not yet converted to deal with mutliple crtcs
8412          * changing their mode at the same time. */
8413         if (modeset_pipes) {
8414                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8415                 if (IS_ERR(pipe_config)) {
8416                         ret = PTR_ERR(pipe_config);
8417                         pipe_config = NULL;
8418
8419                         goto out;
8420                 }
8421                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8422                                        "[modeset]");
8423         }
8424
8425         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8426                 intel_crtc_disable(&intel_crtc->base);
8427
8428         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8429                 if (intel_crtc->base.enabled)
8430                         dev_priv->display.crtc_disable(&intel_crtc->base);
8431         }
8432
8433         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8434          * to set it here already despite that we pass it down the callchain.
8435          */
8436         if (modeset_pipes) {
8437                 crtc->mode = *mode;
8438                 /* mode_set/enable/disable functions rely on a correct pipe
8439                  * config. */
8440                 to_intel_crtc(crtc)->config = *pipe_config;
8441         }
8442
8443         /* Only after disabling all output pipelines that will be changed can we
8444          * update the the output configuration. */
8445         intel_modeset_update_state(dev, prepare_pipes);
8446
8447         if (dev_priv->display.modeset_global_resources)
8448                 dev_priv->display.modeset_global_resources(dev);
8449
8450         /* Set up the DPLL and any encoders state that needs to adjust or depend
8451          * on the DPLL.
8452          */
8453         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8454                 ret = intel_crtc_mode_set(&intel_crtc->base,
8455                                           x, y, fb);
8456                 if (ret)
8457                         goto done;
8458         }
8459
8460         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8461         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8462                 dev_priv->display.crtc_enable(&intel_crtc->base);
8463
8464         if (modeset_pipes) {
8465                 /* Store real post-adjustment hardware mode. */
8466                 crtc->hwmode = pipe_config->adjusted_mode;
8467
8468                 /* Calculate and store various constants which
8469                  * are later needed by vblank and swap-completion
8470                  * timestamping. They are derived from true hwmode.
8471                  */
8472                 drm_calc_timestamping_constants(crtc);
8473         }
8474
8475         /* FIXME: add subpixel order */
8476 done:
8477         if (ret && crtc->enabled) {
8478                 crtc->hwmode = *saved_hwmode;
8479                 crtc->mode = *saved_mode;
8480         }
8481
8482 out:
8483         kfree(pipe_config);
8484         kfree(saved_mode);
8485         return ret;
8486 }
8487
8488 int intel_set_mode(struct drm_crtc *crtc,
8489                      struct drm_display_mode *mode,
8490                      int x, int y, struct drm_framebuffer *fb)
8491 {
8492         int ret;
8493
8494         ret = __intel_set_mode(crtc, mode, x, y, fb);
8495
8496         if (ret == 0)
8497                 intel_modeset_check_state(crtc->dev);
8498
8499         return ret;
8500 }
8501
8502 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8503 {
8504         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8505 }
8506
8507 #undef for_each_intel_crtc_masked
8508
8509 static void intel_set_config_free(struct intel_set_config *config)
8510 {
8511         if (!config)
8512                 return;
8513
8514         kfree(config->save_connector_encoders);
8515         kfree(config->save_encoder_crtcs);
8516         kfree(config);
8517 }
8518
8519 static int intel_set_config_save_state(struct drm_device *dev,
8520                                        struct intel_set_config *config)
8521 {
8522         struct drm_encoder *encoder;
8523         struct drm_connector *connector;
8524         int count;
8525
8526         config->save_encoder_crtcs =
8527                 kmalloc(dev->mode_config.num_encoder *
8528                         sizeof(struct drm_crtc *), M_DRM, M_WAITOK | M_ZERO );
8529         if (!config->save_encoder_crtcs)
8530                 return -ENOMEM;
8531
8532         config->save_connector_encoders =
8533                 kmalloc(dev->mode_config.num_connector *
8534                         sizeof(struct drm_encoder *), M_DRM, M_WAITOK | M_ZERO );
8535         if (!config->save_connector_encoders)
8536                 return -ENOMEM;
8537
8538         /* Copy data. Note that driver private data is not affected.
8539          * Should anything bad happen only the expected state is
8540          * restored, not the drivers personal bookkeeping.
8541          */
8542         count = 0;
8543         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8544                 config->save_encoder_crtcs[count++] = encoder->crtc;
8545         }
8546
8547         count = 0;
8548         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8549                 config->save_connector_encoders[count++] = connector->encoder;
8550         }
8551
8552         return 0;
8553 }
8554
8555 static void intel_set_config_restore_state(struct drm_device *dev,
8556                                            struct intel_set_config *config)
8557 {
8558         struct intel_encoder *encoder;
8559         struct intel_connector *connector;
8560         int count;
8561
8562         count = 0;
8563         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8564                 encoder->new_crtc =
8565                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8566         }
8567
8568         count = 0;
8569         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8570                 connector->new_encoder =
8571                         to_intel_encoder(config->save_connector_encoders[count++]);
8572         }
8573 }
8574
8575 static bool
8576 is_crtc_connector_off(struct drm_mode_set *set)
8577 {
8578         int i;
8579
8580         if (set->num_connectors == 0)
8581                 return false;
8582
8583         if (WARN_ON(set->connectors == NULL))
8584                 return false;
8585
8586         for (i = 0; i < set->num_connectors; i++)
8587                 if (set->connectors[i]->encoder &&
8588                     set->connectors[i]->encoder->crtc == set->crtc &&
8589                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
8590                         return true;
8591
8592         return false;
8593 }
8594
8595 static void
8596 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8597                                       struct intel_set_config *config)
8598 {
8599
8600         /* We should be able to check here if the fb has the same properties
8601          * and then just flip_or_move it */
8602         if (is_crtc_connector_off(set)) {
8603                 config->mode_changed = true;
8604         } else if (set->crtc->fb != set->fb) {
8605                 /* If we have no fb then treat it as a full mode set */
8606                 if (set->crtc->fb == NULL) {
8607                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8608                         config->mode_changed = true;
8609                 } else if (set->fb == NULL) {
8610                         config->mode_changed = true;
8611                 } else if (set->fb->pixel_format !=
8612                            set->crtc->fb->pixel_format) {
8613                         config->mode_changed = true;
8614                 } else {
8615                         config->fb_changed = true;
8616                 }
8617         }
8618
8619         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8620                 config->fb_changed = true;
8621
8622         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8623                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8624                 drm_mode_debug_printmodeline(&set->crtc->mode);
8625                 drm_mode_debug_printmodeline(set->mode);
8626                 config->mode_changed = true;
8627         }
8628 }
8629
8630 static int
8631 intel_modeset_stage_output_state(struct drm_device *dev,
8632                                  struct drm_mode_set *set,
8633                                  struct intel_set_config *config)
8634 {
8635         struct drm_crtc *new_crtc;
8636         struct intel_connector *connector;
8637         struct intel_encoder *encoder;
8638         int count, ro;
8639
8640         /* The upper layers ensure that we either disable a crtc or have a list
8641          * of connectors. For paranoia, double-check this. */
8642         WARN_ON(!set->fb && (set->num_connectors != 0));
8643         WARN_ON(set->fb && (set->num_connectors == 0));
8644
8645         count = 0;
8646         list_for_each_entry(connector, &dev->mode_config.connector_list,
8647                             base.head) {
8648                 /* Otherwise traverse passed in connector list and get encoders
8649                  * for them. */
8650                 for (ro = 0; ro < set->num_connectors; ro++) {
8651                         if (set->connectors[ro] == &connector->base) {
8652                                 connector->new_encoder = connector->encoder;
8653                                 break;
8654                         }
8655                 }
8656
8657                 /* If we disable the crtc, disable all its connectors. Also, if
8658                  * the connector is on the changing crtc but not on the new
8659                  * connector list, disable it. */
8660                 if ((!set->fb || ro == set->num_connectors) &&
8661                     connector->base.encoder &&
8662                     connector->base.encoder->crtc == set->crtc) {
8663                         connector->new_encoder = NULL;
8664
8665                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8666                                 connector->base.base.id,
8667                                 drm_get_connector_name(&connector->base));
8668                 }
8669
8670
8671                 if (&connector->new_encoder->base != connector->base.encoder) {
8672                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8673                         config->mode_changed = true;
8674                 }
8675         }
8676         /* connector->new_encoder is now updated for all connectors. */
8677
8678         /* Update crtc of enabled connectors. */
8679         count = 0;
8680         list_for_each_entry(connector, &dev->mode_config.connector_list,
8681                             base.head) {
8682                 if (!connector->new_encoder)
8683                         continue;
8684
8685                 new_crtc = connector->new_encoder->base.crtc;
8686
8687                 for (ro = 0; ro < set->num_connectors; ro++) {
8688                         if (set->connectors[ro] == &connector->base)
8689                                 new_crtc = set->crtc;
8690                 }
8691
8692                 /* Make sure the new CRTC will work with the encoder */
8693                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8694                                            new_crtc)) {
8695                         return -EINVAL;
8696                 }
8697                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8698
8699                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8700                         connector->base.base.id,
8701                         drm_get_connector_name(&connector->base),
8702                         new_crtc->base.id);
8703         }
8704
8705         /* Check for any encoders that needs to be disabled. */
8706         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8707                             base.head) {
8708                 list_for_each_entry(connector,
8709                                     &dev->mode_config.connector_list,
8710                                     base.head) {
8711                         if (connector->new_encoder == encoder) {
8712                                 WARN_ON(!connector->new_encoder->new_crtc);
8713
8714                                 goto next_encoder;
8715                         }
8716                 }
8717                 encoder->new_crtc = NULL;
8718 next_encoder:
8719                 /* Only now check for crtc changes so we don't miss encoders
8720                  * that will be disabled. */
8721                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8722                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8723                         config->mode_changed = true;
8724                 }
8725         }
8726         /* Now we've also updated encoder->new_crtc for all encoders. */
8727
8728         return 0;
8729 }
8730
8731 static int intel_crtc_set_config(struct drm_mode_set *set)
8732 {
8733         struct drm_device *dev;
8734         struct drm_mode_set save_set;
8735         struct intel_set_config *config;
8736         int ret;
8737
8738         BUG_ON(!set);
8739         BUG_ON(!set->crtc);
8740         BUG_ON(!set->crtc->helper_private);
8741
8742         /* Enforce sane interface api - has been abused by the fb helper. */
8743         BUG_ON(!set->mode && set->fb);
8744         BUG_ON(set->fb && set->num_connectors == 0);
8745
8746         if (set->fb) {
8747                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8748                                 set->crtc->base.id, set->fb->base.id,
8749                                 (int)set->num_connectors, set->x, set->y);
8750         } else {
8751                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8752         }
8753
8754         dev = set->crtc->dev;
8755
8756         ret = -ENOMEM;
8757         config = kzalloc(sizeof(*config), GFP_KERNEL);
8758         if (!config)
8759                 goto out_config;
8760
8761         ret = intel_set_config_save_state(dev, config);
8762         if (ret)
8763                 goto out_config;
8764
8765         save_set.crtc = set->crtc;
8766         save_set.mode = &set->crtc->mode;
8767         save_set.x = set->crtc->x;
8768         save_set.y = set->crtc->y;
8769         save_set.fb = set->crtc->fb;
8770
8771         /* Compute whether we need a full modeset, only an fb base update or no
8772          * change at all. In the future we might also check whether only the
8773          * mode changed, e.g. for LVDS where we only change the panel fitter in
8774          * such cases. */
8775         intel_set_config_compute_mode_changes(set, config);
8776
8777         ret = intel_modeset_stage_output_state(dev, set, config);
8778         if (ret)
8779                 goto fail;
8780
8781         if (config->mode_changed) {
8782                 ret = intel_set_mode(set->crtc, set->mode,
8783                                      set->x, set->y, set->fb);
8784         } else if (config->fb_changed) {
8785                 intel_crtc_wait_for_pending_flips(set->crtc);
8786
8787                 ret = intel_pipe_set_base(set->crtc,
8788                                           set->x, set->y, set->fb);
8789         }
8790
8791         if (ret) {
8792                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8793                               set->crtc->base.id, ret);
8794 fail:
8795                 intel_set_config_restore_state(dev, config);
8796
8797                 /* Try to restore the config */
8798                 if (config->mode_changed &&
8799                     intel_set_mode(save_set.crtc, save_set.mode,
8800                                    save_set.x, save_set.y, save_set.fb))
8801                         DRM_ERROR("failed to restore config after modeset failure\n");
8802         }
8803
8804 out_config:
8805         intel_set_config_free(config);
8806         return ret;
8807 }
8808
8809 static const struct drm_crtc_funcs intel_crtc_funcs = {
8810         .cursor_set = intel_crtc_cursor_set,
8811         .cursor_move = intel_crtc_cursor_move,
8812         .gamma_set = intel_crtc_gamma_set,
8813         .set_config = intel_crtc_set_config,
8814         .destroy = intel_crtc_destroy,
8815         .page_flip = intel_crtc_page_flip,
8816 };
8817
8818 static void intel_cpu_pll_init(struct drm_device *dev)
8819 {
8820         if (HAS_DDI(dev))
8821                 intel_ddi_pll_init(dev);
8822 }
8823
8824 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8825                                       struct intel_shared_dpll *pll,
8826                                       struct intel_dpll_hw_state *hw_state)
8827 {
8828         uint32_t val;
8829
8830         val = I915_READ(PCH_DPLL(pll->id));
8831         hw_state->dpll = val;
8832         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8833         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8834
8835         return val & DPLL_VCO_ENABLE;
8836 }
8837
8838 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8839                                 struct intel_shared_dpll *pll)
8840 {
8841         uint32_t reg, val;
8842
8843         /* PCH refclock must be enabled first */
8844         assert_pch_refclk_enabled(dev_priv);
8845
8846         reg = PCH_DPLL(pll->id);
8847         val = I915_READ(reg);
8848         val |= DPLL_VCO_ENABLE;
8849         I915_WRITE(reg, val);
8850         POSTING_READ(reg);
8851         udelay(200);
8852 }
8853
8854 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8855                                  struct intel_shared_dpll *pll)
8856 {
8857         struct drm_device *dev = dev_priv->dev;
8858         struct intel_crtc *crtc;
8859         uint32_t reg, val;
8860
8861         /* Make sure no transcoder isn't still depending on us. */
8862         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8863                 if (intel_crtc_to_shared_dpll(crtc) == pll)
8864                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8865         }
8866
8867         reg = PCH_DPLL(pll->id);
8868         val = I915_READ(reg);
8869         val &= ~DPLL_VCO_ENABLE;
8870         I915_WRITE(reg, val);
8871         POSTING_READ(reg);
8872         udelay(200);
8873 }
8874
8875 static char *ibx_pch_dpll_names[] = {
8876         "PCH DPLL A",
8877         "PCH DPLL B",
8878 };
8879
8880 static void ibx_pch_dpll_init(struct drm_device *dev)
8881 {
8882         struct drm_i915_private *dev_priv = dev->dev_private;
8883         int i;
8884
8885         dev_priv->num_shared_dpll = 2;
8886
8887         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8888                 dev_priv->shared_dplls[i].id = i;
8889                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8890                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8891                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8892                 dev_priv->shared_dplls[i].get_hw_state =
8893                         ibx_pch_dpll_get_hw_state;
8894         }
8895 }
8896
8897 static void intel_shared_dpll_init(struct drm_device *dev)
8898 {
8899         struct drm_i915_private *dev_priv = dev->dev_private;
8900
8901         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8902                 ibx_pch_dpll_init(dev);
8903         else
8904                 dev_priv->num_shared_dpll = 0;
8905
8906         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8907         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8908                       dev_priv->num_shared_dpll);
8909 }
8910
8911 static void intel_crtc_init(struct drm_device *dev, int pipe)
8912 {
8913         drm_i915_private_t *dev_priv = dev->dev_private;
8914         struct intel_crtc *intel_crtc;
8915         int i;
8916
8917         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8918         if (intel_crtc == NULL)
8919                 return;
8920
8921         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8922
8923         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8924         for (i = 0; i < 256; i++) {
8925                 intel_crtc->lut_r[i] = i;
8926                 intel_crtc->lut_g[i] = i;
8927                 intel_crtc->lut_b[i] = i;
8928         }
8929
8930         /* Swap pipes & planes for FBC on pre-965 */
8931         intel_crtc->pipe = pipe;
8932         intel_crtc->plane = pipe;
8933         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8934                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8935                 intel_crtc->plane = !pipe;
8936         }
8937
8938         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8939                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8940         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8941         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8942
8943         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8944 }
8945
8946 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8947                                 struct drm_file *file)
8948 {
8949         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8950         struct drm_mode_object *drmmode_obj;
8951         struct intel_crtc *crtc;
8952
8953         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8954                 return -ENODEV;
8955
8956         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8957                         DRM_MODE_OBJECT_CRTC);
8958
8959         if (!drmmode_obj) {
8960                 DRM_ERROR("no such CRTC id\n");
8961                 return -EINVAL;
8962         }
8963
8964         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8965         pipe_from_crtc_id->pipe = crtc->pipe;
8966
8967         return 0;
8968 }
8969
8970 static int intel_encoder_clones(struct intel_encoder *encoder)
8971 {
8972         struct drm_device *dev = encoder->base.dev;
8973         struct intel_encoder *source_encoder;
8974         int index_mask = 0;
8975         int entry = 0;
8976
8977         list_for_each_entry(source_encoder,
8978                             &dev->mode_config.encoder_list, base.head) {
8979
8980                 if (encoder == source_encoder)
8981                         index_mask |= (1 << entry);
8982
8983                 /* Intel hw has only one MUX where enocoders could be cloned. */
8984                 if (encoder->cloneable && source_encoder->cloneable)
8985                         index_mask |= (1 << entry);
8986
8987                 entry++;
8988         }
8989
8990         return index_mask;
8991 }
8992
8993 static bool has_edp_a(struct drm_device *dev)
8994 {
8995         struct drm_i915_private *dev_priv = dev->dev_private;
8996
8997         if (!IS_MOBILE(dev))
8998                 return false;
8999
9000         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9001                 return false;
9002
9003         if (IS_GEN5(dev) &&
9004             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9005                 return false;
9006
9007         return true;
9008 }
9009
9010 static void intel_setup_outputs(struct drm_device *dev)
9011 {
9012         struct drm_i915_private *dev_priv = dev->dev_private;
9013         struct intel_encoder *encoder;
9014         bool dpd_is_edp = false;
9015
9016         intel_lvds_init(dev);
9017
9018         if (!IS_ULT(dev))
9019                 intel_crt_init(dev);
9020
9021         if (HAS_DDI(dev)) {
9022                 int found;
9023
9024                 /* Haswell uses DDI functions to detect digital outputs */
9025                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9026                 /* DDI A only supports eDP */
9027                 if (found)
9028                         intel_ddi_init(dev, PORT_A);
9029
9030                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9031                  * register */
9032                 found = I915_READ(SFUSE_STRAP);
9033
9034                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9035                         intel_ddi_init(dev, PORT_B);
9036                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9037                         intel_ddi_init(dev, PORT_C);
9038                 if (found & SFUSE_STRAP_DDID_DETECTED)
9039                         intel_ddi_init(dev, PORT_D);
9040         } else if (HAS_PCH_SPLIT(dev)) {
9041                 int found;
9042                 dpd_is_edp = intel_dpd_is_edp(dev);
9043
9044                 if (has_edp_a(dev))
9045                         intel_dp_init(dev, DP_A, PORT_A);
9046
9047                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9048                         /* PCH SDVOB multiplex with HDMIB */
9049                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9050                         if (!found)
9051                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9052                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9053                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9054                 }
9055
9056                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9057                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9058
9059                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9060                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9061
9062                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9063                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9064
9065                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9066                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9067         } else if (IS_VALLEYVIEW(dev)) {
9068                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9069                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9070                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9071
9072                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9073                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9074                                         PORT_B);
9075                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9076                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9077                 }
9078         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9079                 bool found = false;
9080
9081                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9082                         DRM_DEBUG_KMS("probing SDVOB\n");
9083                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9084                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9085                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9086                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9087                         }
9088
9089                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9090                                 intel_dp_init(dev, DP_B, PORT_B);
9091                 }
9092
9093                 /* Before G4X SDVOC doesn't have its own detect register */
9094
9095                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9096                         DRM_DEBUG_KMS("probing SDVOC\n");
9097                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9098                 }
9099
9100                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9101
9102                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9103                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9104                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9105                         }
9106                         if (SUPPORTS_INTEGRATED_DP(dev))
9107                                 intel_dp_init(dev, DP_C, PORT_C);
9108                 }
9109
9110                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9111                     (I915_READ(DP_D) & DP_DETECTED))
9112                         intel_dp_init(dev, DP_D, PORT_D);
9113         } else if (IS_GEN2(dev)) {
9114 #if 0
9115                 intel_dvo_init(dev);
9116 #endif
9117         }
9118
9119         if (SUPPORTS_TV(dev))
9120                 intel_tv_init(dev);
9121
9122         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9123                 encoder->base.possible_crtcs = encoder->crtc_mask;
9124                 encoder->base.possible_clones =
9125                         intel_encoder_clones(encoder);
9126         }
9127
9128         intel_init_pch_refclk(dev);
9129
9130         drm_helper_move_panel_connectors_to_head(dev);
9131 }
9132
9133 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9134 {
9135         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9136
9137         drm_framebuffer_cleanup(fb);
9138         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9139
9140         kfree(intel_fb);
9141 }
9142
9143 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9144                                                 struct drm_file *file,
9145                                                 unsigned int *handle)
9146 {
9147         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9148         struct drm_i915_gem_object *obj = intel_fb->obj;
9149
9150         return drm_gem_handle_create(file, &obj->base, handle);
9151 }
9152
9153 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9154         .destroy = intel_user_framebuffer_destroy,
9155         .create_handle = intel_user_framebuffer_create_handle,
9156 };
9157
9158 int intel_framebuffer_init(struct drm_device *dev,
9159                            struct intel_framebuffer *intel_fb,
9160                            struct drm_mode_fb_cmd2 *mode_cmd,
9161                            struct drm_i915_gem_object *obj)
9162 {
9163         int pitch_limit;
9164         int ret;
9165
9166         if (obj->tiling_mode == I915_TILING_Y) {
9167                 DRM_DEBUG("hardware does not support tiling Y\n");
9168                 return -EINVAL;
9169         }
9170
9171         if (mode_cmd->pitches[0] & 63) {
9172                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9173                           mode_cmd->pitches[0]);
9174                 return -EINVAL;
9175         }
9176
9177         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9178                 pitch_limit = 32*1024;
9179         } else if (INTEL_INFO(dev)->gen >= 4) {
9180                 if (obj->tiling_mode)
9181                         pitch_limit = 16*1024;
9182                 else
9183                         pitch_limit = 32*1024;
9184         } else if (INTEL_INFO(dev)->gen >= 3) {
9185                 if (obj->tiling_mode)
9186                         pitch_limit = 8*1024;
9187                 else
9188                         pitch_limit = 16*1024;
9189         } else
9190                 /* XXX DSPC is limited to 4k tiled */
9191                 pitch_limit = 8*1024;
9192
9193         if (mode_cmd->pitches[0] > pitch_limit) {
9194                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9195                           obj->tiling_mode ? "tiled" : "linear",
9196                           mode_cmd->pitches[0], pitch_limit);
9197                 return -EINVAL;
9198         }
9199
9200         if (obj->tiling_mode != I915_TILING_NONE &&
9201             mode_cmd->pitches[0] != obj->stride) {
9202                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9203                           mode_cmd->pitches[0], obj->stride);
9204                 return -EINVAL;
9205         }
9206
9207         /* Reject formats not supported by any plane early. */
9208         switch (mode_cmd->pixel_format) {
9209         case DRM_FORMAT_C8:
9210         case DRM_FORMAT_RGB565:
9211         case DRM_FORMAT_XRGB8888:
9212         case DRM_FORMAT_ARGB8888:
9213                 break;
9214         case DRM_FORMAT_XRGB1555:
9215         case DRM_FORMAT_ARGB1555:
9216                 if (INTEL_INFO(dev)->gen > 3) {
9217                         DRM_DEBUG("unsupported pixel format: %s\n",
9218                                   drm_get_format_name(mode_cmd->pixel_format));
9219                         return -EINVAL;
9220                 }
9221                 break;
9222         case DRM_FORMAT_XBGR8888:
9223         case DRM_FORMAT_ABGR8888:
9224         case DRM_FORMAT_XRGB2101010:
9225         case DRM_FORMAT_ARGB2101010:
9226         case DRM_FORMAT_XBGR2101010:
9227         case DRM_FORMAT_ABGR2101010:
9228                 if (INTEL_INFO(dev)->gen < 4) {
9229                         DRM_DEBUG("unsupported pixel format: %s\n",
9230                                   drm_get_format_name(mode_cmd->pixel_format));
9231                         return -EINVAL;
9232                 }
9233                 break;
9234         case DRM_FORMAT_YUYV:
9235         case DRM_FORMAT_UYVY:
9236         case DRM_FORMAT_YVYU:
9237         case DRM_FORMAT_VYUY:
9238                 if (INTEL_INFO(dev)->gen < 5) {
9239                         DRM_DEBUG("unsupported pixel format: %s\n",
9240                                   drm_get_format_name(mode_cmd->pixel_format));
9241                         return -EINVAL;
9242                 }
9243                 break;
9244         default:
9245                 DRM_DEBUG("unsupported pixel format: %s\n",
9246                           drm_get_format_name(mode_cmd->pixel_format));
9247                 return -EINVAL;
9248         }
9249
9250         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9251         if (mode_cmd->offsets[0] != 0)
9252                 return -EINVAL;
9253
9254         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9255         intel_fb->obj = obj;
9256
9257         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9258         if (ret) {
9259                 DRM_ERROR("framebuffer init failed %d\n", ret);
9260                 return ret;
9261         }
9262
9263         return 0;
9264 }
9265
9266 static struct drm_framebuffer *
9267 intel_user_framebuffer_create(struct drm_device *dev,
9268                               struct drm_file *filp,
9269                               struct drm_mode_fb_cmd2 *mode_cmd)
9270 {
9271         struct drm_i915_gem_object *obj;
9272
9273         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9274                                                 mode_cmd->handles[0]));
9275         if (&obj->base == NULL)
9276                 return ERR_PTR(-ENOENT);
9277
9278         return intel_framebuffer_create(dev, mode_cmd, obj);
9279 }
9280
9281 static const struct drm_mode_config_funcs intel_mode_funcs = {
9282         .fb_create = intel_user_framebuffer_create,
9283         .output_poll_changed = intel_fb_output_poll_changed,
9284 };
9285
9286 /* Set up chip specific display functions */
9287 static void intel_init_display(struct drm_device *dev)
9288 {
9289         struct drm_i915_private *dev_priv = dev->dev_private;
9290
9291         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9292                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9293         else if (IS_VALLEYVIEW(dev))
9294                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9295         else if (IS_PINEVIEW(dev))
9296                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9297         else
9298                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9299
9300         if (HAS_DDI(dev)) {
9301                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9302                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9303                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9304                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9305                 dev_priv->display.off = haswell_crtc_off;
9306                 dev_priv->display.update_plane = ironlake_update_plane;
9307         } else if (HAS_PCH_SPLIT(dev)) {
9308                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9309                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9310                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9311                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9312                 dev_priv->display.off = ironlake_crtc_off;
9313                 dev_priv->display.update_plane = ironlake_update_plane;
9314         } else if (IS_VALLEYVIEW(dev)) {
9315                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9316                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9317                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9318                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9319                 dev_priv->display.off = i9xx_crtc_off;
9320                 dev_priv->display.update_plane = i9xx_update_plane;
9321         } else {
9322                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9323                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9324                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9325                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9326                 dev_priv->display.off = i9xx_crtc_off;
9327                 dev_priv->display.update_plane = i9xx_update_plane;
9328         }
9329
9330         /* Returns the core display clock speed */
9331         if (IS_VALLEYVIEW(dev))
9332                 dev_priv->display.get_display_clock_speed =
9333                         valleyview_get_display_clock_speed;
9334         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9335                 dev_priv->display.get_display_clock_speed =
9336                         i945_get_display_clock_speed;
9337         else if (IS_I915G(dev))
9338                 dev_priv->display.get_display_clock_speed =
9339                         i915_get_display_clock_speed;
9340         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9341                 dev_priv->display.get_display_clock_speed =
9342                         i9xx_misc_get_display_clock_speed;
9343         else if (IS_I915GM(dev))
9344                 dev_priv->display.get_display_clock_speed =
9345                         i915gm_get_display_clock_speed;
9346         else if (IS_I865G(dev))
9347                 dev_priv->display.get_display_clock_speed =
9348                         i865_get_display_clock_speed;
9349         else if (IS_I85X(dev))
9350                 dev_priv->display.get_display_clock_speed =
9351                         i855_get_display_clock_speed;
9352         else /* 852, 830 */
9353                 dev_priv->display.get_display_clock_speed =
9354                         i830_get_display_clock_speed;
9355
9356         if (HAS_PCH_SPLIT(dev)) {
9357                 if (IS_GEN5(dev)) {
9358                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9359                         dev_priv->display.write_eld = ironlake_write_eld;
9360                 } else if (IS_GEN6(dev)) {
9361                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9362                         dev_priv->display.write_eld = ironlake_write_eld;
9363                 } else if (IS_IVYBRIDGE(dev)) {
9364                         /* FIXME: detect B0+ stepping and use auto training */
9365                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9366                         dev_priv->display.write_eld = ironlake_write_eld;
9367                         dev_priv->display.modeset_global_resources =
9368                                 ivb_modeset_global_resources;
9369                 } else if (IS_HASWELL(dev)) {
9370                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9371                         dev_priv->display.write_eld = haswell_write_eld;
9372                         dev_priv->display.modeset_global_resources =
9373                                 haswell_modeset_global_resources;
9374                 }
9375         } else if (IS_G4X(dev)) {
9376                 dev_priv->display.write_eld = g4x_write_eld;
9377         }
9378
9379         /* Default just returns -ENODEV to indicate unsupported */
9380         dev_priv->display.queue_flip = intel_default_queue_flip;
9381
9382         switch (INTEL_INFO(dev)->gen) {
9383         case 2:
9384                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9385                 break;
9386
9387         case 3:
9388                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9389                 break;
9390
9391         case 4:
9392         case 5:
9393                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9394                 break;
9395
9396         case 6:
9397                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9398                 break;
9399         case 7:
9400                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9401                 break;
9402         }
9403 }
9404
9405 /*
9406  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9407  * resume, or other times.  This quirk makes sure that's the case for
9408  * affected systems.
9409  */
9410 static void quirk_pipea_force(struct drm_device *dev)
9411 {
9412         struct drm_i915_private *dev_priv = dev->dev_private;
9413
9414         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9415         DRM_INFO("applying pipe a force quirk\n");
9416 }
9417
9418 /*
9419  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9420  */
9421 static void quirk_ssc_force_disable(struct drm_device *dev)
9422 {
9423         struct drm_i915_private *dev_priv = dev->dev_private;
9424         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9425         DRM_INFO("applying lvds SSC disable quirk\n");
9426 }
9427
9428 /*
9429  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9430  * brightness value
9431  */
9432 static void quirk_invert_brightness(struct drm_device *dev)
9433 {
9434         struct drm_i915_private *dev_priv = dev->dev_private;
9435         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9436         DRM_INFO("applying inverted panel brightness quirk\n");
9437 }
9438
9439 /*
9440  * Some machines (Dell XPS13) suffer broken backlight controls if
9441  * BLM_PCH_PWM_ENABLE is set.
9442  */
9443 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9444 {
9445         struct drm_i915_private *dev_priv = dev->dev_private;
9446         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9447         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9448 }
9449
9450 struct intel_quirk {
9451         int device;
9452         int subsystem_vendor;
9453         int subsystem_device;
9454         void (*hook)(struct drm_device *dev);
9455 };
9456
9457 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9458 struct intel_dmi_quirk {
9459         void (*hook)(struct drm_device *dev);
9460         const struct dmi_system_id (*dmi_id_list)[];
9461 };
9462
9463 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9464 {
9465         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9466         return 1;
9467 }
9468
9469 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9470         {
9471                 .dmi_id_list = &(const struct dmi_system_id[]) {
9472                         {
9473                                 .callback = intel_dmi_reverse_brightness,
9474                                 .ident = "NCR Corporation",
9475                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9476                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9477                                 },
9478                         },
9479                         { }  /* terminating entry */
9480                 },
9481                 .hook = quirk_invert_brightness,
9482         },
9483 };
9484
9485 static struct intel_quirk intel_quirks[] = {
9486         /* HP Mini needs pipe A force quirk (LP: #322104) */
9487         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9488
9489         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9490         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9491
9492         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9493         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9494
9495         /* 830/845 need to leave pipe A & dpll A up */
9496         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9497         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9498
9499         /* Lenovo U160 cannot use SSC on LVDS */
9500         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9501
9502         /* Sony Vaio Y cannot use SSC on LVDS */
9503         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9504
9505         /* Acer Aspire 5734Z must invert backlight brightness */
9506         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9507
9508         /* Acer/eMachines G725 */
9509         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9510
9511         /* Acer/eMachines e725 */
9512         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9513
9514         /* Acer/Packard Bell NCL20 */
9515         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9516
9517         /* Acer Aspire 4736Z */
9518         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9519
9520         /* Dell XPS13 HD Sandy Bridge */
9521         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
9522         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
9523         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
9524 };
9525
9526 static void intel_init_quirks(struct drm_device *dev)
9527 {
9528         struct device *d = dev->dev;
9529         int i;
9530
9531         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9532                 struct intel_quirk *q = &intel_quirks[i];
9533
9534                 if (pci_get_device(d) == q->device &&
9535                     (pci_get_subvendor(d) == q->subsystem_vendor ||
9536                      q->subsystem_vendor == PCI_ANY_ID) &&
9537                     (pci_get_subdevice(d) == q->subsystem_device ||
9538                      q->subsystem_device == PCI_ANY_ID))
9539                         q->hook(dev);
9540         }
9541         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9542                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9543                         intel_dmi_quirks[i].hook(dev);
9544         }
9545 }
9546
9547 /* Disable the VGA plane that we never use */
9548 static void i915_disable_vga(struct drm_device *dev)
9549 {
9550         struct drm_i915_private *dev_priv = dev->dev_private;
9551         u8 sr1;
9552         u32 vga_reg = i915_vgacntrl_reg(dev);
9553
9554 #if 0
9555         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9556 #endif
9557         outb(VGA_SR_INDEX, SR01);
9558         sr1 = inb(VGA_SR_DATA);
9559         outb(VGA_SR_DATA, sr1 | 1 << 5);
9560 #if 0
9561         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9562 #endif
9563         udelay(300);
9564
9565         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9566         POSTING_READ(vga_reg);
9567 }
9568
9569 void intel_modeset_init_hw(struct drm_device *dev)
9570 {
9571         intel_init_power_well(dev);
9572
9573         intel_prepare_ddi(dev);
9574
9575         intel_init_clock_gating(dev);
9576
9577         mutex_lock(&dev->struct_mutex);
9578         intel_enable_gt_powersave(dev);
9579         mutex_unlock(&dev->struct_mutex);
9580 }
9581
9582 void intel_modeset_suspend_hw(struct drm_device *dev)
9583 {
9584         intel_suspend_hw(dev);
9585 }
9586
9587 void intel_modeset_init(struct drm_device *dev)
9588 {
9589         struct drm_i915_private *dev_priv = dev->dev_private;
9590         int i, j, ret;
9591
9592         drm_mode_config_init(dev);
9593
9594         dev->mode_config.min_width = 0;
9595         dev->mode_config.min_height = 0;
9596
9597         dev->mode_config.preferred_depth = 24;
9598         dev->mode_config.prefer_shadow = 1;
9599
9600         dev->mode_config.funcs = &intel_mode_funcs;
9601
9602         intel_init_quirks(dev);
9603
9604         intel_init_pm(dev);
9605
9606         if (INTEL_INFO(dev)->num_pipes == 0)
9607                 return;
9608
9609         intel_init_display(dev);
9610
9611         if (IS_GEN2(dev)) {
9612                 dev->mode_config.max_width = 2048;
9613                 dev->mode_config.max_height = 2048;
9614         } else if (IS_GEN3(dev)) {
9615                 dev->mode_config.max_width = 4096;
9616                 dev->mode_config.max_height = 4096;
9617         } else {
9618                 dev->mode_config.max_width = 8192;
9619                 dev->mode_config.max_height = 8192;
9620         }
9621         dev->mode_config.fb_base = dev->agp->base;
9622
9623         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9624                       INTEL_INFO(dev)->num_pipes,
9625                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9626
9627         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9628                 intel_crtc_init(dev, i);
9629                 for (j = 0; j < dev_priv->num_plane; j++) {
9630                         ret = intel_plane_init(dev, i, j);
9631                         if (ret)
9632                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9633                                               pipe_name(i), sprite_name(i, j), ret);
9634                 }
9635         }
9636
9637         intel_cpu_pll_init(dev);
9638         intel_shared_dpll_init(dev);
9639
9640         /* Just disable it once at startup */
9641         i915_disable_vga(dev);
9642         intel_setup_outputs(dev);
9643
9644         /* Just in case the BIOS is doing something questionable. */
9645         intel_disable_fbc(dev);
9646 }
9647
9648 static void
9649 intel_connector_break_all_links(struct intel_connector *connector)
9650 {
9651         connector->base.dpms = DRM_MODE_DPMS_OFF;
9652         connector->base.encoder = NULL;
9653         connector->encoder->connectors_active = false;
9654         connector->encoder->base.crtc = NULL;
9655 }
9656
9657 static void intel_enable_pipe_a(struct drm_device *dev)
9658 {
9659         struct intel_connector *connector;
9660         struct drm_connector *crt = NULL;
9661         struct intel_load_detect_pipe load_detect_temp;
9662
9663         /* We can't just switch on the pipe A, we need to set things up with a
9664          * proper mode and output configuration. As a gross hack, enable pipe A
9665          * by enabling the load detect pipe once. */
9666         list_for_each_entry(connector,
9667                             &dev->mode_config.connector_list,
9668                             base.head) {
9669                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9670                         crt = &connector->base;
9671                         break;
9672                 }
9673         }
9674
9675         if (!crt)
9676                 return;
9677
9678         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9679                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9680
9681
9682 }
9683
9684 static bool
9685 intel_check_plane_mapping(struct intel_crtc *crtc)
9686 {
9687         struct drm_device *dev = crtc->base.dev;
9688         struct drm_i915_private *dev_priv = dev->dev_private;
9689         u32 reg, val;
9690
9691         if (INTEL_INFO(dev)->num_pipes == 1)
9692                 return true;
9693
9694         reg = DSPCNTR(!crtc->plane);
9695         val = I915_READ(reg);
9696
9697         if ((val & DISPLAY_PLANE_ENABLE) &&
9698             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9699                 return false;
9700
9701         return true;
9702 }
9703
9704 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9705 {
9706         struct drm_device *dev = crtc->base.dev;
9707         struct drm_i915_private *dev_priv = dev->dev_private;
9708         u32 reg;
9709
9710         /* Clear any frame start delays used for debugging left by the BIOS */
9711         reg = PIPECONF(crtc->config.cpu_transcoder);
9712         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9713
9714         /* We need to sanitize the plane -> pipe mapping first because this will
9715          * disable the crtc (and hence change the state) if it is wrong. Note
9716          * that gen4+ has a fixed plane -> pipe mapping.  */
9717         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9718                 struct intel_connector *connector;
9719                 bool plane;
9720
9721                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9722                               crtc->base.base.id);
9723
9724                 /* Pipe has the wrong plane attached and the plane is active.
9725                  * Temporarily change the plane mapping and disable everything
9726                  * ...  */
9727                 plane = crtc->plane;
9728                 crtc->plane = !plane;
9729                 dev_priv->display.crtc_disable(&crtc->base);
9730                 crtc->plane = plane;
9731
9732                 /* ... and break all links. */
9733                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9734                                     base.head) {
9735                         if (connector->encoder->base.crtc != &crtc->base)
9736                                 continue;
9737
9738                         intel_connector_break_all_links(connector);
9739                 }
9740
9741                 WARN_ON(crtc->active);
9742                 crtc->base.enabled = false;
9743         }
9744
9745         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9746             crtc->pipe == PIPE_A && !crtc->active) {
9747                 /* BIOS forgot to enable pipe A, this mostly happens after
9748                  * resume. Force-enable the pipe to fix this, the update_dpms
9749                  * call below we restore the pipe to the right state, but leave
9750                  * the required bits on. */
9751                 intel_enable_pipe_a(dev);
9752         }
9753
9754         /* Adjust the state of the output pipe according to whether we
9755          * have active connectors/encoders. */
9756         intel_crtc_update_dpms(&crtc->base);
9757
9758         if (crtc->active != crtc->base.enabled) {
9759                 struct intel_encoder *encoder;
9760
9761                 /* This can happen either due to bugs in the get_hw_state
9762                  * functions or because the pipe is force-enabled due to the
9763                  * pipe A quirk. */
9764                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9765                               crtc->base.base.id,
9766                               crtc->base.enabled ? "enabled" : "disabled",
9767                               crtc->active ? "enabled" : "disabled");
9768
9769                 crtc->base.enabled = crtc->active;
9770
9771                 /* Because we only establish the connector -> encoder ->
9772                  * crtc links if something is active, this means the
9773                  * crtc is now deactivated. Break the links. connector
9774                  * -> encoder links are only establish when things are
9775                  *  actually up, hence no need to break them. */
9776                 WARN_ON(crtc->active);
9777
9778                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9779                         WARN_ON(encoder->connectors_active);
9780                         encoder->base.crtc = NULL;
9781                 }
9782         }
9783 }
9784
9785 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9786 {
9787         struct intel_connector *connector;
9788         struct drm_device *dev = encoder->base.dev;
9789
9790         /* We need to check both for a crtc link (meaning that the
9791          * encoder is active and trying to read from a pipe) and the
9792          * pipe itself being active. */
9793         bool has_active_crtc = encoder->base.crtc &&
9794                 to_intel_crtc(encoder->base.crtc)->active;
9795
9796         if (encoder->connectors_active && !has_active_crtc) {
9797                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9798                               encoder->base.base.id,
9799                               drm_get_encoder_name(&encoder->base));
9800
9801                 /* Connector is active, but has no active pipe. This is
9802                  * fallout from our resume register restoring. Disable
9803                  * the encoder manually again. */
9804                 if (encoder->base.crtc) {
9805                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9806                                       encoder->base.base.id,
9807                                       drm_get_encoder_name(&encoder->base));
9808                         encoder->disable(encoder);
9809                 }
9810
9811                 /* Inconsistent output/port/pipe state happens presumably due to
9812                  * a bug in one of the get_hw_state functions. Or someplace else
9813                  * in our code, like the register restore mess on resume. Clamp
9814                  * things to off as a safer default. */
9815                 list_for_each_entry(connector,
9816                                     &dev->mode_config.connector_list,
9817                                     base.head) {
9818                         if (connector->encoder != encoder)
9819                                 continue;
9820
9821                         intel_connector_break_all_links(connector);
9822                 }
9823         }
9824         /* Enabled encoders without active connectors will be fixed in
9825          * the crtc fixup. */
9826 }
9827
9828 void i915_redisable_vga(struct drm_device *dev)
9829 {
9830         struct drm_i915_private *dev_priv = dev->dev_private;
9831         u32 vga_reg = i915_vgacntrl_reg(dev);
9832
9833         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9834                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9835                 i915_disable_vga(dev);
9836         }
9837 }
9838
9839 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9840 {
9841         struct drm_i915_private *dev_priv = dev->dev_private;
9842         enum i915_pipe pipe;
9843         struct intel_crtc *crtc;
9844         struct intel_encoder *encoder;
9845         struct intel_connector *connector;
9846         int i;
9847
9848         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9849                             base.head) {
9850                 memset(&crtc->config, 0, sizeof(crtc->config));
9851
9852                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9853                                                                  &crtc->config);
9854
9855                 crtc->base.enabled = crtc->active;
9856
9857                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9858                               crtc->base.base.id,
9859                               crtc->active ? "enabled" : "disabled");
9860         }
9861
9862         /* FIXME: Smash this into the new shared dpll infrastructure. */
9863         if (HAS_DDI(dev))
9864                 intel_ddi_setup_hw_pll_state(dev);
9865
9866         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9867                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9868
9869                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9870                 pll->active = 0;
9871                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9872                                     base.head) {
9873                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9874                                 pll->active++;
9875                 }
9876                 pll->refcount = pll->active;
9877
9878                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
9879                               pll->name, pll->refcount, pll->on);
9880         }
9881
9882         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9883                             base.head) {
9884                 pipe = 0;
9885
9886                 if (encoder->get_hw_state(encoder, &pipe)) {
9887                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9888                         encoder->base.crtc = &crtc->base;
9889                         if (encoder->get_config)
9890                                 encoder->get_config(encoder, &crtc->config);
9891                 } else {
9892                         encoder->base.crtc = NULL;
9893                 }
9894
9895                 encoder->connectors_active = false;
9896                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9897                               encoder->base.base.id,
9898                               drm_get_encoder_name(&encoder->base),
9899                               encoder->base.crtc ? "enabled" : "disabled",
9900                               pipe);
9901         }
9902
9903         list_for_each_entry(connector, &dev->mode_config.connector_list,
9904                             base.head) {
9905                 if (connector->get_hw_state(connector)) {
9906                         connector->base.dpms = DRM_MODE_DPMS_ON;
9907                         connector->encoder->connectors_active = true;
9908                         connector->base.encoder = &connector->encoder->base;
9909                 } else {
9910                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9911                         connector->base.encoder = NULL;
9912                 }
9913                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9914                               connector->base.base.id,
9915                               drm_get_connector_name(&connector->base),
9916                               connector->base.encoder ? "enabled" : "disabled");
9917         }
9918 }
9919
9920 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9921  * and i915 state tracking structures. */
9922 void intel_modeset_setup_hw_state(struct drm_device *dev,
9923                                   bool force_restore)
9924 {
9925         struct drm_i915_private *dev_priv = dev->dev_private;
9926         enum i915_pipe pipe;
9927         struct drm_plane *plane;
9928         struct intel_crtc *crtc;
9929         struct intel_encoder *encoder;
9930         int i;
9931
9932         intel_modeset_readout_hw_state(dev);
9933
9934         /* HW state is read out, now we need to sanitize this mess. */
9935         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9936                             base.head) {
9937                 intel_sanitize_encoder(encoder);
9938         }
9939
9940         for_each_pipe(pipe) {
9941                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9942                 intel_sanitize_crtc(crtc);
9943                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9944         }
9945
9946         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9947                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9948
9949                 if (!pll->on || pll->active)
9950                         continue;
9951
9952                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
9953
9954                 pll->disable(dev_priv, pll);
9955                 pll->on = false;
9956         }
9957
9958         if (force_restore) {
9959                 /*
9960                  * We need to use raw interfaces for restoring state to avoid
9961                  * checking (bogus) intermediate states.
9962                  */
9963                 for_each_pipe(pipe) {
9964                         struct drm_crtc *crtc =
9965                                 dev_priv->pipe_to_crtc_mapping[pipe];
9966
9967                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9968                                          crtc->fb);
9969                 }
9970                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9971                         intel_plane_restore(plane);
9972
9973                 i915_redisable_vga(dev);
9974         } else {
9975                 intel_modeset_update_staged_output_state(dev);
9976         }
9977
9978         intel_modeset_check_state(dev);
9979
9980         drm_mode_config_reset(dev);
9981 }
9982
9983 void intel_modeset_gem_init(struct drm_device *dev)
9984 {
9985         intel_modeset_init_hw(dev);
9986
9987         intel_setup_overlay(dev);
9988
9989         intel_modeset_setup_hw_state(dev, false);
9990 }
9991
9992 void intel_modeset_cleanup(struct drm_device *dev)
9993 {
9994         struct drm_i915_private *dev_priv = dev->dev_private;
9995         struct drm_crtc *crtc;
9996         struct intel_crtc *intel_crtc;
9997
9998         /*
9999          * Interrupts and polling as the first thing to avoid creating havoc.
10000          * Too much stuff here (turning of rps, connectors, ...) would
10001          * experience fancy races otherwise.
10002          */
10003         drm_irq_uninstall(dev);
10004         cancel_work_sync(&dev_priv->hotplug_work);
10005         /*
10006          * Due to the hpd irq storm handling the hotplug work can re-arm the
10007          * poll handlers. Hence disable polling after hpd handling is shut down.
10008          */
10009         drm_kms_helper_poll_fini(dev);
10010
10011         mutex_lock(&dev->struct_mutex);
10012
10013         intel_unregister_dsm_handler();
10014
10015         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10016                 /* Skip inactive CRTCs */
10017                 if (!crtc->fb)
10018                         continue;
10019
10020                 intel_crtc = to_intel_crtc(crtc);
10021                 intel_increase_pllclock(crtc);
10022         }
10023
10024         intel_disable_fbc(dev);
10025
10026         intel_disable_gt_powersave(dev);
10027
10028         ironlake_teardown_rc6(dev);
10029
10030         mutex_unlock(&dev->struct_mutex);
10031
10032         /* flush any delayed tasks or pending work */
10033         flush_scheduled_work();
10034
10035         /* destroy backlight, if any, before the connectors */
10036         intel_panel_destroy_backlight(dev);
10037
10038         drm_mode_config_cleanup(dev);
10039
10040         intel_cleanup_overlay(dev);
10041 }
10042
10043 /*
10044  * Return which encoder is currently attached for connector.
10045  */
10046 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10047 {
10048         return &intel_attached_encoder(connector)->base;
10049 }
10050
10051 void intel_connector_attach_encoder(struct intel_connector *connector,
10052                                     struct intel_encoder *encoder)
10053 {
10054         connector->encoder = encoder;
10055         drm_mode_connector_attach_encoder(&connector->base,
10056                                           &encoder->base);
10057 }
10058
10059 /*
10060  * set vga decode state - true == enable VGA decode
10061  */
10062 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10063 {
10064         struct drm_i915_private *dev_priv = dev->dev_private;
10065         u16 gmch_ctrl;
10066
10067         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10068         if (state)
10069                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10070         else
10071                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10072         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10073         return 0;
10074 }
10075
10076 #ifdef CONFIG_DEBUG_FS
10077 #include <linux/seq_file.h>
10078
10079 struct intel_display_error_state {
10080
10081         u32 power_well_driver;
10082
10083         int num_transcoders;
10084
10085         struct intel_cursor_error_state {
10086                 u32 control;
10087                 u32 position;
10088                 u32 base;
10089                 u32 size;
10090         } cursor[I915_MAX_PIPES];
10091
10092         struct intel_pipe_error_state {
10093                 u32 source;
10094         } pipe[I915_MAX_PIPES];
10095
10096         struct intel_plane_error_state {
10097                 u32 control;
10098                 u32 stride;
10099                 u32 size;
10100                 u32 pos;
10101                 u32 addr;
10102                 u32 surface;
10103                 u32 tile_offset;
10104         } plane[I915_MAX_PIPES];
10105
10106         struct intel_transcoder_error_state {
10107                 enum transcoder cpu_transcoder;
10108
10109                 u32 conf;
10110
10111                 u32 htotal;
10112                 u32 hblank;
10113                 u32 hsync;
10114                 u32 vtotal;
10115                 u32 vblank;
10116                 u32 vsync;
10117         } transcoder[4];
10118 };
10119
10120 struct intel_display_error_state *
10121 intel_display_capture_error_state(struct drm_device *dev)
10122 {
10123         drm_i915_private_t *dev_priv = dev->dev_private;
10124         struct intel_display_error_state *error;
10125         int transcoders[] = {
10126                 TRANSCODER_A,
10127                 TRANSCODER_B,
10128                 TRANSCODER_C,
10129                 TRANSCODER_EDP,
10130         };
10131         int i;
10132
10133         if (INTEL_INFO(dev)->num_pipes == 0)
10134                 return NULL;
10135
10136         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10137         if (error == NULL)
10138                 return NULL;
10139
10140         if (HAS_POWER_WELL(dev))
10141                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10142
10143         for_each_pipe(i) {
10144                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10145                         error->cursor[i].control = I915_READ(CURCNTR(i));
10146                         error->cursor[i].position = I915_READ(CURPOS(i));
10147                         error->cursor[i].base = I915_READ(CURBASE(i));
10148                 } else {
10149                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10150                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10151                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10152                 }
10153
10154                 error->plane[i].control = I915_READ(DSPCNTR(i));
10155                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10156                 if (INTEL_INFO(dev)->gen <= 3) {
10157                         error->plane[i].size = I915_READ(DSPSIZE(i));
10158                         error->plane[i].pos = I915_READ(DSPPOS(i));
10159                 }
10160                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10161                         error->plane[i].addr = I915_READ(DSPADDR(i));
10162                 if (INTEL_INFO(dev)->gen >= 4) {
10163                         error->plane[i].surface = I915_READ(DSPSURF(i));
10164                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10165                 }
10166
10167                 error->pipe[i].source = I915_READ(PIPESRC(i));
10168         }
10169
10170         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10171         if (HAS_DDI(dev_priv->dev))
10172                 error->num_transcoders++; /* Account for eDP. */
10173
10174         for (i = 0; i < error->num_transcoders; i++) {
10175                 enum transcoder cpu_transcoder = transcoders[i];
10176
10177                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10178
10179                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10180                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10181                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10182                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10183                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10184                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10185                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10186         }
10187
10188         /* In the code above we read the registers without checking if the power
10189          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10190          * prevent the next I915_WRITE from detecting it and printing an error
10191          * message. */
10192         if (HAS_POWER_WELL(dev))
10193                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10194
10195         return error;
10196 }
10197
10198 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10199
10200 void
10201 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10202                                 struct drm_device *dev,
10203                                 struct intel_display_error_state *error)
10204 {
10205         int i;
10206
10207         if (!error)
10208                 return;
10209
10210         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10211         if (HAS_POWER_WELL(dev))
10212                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10213                            error->power_well_driver);
10214         for_each_pipe(i) {
10215                 err_printf(m, "Pipe [%d]:\n", i);
10216                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10217
10218                 err_printf(m, "Plane [%d]:\n", i);
10219                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10220                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10221                 if (INTEL_INFO(dev)->gen <= 3) {
10222                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10223                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10224                 }
10225                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10226                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10227                 if (INTEL_INFO(dev)->gen >= 4) {
10228                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10229                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10230                 }
10231
10232                 err_printf(m, "Cursor [%d]:\n", i);
10233                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10234                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10235                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10236         }
10237
10238         for (i = 0; i < error->num_transcoders; i++) {
10239                 err_printf(m, "  CPU transcoder: %c\n",
10240                            transcoder_name(error->transcoder[i].cpu_transcoder));
10241                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
10242                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
10243                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
10244                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
10245                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
10246                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
10247                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
10248         }
10249 }
10250 #endif