sys/dev/netif/igb/if_igb.c

   1 /*
   2  * Copyright (c) 2001-2011, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "opt_ifpoll.h"
  33 #include "opt_igb.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/kernel.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mbuf.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/serialize.h>
  45 #include <sys/serialize2.h>
  46 #include <sys/socket.h>
  47 #include <sys/sockio.h>
  48 #include <sys/sysctl.h>
  49 #include <sys/systm.h>
  50
  51 #include <net/bpf.h>
  52 #include <net/ethernet.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <net/if_dl.h>
  56 #include <net/if_media.h>
  57 #include <net/ifq_var.h>
  58 #include <net/toeplitz.h>
  59 #include <net/toeplitz2.h>
  60 #include <net/vlan/if_vlan_var.h>
  61 #include <net/vlan/if_vlan_ether.h>
  62 #include <net/if_poll.h>
  63
  64 #include <netinet/in_systm.h>
  65 #include <netinet/in.h>
  66 #include <netinet/ip.h>
  67 #include <netinet/tcp.h>
  68 #include <netinet/udp.h>
  69
  70 #include <bus/pci/pcivar.h>
  71 #include <bus/pci/pcireg.h>
  72
  73 #include <dev/netif/ig_hal/e1000_api.h>
  74 #include <dev/netif/ig_hal/e1000_82575.h>
  75 #include <dev/netif/igb/if_igb.h>
  76
  77 #ifdef IGB_RSS_DEBUG
  78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
  79 do { \
  80         if (sc->rss_debug >= lvl) \
  81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  82 } while (0)
  83 #else   /* !IGB_RSS_DEBUG */
  84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  85 #endif  /* IGB_RSS_DEBUG */
  86
  87 #define IGB_NAME        "Intel(R) PRO/1000 "
  88 #define IGB_DEVICE(id)  \
  89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
  90 #define IGB_DEVICE_NULL { 0, 0, NULL }
  91
  92 static struct igb_device {
  93         uint16_t        vid;
  94         uint16_t        did;
  95         const char      *desc;
  96 } igb_devices[] = {
  97         IGB_DEVICE(82575EB_COPPER),
  98         IGB_DEVICE(82575EB_FIBER_SERDES),
  99         IGB_DEVICE(82575GB_QUAD_COPPER),
 100         IGB_DEVICE(82576),
 101         IGB_DEVICE(82576_NS),
 102         IGB_DEVICE(82576_NS_SERDES),
 103         IGB_DEVICE(82576_FIBER),
 104         IGB_DEVICE(82576_SERDES),
 105         IGB_DEVICE(82576_SERDES_QUAD),
 106         IGB_DEVICE(82576_QUAD_COPPER),
 107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
 108         IGB_DEVICE(82576_VF),
 109         IGB_DEVICE(82580_COPPER),
 110         IGB_DEVICE(82580_FIBER),
 111         IGB_DEVICE(82580_SERDES),
 112         IGB_DEVICE(82580_SGMII),
 113         IGB_DEVICE(82580_COPPER_DUAL),
 114         IGB_DEVICE(82580_QUAD_FIBER),
 115         IGB_DEVICE(DH89XXCC_SERDES),
 116         IGB_DEVICE(DH89XXCC_SGMII),
 117         IGB_DEVICE(DH89XXCC_SFP),
 118         IGB_DEVICE(DH89XXCC_BACKPLANE),
 119         IGB_DEVICE(I350_COPPER),
 120         IGB_DEVICE(I350_FIBER),
 121         IGB_DEVICE(I350_SERDES),
 122         IGB_DEVICE(I350_SGMII),
 123         IGB_DEVICE(I350_VF),
 124
 125         /* required last entry */
 126         IGB_DEVICE_NULL
 127 };
 128
 129 static int      igb_probe(device_t);
 130 static int      igb_attach(device_t);
 131 static int      igb_detach(device_t);
 132 static int      igb_shutdown(device_t);
 133 static int      igb_suspend(device_t);
 134 static int      igb_resume(device_t);
 135
 136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
 137 static void     igb_setup_ifp(struct igb_softc *);
 138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
 139 static int      igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
 140 static void     igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
 141 static void     igb_add_sysctl(struct igb_softc *);
 142 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
 143 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
 144 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
 145 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
 146 #ifdef IFPOLL_ENABLE
 147 static int      igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
 148 static int      igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
 149 #endif
 150
 151 static void     igb_vf_init_stats(struct igb_softc *);
 152 static void     igb_reset(struct igb_softc *);
 153 static void     igb_update_stats_counters(struct igb_softc *);
 154 static void     igb_update_vf_stats_counters(struct igb_softc *);
 155 static void     igb_update_link_status(struct igb_softc *);
 156 static void     igb_init_tx_unit(struct igb_softc *);
 157 static void     igb_init_rx_unit(struct igb_softc *);
 158
 159 static void     igb_set_vlan(struct igb_softc *);
 160 static void     igb_set_multi(struct igb_softc *);
 161 static void     igb_set_promisc(struct igb_softc *);
 162 static void     igb_disable_promisc(struct igb_softc *);
 163
 164 static int      igb_alloc_rings(struct igb_softc *);
 165 static void     igb_free_rings(struct igb_softc *);
 166 static int      igb_create_tx_ring(struct igb_tx_ring *);
 167 static int      igb_create_rx_ring(struct igb_rx_ring *);
 168 static void     igb_free_tx_ring(struct igb_tx_ring *);
 169 static void     igb_free_rx_ring(struct igb_rx_ring *);
 170 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
 171 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
 172 static void     igb_init_tx_ring(struct igb_tx_ring *);
 173 static int      igb_init_rx_ring(struct igb_rx_ring *);
 174 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
 175 static int      igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
 176 static void     igb_rx_refresh(struct igb_rx_ring *, int);
 177
 178 static void     igb_stop(struct igb_softc *);
 179 static void     igb_init(void *);
 180 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 181 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
 182 static int      igb_media_change(struct ifnet *);
 183 static void     igb_timer(void *);
 184 static void     igb_watchdog(struct ifnet *);
 185 static void     igb_start(struct ifnet *);
 186 #ifdef IFPOLL_ENABLE
 187 static void     igb_npoll(struct ifnet *, struct ifpoll_info *);
 188 static void     igb_npoll_rx(struct ifnet *, void *, int);
 189 static void     igb_npoll_tx(struct ifnet *, void *, int);
 190 static void     igb_npoll_status(struct ifnet *);
 191 #endif
 192 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
 193 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
 194 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
 195 #ifdef INVARIANTS
 196 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
 197                     boolean_t);
 198 #endif
 199
 200 static void     igb_intr(void *);
 201 static void     igb_intr_shared(void *);
 202 static void     igb_rxeof(struct igb_rx_ring *, int);
 203 static void     igb_txeof(struct igb_tx_ring *);
 204 static void     igb_set_eitr(struct igb_softc *, int, int);
 205 static void     igb_enable_intr(struct igb_softc *);
 206 static void     igb_disable_intr(struct igb_softc *);
 207 static void     igb_init_unshared_intr(struct igb_softc *);
 208 static void     igb_init_intr(struct igb_softc *);
 209 static int      igb_setup_intr(struct igb_softc *);
 210 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
 211 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
 212 static void     igb_set_intr_mask(struct igb_softc *);
 213 static int      igb_alloc_intr(struct igb_softc *);
 214 static void     igb_free_intr(struct igb_softc *);
 215 static void     igb_teardown_intr(struct igb_softc *);
 216 static void     igb_msix_try_alloc(struct igb_softc *);
 217 static void     igb_msix_free(struct igb_softc *, boolean_t);
 218 static int      igb_msix_setup(struct igb_softc *);
 219 static void     igb_msix_teardown(struct igb_softc *, int);
 220 static void     igb_msix_rx(void *);
 221 static void     igb_msix_tx(void *);
 222 static void     igb_msix_status(void *);
 223
 224 /* Management and WOL Support */
 225 static void     igb_get_mgmt(struct igb_softc *);
 226 static void     igb_rel_mgmt(struct igb_softc *);
 227 static void     igb_get_hw_control(struct igb_softc *);
 228 static void     igb_rel_hw_control(struct igb_softc *);
 229 static void     igb_enable_wol(device_t);
 230
 231 static device_method_t igb_methods[] = {
 232         /* Device interface */
 233         DEVMETHOD(device_probe,         igb_probe),
 234         DEVMETHOD(device_attach,        igb_attach),
 235         DEVMETHOD(device_detach,        igb_detach),
 236         DEVMETHOD(device_shutdown,      igb_shutdown),
 237         DEVMETHOD(device_suspend,       igb_suspend),
 238         DEVMETHOD(device_resume,        igb_resume),
 239         { 0, 0 }
 240 };
 241
 242 static driver_t igb_driver = {
 243         "igb",
 244         igb_methods,
 245         sizeof(struct igb_softc),
 246 };
 247
 248 static devclass_t igb_devclass;
 249
 250 DECLARE_DUMMY_MODULE(if_igb);
 251 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
 252 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
 253
 254 static int      igb_rxd = IGB_DEFAULT_RXD;
 255 static int      igb_txd = IGB_DEFAULT_TXD;
 256 static int      igb_rxr = 0;
 257 static int      igb_msi_enable = 1;
 258 static int      igb_msix_enable = 1;
 259 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
 260 static int      igb_fc_setting = e1000_fc_full;
 261
 262 /*
 263  * DMA Coalescing, only for i350 - default to off,
 264  * this feature is for power savings
 265  */
 266 static int      igb_dma_coalesce = 0;
 267
 268 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 269 TUNABLE_INT("hw.igb.txd", &igb_txd);
 270 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
 271 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
 272 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
 273 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
 274
 275 /* i350 specific */
 276 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
 277 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
 278
 279 static __inline void
 280 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
 281 {
 282         /* Ignore Checksum bit is set */
 283         if (staterr & E1000_RXD_STAT_IXSM)
 284                 return;
 285
 286         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
 287             E1000_RXD_STAT_IPCS)
 288                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
 289
 290         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
 291                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
 292                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 293                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
 294                         mp->m_pkthdr.csum_data = htons(0xffff);
 295                 }
 296         }
 297 }
 298
 299 static __inline struct pktinfo *
 300 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
 301     uint32_t hash, uint32_t hashtype, uint32_t staterr)
 302 {
 303         switch (hashtype) {
 304         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
 305                 pi->pi_netisr = NETISR_IP;
 306                 pi->pi_flags = 0;
 307                 pi->pi_l3proto = IPPROTO_TCP;
 308                 break;
 309
 310         case E1000_RXDADV_RSSTYPE_IPV4:
 311                 if (staterr & E1000_RXD_STAT_IXSM)
 312                         return NULL;
 313
 314                 if ((staterr &
 315                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
 316                     E1000_RXD_STAT_TCPCS) {
 317                         pi->pi_netisr = NETISR_IP;
 318                         pi->pi_flags = 0;
 319                         pi->pi_l3proto = IPPROTO_UDP;
 320                         break;
 321                 }
 322                 /* FALL THROUGH */
 323         default:
 324                 return NULL;
 325         }
 326
 327         m->m_flags |= M_HASH;
 328         m->m_pkthdr.hash = toeplitz_hash(hash);
 329         return pi;
 330 }
 331
 332 static int
 333 igb_probe(device_t dev)
 334 {
 335         const struct igb_device *d;
 336         uint16_t vid, did;
 337
 338         vid = pci_get_vendor(dev);
 339         did = pci_get_device(dev);
 340
 341         for (d = igb_devices; d->desc != NULL; ++d) {
 342                 if (vid == d->vid && did == d->did) {
 343                         device_set_desc(dev, d->desc);
 344                         return 0;
 345                 }
 346         }
 347         return ENXIO;
 348 }
 349
 350 static int
 351 igb_attach(device_t dev)
 352 {
 353         struct igb_softc *sc = device_get_softc(dev);
 354         uint16_t eeprom_data;
 355         int error = 0, i, j, ring_max;
 356 #ifdef IFPOLL_ENABLE
 357         int offset, offset_def;
 358 #endif
 359
 360 #ifdef notyet
 361         /* SYSCTL stuff */
 362         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 363             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 364             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 365             igb_sysctl_nvm_info, "I", "NVM Information");
 366         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 367             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 368             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
 369             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
 370 #endif
 371
 372         callout_init_mp(&sc->timer);
 373         lwkt_serialize_init(&sc->main_serialize);
 374
 375         if_initname(&sc->arpcom.ac_if, device_get_name(dev),
 376             device_get_unit(dev));
 377         sc->dev = sc->osdep.dev = dev;
 378
 379         /*
 380          * Determine hardware and mac type
 381          */
 382         sc->hw.vendor_id = pci_get_vendor(dev);
 383         sc->hw.device_id = pci_get_device(dev);
 384         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
 385         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 386         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 387
 388         if (e1000_set_mac_type(&sc->hw))
 389                 return ENXIO;
 390
 391         /* Are we a VF device? */
 392         if (sc->hw.mac.type == e1000_vfadapt ||
 393             sc->hw.mac.type == e1000_vfadapt_i350)
 394                 sc->vf_ifp = 1;
 395         else
 396                 sc->vf_ifp = 0;
 397
 398         /*
 399          * Configure total supported RX/TX ring count
 400          */
 401         switch (sc->hw.mac.type) {
 402         case e1000_82575:
 403                 ring_max = IGB_MAX_RING_82575;
 404                 break;
 405         case e1000_82580:
 406                 ring_max = IGB_MAX_RING_82580;
 407                 break;
 408         case e1000_i350:
 409                 ring_max = IGB_MAX_RING_I350;
 410                 break;
 411         case e1000_82576:
 412                 ring_max = IGB_MAX_RING_82576;
 413                 break;
 414         default:
 415                 ring_max = IGB_MIN_RING;
 416                 break;
 417         }
 418         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
 419         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
 420 #ifdef IGB_RSS_DEBUG
 421         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
 422 #endif
 423         sc->rx_ring_inuse = sc->rx_ring_cnt;
 424         sc->tx_ring_cnt = 1; /* XXX */
 425
 426         if (sc->hw.mac.type == e1000_82575)
 427                 sc->flags |= IGB_FLAG_TSO_IPLEN0;
 428
 429         /* Enable bus mastering */
 430         pci_enable_busmaster(dev);
 431
 432         /*
 433          * Allocate IO memory
 434          */
 435         sc->mem_rid = PCIR_BAR(0);
 436         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 437             RF_ACTIVE);
 438         if (sc->mem_res == NULL) {
 439                 device_printf(dev, "Unable to allocate bus resource: memory\n");
 440                 error = ENXIO;
 441                 goto failed;
 442         }
 443         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
 444         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
 445
 446         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
 447
 448         /* Save PCI command register for Shared Code */
 449         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 450         sc->hw.back = &sc->osdep;
 451
 452         /* Do Shared Code initialization */
 453         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
 454                 device_printf(dev, "Setup of Shared code failed\n");
 455                 error = ENXIO;
 456                 goto failed;
 457         }
 458
 459         e1000_get_bus_info(&sc->hw);
 460
 461         sc->hw.mac.autoneg = DO_AUTO_NEG;
 462         sc->hw.phy.autoneg_wait_to_complete = FALSE;
 463         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 464
 465         /* Copper options */
 466         if (sc->hw.phy.media_type == e1000_media_type_copper) {
 467                 sc->hw.phy.mdix = AUTO_ALL_MODES;
 468                 sc->hw.phy.disable_polarity_correction = FALSE;
 469                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
 470         }
 471
 472         /* Set the frame limits assuming  standard ethernet sized frames. */
 473         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
 474
 475         /* Allocate RX/TX rings */
 476         error = igb_alloc_rings(sc);
 477         if (error)
 478                 goto failed;
 479
 480 #ifdef IFPOLL_ENABLE
 481         /*
 482          * NPOLLING RX CPU offset
 483          */
 484         if (sc->rx_ring_cnt == ncpus2) {
 485                 offset = 0;
 486         } else {
 487                 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
 488                 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
 489                 if (offset >= ncpus2 ||
 490                     offset % sc->rx_ring_cnt != 0) {
 491                         device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
 492                             offset, offset_def);
 493                         offset = offset_def;
 494                 }
 495         }
 496         sc->rx_npoll_off = offset;
 497
 498         /*
 499          * NPOLLING TX CPU offset
 500          */
 501         offset_def = sc->rx_npoll_off;
 502         offset = device_getenv_int(dev, "npoll.txoff", offset_def);
 503         if (offset >= ncpus2) {
 504                 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
 505                     offset, offset_def);
 506                 offset = offset_def;
 507         }
 508         sc->tx_npoll_off = offset;
 509 #endif
 510
 511         /* Allocate interrupt */
 512         error = igb_alloc_intr(sc);
 513         if (error)
 514                 goto failed;
 515
 516         /*
 517          * Setup serializers
 518          */
 519         i = 0;
 520         sc->serializes[i++] = &sc->main_serialize;
 521
 522         sc->tx_serialize = i;
 523         for (j = 0; j < sc->tx_ring_cnt; ++j)
 524                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
 525
 526         sc->rx_serialize = i;
 527         for (j = 0; j < sc->rx_ring_cnt; ++j)
 528                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
 529
 530         sc->serialize_cnt = i;
 531         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
 532
 533         /* Allocate the appropriate stats memory */
 534         if (sc->vf_ifp) {
 535                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
 536                     M_WAITOK | M_ZERO);
 537                 igb_vf_init_stats(sc);
 538         } else {
 539                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
 540                     M_WAITOK | M_ZERO);
 541         }
 542
 543         /* Allocate multicast array memory. */
 544         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
 545             M_DEVBUF, M_WAITOK);
 546
 547         /* Some adapter-specific advanced features */
 548         if (sc->hw.mac.type >= e1000_i350) {
 549 #ifdef notyet
 550                 igb_set_sysctl_value(adapter, "dma_coalesce",
 551                     "configure dma coalesce",
 552                     &adapter->dma_coalesce, igb_dma_coalesce);
 553                 igb_set_sysctl_value(adapter, "eee_disabled",
 554                     "enable Energy Efficient Ethernet",
 555                     &adapter->hw.dev_spec._82575.eee_disable,
 556                     igb_eee_disabled);
 557 #else
 558                 sc->dma_coalesce = igb_dma_coalesce;
 559                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
 560 #endif
 561                 e1000_set_eee_i350(&sc->hw);
 562         }
 563
 564         /*
 565          * Start from a known state, this is important in reading the nvm and
 566          * mac from that.
 567          */
 568         e1000_reset_hw(&sc->hw);
 569
 570         /* Make sure we have a good EEPROM before we read from it */
 571         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 572                 /*
 573                  * Some PCI-E parts fail the first check due to
 574                  * the link being in sleep state, call it again,
 575                  * if it fails a second time its a real issue.
 576                  */
 577                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 578                         device_printf(dev,
 579                             "The EEPROM Checksum Is Not Valid\n");
 580                         error = EIO;
 581                         goto failed;
 582                 }
 583         }
 584
 585         /* Copy the permanent MAC address out of the EEPROM */
 586         if (e1000_read_mac_addr(&sc->hw) < 0) {
 587                 device_printf(dev, "EEPROM read error while reading MAC"
 588                     " address\n");
 589                 error = EIO;
 590                 goto failed;
 591         }
 592         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
 593                 device_printf(dev, "Invalid MAC address\n");
 594                 error = EIO;
 595                 goto failed;
 596         }
 597
 598         /* Setup OS specific network interface */
 599         igb_setup_ifp(sc);
 600
 601         /* Add sysctl tree, must after igb_setup_ifp() */
 602         igb_add_sysctl(sc);
 603
 604         /* Now get a good starting state */
 605         igb_reset(sc);
 606
 607         /* Initialize statistics */
 608         igb_update_stats_counters(sc);
 609
 610         sc->hw.mac.get_link_status = 1;
 611         igb_update_link_status(sc);
 612
 613         /* Indicate SOL/IDER usage */
 614         if (e1000_check_reset_block(&sc->hw)) {
 615                 device_printf(dev,
 616                     "PHY reset is blocked due to SOL/IDER session.\n");
 617         }
 618
 619         /* Determine if we have to control management hardware */
 620         if (e1000_enable_mng_pass_thru(&sc->hw))
 621                 sc->flags |= IGB_FLAG_HAS_MGMT;
 622
 623         /*
 624          * Setup Wake-on-Lan
 625          */
 626         /* APME bit in EEPROM is mapped to WUC.APME */
 627         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
 628         if (eeprom_data)
 629                 sc->wol = E1000_WUFC_MAG;
 630         /* XXX disable WOL */
 631         sc->wol = 0;
 632
 633 #ifdef notyet
 634         /* Register for VLAN events */
 635         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 636              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 637         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 638              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 639 #endif
 640
 641 #ifdef notyet
 642         igb_add_hw_stats(adapter);
 643 #endif
 644
 645         error = igb_setup_intr(sc);
 646         if (error) {
 647                 ether_ifdetach(&sc->arpcom.ac_if);
 648                 goto failed;
 649         }
 650         return 0;
 651
 652 failed:
 653         igb_detach(dev);
 654         return error;
 655 }
 656
 657 static int
 658 igb_detach(device_t dev)
 659 {
 660         struct igb_softc *sc = device_get_softc(dev);
 661
 662         if (device_is_attached(dev)) {
 663                 struct ifnet *ifp = &sc->arpcom.ac_if;
 664
 665                 ifnet_serialize_all(ifp);
 666
 667                 igb_stop(sc);
 668
 669                 e1000_phy_hw_reset(&sc->hw);
 670
 671                 /* Give control back to firmware */
 672                 igb_rel_mgmt(sc);
 673                 igb_rel_hw_control(sc);
 674
 675                 if (sc->wol) {
 676                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 677                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 678                         igb_enable_wol(dev);
 679                 }
 680
 681                 igb_teardown_intr(sc);
 682
 683                 ifnet_deserialize_all(ifp);
 684
 685                 ether_ifdetach(ifp);
 686         } else if (sc->mem_res != NULL) {
 687                 igb_rel_hw_control(sc);
 688         }
 689         bus_generic_detach(dev);
 690
 691         if (sc->sysctl_tree != NULL)
 692                 sysctl_ctx_free(&sc->sysctl_ctx);
 693
 694         igb_free_intr(sc);
 695
 696         if (sc->msix_mem_res != NULL) {
 697                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
 698                     sc->msix_mem_res);
 699         }
 700         if (sc->mem_res != NULL) {
 701                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 702                     sc->mem_res);
 703         }
 704
 705         igb_free_rings(sc);
 706
 707         if (sc->mta != NULL)
 708                 kfree(sc->mta, M_DEVBUF);
 709         if (sc->stats != NULL)
 710                 kfree(sc->stats, M_DEVBUF);
 711
 712         return 0;
 713 }
 714
 715 static int
 716 igb_shutdown(device_t dev)
 717 {
 718         return igb_suspend(dev);
 719 }
 720
 721 static int
 722 igb_suspend(device_t dev)
 723 {
 724         struct igb_softc *sc = device_get_softc(dev);
 725         struct ifnet *ifp = &sc->arpcom.ac_if;
 726
 727         ifnet_serialize_all(ifp);
 728
 729         igb_stop(sc);
 730
 731         igb_rel_mgmt(sc);
 732         igb_rel_hw_control(sc);
 733
 734         if (sc->wol) {
 735                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 736                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 737                 igb_enable_wol(dev);
 738         }
 739
 740         ifnet_deserialize_all(ifp);
 741
 742         return bus_generic_suspend(dev);
 743 }
 744
 745 static int
 746 igb_resume(device_t dev)
 747 {
 748         struct igb_softc *sc = device_get_softc(dev);
 749         struct ifnet *ifp = &sc->arpcom.ac_if;
 750
 751         ifnet_serialize_all(ifp);
 752
 753         igb_init(sc);
 754         igb_get_mgmt(sc);
 755
 756         if_devstart(ifp);
 757
 758         ifnet_deserialize_all(ifp);
 759
 760         return bus_generic_resume(dev);
 761 }
 762
 763 static int
 764 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 765 {
 766         struct igb_softc *sc = ifp->if_softc;
 767         struct ifreq *ifr = (struct ifreq *)data;
 768         int max_frame_size, mask, reinit;
 769         int error = 0;
 770
 771         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 772
 773         switch (command) {
 774         case SIOCSIFMTU:
 775                 max_frame_size = 9234;
 776                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
 777                     ETHER_CRC_LEN) {
 778                         error = EINVAL;
 779                         break;
 780                 }
 781
 782                 ifp->if_mtu = ifr->ifr_mtu;
 783                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
 784                     ETHER_CRC_LEN;
 785
 786                 if (ifp->if_flags & IFF_RUNNING)
 787                         igb_init(sc);
 788                 break;
 789
 790         case SIOCSIFFLAGS:
 791                 if (ifp->if_flags & IFF_UP) {
 792                         if (ifp->if_flags & IFF_RUNNING) {
 793                                 if ((ifp->if_flags ^ sc->if_flags) &
 794                                     (IFF_PROMISC | IFF_ALLMULTI)) {
 795                                         igb_disable_promisc(sc);
 796                                         igb_set_promisc(sc);
 797                                 }
 798                         } else {
 799                                 igb_init(sc);
 800                         }
 801                 } else if (ifp->if_flags & IFF_RUNNING) {
 802                         igb_stop(sc);
 803                 }
 804                 sc->if_flags = ifp->if_flags;
 805                 break;
 806
 807         case SIOCADDMULTI:
 808         case SIOCDELMULTI:
 809                 if (ifp->if_flags & IFF_RUNNING) {
 810                         igb_disable_intr(sc);
 811                         igb_set_multi(sc);
 812 #ifdef IFPOLL_ENABLE
 813                         if (!(ifp->if_flags & IFF_NPOLLING))
 814 #endif
 815                                 igb_enable_intr(sc);
 816                 }
 817                 break;
 818
 819         case SIOCSIFMEDIA:
 820                 /*
 821                  * As the speed/duplex settings are being
 822                  * changed, we need toreset the PHY.
 823                  */
 824                 sc->hw.phy.reset_disable = FALSE;
 825
 826                 /* Check SOL/IDER usage */
 827                 if (e1000_check_reset_block(&sc->hw)) {
 828                         if_printf(ifp, "Media change is "
 829                             "blocked due to SOL/IDER session.\n");
 830                         break;
 831                 }
 832                 /* FALL THROUGH */
 833
 834         case SIOCGIFMEDIA:
 835                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 836                 break;
 837
 838         case SIOCSIFCAP:
 839                 reinit = 0;
 840                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 841                 if (mask & IFCAP_RXCSUM) {
 842                         ifp->if_capenable ^= IFCAP_RXCSUM;
 843                         reinit = 1;
 844                 }
 845                 if (mask & IFCAP_VLAN_HWTAGGING) {
 846                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 847                         reinit = 1;
 848                 }
 849                 if (mask & IFCAP_TXCSUM) {
 850                         ifp->if_capenable ^= IFCAP_TXCSUM;
 851                         if (ifp->if_capenable & IFCAP_TXCSUM)
 852                                 ifp->if_hwassist |= IGB_CSUM_FEATURES;
 853                         else
 854                                 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
 855                 }
 856                 if (mask & IFCAP_TSO) {
 857                         ifp->if_capenable ^= IFCAP_TSO;
 858                         if (ifp->if_capenable & IFCAP_TSO)
 859                                 ifp->if_hwassist |= CSUM_TSO;
 860                         else
 861                                 ifp->if_hwassist &= ~CSUM_TSO;
 862                 }
 863                 if (mask & IFCAP_RSS)
 864                         ifp->if_capenable ^= IFCAP_RSS;
 865                 if (reinit && (ifp->if_flags & IFF_RUNNING))
 866                         igb_init(sc);
 867                 break;
 868
 869         default:
 870                 error = ether_ioctl(ifp, command, data);
 871                 break;
 872         }
 873         return error;
 874 }
 875
 876 static void
 877 igb_init(void *xsc)
 878 {
 879         struct igb_softc *sc = xsc;
 880         struct ifnet *ifp = &sc->arpcom.ac_if;
 881         boolean_t polling;
 882         int i;
 883
 884         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 885
 886         igb_stop(sc);
 887
 888         /* Get the latest mac address, User can use a LAA */
 889         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
 890
 891         /* Put the address into the Receive Address Array */
 892         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
 893
 894         igb_reset(sc);
 895         igb_update_link_status(sc);
 896
 897         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
 898
 899         /* Configure for OS presence */
 900         igb_get_mgmt(sc);
 901
 902         polling = FALSE;
 903 #ifdef IFPOLL_ENABLE
 904         if (ifp->if_flags & IFF_NPOLLING)
 905                 polling = TRUE;
 906 #endif
 907
 908         /* Configured used RX/TX rings */
 909         igb_set_ring_inuse(sc, polling);
 910
 911         /* Initialize interrupt */
 912         igb_init_intr(sc);
 913
 914         /* Prepare transmit descriptors and buffers */
 915         for (i = 0; i < sc->tx_ring_cnt; ++i)
 916                 igb_init_tx_ring(&sc->tx_rings[i]);
 917         igb_init_tx_unit(sc);
 918
 919         /* Setup Multicast table */
 920         igb_set_multi(sc);
 921
 922 #if 0
 923         /*
 924          * Figure out the desired mbuf pool
 925          * for doing jumbo/packetsplit
 926          */
 927         if (adapter->max_frame_size <= 2048)
 928                 adapter->rx_mbuf_sz = MCLBYTES;
 929         else if (adapter->max_frame_size <= 4096)
 930                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
 931         else
 932                 adapter->rx_mbuf_sz = MJUM9BYTES;
 933 #endif
 934
 935         /* Prepare receive descriptors and buffers */
 936         for (i = 0; i < sc->rx_ring_inuse; ++i) {
 937                 int error;
 938
 939                 error = igb_init_rx_ring(&sc->rx_rings[i]);
 940                 if (error) {
 941                         if_printf(ifp, "Could not setup receive structures\n");
 942                         igb_stop(sc);
 943                         return;
 944                 }
 945         }
 946         igb_init_rx_unit(sc);
 947
 948         /* Enable VLAN support */
 949         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 950                 igb_set_vlan(sc);
 951
 952         /* Don't lose promiscuous settings */
 953         igb_set_promisc(sc);
 954
 955         ifp->if_flags |= IFF_RUNNING;
 956         ifq_clr_oactive(&ifp->if_snd);
 957
 958         if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
 959                 sc->timer_cpuid = 0; /* XXX fixed */
 960         else
 961                 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
 962         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
 963         e1000_clear_hw_cntrs_base_generic(&sc->hw);
 964
 965         /* This clears any pending interrupts */
 966         E1000_READ_REG(&sc->hw, E1000_ICR);
 967
 968         /*
 969          * Only enable interrupts if we are not polling, make sure
 970          * they are off otherwise.
 971          */
 972         if (polling) {
 973                 igb_disable_intr(sc);
 974         } else {
 975                 igb_enable_intr(sc);
 976                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
 977         }
 978
 979         /* Set Energy Efficient Ethernet */
 980         e1000_set_eee_i350(&sc->hw);
 981
 982         /* Don't reset the phy next time init gets called */
 983         sc->hw.phy.reset_disable = TRUE;
 984 }
 985
 986 static void
 987 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
 988 {
 989         struct igb_softc *sc = ifp->if_softc;
 990         u_char fiber_type = IFM_1000_SX;
 991
 992         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 993
 994         igb_update_link_status(sc);
 995
 996         ifmr->ifm_status = IFM_AVALID;
 997         ifmr->ifm_active = IFM_ETHER;
 998
 999         if (!sc->link_active)
1000                 return;
1001
1002         ifmr->ifm_status |= IFM_ACTIVE;
1003
1004         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1005             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1006                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1007         } else {
1008                 switch (sc->link_speed) {
1009                 case 10:
1010                         ifmr->ifm_active |= IFM_10_T;
1011                         break;
1012
1013                 case 100:
1014                         ifmr->ifm_active |= IFM_100_TX;
1015                         break;
1016
1017                 case 1000:
1018                         ifmr->ifm_active |= IFM_1000_T;
1019                         break;
1020                 }
1021                 if (sc->link_duplex == FULL_DUPLEX)
1022                         ifmr->ifm_active |= IFM_FDX;
1023                 else
1024                         ifmr->ifm_active |= IFM_HDX;
1025         }
1026 }
1027
1028 static int
1029 igb_media_change(struct ifnet *ifp)
1030 {
1031         struct igb_softc *sc = ifp->if_softc;
1032         struct ifmedia *ifm = &sc->media;
1033
1034         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1035
1036         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1037                 return EINVAL;
1038
1039         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1040         case IFM_AUTO:
1041                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1042                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1043                 break;
1044
1045         case IFM_1000_LX:
1046         case IFM_1000_SX:
1047         case IFM_1000_T:
1048                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1049                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1050                 break;
1051
1052         case IFM_100_TX:
1053                 sc->hw.mac.autoneg = FALSE;
1054                 sc->hw.phy.autoneg_advertised = 0;
1055                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1056                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1057                 else
1058                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1059                 break;
1060
1061         case IFM_10_T:
1062                 sc->hw.mac.autoneg = FALSE;
1063                 sc->hw.phy.autoneg_advertised = 0;
1064                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1065                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1066                 else
1067                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1068                 break;
1069
1070         default:
1071                 if_printf(ifp, "Unsupported media type\n");
1072                 break;
1073         }
1074
1075         igb_init(sc);
1076
1077         return 0;
1078 }
1079
1080 static void
1081 igb_set_promisc(struct igb_softc *sc)
1082 {
1083         struct ifnet *ifp = &sc->arpcom.ac_if;
1084         struct e1000_hw *hw = &sc->hw;
1085         uint32_t reg;
1086
1087         if (sc->vf_ifp) {
1088                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1089                 return;
1090         }
1091
1092         reg = E1000_READ_REG(hw, E1000_RCTL);
1093         if (ifp->if_flags & IFF_PROMISC) {
1094                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1095                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1096         } else if (ifp->if_flags & IFF_ALLMULTI) {
1097                 reg |= E1000_RCTL_MPE;
1098                 reg &= ~E1000_RCTL_UPE;
1099                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1100         }
1101 }
1102
1103 static void
1104 igb_disable_promisc(struct igb_softc *sc)
1105 {
1106         struct e1000_hw *hw = &sc->hw;
1107         uint32_t reg;
1108
1109         if (sc->vf_ifp) {
1110                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1111                 return;
1112         }
1113         reg = E1000_READ_REG(hw, E1000_RCTL);
1114         reg &= ~E1000_RCTL_UPE;
1115         reg &= ~E1000_RCTL_MPE;
1116         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1117 }
1118
1119 static void
1120 igb_set_multi(struct igb_softc *sc)
1121 {
1122         struct ifnet *ifp = &sc->arpcom.ac_if;
1123         struct ifmultiaddr *ifma;
1124         uint32_t reg_rctl = 0;
1125         uint8_t *mta;
1126         int mcnt = 0;
1127
1128         mta = sc->mta;
1129         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1130
1131         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1132                 if (ifma->ifma_addr->sa_family != AF_LINK)
1133                         continue;
1134
1135                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1136                         break;
1137
1138                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1139                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1140                 mcnt++;
1141         }
1142
1143         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1144                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1145                 reg_rctl |= E1000_RCTL_MPE;
1146                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1147         } else {
1148                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1149         }
1150 }
1151
1152 static void
1153 igb_timer(void *xsc)
1154 {
1155         struct igb_softc *sc = xsc;
1156
1157         lwkt_serialize_enter(&sc->main_serialize);
1158
1159         igb_update_link_status(sc);
1160         igb_update_stats_counters(sc);
1161
1162         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1163
1164         lwkt_serialize_exit(&sc->main_serialize);
1165 }
1166
1167 static void
1168 igb_update_link_status(struct igb_softc *sc)
1169 {
1170         struct ifnet *ifp = &sc->arpcom.ac_if;
1171         struct e1000_hw *hw = &sc->hw;
1172         uint32_t link_check, thstat, ctrl;
1173
1174         link_check = thstat = ctrl = 0;
1175
1176         /* Get the cached link value or read for real */
1177         switch (hw->phy.media_type) {
1178         case e1000_media_type_copper:
1179                 if (hw->mac.get_link_status) {
1180                         /* Do the work to read phy */
1181                         e1000_check_for_link(hw);
1182                         link_check = !hw->mac.get_link_status;
1183                 } else {
1184                         link_check = TRUE;
1185                 }
1186                 break;
1187
1188         case e1000_media_type_fiber:
1189                 e1000_check_for_link(hw);
1190                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1191                 break;
1192
1193         case e1000_media_type_internal_serdes:
1194                 e1000_check_for_link(hw);
1195                 link_check = hw->mac.serdes_has_link;
1196                 break;
1197
1198         /* VF device is type_unknown */
1199         case e1000_media_type_unknown:
1200                 e1000_check_for_link(hw);
1201                 link_check = !hw->mac.get_link_status;
1202                 /* Fall thru */
1203         default:
1204                 break;
1205         }
1206
1207         /* Check for thermal downshift or shutdown */
1208         if (hw->mac.type == e1000_i350) {
1209                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1210                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1211         }
1212
1213         /* Now we check if a transition has happened */
1214         if (link_check && sc->link_active == 0) {
1215                 e1000_get_speed_and_duplex(hw,
1216                     &sc->link_speed, &sc->link_duplex);
1217                 if (bootverbose) {
1218                         if_printf(ifp, "Link is up %d Mbps %s\n",
1219                             sc->link_speed,
1220                             sc->link_duplex == FULL_DUPLEX ?
1221                             "Full Duplex" : "Half Duplex");
1222                 }
1223                 sc->link_active = 1;
1224
1225                 ifp->if_baudrate = sc->link_speed * 1000000;
1226                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1227                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1228                         if_printf(ifp, "Link: thermal downshift\n");
1229                 /* This can sleep */
1230                 ifp->if_link_state = LINK_STATE_UP;
1231                 if_link_state_change(ifp);
1232         } else if (!link_check && sc->link_active == 1) {
1233                 ifp->if_baudrate = sc->link_speed = 0;
1234                 sc->link_duplex = 0;
1235                 if (bootverbose)
1236                         if_printf(ifp, "Link is Down\n");
1237                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1238                     (thstat & E1000_THSTAT_PWR_DOWN))
1239                         if_printf(ifp, "Link: thermal shutdown\n");
1240                 sc->link_active = 0;
1241                 /* This can sleep */
1242                 ifp->if_link_state = LINK_STATE_DOWN;
1243                 if_link_state_change(ifp);
1244         }
1245 }
1246
1247 static void
1248 igb_stop(struct igb_softc *sc)
1249 {
1250         struct ifnet *ifp = &sc->arpcom.ac_if;
1251         int i;
1252
1253         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1254
1255         igb_disable_intr(sc);
1256
1257         callout_stop(&sc->timer);
1258
1259         ifp->if_flags &= ~IFF_RUNNING;
1260         ifq_clr_oactive(&ifp->if_snd);
1261         ifp->if_timer = 0;
1262
1263         e1000_reset_hw(&sc->hw);
1264         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1265
1266         e1000_led_off(&sc->hw);
1267         e1000_cleanup_led(&sc->hw);
1268
1269         for (i = 0; i < sc->tx_ring_cnt; ++i)
1270                 igb_free_tx_ring(&sc->tx_rings[i]);
1271         for (i = 0; i < sc->rx_ring_cnt; ++i)
1272                 igb_free_rx_ring(&sc->rx_rings[i]);
1273 }
1274
1275 static void
1276 igb_reset(struct igb_softc *sc)
1277 {
1278         struct ifnet *ifp = &sc->arpcom.ac_if;
1279         struct e1000_hw *hw = &sc->hw;
1280         struct e1000_fc_info *fc = &hw->fc;
1281         uint32_t pba = 0;
1282         uint16_t hwm;
1283
1284         /* Let the firmware know the OS is in control */
1285         igb_get_hw_control(sc);
1286
1287         /*
1288          * Packet Buffer Allocation (PBA)
1289          * Writing PBA sets the receive portion of the buffer
1290          * the remainder is used for the transmit buffer.
1291          */
1292         switch (hw->mac.type) {
1293         case e1000_82575:
1294                 pba = E1000_PBA_32K;
1295                 break;
1296
1297         case e1000_82576:
1298         case e1000_vfadapt:
1299                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1300                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1301                 break;
1302
1303         case e1000_82580:
1304         case e1000_i350:
1305         case e1000_vfadapt_i350:
1306                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1307                 pba = e1000_rxpbs_adjust_82580(pba);
1308                 break;
1309                 /* XXX pba = E1000_PBA_35K; */
1310
1311         default:
1312                 break;
1313         }
1314
1315         /* Special needs in case of Jumbo frames */
1316         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1317                 uint32_t tx_space, min_tx, min_rx;
1318
1319                 pba = E1000_READ_REG(hw, E1000_PBA);
1320                 tx_space = pba >> 16;
1321                 pba &= 0xffff;
1322
1323                 min_tx = (sc->max_frame_size +
1324                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1325                 min_tx = roundup2(min_tx, 1024);
1326                 min_tx >>= 10;
1327                 min_rx = sc->max_frame_size;
1328                 min_rx = roundup2(min_rx, 1024);
1329                 min_rx >>= 10;
1330                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1331                         pba = pba - (min_tx - tx_space);
1332                         /*
1333                          * if short on rx space, rx wins
1334                          * and must trump tx adjustment
1335                          */
1336                         if (pba < min_rx)
1337                                 pba = min_rx;
1338                 }
1339                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1340         }
1341
1342         /*
1343          * These parameters control the automatic generation (Tx) and
1344          * response (Rx) to Ethernet PAUSE frames.
1345          * - High water mark should allow for at least two frames to be
1346          *   received after sending an XOFF.
1347          * - Low water mark works best when it is very near the high water mark.
1348          *   This allows the receiver to restart by sending XON when it has
1349          *   drained a bit.
1350          */
1351         hwm = min(((pba << 10) * 9 / 10),
1352             ((pba << 10) - 2 * sc->max_frame_size));
1353
1354         if (hw->mac.type < e1000_82576) {
1355                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1356                 fc->low_water = fc->high_water - 8;
1357         } else {
1358                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1359                 fc->low_water = fc->high_water - 16;
1360         }
1361         fc->pause_time = IGB_FC_PAUSE_TIME;
1362         fc->send_xon = TRUE;
1363
1364         /* Issue a global reset */
1365         e1000_reset_hw(hw);
1366         E1000_WRITE_REG(hw, E1000_WUC, 0);
1367
1368         if (e1000_init_hw(hw) < 0)
1369                 if_printf(ifp, "Hardware Initialization Failed\n");
1370
1371         /* Setup DMA Coalescing */
1372         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1373                 uint32_t reg;
1374
1375                 hwm = (pba - 4) << 10;
1376                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1377                     & E1000_DMACR_DMACTHR_MASK;
1378
1379                 /* transition to L0x or L1 if available..*/
1380                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1381
1382                 /* timer = +-1000 usec in 32usec intervals */
1383                 reg |= (1000 >> 5);
1384                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1385
1386                 /* No lower threshold */
1387                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1388
1389                 /* set hwm to PBA -  2 * max frame size */
1390                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1391
1392                 /* Set the interval before transition */
1393                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1394                 reg |= 0x800000FF; /* 255 usec */
1395                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1396
1397                 /* free space in tx packet buffer to wake from DMA coal */
1398                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1399                     (20480 - (2 * sc->max_frame_size)) >> 6);
1400
1401                 /* make low power state decision controlled by DMA coal */
1402                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1403                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1404                     reg | E1000_PCIEMISC_LX_DECISION);
1405                 if_printf(ifp, "DMA Coalescing enabled\n");
1406         }
1407
1408         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1409         e1000_get_phy_info(hw);
1410         e1000_check_for_link(hw);
1411 }
1412
1413 static void
1414 igb_setup_ifp(struct igb_softc *sc)
1415 {
1416         struct ifnet *ifp = &sc->arpcom.ac_if;
1417
1418         ifp->if_softc = sc;
1419         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1420         ifp->if_init = igb_init;
1421         ifp->if_ioctl = igb_ioctl;
1422         ifp->if_start = igb_start;
1423         ifp->if_serialize = igb_serialize;
1424         ifp->if_deserialize = igb_deserialize;
1425         ifp->if_tryserialize = igb_tryserialize;
1426 #ifdef INVARIANTS
1427         ifp->if_serialize_assert = igb_serialize_assert;
1428 #endif
1429 #ifdef IFPOLL_ENABLE
1430         ifp->if_npoll = igb_npoll;
1431 #endif
1432         ifp->if_watchdog = igb_watchdog;
1433
1434         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1435         ifq_set_ready(&ifp->if_snd);
1436
1437         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1438
1439         ifp->if_capabilities =
1440             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1441         if (IGB_ENABLE_HWRSS(sc))
1442                 ifp->if_capabilities |= IFCAP_RSS;
1443         ifp->if_capenable = ifp->if_capabilities;
1444         ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1445
1446         /*
1447          * Tell the upper layer(s) we support long frames
1448          */
1449         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1450
1451         /*
1452          * Specify the media types supported by this adapter and register
1453          * callbacks to update media and link information
1454          */
1455         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1456         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1457             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1458                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1459                     0, NULL);
1460                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1461         } else {
1462                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1463                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1464                     0, NULL);
1465                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1466                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1467                     0, NULL);
1468                 if (sc->hw.phy.type != e1000_phy_ife) {
1469                         ifmedia_add(&sc->media,
1470                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1471                         ifmedia_add(&sc->media,
1472                             IFM_ETHER | IFM_1000_T, 0, NULL);
1473                 }
1474         }
1475         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1476         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1477 }
1478
1479 static void
1480 igb_add_sysctl(struct igb_softc *sc)
1481 {
1482         char node[32];
1483         int i;
1484
1485         sysctl_ctx_init(&sc->sysctl_ctx);
1486         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1487             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1488             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1489         if (sc->sysctl_tree == NULL) {
1490                 device_printf(sc->dev, "can't add sysctl node\n");
1491                 return;
1492         }
1493
1494         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1495             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1496         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1497             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1498             "# of RX rings used");
1499         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1500             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1501             "# of RX descs");
1502         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1503             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1504             "# of TX descs");
1505
1506         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1507                 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1508                     SYSCTL_CHILDREN(sc->sysctl_tree),
1509                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1510                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1511         } else {
1512                 for (i = 0; i < sc->msix_cnt; ++i) {
1513                         struct igb_msix_data *msix = &sc->msix_data[i];
1514
1515                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1516                         SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1517                             SYSCTL_CHILDREN(sc->sysctl_tree),
1518                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1519                             msix, 0, igb_sysctl_msix_rate, "I",
1520                             msix->msix_rate_desc);
1521                 }
1522         }
1523
1524         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1525             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1526             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1527             "# of segments per TX interrupt");
1528
1529         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1530             OID_AUTO, "tx_wreg_nsegs", CTLFLAG_RW,
1531             &sc->tx_rings[0].wreg_nsegs, 0,
1532             "# of segments before write to hardare register");
1533
1534 #ifdef IFPOLL_ENABLE
1535         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1536             OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1537             sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1538         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1539             OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1540             sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1541 #endif
1542
1543 #ifdef IGB_RSS_DEBUG
1544         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1545             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1546             "RSS debug level");
1547 #endif
1548         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1549 #ifdef IGB_RSS_DEBUG
1550                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1551                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1552                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1553                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1554 #endif
1555                 ksnprintf(node, sizeof(node), "rx%d_wreg", i);
1556                 SYSCTL_ADD_INT(&sc->sysctl_ctx,
1557                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1558                     CTLFLAG_RW, &sc->rx_rings[i].rx_wreg, 0,
1559                     "# of segments before write to hardare register");
1560         }
1561 }
1562
1563 static int
1564 igb_alloc_rings(struct igb_softc *sc)
1565 {
1566         int error, i;
1567
1568         /*
1569          * Create top level busdma tag
1570          */
1571         error = bus_dma_tag_create(NULL, 1, 0,
1572             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1573             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1574             &sc->parent_tag);
1575         if (error) {
1576                 device_printf(sc->dev, "could not create top level DMA tag\n");
1577                 return error;
1578         }
1579
1580         /*
1581          * Allocate TX descriptor rings and buffers
1582          */
1583         sc->tx_rings = kmalloc_cachealign(
1584             sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1585             M_DEVBUF, M_WAITOK | M_ZERO);
1586         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1587                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1588
1589                 /* Set up some basics */
1590                 txr->sc = sc;
1591                 txr->me = i;
1592                 lwkt_serialize_init(&txr->tx_serialize);
1593
1594                 error = igb_create_tx_ring(txr);
1595                 if (error)
1596                         return error;
1597         }
1598
1599         /*
1600          * Allocate RX descriptor rings and buffers
1601          */
1602         sc->rx_rings = kmalloc_cachealign(
1603             sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1604             M_DEVBUF, M_WAITOK | M_ZERO);
1605         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1606                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1607
1608                 /* Set up some basics */
1609                 rxr->sc = sc;
1610                 rxr->me = i;
1611                 lwkt_serialize_init(&rxr->rx_serialize);
1612
1613                 error = igb_create_rx_ring(rxr);
1614                 if (error)
1615                         return error;
1616         }
1617
1618         return 0;
1619 }
1620
1621 static void
1622 igb_free_rings(struct igb_softc *sc)
1623 {
1624         int i;
1625
1626         if (sc->tx_rings != NULL) {
1627                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1628                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1629
1630                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1631                 }
1632                 kfree(sc->tx_rings, M_DEVBUF);
1633         }
1634
1635         if (sc->rx_rings != NULL) {
1636                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1637                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1638
1639                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1640                 }
1641                 kfree(sc->rx_rings, M_DEVBUF);
1642         }
1643 }
1644
1645 static int
1646 igb_create_tx_ring(struct igb_tx_ring *txr)
1647 {
1648         int tsize, error, i, ntxd;
1649
1650         /*
1651          * Validate number of transmit descriptors. It must not exceed
1652          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1653          */
1654         ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1655         if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1656             ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1657                 device_printf(txr->sc->dev,
1658                     "Using %d TX descriptors instead of %d!\n",
1659                     IGB_DEFAULT_TXD, ntxd);
1660                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1661         } else {
1662                 txr->num_tx_desc = ntxd;
1663         }
1664
1665         /*
1666          * Allocate TX descriptor ring
1667          */
1668         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1669             IGB_DBA_ALIGN);
1670         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1671             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1672             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1673         if (txr->txdma.dma_vaddr == NULL) {
1674                 device_printf(txr->sc->dev,
1675                     "Unable to allocate TX Descriptor memory\n");
1676                 return ENOMEM;
1677         }
1678         txr->tx_base = txr->txdma.dma_vaddr;
1679         bzero(txr->tx_base, tsize);
1680
1681         tsize = __VM_CACHELINE_ALIGN(
1682             sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1683         txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1684
1685         /*
1686          * Allocate TX head write-back buffer
1687          */
1688         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1689             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1690             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1691         if (txr->tx_hdr == NULL) {
1692                 device_printf(txr->sc->dev,
1693                     "Unable to allocate TX head write-back buffer\n");
1694                 return ENOMEM;
1695         }
1696
1697         /*
1698          * Create DMA tag for TX buffers
1699          */
1700         error = bus_dma_tag_create(txr->sc->parent_tag,
1701             1, 0,               /* alignment, bounds */
1702             BUS_SPACE_MAXADDR,  /* lowaddr */
1703             BUS_SPACE_MAXADDR,  /* highaddr */
1704             NULL, NULL,         /* filter, filterarg */
1705             IGB_TSO_SIZE,       /* maxsize */
1706             IGB_MAX_SCATTER,    /* nsegments */
1707             PAGE_SIZE,          /* maxsegsize */
1708             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1709             BUS_DMA_ONEBPAGE,   /* flags */
1710             &txr->tx_tag);
1711         if (error) {
1712                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1713                 kfree(txr->tx_buf, M_DEVBUF);
1714                 txr->tx_buf = NULL;
1715                 return error;
1716         }
1717
1718         /*
1719          * Create DMA maps for TX buffers
1720          */
1721         for (i = 0; i < txr->num_tx_desc; ++i) {
1722                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1723
1724                 error = bus_dmamap_create(txr->tx_tag,
1725                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1726                 if (error) {
1727                         device_printf(txr->sc->dev,
1728                             "Unable to create TX DMA map\n");
1729                         igb_destroy_tx_ring(txr, i);
1730                         return error;
1731                 }
1732         }
1733
1734         /*
1735          * Initialize various watermark
1736          */
1737         txr->spare_desc = IGB_TX_SPARE;
1738         txr->intr_nsegs = txr->num_tx_desc / 16;
1739         txr->wreg_nsegs = 8;
1740         txr->oact_hi_desc = txr->num_tx_desc / 2;
1741         txr->oact_lo_desc = txr->num_tx_desc / 8;
1742         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1743                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1744         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1745                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1746
1747         return 0;
1748 }
1749
1750 static void
1751 igb_free_tx_ring(struct igb_tx_ring *txr)
1752 {
1753         int i;
1754
1755         for (i = 0; i < txr->num_tx_desc; ++i) {
1756                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1757
1758                 if (txbuf->m_head != NULL) {
1759                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1760                         m_freem(txbuf->m_head);
1761                         txbuf->m_head = NULL;
1762                 }
1763         }
1764 }
1765
1766 static void
1767 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1768 {
1769         int i;
1770
1771         if (txr->txdma.dma_vaddr != NULL) {
1772                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1773                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1774                     txr->txdma.dma_map);
1775                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1776                 txr->txdma.dma_vaddr = NULL;
1777         }
1778
1779         if (txr->tx_hdr != NULL) {
1780                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1781                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1782                     txr->tx_hdr_dmap);
1783                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1784                 txr->tx_hdr = NULL;
1785         }
1786
1787         if (txr->tx_buf == NULL)
1788                 return;
1789
1790         for (i = 0; i < ndesc; ++i) {
1791                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1792
1793                 KKASSERT(txbuf->m_head == NULL);
1794                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1795         }
1796         bus_dma_tag_destroy(txr->tx_tag);
1797
1798         kfree(txr->tx_buf, M_DEVBUF);
1799         txr->tx_buf = NULL;
1800 }
1801
1802 static void
1803 igb_init_tx_ring(struct igb_tx_ring *txr)
1804 {
1805         /* Clear the old descriptor contents */
1806         bzero(txr->tx_base,
1807             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1808
1809         /* Clear TX head write-back buffer */
1810         *(txr->tx_hdr) = 0;
1811
1812         /* Reset indices */
1813         txr->next_avail_desc = 0;
1814         txr->next_to_clean = 0;
1815         txr->tx_nsegs = 0;
1816
1817         /* Set number of descriptors available */
1818         txr->tx_avail = txr->num_tx_desc;
1819 }
1820
1821 static void
1822 igb_init_tx_unit(struct igb_softc *sc)
1823 {
1824         struct e1000_hw *hw = &sc->hw;
1825         uint32_t tctl;
1826         int i;
1827
1828         /* Setup the Tx Descriptor Rings */
1829         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1830                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1831                 uint64_t bus_addr = txr->txdma.dma_paddr;
1832                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1833                 uint32_t txdctl = 0;
1834                 uint32_t dca_txctrl;
1835
1836                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1837                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1838                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1839                     (uint32_t)(bus_addr >> 32));
1840                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1841                     (uint32_t)bus_addr);
1842
1843                 /* Setup the HW Tx Head and Tail descriptor pointers */
1844                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1845                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1846
1847                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1848                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1849                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1850
1851                 /*
1852                  * Don't set WB_on_EITR:
1853                  * - 82575 does not have it
1854                  * - It almost has no effect on 82576, see:
1855                  *   82576 specification update errata #26
1856                  * - It causes unnecessary bus traffic
1857                  */
1858                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1859                     (uint32_t)(hdr_paddr >> 32));
1860                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1861                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1862
1863                 /*
1864                  * WTHRESH is ignored by the hardware, since header
1865                  * write back mode is used.
1866                  */
1867                 txdctl |= IGB_TX_PTHRESH;
1868                 txdctl |= IGB_TX_HTHRESH << 8;
1869                 txdctl |= IGB_TX_WTHRESH << 16;
1870                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1871                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1872         }
1873
1874         if (sc->vf_ifp)
1875                 return;
1876
1877         e1000_config_collision_dist(hw);
1878
1879         /* Program the Transmit Control Register */
1880         tctl = E1000_READ_REG(hw, E1000_TCTL);
1881         tctl &= ~E1000_TCTL_CT;
1882         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1883             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1884
1885         /* This write will effectively turn on the transmit unit. */
1886         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1887 }
1888
1889 static boolean_t
1890 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1891 {
1892         struct e1000_adv_tx_context_desc *TXD;
1893         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1894         int ehdrlen, ctxd, ip_hlen = 0;
1895         boolean_t offload = TRUE;
1896
1897         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1898                 offload = FALSE;
1899
1900         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1901
1902         ctxd = txr->next_avail_desc;
1903         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1904
1905         /*
1906          * In advanced descriptors the vlan tag must
1907          * be placed into the context descriptor, thus
1908          * we need to be here just for that setup.
1909          */
1910         if (mp->m_flags & M_VLANTAG) {
1911                 uint16_t vlantag;
1912
1913                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1914                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1915         } else if (!offload) {
1916                 return FALSE;
1917         }
1918
1919         ehdrlen = mp->m_pkthdr.csum_lhlen;
1920         KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1921
1922         /* Set the ether header length */
1923         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1924         if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1925                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1926                 ip_hlen = mp->m_pkthdr.csum_iphlen;
1927                 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1928         }
1929         vlan_macip_lens |= ip_hlen;
1930
1931         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1932         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1933                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1934         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1935                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1936
1937         /* 82575 needs the queue index added */
1938         if (txr->sc->hw.mac.type == e1000_82575)
1939                 mss_l4len_idx = txr->me << 4;
1940
1941         /* Now copy bits into descriptor */
1942         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1943         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1944         TXD->seqnum_seed = htole32(0);
1945         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1946
1947         /* We've consumed the first desc, adjust counters */
1948         if (++ctxd == txr->num_tx_desc)
1949                 ctxd = 0;
1950         txr->next_avail_desc = ctxd;
1951         --txr->tx_avail;
1952
1953         return offload;
1954 }
1955
1956 static void
1957 igb_txeof(struct igb_tx_ring *txr)
1958 {
1959         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1960         int first, hdr, avail;
1961
1962         if (txr->tx_avail == txr->num_tx_desc)
1963                 return;
1964
1965         first = txr->next_to_clean;
1966         hdr = *(txr->tx_hdr);
1967
1968         if (first == hdr)
1969                 return;
1970
1971         avail = txr->tx_avail;
1972         while (first != hdr) {
1973                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1974
1975                 ++avail;
1976                 if (txbuf->m_head) {
1977                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1978                         m_freem(txbuf->m_head);
1979                         txbuf->m_head = NULL;
1980                         ++ifp->if_opackets;
1981                 }
1982                 if (++first == txr->num_tx_desc)
1983                         first = 0;
1984         }
1985         txr->next_to_clean = first;
1986         txr->tx_avail = avail;
1987
1988         /*
1989          * If we have a minimum free, clear OACTIVE
1990          * to tell the stack that it is OK to send packets.
1991          */
1992         if (IGB_IS_NOT_OACTIVE(txr)) {
1993                 ifq_clr_oactive(&ifp->if_snd);
1994
1995                 /*
1996                  * We have enough TX descriptors, turn off
1997                  * the watchdog.  We allow small amount of
1998                  * packets (roughly intr_nsegs) pending on
1999                  * the transmit ring.
2000                  */
2001                 ifp->if_timer = 0;
2002         }
2003 }
2004
2005 static int
2006 igb_create_rx_ring(struct igb_rx_ring *rxr)
2007 {
2008         int rsize, i, error, nrxd;
2009
2010         /*
2011          * Validate number of receive descriptors. It must not exceed
2012          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2013          */
2014         nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2015         if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2016             nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2017                 device_printf(rxr->sc->dev,
2018                     "Using %d RX descriptors instead of %d!\n",
2019                     IGB_DEFAULT_RXD, nrxd);
2020                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2021         } else {
2022                 rxr->num_rx_desc = nrxd;
2023         }
2024
2025         /*
2026          * Allocate RX descriptor ring
2027          */
2028         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2029             IGB_DBA_ALIGN);
2030         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2031             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2032             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2033             &rxr->rxdma.dma_paddr);
2034         if (rxr->rxdma.dma_vaddr == NULL) {
2035                 device_printf(rxr->sc->dev,
2036                     "Unable to allocate RxDescriptor memory\n");
2037                 return ENOMEM;
2038         }
2039         rxr->rx_base = rxr->rxdma.dma_vaddr;
2040         bzero(rxr->rx_base, rsize);
2041
2042         rsize = __VM_CACHELINE_ALIGN(
2043             sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2044         rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2045
2046         /*
2047          * Create DMA tag for RX buffers
2048          */
2049         error = bus_dma_tag_create(rxr->sc->parent_tag,
2050             1, 0,               /* alignment, bounds */
2051             BUS_SPACE_MAXADDR,  /* lowaddr */
2052             BUS_SPACE_MAXADDR,  /* highaddr */
2053             NULL, NULL,         /* filter, filterarg */
2054             MCLBYTES,           /* maxsize */
2055             1,                  /* nsegments */
2056             MCLBYTES,           /* maxsegsize */
2057             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2058             &rxr->rx_tag);
2059         if (error) {
2060                 device_printf(rxr->sc->dev,
2061                     "Unable to create RX payload DMA tag\n");
2062                 kfree(rxr->rx_buf, M_DEVBUF);
2063                 rxr->rx_buf = NULL;
2064                 return error;
2065         }
2066
2067         /*
2068          * Create spare DMA map for RX buffers
2069          */
2070         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2071             &rxr->rx_sparemap);
2072         if (error) {
2073                 device_printf(rxr->sc->dev,
2074                     "Unable to create spare RX DMA maps\n");
2075                 bus_dma_tag_destroy(rxr->rx_tag);
2076                 kfree(rxr->rx_buf, M_DEVBUF);
2077                 rxr->rx_buf = NULL;
2078                 return error;
2079         }
2080
2081         /*
2082          * Create DMA maps for RX buffers
2083          */
2084         for (i = 0; i < rxr->num_rx_desc; i++) {
2085                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2086
2087                 error = bus_dmamap_create(rxr->rx_tag,
2088                     BUS_DMA_WAITOK, &rxbuf->map);
2089                 if (error) {
2090                         device_printf(rxr->sc->dev,
2091                             "Unable to create RX DMA maps\n");
2092                         igb_destroy_rx_ring(rxr, i);
2093                         return error;
2094                 }
2095         }
2096
2097         /*
2098          * Initialize various watermark
2099          */
2100         rxr->rx_wreg = 32;
2101
2102         return 0;
2103 }
2104
2105 static void
2106 igb_free_rx_ring(struct igb_rx_ring *rxr)
2107 {
2108         int i;
2109
2110         for (i = 0; i < rxr->num_rx_desc; ++i) {
2111                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2112
2113                 if (rxbuf->m_head != NULL) {
2114                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2115                         m_freem(rxbuf->m_head);
2116                         rxbuf->m_head = NULL;
2117                 }
2118         }
2119
2120         if (rxr->fmp != NULL)
2121                 m_freem(rxr->fmp);
2122         rxr->fmp = NULL;
2123         rxr->lmp = NULL;
2124 }
2125
2126 static void
2127 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2128 {
2129         int i;
2130
2131         if (rxr->rxdma.dma_vaddr != NULL) {
2132                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2133                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2134                     rxr->rxdma.dma_map);
2135                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2136                 rxr->rxdma.dma_vaddr = NULL;
2137         }
2138
2139         if (rxr->rx_buf == NULL)
2140                 return;
2141
2142         for (i = 0; i < ndesc; ++i) {
2143                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2144
2145                 KKASSERT(rxbuf->m_head == NULL);
2146                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2147         }
2148         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2149         bus_dma_tag_destroy(rxr->rx_tag);
2150
2151         kfree(rxr->rx_buf, M_DEVBUF);
2152         rxr->rx_buf = NULL;
2153 }
2154
2155 static void
2156 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2157 {
2158         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2159         rxd->wb.upper.status_error = 0;
2160 }
2161
2162 static int
2163 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2164 {
2165         struct mbuf *m;
2166         bus_dma_segment_t seg;
2167         bus_dmamap_t map;
2168         struct igb_rx_buf *rxbuf;
2169         int error, nseg;
2170
2171         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2172         if (m == NULL) {
2173                 if (wait) {
2174                         if_printf(&rxr->sc->arpcom.ac_if,
2175                             "Unable to allocate RX mbuf\n");
2176                 }
2177                 return ENOBUFS;
2178         }
2179         m->m_len = m->m_pkthdr.len = MCLBYTES;
2180
2181         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2182                 m_adj(m, ETHER_ALIGN);
2183
2184         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2185             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2186         if (error) {
2187                 m_freem(m);
2188                 if (wait) {
2189                         if_printf(&rxr->sc->arpcom.ac_if,
2190                             "Unable to load RX mbuf\n");
2191                 }
2192                 return error;
2193         }
2194
2195         rxbuf = &rxr->rx_buf[i];
2196         if (rxbuf->m_head != NULL)
2197                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2198
2199         map = rxbuf->map;
2200         rxbuf->map = rxr->rx_sparemap;
2201         rxr->rx_sparemap = map;
2202
2203         rxbuf->m_head = m;
2204         rxbuf->paddr = seg.ds_addr;
2205
2206         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2207         return 0;
2208 }
2209
2210 static int
2211 igb_init_rx_ring(struct igb_rx_ring *rxr)
2212 {
2213         int i;
2214
2215         /* Clear the ring contents */
2216         bzero(rxr->rx_base,
2217             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2218
2219         /* Now replenish the ring mbufs */
2220         for (i = 0; i < rxr->num_rx_desc; ++i) {
2221                 int error;
2222
2223                 error = igb_newbuf(rxr, i, TRUE);
2224                 if (error)
2225                         return error;
2226         }
2227
2228         /* Setup our descriptor indices */
2229         rxr->next_to_check = 0;
2230
2231         rxr->fmp = NULL;
2232         rxr->lmp = NULL;
2233         rxr->discard = FALSE;
2234
2235         return 0;
2236 }
2237
2238 static void
2239 igb_init_rx_unit(struct igb_softc *sc)
2240 {
2241         struct ifnet *ifp = &sc->arpcom.ac_if;
2242         struct e1000_hw *hw = &sc->hw;
2243         uint32_t rctl, rxcsum, srrctl = 0;
2244         int i;
2245
2246         /*
2247          * Make sure receives are disabled while setting
2248          * up the descriptor ring
2249          */
2250         rctl = E1000_READ_REG(hw, E1000_RCTL);
2251         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2252
2253 #if 0
2254         /*
2255         ** Set up for header split
2256         */
2257         if (igb_header_split) {
2258                 /* Use a standard mbuf for the header */
2259                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2260                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2261         } else
2262 #endif
2263                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2264
2265         /*
2266         ** Set up for jumbo frames
2267         */
2268         if (ifp->if_mtu > ETHERMTU) {
2269                 rctl |= E1000_RCTL_LPE;
2270 #if 0
2271                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2272                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2273                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2274                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2275                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2276                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2277                 }
2278                 /* Set maximum packet len */
2279                 psize = adapter->max_frame_size;
2280                 /* are we on a vlan? */
2281                 if (adapter->ifp->if_vlantrunk != NULL)
2282                         psize += VLAN_TAG_SIZE;
2283                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2284 #else
2285                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2286                 rctl |= E1000_RCTL_SZ_2048;
2287 #endif
2288         } else {
2289                 rctl &= ~E1000_RCTL_LPE;
2290                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2291                 rctl |= E1000_RCTL_SZ_2048;
2292         }
2293
2294         /* Setup the Base and Length of the Rx Descriptor Rings */
2295         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2296                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2297                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2298                 uint32_t rxdctl;
2299
2300                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2301                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2302                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2303                     (uint32_t)(bus_addr >> 32));
2304                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2305                     (uint32_t)bus_addr);
2306                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2307                 /* Enable this Queue */
2308                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2309                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2310                 rxdctl &= 0xFFF00000;
2311                 rxdctl |= IGB_RX_PTHRESH;
2312                 rxdctl |= IGB_RX_HTHRESH << 8;
2313                 /*
2314                  * Don't set WTHRESH to a value above 1 on 82576, see:
2315                  * 82576 specification update errata #26
2316                  */
2317                 rxdctl |= IGB_RX_WTHRESH << 16;
2318                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2319         }
2320
2321         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2322         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2323
2324         /*
2325          * Receive Checksum Offload for TCP and UDP
2326          *
2327          * Checksum offloading is also enabled if multiple receive
2328          * queue is to be supported, since we need it to figure out
2329          * fragments.
2330          */
2331         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2332                 /*
2333                  * NOTE:
2334                  * PCSD must be enabled to enable multiple
2335                  * receive queues.
2336                  */
2337                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2338                     E1000_RXCSUM_PCSD;
2339         } else {
2340                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2341                     E1000_RXCSUM_PCSD);
2342         }
2343         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2344
2345         if (IGB_ENABLE_HWRSS(sc)) {
2346                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2347                 uint32_t reta_shift;
2348                 int j, r;
2349
2350                 /*
2351                  * NOTE:
2352                  * When we reach here, RSS has already been disabled
2353                  * in igb_stop(), so we could safely configure RSS key
2354                  * and redirect table.
2355                  */
2356
2357                 /*
2358                  * Configure RSS key
2359                  */
2360                 toeplitz_get_key(key, sizeof(key));
2361                 for (i = 0; i < IGB_NRSSRK; ++i) {
2362                         uint32_t rssrk;
2363
2364                         rssrk = IGB_RSSRK_VAL(key, i);
2365                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2366
2367                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2368                 }
2369
2370                 /*
2371                  * Configure RSS redirect table in following fashion:
2372                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2373                  */
2374                 reta_shift = IGB_RETA_SHIFT;
2375                 if (hw->mac.type == e1000_82575)
2376                         reta_shift = IGB_RETA_SHIFT_82575;
2377
2378                 r = 0;
2379                 for (j = 0; j < IGB_NRETA; ++j) {
2380                         uint32_t reta = 0;
2381
2382                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2383                                 uint32_t q;
2384
2385                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2386                                 reta |= q << (8 * i);
2387                                 ++r;
2388                         }
2389                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2390                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2391                 }
2392
2393                 /*
2394                  * Enable multiple receive queues.
2395                  * Enable IPv4 RSS standard hash functions.
2396                  * Disable RSS interrupt on 82575
2397                  */
2398                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2399                                 E1000_MRQC_ENABLE_RSS_4Q |
2400                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2401                                 E1000_MRQC_RSS_FIELD_IPV4);
2402         }
2403
2404         /* Setup the Receive Control Register */
2405         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2406         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2407             E1000_RCTL_RDMTS_HALF |
2408             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2409         /* Strip CRC bytes. */
2410         rctl |= E1000_RCTL_SECRC;
2411         /* Make sure VLAN Filters are off */
2412         rctl &= ~E1000_RCTL_VFE;
2413         /* Don't store bad packets */
2414         rctl &= ~E1000_RCTL_SBP;
2415
2416         /* Enable Receives */
2417         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2418
2419         /*
2420          * Setup the HW Rx Head and Tail Descriptor Pointers
2421          *   - needs to be after enable
2422          */
2423         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2424                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2425
2426                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2427                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2428         }
2429 }
2430
2431 static void
2432 igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2433 {
2434         if (--i < 0)
2435                 i = rxr->num_rx_desc - 1;
2436         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2437 }
2438
2439 static void
2440 igb_rxeof(struct igb_rx_ring *rxr, int count)
2441 {
2442         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2443         union e1000_adv_rx_desc *cur;
2444         uint32_t staterr;
2445         int i, ncoll = 0;
2446
2447         i = rxr->next_to_check;
2448         cur = &rxr->rx_base[i];
2449         staterr = le32toh(cur->wb.upper.status_error);
2450
2451         if ((staterr & E1000_RXD_STAT_DD) == 0)
2452                 return;
2453
2454         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2455                 struct pktinfo *pi = NULL, pi0;
2456                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2457                 struct mbuf *m = NULL;
2458                 boolean_t eop;
2459
2460                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2461                 if (eop)
2462                         --count;
2463
2464                 ++ncoll;
2465                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2466                     !rxr->discard) {
2467                         struct mbuf *mp = rxbuf->m_head;
2468                         uint32_t hash, hashtype;
2469                         uint16_t vlan;
2470                         int len;
2471
2472                         len = le16toh(cur->wb.upper.length);
2473                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2474                             (staterr & E1000_RXDEXT_STATERR_LB))
2475                                 vlan = be16toh(cur->wb.upper.vlan);
2476                         else
2477                                 vlan = le16toh(cur->wb.upper.vlan);
2478
2479                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2480                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2481                             E1000_RXDADV_RSSTYPE_MASK;
2482
2483                         IGB_RSS_DPRINTF(rxr->sc, 10,
2484                             "ring%d, hash 0x%08x, hashtype %u\n",
2485                             rxr->me, hash, hashtype);
2486
2487                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2488                             BUS_DMASYNC_POSTREAD);
2489
2490                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2491                                 ifp->if_iqdrops++;
2492                                 goto discard;
2493                         }
2494
2495                         mp->m_len = len;
2496                         if (rxr->fmp == NULL) {
2497                                 mp->m_pkthdr.len = len;
2498                                 rxr->fmp = mp;
2499                                 rxr->lmp = mp;
2500                         } else {
2501                                 rxr->lmp->m_next = mp;
2502                                 rxr->lmp = rxr->lmp->m_next;
2503                                 rxr->fmp->m_pkthdr.len += len;
2504                         }
2505
2506                         if (eop) {
2507                                 m = rxr->fmp;
2508                                 rxr->fmp = NULL;
2509                                 rxr->lmp = NULL;
2510
2511                                 m->m_pkthdr.rcvif = ifp;
2512                                 ifp->if_ipackets++;
2513
2514                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2515                                         igb_rxcsum(staterr, m);
2516
2517                                 if (staterr & E1000_RXD_STAT_VP) {
2518                                         m->m_pkthdr.ether_vlantag = vlan;
2519                                         m->m_flags |= M_VLANTAG;
2520                                 }
2521
2522                                 if (ifp->if_capenable & IFCAP_RSS) {
2523                                         pi = igb_rssinfo(m, &pi0,
2524                                             hash, hashtype, staterr);
2525                                 }
2526 #ifdef IGB_RSS_DEBUG
2527                                 rxr->rx_packets++;
2528 #endif
2529                         }
2530                 } else {
2531                         ifp->if_ierrors++;
2532 discard:
2533                         igb_setup_rxdesc(cur, rxbuf);
2534                         if (!eop)
2535                                 rxr->discard = TRUE;
2536                         else
2537                                 rxr->discard = FALSE;
2538                         if (rxr->fmp != NULL) {
2539                                 m_freem(rxr->fmp);
2540                                 rxr->fmp = NULL;
2541                                 rxr->lmp = NULL;
2542                         }
2543                         m = NULL;
2544                 }
2545
2546                 if (m != NULL)
2547                         ether_input_pkt(ifp, m, pi);
2548
2549                 /* Advance our pointers to the next descriptor. */
2550                 if (++i == rxr->num_rx_desc)
2551                         i = 0;
2552
2553                 if (ncoll >= rxr->rx_wreg) {
2554                         igb_rx_refresh(rxr, i);
2555                         ncoll = 0;
2556                 }
2557
2558                 cur = &rxr->rx_base[i];
2559                 staterr = le32toh(cur->wb.upper.status_error);
2560         }
2561         rxr->next_to_check = i;
2562
2563         if (ncoll > 0)
2564                 igb_rx_refresh(rxr, i);
2565 }
2566
2567
2568 static void
2569 igb_set_vlan(struct igb_softc *sc)
2570 {
2571         struct e1000_hw *hw = &sc->hw;
2572         uint32_t reg;
2573 #if 0
2574         struct ifnet *ifp = sc->arpcom.ac_if;
2575 #endif
2576
2577         if (sc->vf_ifp) {
2578                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2579                 return;
2580         }
2581
2582         reg = E1000_READ_REG(hw, E1000_CTRL);
2583         reg |= E1000_CTRL_VME;
2584         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2585
2586 #if 0
2587         /* Enable the Filter Table */
2588         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2589                 reg = E1000_READ_REG(hw, E1000_RCTL);
2590                 reg &= ~E1000_RCTL_CFIEN;
2591                 reg |= E1000_RCTL_VFE;
2592                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2593         }
2594 #endif
2595
2596         /* Update the frame size */
2597         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2598             sc->max_frame_size + VLAN_TAG_SIZE);
2599
2600 #if 0
2601         /* Don't bother with table if no vlans */
2602         if ((adapter->num_vlans == 0) ||
2603             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2604                 return;
2605         /*
2606         ** A soft reset zero's out the VFTA, so
2607         ** we need to repopulate it now.
2608         */
2609         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2610                 if (adapter->shadow_vfta[i] != 0) {
2611                         if (adapter->vf_ifp)
2612                                 e1000_vfta_set_vf(hw,
2613                                     adapter->shadow_vfta[i], TRUE);
2614                         else
2615                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2616                                  i, adapter->shadow_vfta[i]);
2617                 }
2618 #endif
2619 }
2620
2621 static void
2622 igb_enable_intr(struct igb_softc *sc)
2623 {
2624         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2625                 lwkt_serialize_handler_enable(&sc->main_serialize);
2626         } else {
2627                 int i;
2628
2629                 for (i = 0; i < sc->msix_cnt; ++i) {
2630                         lwkt_serialize_handler_enable(
2631                             sc->msix_data[i].msix_serialize);
2632                 }
2633         }
2634
2635         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2636                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2637                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2638                 else
2639                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2640                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2641                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2642                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2643         } else {
2644                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2645         }
2646         E1000_WRITE_FLUSH(&sc->hw);
2647 }
2648
2649 static void
2650 igb_disable_intr(struct igb_softc *sc)
2651 {
2652         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2653                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2654                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2655         }
2656         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2657         E1000_WRITE_FLUSH(&sc->hw);
2658
2659         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2660                 lwkt_serialize_handler_disable(&sc->main_serialize);
2661         } else {
2662                 int i;
2663
2664                 for (i = 0; i < sc->msix_cnt; ++i) {
2665                         lwkt_serialize_handler_disable(
2666                             sc->msix_data[i].msix_serialize);
2667                 }
2668         }
2669 }
2670
2671 /*
2672  * Bit of a misnomer, what this really means is
2673  * to enable OS management of the system... aka
2674  * to disable special hardware management features
2675  */
2676 static void
2677 igb_get_mgmt(struct igb_softc *sc)
2678 {
2679         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2680                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2681                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2682
2683                 /* disable hardware interception of ARP */
2684                 manc &= ~E1000_MANC_ARP_EN;
2685
2686                 /* enable receiving management packets to the host */
2687                 manc |= E1000_MANC_EN_MNG2HOST;
2688                 manc2h |= 1 << 5; /* Mng Port 623 */
2689                 manc2h |= 1 << 6; /* Mng Port 664 */
2690                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2691                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2692         }
2693 }
2694
2695 /*
2696  * Give control back to hardware management controller
2697  * if there is one.
2698  */
2699 static void
2700 igb_rel_mgmt(struct igb_softc *sc)
2701 {
2702         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2703                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2704
2705                 /* Re-enable hardware interception of ARP */
2706                 manc |= E1000_MANC_ARP_EN;
2707                 manc &= ~E1000_MANC_EN_MNG2HOST;
2708
2709                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2710         }
2711 }
2712
2713 /*
2714  * Sets CTRL_EXT:DRV_LOAD bit.
2715  *
2716  * For ASF and Pass Through versions of f/w this means that
2717  * the driver is loaded.
2718  */
2719 static void
2720 igb_get_hw_control(struct igb_softc *sc)
2721 {
2722         uint32_t ctrl_ext;
2723
2724         if (sc->vf_ifp)
2725                 return;
2726
2727         /* Let firmware know the driver has taken over */
2728         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2729         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2730             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2731 }
2732
2733 /*
2734  * Resets CTRL_EXT:DRV_LOAD bit.
2735  *
2736  * For ASF and Pass Through versions of f/w this means that the
2737  * driver is no longer loaded.
2738  */
2739 static void
2740 igb_rel_hw_control(struct igb_softc *sc)
2741 {
2742         uint32_t ctrl_ext;
2743
2744         if (sc->vf_ifp)
2745                 return;
2746
2747         /* Let firmware taken over control of h/w */
2748         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2749         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2750             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2751 }
2752
2753 static int
2754 igb_is_valid_ether_addr(const uint8_t *addr)
2755 {
2756         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2757
2758         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2759                 return FALSE;
2760         return TRUE;
2761 }
2762
2763 /*
2764  * Enable PCI Wake On Lan capability
2765  */
2766 static void
2767 igb_enable_wol(device_t dev)
2768 {
2769         uint16_t cap, status;
2770         uint8_t id;
2771
2772         /* First find the capabilities pointer*/
2773         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2774
2775         /* Read the PM Capabilities */
2776         id = pci_read_config(dev, cap, 1);
2777         if (id != PCIY_PMG)     /* Something wrong */
2778                 return;
2779
2780         /*
2781          * OK, we have the power capabilities,
2782          * so now get the status register
2783          */
2784         cap += PCIR_POWER_STATUS;
2785         status = pci_read_config(dev, cap, 2);
2786         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2787         pci_write_config(dev, cap, status, 2);
2788 }
2789
2790 static void
2791 igb_update_stats_counters(struct igb_softc *sc)
2792 {
2793         struct e1000_hw *hw = &sc->hw;
2794         struct e1000_hw_stats *stats;
2795         struct ifnet *ifp = &sc->arpcom.ac_if;
2796
2797         /*
2798          * The virtual function adapter has only a
2799          * small controlled set of stats, do only
2800          * those and return.
2801          */
2802         if (sc->vf_ifp) {
2803                 igb_update_vf_stats_counters(sc);
2804                 return;
2805         }
2806         stats = sc->stats;
2807
2808         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2809             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2810                 stats->symerrs +=
2811                     E1000_READ_REG(hw,E1000_SYMERRS);
2812                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2813         }
2814
2815         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2816         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2817         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2818         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2819
2820         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2821         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2822         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2823         stats->dc += E1000_READ_REG(hw, E1000_DC);
2824         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2825         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2826         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2827
2828         /*
2829          * For watchdog management we need to know if we have been
2830          * paused during the last interval, so capture that here.
2831          */
2832         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2833         stats->xoffrxc += sc->pause_frames;
2834         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2835         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2836         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2837         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2838         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2839         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2840         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2841         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2842         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2843         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2844         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2845         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2846
2847         /* For the 64-bit byte counters the low dword must be read first. */
2848         /* Both registers clear on the read of the high dword */
2849
2850         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2851             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2852         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2853             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2854
2855         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2856         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2857         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2858         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2859         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2860
2861         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2862         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2863
2864         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2865         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2866         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2867         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2868         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2869         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2870         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2871         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2872         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2873         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2874
2875         /* Interrupt Counts */
2876
2877         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2878         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2879         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2880         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2881         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2882         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2883         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2884         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2885         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2886
2887         /* Host to Card Statistics */
2888
2889         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2890         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2891         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2892         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2893         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2894         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2895         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2896         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2897             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2898         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2899             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2900         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2901         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2902         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2903
2904         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2905         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2906         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2907         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2908         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2909         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2910
2911         ifp->if_collisions = stats->colc;
2912
2913         /* Rx Errors */
2914         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2915             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2916
2917         /* Tx Errors */
2918         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2919
2920         /* Driver specific counters */
2921         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2922         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2923         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2924         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2925         sc->packet_buf_alloc_tx =
2926             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2927         sc->packet_buf_alloc_rx =
2928             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2929 }
2930
2931 static void
2932 igb_vf_init_stats(struct igb_softc *sc)
2933 {
2934         struct e1000_hw *hw = &sc->hw;
2935         struct e1000_vf_stats *stats;
2936
2937         stats = sc->stats;
2938         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2939         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2940         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2941         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2942         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2943 }
2944
2945 static void
2946 igb_update_vf_stats_counters(struct igb_softc *sc)
2947 {
2948         struct e1000_hw *hw = &sc->hw;
2949         struct e1000_vf_stats *stats;
2950
2951         if (sc->link_speed == 0)
2952                 return;
2953
2954         stats = sc->stats;
2955         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2956         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2957         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2958         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2959         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2960 }
2961
2962 #ifdef IFPOLL_ENABLE
2963
2964 static void
2965 igb_npoll_status(struct ifnet *ifp)
2966 {
2967         struct igb_softc *sc = ifp->if_softc;
2968         uint32_t reg_icr;
2969
2970         ASSERT_SERIALIZED(&sc->main_serialize);
2971
2972         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2973         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2974                 sc->hw.mac.get_link_status = 1;
2975                 igb_update_link_status(sc);
2976         }
2977 }
2978
2979 static void
2980 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
2981 {
2982         struct igb_tx_ring *txr = arg;
2983
2984         ASSERT_SERIALIZED(&txr->tx_serialize);
2985
2986         igb_txeof(txr);
2987         if (!ifq_is_empty(&ifp->if_snd))
2988                 if_devstart(ifp);
2989 }
2990
2991 static void
2992 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
2993 {
2994         struct igb_rx_ring *rxr = arg;
2995
2996         ASSERT_SERIALIZED(&rxr->rx_serialize);
2997
2998         igb_rxeof(rxr, cycle);
2999 }
3000
3001 static void
3002 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3003 {
3004         struct igb_softc *sc = ifp->if_softc;
3005
3006         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3007
3008         if (info) {
3009                 struct igb_tx_ring *txr;
3010                 int i, off;
3011
3012                 info->ifpi_status.status_func = igb_npoll_status;
3013                 info->ifpi_status.serializer = &sc->main_serialize;
3014
3015                 off = sc->tx_npoll_off;
3016                 KKASSERT(off < ncpus2);
3017                 txr = &sc->tx_rings[0];
3018                 info->ifpi_tx[off].poll_func = igb_npoll_tx;
3019                 info->ifpi_tx[off].arg = txr;
3020                 info->ifpi_tx[off].serializer = &txr->tx_serialize;
3021
3022                 off = sc->rx_npoll_off;
3023                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3024                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3025                         int idx = i + off;
3026
3027                         KKASSERT(idx < ncpus2);
3028                         info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3029                         info->ifpi_rx[idx].arg = rxr;
3030                         info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3031                 }
3032
3033                 if (ifp->if_flags & IFF_RUNNING) {
3034                         if (sc->rx_ring_inuse == sc->rx_ring_cnt)
3035                                 igb_disable_intr(sc);
3036                         else
3037                                 igb_init(sc);
3038                 }
3039                 ifp->if_npoll_cpuid = sc->tx_npoll_off;
3040         } else {
3041                 if (ifp->if_flags & IFF_RUNNING) {
3042                         if (sc->rx_ring_inuse == sc->rx_ring_cnt)
3043                                 igb_enable_intr(sc);
3044                         else
3045                                 igb_init(sc);
3046                 }
3047                 ifp->if_npoll_cpuid = -1;
3048         }
3049 }
3050
3051 #endif /* IFPOLL_ENABLE */
3052
3053 static void
3054 igb_intr(void *xsc)
3055 {
3056         struct igb_softc *sc = xsc;
3057         struct ifnet *ifp = &sc->arpcom.ac_if;
3058         uint32_t eicr;
3059
3060         ASSERT_SERIALIZED(&sc->main_serialize);
3061
3062         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3063
3064         if (eicr == 0)
3065                 return;
3066
3067         if (ifp->if_flags & IFF_RUNNING) {
3068                 struct igb_tx_ring *txr;
3069                 int i;
3070
3071                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3072                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3073
3074                         if (eicr & rxr->rx_intr_mask) {
3075                                 lwkt_serialize_enter(&rxr->rx_serialize);
3076                                 igb_rxeof(rxr, -1);
3077                                 lwkt_serialize_exit(&rxr->rx_serialize);
3078                         }
3079                 }
3080
3081                 txr = &sc->tx_rings[0];
3082                 if (eicr & txr->tx_intr_mask) {
3083                         lwkt_serialize_enter(&txr->tx_serialize);
3084                         igb_txeof(txr);
3085                         if (!ifq_is_empty(&ifp->if_snd))
3086                                 if_devstart(ifp);
3087                         lwkt_serialize_exit(&txr->tx_serialize);
3088                 }
3089         }
3090
3091         if (eicr & E1000_EICR_OTHER) {
3092                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3093
3094                 /* Link status change */
3095                 if (icr & E1000_ICR_LSC) {
3096                         sc->hw.mac.get_link_status = 1;
3097                         igb_update_link_status(sc);
3098                 }
3099         }
3100
3101         /*
3102          * Reading EICR has the side effect to clear interrupt mask,
3103          * so all interrupts need to be enabled here.
3104          */
3105         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3106 }
3107
3108 static void
3109 igb_intr_shared(void *xsc)
3110 {
3111         struct igb_softc *sc = xsc;
3112         struct ifnet *ifp = &sc->arpcom.ac_if;
3113         uint32_t reg_icr;
3114
3115         ASSERT_SERIALIZED(&sc->main_serialize);
3116
3117         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3118
3119         /* Hot eject?  */
3120         if (reg_icr == 0xffffffff)
3121                 return;
3122
3123         /* Definitely not our interrupt.  */
3124         if (reg_icr == 0x0)
3125                 return;
3126
3127         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3128                 return;
3129
3130         if (ifp->if_flags & IFF_RUNNING) {
3131                 if (reg_icr &
3132                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3133                         int i;
3134
3135                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3136                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3137
3138                                 lwkt_serialize_enter(&rxr->rx_serialize);
3139                                 igb_rxeof(rxr, -1);
3140                                 lwkt_serialize_exit(&rxr->rx_serialize);
3141                         }
3142                 }
3143
3144                 if (reg_icr & E1000_ICR_TXDW) {
3145                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3146
3147                         lwkt_serialize_enter(&txr->tx_serialize);
3148                         igb_txeof(txr);
3149                         if (!ifq_is_empty(&ifp->if_snd))
3150                                 if_devstart(ifp);
3151                         lwkt_serialize_exit(&txr->tx_serialize);
3152                 }
3153         }
3154
3155         /* Link status change */
3156         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3157                 sc->hw.mac.get_link_status = 1;
3158                 igb_update_link_status(sc);
3159         }
3160
3161         if (reg_icr & E1000_ICR_RXO)
3162                 sc->rx_overruns++;
3163 }
3164
3165 static int
3166 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3167     int *segs_used, int *idx)
3168 {
3169         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3170         bus_dmamap_t map;
3171         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3172         union e1000_adv_tx_desc *txd = NULL;
3173         struct mbuf *m_head = *m_headp;
3174         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3175         int maxsegs, nsegs, i, j, error, last = 0;
3176         uint32_t hdrlen = 0;
3177
3178         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3179                 error = igb_tso_pullup(txr, m_headp);
3180                 if (error)
3181                         return error;
3182                 m_head = *m_headp;
3183         }
3184
3185         /* Set basic descriptor constants */
3186         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3187         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3188         if (m_head->m_flags & M_VLANTAG)
3189                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3190
3191         /*
3192          * Map the packet for DMA.
3193          */
3194         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3195         tx_buf_mapped = tx_buf;
3196         map = tx_buf->map;
3197
3198         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3199         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3200         if (maxsegs > IGB_MAX_SCATTER)
3201                 maxsegs = IGB_MAX_SCATTER;
3202
3203         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3204             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3205         if (error) {
3206                 if (error == ENOBUFS)
3207                         txr->sc->mbuf_defrag_failed++;
3208                 else
3209                         txr->sc->no_tx_dma_setup++;
3210
3211                 m_freem(*m_headp);
3212                 *m_headp = NULL;
3213                 return error;
3214         }
3215         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3216
3217         m_head = *m_headp;
3218
3219         /*
3220          * Set up the TX context descriptor, if any hardware offloading is
3221          * needed.  This includes CSUM, VLAN, and TSO.  It will consume one
3222          * TX descriptor.
3223          *
3224          * Unlike these chips' predecessors (em/emx), TX context descriptor
3225          * will _not_ interfere TX data fetching pipelining.
3226          */
3227         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3228                 igb_tso_ctx(txr, m_head, &hdrlen);
3229                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3230                 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3231                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3232                 txr->tx_nsegs++;
3233                 (*segs_used)++;
3234         } else if (igb_txcsum_ctx(txr, m_head)) {
3235                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3236                         olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3237                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3238                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3239                 txr->tx_nsegs++;
3240                 (*segs_used)++;
3241         }
3242
3243         *segs_used += nsegs;
3244         txr->tx_nsegs += nsegs;
3245         if (txr->tx_nsegs >= txr->intr_nsegs) {
3246                 /*
3247                  * Report Status (RS) is turned on every intr_nsegs
3248                  * descriptors (roughly).
3249                  */
3250                 txr->tx_nsegs = 0;
3251                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3252         }
3253
3254         /* Calculate payload length */
3255         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3256             << E1000_ADVTXD_PAYLEN_SHIFT);
3257
3258         /* 82575 needs the queue index added */
3259         if (txr->sc->hw.mac.type == e1000_82575)
3260                 olinfo_status |= txr->me << 4;
3261
3262         /* Set up our transmit descriptors */
3263         i = txr->next_avail_desc;
3264         for (j = 0; j < nsegs; j++) {
3265                 bus_size_t seg_len;
3266                 bus_addr_t seg_addr;
3267
3268                 tx_buf = &txr->tx_buf[i];
3269                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3270                 seg_addr = segs[j].ds_addr;
3271                 seg_len = segs[j].ds_len;
3272
3273                 txd->read.buffer_addr = htole64(seg_addr);
3274                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3275                 txd->read.olinfo_status = htole32(olinfo_status);
3276                 last = i;
3277                 if (++i == txr->num_tx_desc)
3278                         i = 0;
3279                 tx_buf->m_head = NULL;
3280         }
3281
3282         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3283         txr->next_avail_desc = i;
3284         txr->tx_avail -= nsegs;
3285
3286         tx_buf->m_head = m_head;
3287         tx_buf_mapped->map = tx_buf->map;
3288         tx_buf->map = map;
3289
3290         /*
3291          * Last Descriptor of Packet needs End Of Packet (EOP)
3292          */
3293         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3294
3295         /*
3296          * Defer TDT updating, until enough descrptors are setup
3297          */
3298         *idx = i;
3299         ++txr->tx_packets;
3300
3301         return 0;
3302 }
3303
3304 static void
3305 igb_start(struct ifnet *ifp)
3306 {
3307         struct igb_softc *sc = ifp->if_softc;
3308         struct igb_tx_ring *txr = &sc->tx_rings[0];
3309         struct mbuf *m_head;
3310         int idx = -1, nsegs = 0;
3311
3312         ASSERT_SERIALIZED(&txr->tx_serialize);
3313
3314         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
3315                 return;
3316
3317         if (!sc->link_active) {
3318                 ifq_purge(&ifp->if_snd);
3319                 return;
3320         }
3321
3322         if (!IGB_IS_NOT_OACTIVE(txr))
3323                 igb_txeof(txr);
3324
3325         while (!ifq_is_empty(&ifp->if_snd)) {
3326                 if (IGB_IS_OACTIVE(txr)) {
3327                         ifq_set_oactive(&ifp->if_snd);
3328                         /* Set watchdog on */
3329                         ifp->if_timer = 5;
3330                         break;
3331                 }
3332
3333                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3334                 if (m_head == NULL)
3335                         break;
3336
3337                 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3338                         ifp->if_oerrors++;
3339                         continue;
3340                 }
3341
3342                 if (nsegs >= txr->wreg_nsegs) {
3343                         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3344                         idx = -1;
3345                         nsegs = 0;
3346                 }
3347
3348                 /* Send a copy of the frame to the BPF listener */
3349                 ETHER_BPF_MTAP(ifp, m_head);
3350         }
3351         if (idx >= 0)
3352                 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3353 }
3354
3355 static void
3356 igb_watchdog(struct ifnet *ifp)
3357 {
3358         struct igb_softc *sc = ifp->if_softc;
3359         struct igb_tx_ring *txr = &sc->tx_rings[0];
3360
3361         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3362
3363         /*
3364          * If flow control has paused us since last checking
3365          * it invalidates the watchdog timing, so dont run it.
3366          */
3367         if (sc->pause_frames) {
3368                 sc->pause_frames = 0;
3369                 ifp->if_timer = 5;
3370                 return;
3371         }
3372
3373         if_printf(ifp, "Watchdog timeout -- resetting\n");
3374         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3375             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3376             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3377         if_printf(ifp, "TX(%d) desc avail = %d, "
3378             "Next TX to Clean = %d\n",
3379             txr->me, txr->tx_avail, txr->next_to_clean);
3380
3381         ifp->if_oerrors++;
3382         sc->watchdog_events++;
3383
3384         igb_init(sc);
3385         if (!ifq_is_empty(&ifp->if_snd))
3386                 if_devstart(ifp);
3387 }
3388
3389 static void
3390 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3391 {
3392         uint32_t eitr = 0;
3393
3394         if (rate > 0) {
3395                 if (sc->hw.mac.type == e1000_82575) {
3396                         eitr = 1000000000 / 256 / rate;
3397                         /*
3398                          * NOTE:
3399                          * Document is wrong on the 2 bits left shift
3400                          */
3401                 } else {
3402                         eitr = 1000000 / rate;
3403                         eitr <<= IGB_EITR_INTVL_SHIFT;
3404                 }
3405
3406                 if (eitr == 0) {
3407                         /* Don't disable it */
3408                         eitr = 1 << IGB_EITR_INTVL_SHIFT;
3409                 } else if (eitr > IGB_EITR_INTVL_MASK) {
3410                         /* Don't allow it to be too large */
3411                         eitr = IGB_EITR_INTVL_MASK;
3412                 }
3413         }
3414         if (sc->hw.mac.type == e1000_82575)
3415                 eitr |= eitr << 16;
3416         else
3417                 eitr |= E1000_EITR_CNT_IGNR;
3418         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3419 }
3420
3421 static int
3422 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3423 {
3424         struct igb_softc *sc = (void *)arg1;
3425         struct ifnet *ifp = &sc->arpcom.ac_if;
3426         int error, intr_rate;
3427
3428         intr_rate = sc->intr_rate;
3429         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3430         if (error || req->newptr == NULL)
3431                 return error;
3432         if (intr_rate < 0)
3433                 return EINVAL;
3434
3435         ifnet_serialize_all(ifp);
3436
3437         sc->intr_rate = intr_rate;
3438         if (ifp->if_flags & IFF_RUNNING)
3439                 igb_set_eitr(sc, 0, sc->intr_rate);
3440
3441         if (bootverbose)
3442                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3443
3444         ifnet_deserialize_all(ifp);
3445
3446         return 0;
3447 }
3448
3449 static int
3450 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3451 {
3452         struct igb_msix_data *msix = (void *)arg1;
3453         struct igb_softc *sc = msix->msix_sc;
3454         struct ifnet *ifp = &sc->arpcom.ac_if;
3455         int error, msix_rate;
3456
3457         msix_rate = msix->msix_rate;
3458         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3459         if (error || req->newptr == NULL)
3460                 return error;
3461         if (msix_rate < 0)
3462                 return EINVAL;
3463
3464         lwkt_serialize_enter(msix->msix_serialize);
3465
3466         msix->msix_rate = msix_rate;
3467         if (ifp->if_flags & IFF_RUNNING)
3468                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3469
3470         if (bootverbose) {
3471                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3472                     msix->msix_rate);
3473         }
3474
3475         lwkt_serialize_exit(msix->msix_serialize);
3476
3477         return 0;
3478 }
3479
3480 static int
3481 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3482 {
3483         struct igb_softc *sc = (void *)arg1;
3484         struct ifnet *ifp = &sc->arpcom.ac_if;
3485         struct igb_tx_ring *txr = &sc->tx_rings[0];
3486         int error, nsegs;
3487
3488         nsegs = txr->intr_nsegs;
3489         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3490         if (error || req->newptr == NULL)
3491                 return error;
3492         if (nsegs <= 0)
3493                 return EINVAL;
3494
3495         ifnet_serialize_all(ifp);
3496
3497         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3498             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3499                 error = EINVAL;
3500         } else {
3501                 error = 0;
3502                 txr->intr_nsegs = nsegs;
3503         }
3504
3505         ifnet_deserialize_all(ifp);
3506
3507         return error;
3508 }
3509
3510 #ifdef IFPOLL_ENABLE
3511
3512 static int
3513 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3514 {
3515         struct igb_softc *sc = (void *)arg1;
3516         struct ifnet *ifp = &sc->arpcom.ac_if;
3517         int error, off;
3518
3519         off = sc->rx_npoll_off;
3520         error = sysctl_handle_int(oidp, &off, 0, req);
3521         if (error || req->newptr == NULL)
3522                 return error;
3523         if (off < 0)
3524                 return EINVAL;
3525
3526         ifnet_serialize_all(ifp);
3527         if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3528                 error = EINVAL;
3529         } else {
3530                 error = 0;
3531                 sc->rx_npoll_off = off;
3532         }
3533         ifnet_deserialize_all(ifp);
3534
3535         return error;
3536 }
3537
3538 static int
3539 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3540 {
3541         struct igb_softc *sc = (void *)arg1;
3542         struct ifnet *ifp = &sc->arpcom.ac_if;
3543         int error, off;
3544
3545         off = sc->tx_npoll_off;
3546         error = sysctl_handle_int(oidp, &off, 0, req);
3547         if (error || req->newptr == NULL)
3548                 return error;
3549         if (off < 0)
3550                 return EINVAL;
3551
3552         ifnet_serialize_all(ifp);
3553         if (off >= ncpus2) {
3554                 error = EINVAL;
3555         } else {
3556                 error = 0;
3557                 sc->tx_npoll_off = off;
3558         }
3559         ifnet_deserialize_all(ifp);
3560
3561         return error;
3562 }
3563
3564 #endif  /* IFPOLL_ENABLE */
3565
3566 static void
3567 igb_init_intr(struct igb_softc *sc)
3568 {
3569         igb_set_intr_mask(sc);
3570
3571         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3572                 igb_init_unshared_intr(sc);
3573
3574         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3575                 igb_set_eitr(sc, 0, sc->intr_rate);
3576         } else {
3577                 int i;
3578
3579                 for (i = 0; i < sc->msix_cnt; ++i)
3580                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3581         }
3582 }
3583
3584 static void
3585 igb_init_unshared_intr(struct igb_softc *sc)
3586 {
3587         struct e1000_hw *hw = &sc->hw;
3588         const struct igb_rx_ring *rxr;
3589         const struct igb_tx_ring *txr;
3590         uint32_t ivar, index;
3591         int i;
3592
3593         /*
3594          * Enable extended mode
3595          */
3596         if (sc->hw.mac.type != e1000_82575) {
3597                 uint32_t gpie;
3598                 int ivar_max;
3599
3600                 gpie = E1000_GPIE_NSICR;
3601                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3602                         gpie |= E1000_GPIE_MSIX_MODE |
3603                             E1000_GPIE_EIAME |
3604                             E1000_GPIE_PBA;
3605                 }
3606                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3607
3608                 /*
3609                  * Clear IVARs
3610                  */
3611                 switch (sc->hw.mac.type) {
3612                 case e1000_82580:
3613                         ivar_max = IGB_MAX_IVAR_82580;
3614                         break;
3615
3616                 case e1000_i350:
3617                         ivar_max = IGB_MAX_IVAR_I350;
3618                         break;
3619
3620                 case e1000_vfadapt:
3621                 case e1000_vfadapt_i350:
3622                         ivar_max = IGB_MAX_IVAR_VF;
3623                         break;
3624
3625                 case e1000_82576:
3626                         ivar_max = IGB_MAX_IVAR_82576;
3627                         break;
3628
3629                 default:
3630                         panic("unknown mac type %d\n", sc->hw.mac.type);
3631                 }
3632                 for (i = 0; i < ivar_max; ++i)
3633                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3634                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3635         } else {
3636                 uint32_t tmp;
3637
3638                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3639                     ("82575 w/ MSI-X"));
3640                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3641                 tmp |= E1000_CTRL_EXT_IRCA;
3642                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3643         }
3644
3645         /*
3646          * Map TX/RX interrupts to EICR
3647          */
3648         switch (sc->hw.mac.type) {
3649         case e1000_82580:
3650         case e1000_i350:
3651         case e1000_vfadapt:
3652         case e1000_vfadapt_i350:
3653                 /* RX entries */
3654                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3655                         rxr = &sc->rx_rings[i];
3656
3657                         index = i >> 1;
3658                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3659
3660                         if (i & 1) {
3661                                 ivar &= 0xff00ffff;
3662                                 ivar |=
3663                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3664                         } else {
3665                                 ivar &= 0xffffff00;
3666                                 ivar |=
3667                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3668                         }
3669                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3670                 }
3671                 /* TX entries */
3672                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3673                         txr = &sc->tx_rings[i];
3674
3675                         index = i >> 1;
3676                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3677
3678                         if (i & 1) {
3679                                 ivar &= 0x00ffffff;
3680                                 ivar |=
3681                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3682                         } else {
3683                                 ivar &= 0xffff00ff;
3684                                 ivar |=
3685                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3686                         }
3687                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3688                 }
3689                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3690                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3691                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3692                 }
3693                 break;
3694
3695         case e1000_82576:
3696                 /* RX entries */
3697                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3698                         rxr = &sc->rx_rings[i];
3699
3700                         index = i & 0x7; /* Each IVAR has two entries */
3701                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3702
3703                         if (i < 8) {
3704                                 ivar &= 0xffffff00;
3705                                 ivar |=
3706                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3707                         } else {
3708                                 ivar &= 0xff00ffff;
3709                                 ivar |=
3710                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3711                         }
3712                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3713                 }
3714                 /* TX entries */
3715                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3716                         txr = &sc->tx_rings[i];
3717
3718                         index = i & 0x7; /* Each IVAR has two entries */
3719                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3720
3721                         if (i < 8) {
3722                                 ivar &= 0xffff00ff;
3723                                 ivar |=
3724                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3725                         } else {
3726                                 ivar &= 0x00ffffff;
3727                                 ivar |=
3728                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3729                         }
3730                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3731                 }
3732                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3733                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3734                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3735                 }
3736                 break;
3737
3738         case e1000_82575:
3739                 /*
3740                  * Enable necessary interrupt bits.
3741                  *
3742                  * The name of the register is confusing; in addition to
3743                  * configuring the first vector of MSI-X, it also configures
3744                  * which bits of EICR could be set by the hardware even when
3745                  * MSI or line interrupt is used; it thus controls interrupt
3746                  * generation.  It MUST be configured explicitly; the default
3747                  * value mentioned in the datasheet is wrong: RX queue0 and
3748                  * TX queue0 are NOT enabled by default.
3749                  */
3750                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3751                 break;
3752
3753         default:
3754                 panic("unknown mac type %d\n", sc->hw.mac.type);
3755         }
3756 }
3757
3758 static int
3759 igb_setup_intr(struct igb_softc *sc)
3760 {
3761         struct ifnet *ifp = &sc->arpcom.ac_if;
3762         int error;
3763
3764         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3765                 return igb_msix_setup(sc);
3766
3767         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3768             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3769             sc, &sc->intr_tag, &sc->main_serialize);
3770         if (error) {
3771                 device_printf(sc->dev, "Failed to register interrupt handler");
3772                 return error;
3773         }
3774
3775         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3776         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3777
3778         return 0;
3779 }
3780
3781 static void
3782 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3783 {
3784         if (txr->sc->hw.mac.type == e1000_82575) {
3785                 txr->tx_intr_bit = 0;   /* unused */
3786                 switch (txr->me) {
3787                 case 0:
3788                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3789                         break;
3790                 case 1:
3791                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3792                         break;
3793                 case 2:
3794                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3795                         break;
3796                 case 3:
3797                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3798                         break;
3799                 default:
3800                         panic("unsupported # of TX ring, %d\n", txr->me);
3801                 }
3802         } else {
3803                 int intr_bit = *intr_bit0;
3804
3805                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3806                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3807
3808                 *intr_bit0 = intr_bit + 1;
3809         }
3810 }
3811
3812 static void
3813 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3814 {
3815         if (rxr->sc->hw.mac.type == e1000_82575) {
3816                 rxr->rx_intr_bit = 0;   /* unused */
3817                 switch (rxr->me) {
3818                 case 0:
3819                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3820                         break;
3821                 case 1:
3822                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3823                         break;
3824                 case 2:
3825                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3826                         break;
3827                 case 3:
3828                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3829                         break;
3830                 default:
3831                         panic("unsupported # of RX ring, %d\n", rxr->me);
3832                 }
3833         } else {
3834                 int intr_bit = *intr_bit0;
3835
3836                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3837                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3838
3839                 *intr_bit0 = intr_bit + 1;
3840         }
3841 }
3842
3843 static void
3844 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3845 {
3846         struct igb_softc *sc = ifp->if_softc;
3847
3848         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3849             sc->tx_serialize, sc->rx_serialize, slz);
3850 }
3851
3852 static void
3853 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3854 {
3855         struct igb_softc *sc = ifp->if_softc;
3856
3857         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3858             sc->tx_serialize, sc->rx_serialize, slz);
3859 }
3860
3861 static int
3862 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3863 {
3864         struct igb_softc *sc = ifp->if_softc;
3865
3866         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3867             sc->tx_serialize, sc->rx_serialize, slz);
3868 }
3869
3870 #ifdef INVARIANTS
3871
3872 static void
3873 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3874     boolean_t serialized)
3875 {
3876         struct igb_softc *sc = ifp->if_softc;
3877
3878         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3879             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3880 }
3881
3882 #endif  /* INVARIANTS */
3883
3884 static void
3885 igb_set_intr_mask(struct igb_softc *sc)
3886 {
3887         int i;
3888
3889         sc->intr_mask = sc->sts_intr_mask;
3890         for (i = 0; i < sc->rx_ring_inuse; ++i)
3891                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3892         for (i = 0; i < sc->tx_ring_cnt; ++i)
3893                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3894         if (bootverbose) {
3895                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3896                     sc->intr_mask);
3897         }
3898 }
3899
3900 static int
3901 igb_alloc_intr(struct igb_softc *sc)
3902 {
3903         int i, intr_bit, intr_bitmax;
3904         u_int intr_flags;
3905
3906         igb_msix_try_alloc(sc);
3907         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3908                 goto done;
3909
3910         /*
3911          * Allocate MSI/legacy interrupt resource
3912          */
3913         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3914             &sc->intr_rid, &intr_flags);
3915
3916         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3917                 int unshared;
3918
3919                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3920                 if (!unshared) {
3921                         sc->flags |= IGB_FLAG_SHARED_INTR;
3922                         if (bootverbose)
3923                                 device_printf(sc->dev, "IRQ shared\n");
3924                 } else {
3925                         intr_flags &= ~RF_SHAREABLE;
3926                         if (bootverbose)
3927                                 device_printf(sc->dev, "IRQ unshared\n");
3928                 }
3929         }
3930
3931         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3932             &sc->intr_rid, intr_flags);
3933         if (sc->intr_res == NULL) {
3934                 device_printf(sc->dev, "Unable to allocate bus resource: "
3935                     "interrupt\n");
3936                 return ENXIO;
3937         }
3938
3939         /*
3940          * Setup MSI/legacy interrupt mask
3941          */
3942         switch (sc->hw.mac.type) {
3943         case e1000_82575:
3944                 intr_bitmax = IGB_MAX_TXRXINT_82575;
3945                 break;
3946         case e1000_82580:
3947                 intr_bitmax = IGB_MAX_TXRXINT_82580;
3948                 break;
3949         case e1000_i350:
3950                 intr_bitmax = IGB_MAX_TXRXINT_I350;
3951                 break;
3952         case e1000_82576:
3953                 intr_bitmax = IGB_MAX_TXRXINT_82576;
3954                 break;
3955         default:
3956                 intr_bitmax = IGB_MIN_TXRXINT;
3957                 break;
3958         }
3959         intr_bit = 0;
3960         for (i = 0; i < sc->tx_ring_cnt; ++i)
3961                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3962         for (i = 0; i < sc->rx_ring_cnt; ++i)
3963                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3964         sc->sts_intr_bit = 0;
3965         sc->sts_intr_mask = E1000_EICR_OTHER;
3966
3967         /* Initialize interrupt rate */
3968         sc->intr_rate = IGB_INTR_RATE;
3969 done:
3970         igb_set_ring_inuse(sc, FALSE);
3971         igb_set_intr_mask(sc);
3972         return 0;
3973 }
3974
3975 static void
3976 igb_free_intr(struct igb_softc *sc)
3977 {
3978         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3979                 if (sc->intr_res != NULL) {
3980                         bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
3981                             sc->intr_res);
3982                 }
3983                 if (sc->intr_type == PCI_INTR_TYPE_MSI)
3984                         pci_release_msi(sc->dev);
3985         } else {
3986                 igb_msix_free(sc, TRUE);
3987         }
3988 }
3989
3990 static void
3991 igb_teardown_intr(struct igb_softc *sc)
3992 {
3993         if (sc->intr_type != PCI_INTR_TYPE_MSIX)
3994                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
3995         else
3996                 igb_msix_teardown(sc, sc->msix_cnt);
3997 }
3998
3999 static void
4000 igb_msix_try_alloc(struct igb_softc *sc)
4001 {
4002         int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
4003         int i, x, error;
4004         struct igb_msix_data *msix;
4005         boolean_t aggregate, setup = FALSE;
4006
4007         /*
4008          * Don't enable MSI-X on 82575, see:
4009          * 82575 specification update errata #25
4010          */
4011         if (sc->hw.mac.type == e1000_82575)
4012                 return;
4013
4014         /* Don't enable MSI-X on VF */
4015         if (sc->vf_ifp)
4016                 return;
4017
4018         msix_enable = device_getenv_int(sc->dev, "msix.enable",
4019             igb_msix_enable);
4020         if (!msix_enable)
4021                 return;
4022
4023         msix_cnt = pci_msix_count(sc->dev);
4024 #ifdef IGB_MSIX_DEBUG
4025         msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
4026 #endif
4027         if (msix_cnt <= 1) {
4028                 /* One MSI-X model does not make sense */
4029                 return;
4030         }
4031
4032         i = 0;
4033         while ((1 << (i + 1)) <= msix_cnt)
4034                 ++i;
4035         msix_cnt2 = 1 << i;
4036
4037         if (bootverbose) {
4038                 device_printf(sc->dev, "MSI-X count %d/%d\n",
4039                     msix_cnt2, msix_cnt);
4040         }
4041
4042         KKASSERT(msix_cnt2 <= msix_cnt);
4043         if (msix_cnt == msix_cnt2) {
4044                 /* We need at least one MSI-X for link status */
4045                 msix_cnt2 >>= 1;
4046                 if (msix_cnt2 <= 1) {
4047                         /* One MSI-X for RX/TX does not make sense */
4048                         device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4049                             "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4050                         return;
4051                 }
4052                 KKASSERT(msix_cnt > msix_cnt2);
4053
4054                 if (bootverbose) {
4055                         device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4056                             msix_cnt2, msix_cnt);
4057                 }
4058         }
4059
4060         sc->rx_ring_msix = sc->rx_ring_cnt;
4061         if (sc->rx_ring_msix > msix_cnt2)
4062                 sc->rx_ring_msix = msix_cnt2;
4063
4064         if (msix_cnt >= sc->tx_ring_cnt + sc->rx_ring_msix + 1) {
4065                 /*
4066                  * Independent TX/RX MSI-X
4067                  */
4068                 aggregate = FALSE;
4069                 if (bootverbose)
4070                         device_printf(sc->dev, "independent TX/RX MSI-X\n");
4071                 alloc_cnt = sc->tx_ring_cnt + sc->rx_ring_msix;
4072         } else {
4073                 /*
4074                  * Aggregate TX/RX MSI-X
4075                  */
4076                 aggregate = TRUE;
4077                 if (bootverbose)
4078                         device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4079                 alloc_cnt = msix_cnt2;
4080                 if (alloc_cnt > ncpus2)
4081                         alloc_cnt = ncpus2;
4082                 if (sc->rx_ring_msix > alloc_cnt)
4083                         sc->rx_ring_msix = alloc_cnt;
4084         }
4085         ++alloc_cnt;    /* For link status */
4086
4087         if (bootverbose) {
4088                 device_printf(sc->dev, "MSI-X alloc %d, RX ring %d\n",
4089                     alloc_cnt, sc->rx_ring_msix);
4090         }
4091
4092         sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4093         sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4094             &sc->msix_mem_rid, RF_ACTIVE);
4095         if (sc->msix_mem_res == NULL) {
4096                 device_printf(sc->dev, "Unable to map MSI-X table\n");
4097                 return;
4098         }
4099
4100         sc->msix_cnt = alloc_cnt;
4101         sc->msix_data = kmalloc_cachealign(
4102             sizeof(struct igb_msix_data) * sc->msix_cnt,
4103             M_DEVBUF, M_WAITOK | M_ZERO);
4104         for (x = 0; x < sc->msix_cnt; ++x) {
4105                 msix = &sc->msix_data[x];
4106
4107                 lwkt_serialize_init(&msix->msix_serialize0);
4108                 msix->msix_sc = sc;
4109                 msix->msix_rid = -1;
4110                 msix->msix_vector = x;
4111                 msix->msix_mask = 1 << msix->msix_vector;
4112                 msix->msix_rate = IGB_INTR_RATE;
4113         }
4114
4115         x = 0;
4116         if (!aggregate) {
4117                 int offset, offset_def;
4118
4119                 if (sc->rx_ring_msix == ncpus2) {
4120                         offset = 0;
4121                 } else {
4122                         offset_def = (sc->rx_ring_msix *
4123                             device_get_unit(sc->dev)) % ncpus2;
4124
4125                         offset = device_getenv_int(sc->dev,
4126                             "msix.rxoff", offset_def);
4127                         if (offset >= ncpus2 ||
4128                             offset % sc->rx_ring_msix != 0) {
4129                                 device_printf(sc->dev,
4130                                     "invalid msix.rxoff %d, use %d\n",
4131                                     offset, offset_def);
4132                                 offset = offset_def;
4133                         }
4134                 }
4135
4136                 /* RX rings */
4137                 for (i = 0; i < sc->rx_ring_msix; ++i) {
4138                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
4139
4140                         KKASSERT(x < sc->msix_cnt);
4141                         msix = &sc->msix_data[x++];
4142                         rxr->rx_intr_bit = msix->msix_vector;
4143                         rxr->rx_intr_mask = msix->msix_mask;
4144
4145                         msix->msix_serialize = &rxr->rx_serialize;
4146                         msix->msix_func = igb_msix_rx;
4147                         msix->msix_arg = rxr;
4148                         msix->msix_cpuid = i + offset;
4149                         KKASSERT(msix->msix_cpuid < ncpus2);
4150                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4151                             "%s rx%d", device_get_nameunit(sc->dev), i);
4152                         msix->msix_rate = IGB_MSIX_RX_RATE;
4153                         ksnprintf(msix->msix_rate_desc,
4154                             sizeof(msix->msix_rate_desc),
4155                             "RX%d interrupt rate", i);
4156                 }
4157
4158                 offset_def = device_get_unit(sc->dev) % ncpus2;
4159                 offset = device_getenv_int(sc->dev, "msix.txoff", offset_def);
4160                 if (offset >= ncpus2) {
4161                         device_printf(sc->dev, "invalid msix.txoff %d, "
4162                             "use %d\n", offset, offset_def);
4163                         offset = offset_def;
4164                 }
4165
4166                 /* TX rings */
4167                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4168                         struct igb_tx_ring *txr = &sc->tx_rings[i];
4169
4170                         KKASSERT(x < sc->msix_cnt);
4171                         msix = &sc->msix_data[x++];
4172                         txr->tx_intr_bit = msix->msix_vector;
4173                         txr->tx_intr_mask = msix->msix_mask;
4174
4175                         msix->msix_serialize = &txr->tx_serialize;
4176                         msix->msix_func = igb_msix_tx;
4177                         msix->msix_arg = txr;
4178                         msix->msix_cpuid = i + offset;
4179                         sc->msix_tx_cpuid = msix->msix_cpuid; /* XXX */
4180                         KKASSERT(msix->msix_cpuid < ncpus2);
4181                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4182                             "%s tx%d", device_get_nameunit(sc->dev), i);
4183                         msix->msix_rate = IGB_MSIX_TX_RATE;
4184                         ksnprintf(msix->msix_rate_desc,
4185                             sizeof(msix->msix_rate_desc),
4186                             "TX%d interrupt rate", i);
4187                 }
4188         } else {
4189                 /* TODO */
4190                 error = EOPNOTSUPP;
4191                 goto back;
4192         }
4193
4194         /*
4195          * Link status
4196          */
4197         KKASSERT(x < sc->msix_cnt);
4198         msix = &sc->msix_data[x++];
4199         sc->sts_intr_bit = msix->msix_vector;
4200         sc->sts_intr_mask = msix->msix_mask;
4201
4202         msix->msix_serialize = &sc->main_serialize;
4203         msix->msix_func = igb_msix_status;
4204         msix->msix_arg = sc;
4205         msix->msix_cpuid = 0; /* TODO tunable */
4206         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4207             device_get_nameunit(sc->dev));
4208         ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4209             "status interrupt rate");
4210
4211         KKASSERT(x == sc->msix_cnt);
4212
4213         error = pci_setup_msix(sc->dev);
4214         if (error) {
4215                 device_printf(sc->dev, "Setup MSI-X failed\n");
4216                 goto back;
4217         }
4218         setup = TRUE;
4219
4220         for (i = 0; i < sc->msix_cnt; ++i) {
4221                 msix = &sc->msix_data[i];
4222
4223                 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4224                     &msix->msix_rid, msix->msix_cpuid);
4225                 if (error) {
4226                         device_printf(sc->dev,
4227                             "Unable to allocate MSI-X %d on cpu%d\n",
4228                             msix->msix_vector, msix->msix_cpuid);
4229                         goto back;
4230                 }
4231
4232                 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4233                     &msix->msix_rid, RF_ACTIVE);
4234                 if (msix->msix_res == NULL) {
4235                         device_printf(sc->dev,
4236                             "Unable to allocate MSI-X %d resource\n",
4237                             msix->msix_vector);
4238                         error = ENOMEM;
4239                         goto back;
4240                 }
4241         }
4242
4243         pci_enable_msix(sc->dev);
4244         sc->intr_type = PCI_INTR_TYPE_MSIX;
4245 back:
4246         if (error)
4247                 igb_msix_free(sc, setup);
4248 }
4249
4250 static void
4251 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4252 {
4253         int i;
4254
4255         KKASSERT(sc->msix_cnt > 1);
4256
4257         for (i = 0; i < sc->msix_cnt; ++i) {
4258                 struct igb_msix_data *msix = &sc->msix_data[i];
4259
4260                 if (msix->msix_res != NULL) {
4261                         bus_release_resource(sc->dev, SYS_RES_IRQ,
4262                             msix->msix_rid, msix->msix_res);
4263                 }
4264                 if (msix->msix_rid >= 0)
4265                         pci_release_msix_vector(sc->dev, msix->msix_rid);
4266         }
4267         if (setup)
4268                 pci_teardown_msix(sc->dev);
4269
4270         sc->msix_cnt = 0;
4271         kfree(sc->msix_data, M_DEVBUF);
4272         sc->msix_data = NULL;
4273 }
4274
4275 static int
4276 igb_msix_setup(struct igb_softc *sc)
4277 {
4278         struct ifnet *ifp = &sc->arpcom.ac_if;
4279         int i;
4280
4281         for (i = 0; i < sc->msix_cnt; ++i) {
4282                 struct igb_msix_data *msix = &sc->msix_data[i];
4283                 int error;
4284
4285                 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4286                     INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4287                     &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4288                 if (error) {
4289                         device_printf(sc->dev, "could not set up %s "
4290                             "interrupt handler.\n", msix->msix_desc);
4291                         igb_msix_teardown(sc, i);
4292                         return error;
4293                 }
4294         }
4295         ifp->if_cpuid = sc->msix_tx_cpuid;
4296
4297         return 0;
4298 }
4299
4300 static void
4301 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4302 {
4303         int i;
4304
4305         for (i = 0; i < msix_cnt; ++i) {
4306                 struct igb_msix_data *msix = &sc->msix_data[i];
4307
4308                 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4309         }
4310 }
4311
4312 static void
4313 igb_msix_rx(void *arg)
4314 {
4315         struct igb_rx_ring *rxr = arg;
4316
4317         ASSERT_SERIALIZED(&rxr->rx_serialize);
4318         igb_rxeof(rxr, -1);
4319
4320         E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4321 }
4322
4323 static void
4324 igb_msix_tx(void *arg)
4325 {
4326         struct igb_tx_ring *txr = arg;
4327         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
4328
4329         ASSERT_SERIALIZED(&txr->tx_serialize);
4330
4331         igb_txeof(txr);
4332         if (!ifq_is_empty(&ifp->if_snd))
4333                 if_devstart(ifp);
4334
4335         E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4336 }
4337
4338 static void
4339 igb_msix_status(void *arg)
4340 {
4341         struct igb_softc *sc = arg;
4342         uint32_t icr;
4343
4344         ASSERT_SERIALIZED(&sc->main_serialize);
4345
4346         icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4347         if (icr & E1000_ICR_LSC) {
4348                 sc->hw.mac.get_link_status = 1;
4349                 igb_update_link_status(sc);
4350         }
4351
4352         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4353 }
4354
4355 static void
4356 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4357 {
4358         if (!IGB_ENABLE_HWRSS(sc))
4359                 return;
4360
4361         if (polling)
4362                 sc->rx_ring_inuse = sc->rx_ring_cnt;
4363         else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4364                 sc->rx_ring_inuse = IGB_MIN_RING_RSS;
4365         else
4366                 sc->rx_ring_inuse = sc->rx_ring_msix;
4367         if (bootverbose) {
4368                 if_printf(&sc->arpcom.ac_if, "RX rings %d/%d\n",
4369                     sc->rx_ring_inuse, sc->rx_ring_cnt);
4370         }
4371 }
4372
4373 static int
4374 igb_tso_pullup(struct igb_tx_ring *txr, struct mbuf **mp)
4375 {
4376         int hoff, iphlen, thoff;
4377         struct mbuf *m;
4378
4379         m = *mp;
4380         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4381
4382         iphlen = m->m_pkthdr.csum_iphlen;
4383         thoff = m->m_pkthdr.csum_thlen;
4384         hoff = m->m_pkthdr.csum_lhlen;
4385
4386         KASSERT(iphlen > 0, ("invalid ip hlen"));
4387         KASSERT(thoff > 0, ("invalid tcp hlen"));
4388         KASSERT(hoff > 0, ("invalid ether hlen"));
4389
4390         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4391                 m = m_pullup(m, hoff + iphlen + thoff);
4392                 if (m == NULL) {
4393                         *mp = NULL;
4394                         return ENOBUFS;
4395                 }
4396                 *mp = m;
4397         }
4398         if (txr->sc->flags & IGB_FLAG_TSO_IPLEN0) {
4399                 struct ip *ip;
4400
4401                 ip = mtodoff(m, struct ip *, hoff);
4402                 ip->ip_len = 0;
4403         }
4404
4405         return 0;
4406 }
4407
4408 static void
4409 igb_tso_ctx(struct igb_tx_ring *txr, struct mbuf *m, uint32_t *hlen)
4410 {
4411         struct e1000_adv_tx_context_desc *TXD;
4412         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
4413         int hoff, ctxd, iphlen, thoff;
4414
4415         iphlen = m->m_pkthdr.csum_iphlen;
4416         thoff = m->m_pkthdr.csum_thlen;
4417         hoff = m->m_pkthdr.csum_lhlen;
4418
4419         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
4420
4421         ctxd = txr->next_avail_desc;
4422         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
4423
4424         if (m->m_flags & M_VLANTAG) {
4425                 uint16_t vlantag;
4426
4427                 vlantag = htole16(m->m_pkthdr.ether_vlantag);
4428                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
4429         }
4430
4431         vlan_macip_lens |= (hoff << E1000_ADVTXD_MACLEN_SHIFT);
4432         vlan_macip_lens |= iphlen;
4433
4434         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4435         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
4436         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
4437
4438         mss_l4len_idx |= (m->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT);
4439         mss_l4len_idx |= (thoff << E1000_ADVTXD_L4LEN_SHIFT);
4440         /* 82575 needs the queue index added */
4441         if (txr->sc->hw.mac.type == e1000_82575)
4442                 mss_l4len_idx |= txr->me << 4;
4443
4444         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
4445         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
4446         TXD->seqnum_seed = htole32(0);
4447         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
4448
4449         /* We've consumed the first desc, adjust counters */
4450         if (++ctxd == txr->num_tx_desc)
4451                 ctxd = 0;
4452         txr->next_avail_desc = ctxd;
4453         --txr->tx_avail;
4454
4455         *hlen = hoff + iphlen + thoff;
4456 }