sys/contrib/dev/ath/ath_hal/ar9300/ar9300_tx99_tgt.c

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
   9  * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
  10  * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
  11  * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
  12  * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
  13  * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  14  * PERFORMANCE OF THIS SOFTWARE.
  15  */
  16 /*
  17  *  Copyright (c) 2010 Atheros Communications Inc.
  18  *
  19  * Permission to use, copy, modify, and/or distribute this software for any
  20  * purpose with or without fee is hereby granted, provided that the above
  21  * copyright notice and this permission notice appear in all copies.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  24  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  26  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  27  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  28  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  29  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  30  */
  31
  32 #include "ah.h"
  33 #include "ah_internal.h"
  34 #include "ar9300phy.h"
  35 #include "ar9300reg.h"
  36 #include "ar9300eep.h"
  37
  38 #ifdef ATH_TX99_DIAG
  39 void
  40 ar9300_tx99_tgt_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, u_int32_t txpower)
  41 {
  42 #define PWR_MAS(_r, _s)     (((_r) & 0x3f) << (_s))
  43     static int16_t pPwrArray[ar9300_rate_size] = { 0 };
  44     int32_t i;
  45     //u_int8_t ht40PowerIncForPdadc = 2;
  46
  47     for (i = 0; i < ar9300_rate_size; i++)
  48         pPwrArray[i] = txpower;
  49
  50     OS_REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
  51
  52     /* Write the OFDM power per rate set */
  53     /* 6 (LSB), 9, 12, 18 (MSB) */
  54     OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
  55         PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 24)
  56           | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24], 16)
  57           | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24],  8)
  58           | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24],  0)
  59     );
  60     /* 24 (LSB), 36, 48, 54 (MSB) */
  61     OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
  62         PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_54], 24)
  63           | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_48], 16)
  64           | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_36],  8)
  65           | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_6_24],  0)
  66     );
  67
  68         /* Write the CCK power per rate set */
  69     /* 1L (LSB), reserved, 2L, 2S (MSB) */
  70         OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
  71             PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24)
  72                   | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  16)
  73 //                | PWR_MAS(txPowerTimes2,  8) /* this is reserved for Osprey */
  74                   | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L],   0)
  75         );
  76     /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
  77         OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
  78             PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_11S], 24)
  79                   | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_11L], 16)
  80                   | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_5S],  8)
  81                   | PWR_MAS(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
  82         );
  83
  84     /* Write the HT20 power per rate set */
  85     /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
  86     OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
  87         PWR_MAS(pPwrArray[ALL_TARGET_HT20_5], 24)
  88           | PWR_MAS(pPwrArray[ALL_TARGET_HT20_4],  16)
  89           | PWR_MAS(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19],  8)
  90           | PWR_MAS(pPwrArray[ALL_TARGET_HT20_0_8_16],   0)
  91     );
  92
  93     /* 6 (LSB), 7, 12, 13 (MSB) */
  94     OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
  95         PWR_MAS(pPwrArray[ALL_TARGET_HT20_13], 24)
  96           | PWR_MAS(pPwrArray[ALL_TARGET_HT20_12],  16)
  97           | PWR_MAS(pPwrArray[ALL_TARGET_HT20_7],  8)
  98           | PWR_MAS(pPwrArray[ALL_TARGET_HT20_6],   0)
  99     );
 100
 101     /* 14 (LSB), 15, 20, 21 */
 102     OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
 103         PWR_MAS(pPwrArray[ALL_TARGET_HT20_21], 24)
 104           | PWR_MAS(pPwrArray[ALL_TARGET_HT20_20],  16)
 105           | PWR_MAS(pPwrArray[ALL_TARGET_HT20_15],  8)
 106           | PWR_MAS(pPwrArray[ALL_TARGET_HT20_14],   0)
 107     );
 108
 109     /* Mixed HT20 and HT40 rates */
 110     /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
 111     OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
 112         PWR_MAS(pPwrArray[ALL_TARGET_HT40_23], 24)
 113           | PWR_MAS(pPwrArray[ALL_TARGET_HT40_22],  16)
 114           | PWR_MAS(pPwrArray[ALL_TARGET_HT20_23],  8)
 115           | PWR_MAS(pPwrArray[ALL_TARGET_HT20_22],   0)
 116     );
 117
 118     /* Write the HT40 power per rate set */
 119     // correct PAR difference between HT40 and HT20/LEGACY
 120     /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
 121     OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
 122         PWR_MAS(pPwrArray[ALL_TARGET_HT40_5], 24)
 123           | PWR_MAS(pPwrArray[ALL_TARGET_HT40_4],  16)
 124           | PWR_MAS(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19],  8)
 125           | PWR_MAS(pPwrArray[ALL_TARGET_HT40_0_8_16],   0)
 126     );
 127
 128     /* 6 (LSB), 7, 12, 13 (MSB) */
 129     OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
 130         PWR_MAS(pPwrArray[ALL_TARGET_HT40_13], 24)
 131           | PWR_MAS(pPwrArray[ALL_TARGET_HT40_12],  16)
 132           | PWR_MAS(pPwrArray[ALL_TARGET_HT40_7], 8)
 133           | PWR_MAS(pPwrArray[ALL_TARGET_HT40_6], 0)
 134     );
 135
 136     /* 14 (LSB), 15, 20, 21 */
 137         OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE(12),
 138             PWR_MAS(pPwrArray[ALL_TARGET_HT40_21], 24)
 139               | PWR_MAS(pPwrArray[ALL_TARGET_HT40_20],  16)
 140               | PWR_MAS(pPwrArray[ALL_TARGET_HT40_15],  8)
 141               | PWR_MAS(pPwrArray[ALL_TARGET_HT40_14],   0)
 142         );
 143 #undef PWR_MAS
 144 }
 145
 146 void
 147 ar9300_tx99_tgt_chainmsk_setup(struct ath_hal *ah, int tx_chainmask)
 148 {
 149     if (tx_chainmask == 0x5) {
 150         OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
 151     }
 152     OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask);
 153     OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask);
 154
 155     OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
 156     if (tx_chainmask == 0x5) {
 157         OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
 158     }
 159 }
 160
 161 void
 162 ar9300_tx99_tgt_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype)
 163 {
 164     OS_REG_WRITE(ah, AR_PHY_TST_DAC_CONST, OS_REG_READ(ah, AR_PHY_TST_DAC_CONST) | (0x7ff<<11) | 0x7ff);
 165     OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, OS_REG_READ(ah, AR_PHY_TEST_CTL_STATUS) | (1<<7) | (1<<1));
 166     OS_REG_WRITE(ah, AR_PHY_ADDAC_PARA_CTL, (OS_REG_READ(ah, AR_PHY_ADDAC_PARA_CTL) | (1<<31) | (1<<15)) & ~(1<<13));
 167
 168     /* 11G mode */
 169     if (!chtype)
 170     {
 171         OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
 172                                                     | (0x1 << 3) | (0x1 << 2));
 173         if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
 174             OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP)
 175                                                         & ~(0x1 << 4));
 176             OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
 177                                                         | (0x1 << 26)  | (0x7 << 24))
 178                                                         & ~(0x1 << 22));
 179         } else {
 180             OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP)
 181                                                         & ~(0x1 << 4));
 182             OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, (OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
 183                                                         | (0x1 << 26)  | (0x7 << 24))
 184                                                         & ~(0x1 << 22));
 185         }
 186
 187         /* chain zero */
 188         if((tx_chain_mask & 0x01) == 0x01) {
 189                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
 190                                                           | (0x1 << 31) | (0x5 << 15)
 191                                                           | (0x3 << 9)) & ~(0x1 << 27)
 192                                                           & ~(0x1 << 12));
 193                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
 194                                                           | (0x1 << 12) | (0x1 << 10)
 195                                                           | (0x1 << 9)  | (0x1 << 8)
 196                                                           | (0x1 << 7)) & ~(0x1 << 11));
 197                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
 198                                                           | (0x1 << 29) | (0x1 << 25)
 199                                                           | (0x1 << 23) | (0x1 << 19)
 200                                                           | (0x1 << 10) | (0x1 << 9)
 201                                                           | (0x1 << 8)  | (0x1 << 3))
 202                                                           & ~(0x1 << 28)& ~(0x1 << 24)
 203                                                           & ~(0x1 << 22)& ~(0x1 << 7));
 204                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
 205                                                           | (0x1 << 23))& ~(0x1 << 21));
 206                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
 207                                                           | (0x1 << 12) | (0x1 << 10)
 208                                                           | (0x1 << 9)  | (0x1 << 8)
 209                                                           | (0x1 << 6)  | (0x1 << 5)
 210                                                           | (0x1 << 4)  | (0x1 << 3)
 211                                                           | (0x1 << 2));
 212             OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2)
 213                                                           | (0x1 << 31));
 214         }
 215         if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
 216             /* chain one */
 217                 if ((tx_chain_mask & 0x02) == 0x02 ) {
 218                     OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
 219                                                               | (0x1 << 31) | (0x5 << 15)
 220                                                               | (0x3 << 9)) & ~(0x1 << 27)
 221                                                               & ~(0x1 << 12));
 222                         OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
 223                                                               | (0x1 << 12) | (0x1 << 10)
 224                                                               | (0x1 << 9)  | (0x1 << 8)
 225                                                               | (0x1 << 7)) & ~(0x1 << 11));
 226                 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
 227                                                               | (0x1 << 29) | (0x1 << 25)
 228                                                               | (0x1 << 23) | (0x1 << 19)
 229                                                               | (0x1 << 10) | (0x1 << 9)
 230                                                               | (0x1 << 8)  | (0x1 << 3))
 231                                                               & ~(0x1 << 28)& ~(0x1 << 24)
 232                                                               & ~(0x1 << 22)& ~(0x1 << 7));
 233                 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
 234                                                               | (0x1 << 23))& ~(0x1 << 21));
 235                         OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
 236                                                               | (0x1 << 12) | (0x1 << 10)
 237                                                               | (0x1 << 9)  | (0x1 << 8)
 238                                                               | (0x1 << 6)  | (0x1 << 5)
 239                                                               | (0x1 << 4)  | (0x1 << 3)
 240                                                               | (0x1 << 2));
 241                 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2)
 242                                                               | (0x1 << 31));
 243                 }
 244         }
 245         if (AR_SREV_OSPREY(ah)) {
 246                 /* chain two */
 247                 if ((tx_chain_mask & 0x04) == 0x04 ) {
 248                     OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
 249                                                               | (0x1 << 31) | (0x5 << 15)
 250                                                               | (0x3 << 9)) & ~(0x1 << 27)
 251                                                               & ~(0x1 << 12));
 252                         OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
 253                                                               | (0x1 << 12) | (0x1 << 10)
 254                                                               | (0x1 << 9)  | (0x1 << 8)
 255                                                               | (0x1 << 7)) & ~(0x1 << 11));
 256                 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
 257                                                               | (0x1 << 29) | (0x1 << 25)
 258                                                               | (0x1 << 23) | (0x1 << 19)
 259                                                               | (0x1 << 10) | (0x1 << 9)
 260                                                               | (0x1 << 8)  | (0x1 << 3))
 261                                                               & ~(0x1 << 28)& ~(0x1 << 24)
 262                                                               & ~(0x1 << 22)& ~(0x1 << 7));
 263                 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
 264                                                               | (0x1 << 23))& ~(0x1 << 21));
 265                         OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
 266                                                               | (0x1 << 12) | (0x1 << 10)
 267                                                               | (0x1 << 9)  | (0x1 << 8)
 268                                                               | (0x1 << 6)  | (0x1 << 5)
 269                                                               | (0x1 << 4)  | (0x1 << 3)
 270                                                               | (0x1 << 2));
 271                 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2)
 272                                                               | (0x1 << 31));
 273                 }
 274         }
 275
 276         OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0x11111);
 277         OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x111);
 278     }
 279     else
 280     {
 281         /* chain zero */
 282         if((tx_chain_mask & 0x01) == 0x01) {
 283             OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
 284                                                               | (0x1 << 31) | (0x1 << 27)
 285                                                           | (0x3 << 23) | (0x1 << 19)
 286                                                           | (0x1 << 15) | (0x3 << 9))
 287                                                           & ~(0x1 << 12));
 288                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
 289                                                           | (0x1 << 12) | (0x1 << 10)
 290                                                           | (0x1 << 9)  | (0x1 << 8)
 291                                                           | (0x1 << 7)  | (0x1 << 3)
 292                                                           | (0x1 << 2)  | (0x1 << 1))
 293                                                           & ~(0x1 << 11)& ~(0x1 << 0));
 294             OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
 295                                                                       | (0x1 << 29) | (0x1 << 25)
 296                                                           | (0x1 << 23) | (0x1 << 19)
 297                                                           | (0x1 << 10) | (0x1 << 9)
 298                                                           | (0x1 << 8)  | (0x1 << 3))
 299                                                           & ~(0x1 << 28)& ~(0x1 << 24)
 300                                                           & ~(0x1 << 22)& ~(0x1 << 7));
 301                         OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
 302                                                                       | (0x1 << 23))& ~(0x1 << 21));
 303                         OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2)
 304                                                           | (0x3 << 3)  | (0x3 << 0));
 305                         OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3)
 306                                                           | (0x3 << 29) | (0x3 << 26)
 307                                                           | (0x2 << 23) | (0x2 << 20)
 308                                                           | (0x2 << 17))& ~(0x1 << 14));
 309                         OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
 310                                                                       | (0x1 << 12) | (0x1 << 10)
 311                                                           | (0x1 << 9)  | (0x1 << 8)
 312                                                           | (0x1 << 6)  | (0x1 << 5)
 313                                                           | (0x1 << 4)  | (0x1 << 3)
 314                                                           | (0x1 << 2));
 315                         OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2)
 316                                                           | (0x1 << 31));
 317                         if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
 318                         OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP)
 319                                                                       & ~(0x1 << 4));
 320                         OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
 321                                                                   | (0x1 << 26) | (0x7 << 24)
 322                                                                   | (0x3 << 22));
 323             } else {
 324                         OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP)
 325                                                                       & ~(0x1 << 4));
 326                         OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
 327                                                                   | (0x1 << 26) | (0x7 << 24)
 328                                                                   | (0x3 << 22));
 329                     }
 330
 331             if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
 332                 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
 333                                                                       | (0x1 << 3)  | (0x1 << 2)
 334                                                               | (0x1 << 1)) & ~(0x1 << 0));
 335                         OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
 336                                                                       | (0x1 << 19) | (0x1 << 3));
 337                 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
 338                                                                       | (0x1 << 23));
 339                         }
 340                         if (AR_SREV_OSPREY(ah)) {
 341                 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
 342                                                                       | (0x1 << 3)  | (0x1 << 2)
 343                                                               | (0x1 << 1)) & ~(0x1 << 0));
 344                         OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
 345                                                                       | (0x1 << 19) | (0x1 << 3));
 346                         OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
 347                                                                       | (0x1 << 23));
 348             }
 349         }
 350         if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
 351             /* chain one */
 352                 if ((tx_chain_mask & 0x02) == 0x02 ) {
 353                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
 354                                                               | (0x1 << 3)  | (0x1 << 2)
 355                                                               | (0x1 << 1)) & ~(0x1 << 0));
 356                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
 357                                                                       | (0x1 << 19) | (0x1 << 3));
 358                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
 359                                                                       | (0x1 << 23));
 360                         if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
 361                                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP)
 362                                                                   & ~(0x1 << 4));
 363                                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
 364                                                                           | (0x1 << 26) | (0x7 << 24)
 365                                                                           | (0x3 << 22));
 366                 } else {
 367                                 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP)
 368                                                                   & ~(0x1 << 4));
 369                                 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
 370                                                                           | (0x1 << 26) | (0x7 << 24)
 371                                                                           | (0x3 << 22));
 372                 }
 373
 374                 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
 375                                                                       | (0x1 << 31) | (0x1 << 27)
 376                                                               | (0x3 << 23) | (0x1 << 19)
 377                                                               | (0x1 << 15) | (0x3 << 9))
 378                                                               & ~(0x1 << 12));
 379                         OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
 380                                                               | (0x1 << 12) | (0x1 << 10)
 381                                                               | (0x1 << 9)  | (0x1 << 8)
 382                                                               | (0x1 << 7)  | (0x1 << 3)
 383                                                               | (0x1 << 2)  | (0x1 << 1))
 384                                                               & ~(0x1 << 11)& ~(0x1 << 0));
 385                         OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
 386                                                                       | (0x1 << 29) | (0x1 << 25)
 387                                                               | (0x1 << 23) | (0x1 << 19)
 388                                                               | (0x1 << 10) | (0x1 << 9)
 389                                                               | (0x1 << 8)  | (0x1 << 3))
 390                                                               & ~(0x1 << 28)& ~(0x1 << 24)
 391                                                               & ~(0x1 << 22)& ~(0x1 << 7));
 392                         OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
 393                                                                       | (0x1 << 23))& ~(0x1 << 21));
 394                         OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2)
 395                                                               | (0x3 << 3)  | (0x3 << 0));
 396                         OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3)
 397                                                               | (0x3 << 29) | (0x3 << 26)
 398                                                               | (0x2 << 23) | (0x2 << 20)
 399                                                               | (0x2 << 17))& ~(0x1 << 14));
 400                         OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
 401                                                                       | (0x1 << 12) | (0x1 << 10)
 402                                                               | (0x1 << 9)  | (0x1 << 8)
 403                                                               | (0x1 << 6)  | (0x1 << 5)
 404                                                               | (0x1 << 4)  | (0x1 << 3)
 405                                                               | (0x1 << 2));
 406                         OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2)
 407                                                               | (0x1 << 31));
 408
 409                         if (AR_SREV_OSPREY(ah)) {
 410                     OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
 411                                                                               | (0x1 << 3)  | (0x1 << 2)
 412                                                                   | (0x1 << 1)) & ~(0x1 << 0));
 413                                 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
 414                                                                               | (0x1 << 19) | (0x1 << 3));
 415                                 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
 416                                                                               | (0x1 << 23));
 417                     }
 418                 }
 419         }
 420         if (AR_SREV_OSPREY(ah)) {
 421                 /* chain two */
 422                 if ((tx_chain_mask & 0x04) == 0x04 ) {
 423                         OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
 424                                                               | (0x1 << 3)  | (0x1 << 2)
 425                                                               | (0x1 << 1)) & ~(0x1 << 0));
 426                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
 427                                                                       | (0x1 << 19) | (0x1 << 3));
 428                         OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
 429                                                                       | (0x1 << 23));
 430                         if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
 431                                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP)
 432                                                                               & ~(0x1 << 4));
 433                                 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
 434                                                                           | (0x1 << 26) | (0x7 << 24)
 435                                                                           | (0x3 << 22));
 436                     } else {
 437                                 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP)
 438                                                                               & ~(0x1 << 4));
 439                                 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
 440                                                                           | (0x1 << 26) | (0x7 << 24)
 441                                                                           | (0x3 << 22));
 442                     }
 443
 444                 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
 445                                                                       | (0x1 << 3)  | (0x1 << 2)
 446                                                               | (0x1 << 1)) & ~(0x1 << 0));
 447                         OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
 448                                                                       | (0x1 << 19) | (0x1 << 3));
 449                 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
 450                                                                       | (0x1 << 23));
 451
 452                 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
 453                                                                       | (0x1 << 31) | (0x1 << 27)
 454                                                               | (0x3 << 23) | (0x1 << 19)
 455                                                               | (0x1 << 15) | (0x3 << 9))
 456                                                               & ~(0x1 << 12));
 457                 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
 458                                                               | (0x1 << 12) | (0x1 << 10)
 459                                                               | (0x1 << 9)  | (0x1 << 8)
 460                                                               | (0x1 << 7)  | (0x1 << 3)
 461                                                               | (0x1 << 2)  | (0x1 << 1))
 462                                                               & ~(0x1 << 11)& ~(0x1 << 0));
 463                         OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
 464                                                                       | (0x1 << 29) | (0x1 << 25)
 465                                                               | (0x1 << 23) | (0x1 << 19)
 466                                                               | (0x1 << 10) | (0x1 << 9)
 467                                                               | (0x1 << 8)  | (0x1 << 3))
 468                                                               & ~(0x1 << 28)& ~(0x1 << 24)
 469                                                               & ~(0x1 << 22)& ~(0x1 << 7));
 470                         OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
 471                                                                       | (0x1 << 23))& ~(0x1 << 21));
 472                         OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2)
 473                                                               | (0x3 << 3)  | (0x3 << 0));
 474                         OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3)
 475                                                               | (0x3 << 29) | (0x3 << 26)
 476                                                               | (0x2 << 23) | (0x2 << 20)
 477                                                               | (0x2 << 17))& ~(0x1 << 14));
 478                         OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
 479                                                                       | (0x1 << 12) | (0x1 << 10)
 480                                                               | (0x1 << 9)  | (0x1 << 8)
 481                                                               | (0x1 << 6)  | (0x1 << 5)
 482                                                               | (0x1 << 4)  | (0x1 << 3)
 483                                                               | (0x1 << 2));
 484                         OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2)
 485                                                               | (0x1 << 31));
 486                 }
 487                 }
 488
 489         OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0x22222);
 490         OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x222);
 491     }
 492 }
 493
 494 void
 495 ar9300_tx99_tgt_start(struct ath_hal *ah, u_int8_t data)
 496 {
 497     a_uint32_t val;
 498     a_uint32_t qnum = (a_uint32_t)data;
 499
 500     /* Disable AGC to A2 */
 501     OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) );
 502     OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000);
 503     OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe);
 504     OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
 505     //OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_FORCE_RX_CLEAR+AR_DIAG_IGNORE_VIRT_CS));
 506     OS_REG_WRITE(ah, AR_CR, AR_CR_RXD);     // set receive disable
 507     //set CW_MIN and CW_MAX both to 0, AIFS=2
 508     OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
 509     OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); //50 OK
 510     OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
 511     OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); //200 ok for HT20, 400 ok for HT40
 512     OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
 513
 514     /* set QCU modes to early termination */
 515     val = OS_REG_READ(ah, AR_QMISC(qnum));
 516     OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ);
 517 }
 518
 519 void
 520 ar9300_tx99_tgt_stop(struct ath_hal *ah)
 521 {
 522     OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR);
 523     OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ (AR_DIAG_FORCE_RX_CLEAR | AR_DIAG_IGNORE_VIRT_CS));
 524 }
 525 #endif