sys/dev/netif/bnx/if_bnx.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 #include "opt_bnx.h"
  37 #include "opt_ifpoll.h"
  38
  39 #include <sys/param.h>
  40 #include <sys/bus.h>
  41 #include <sys/endian.h>
  42 #include <sys/kernel.h>
  43 #include <sys/interrupt.h>
  44 #include <sys/mbuf.h>
  45 #include <sys/malloc.h>
  46 #include <sys/queue.h>
  47 #include <sys/rman.h>
  48 #include <sys/serialize.h>
  49 #include <sys/socket.h>
  50 #include <sys/sockio.h>
  51 #include <sys/sysctl.h>
  52
  53 #include <netinet/ip.h>
  54 #include <netinet/tcp.h>
  55
  56 #include <net/bpf.h>
  57 #include <net/ethernet.h>
  58 #include <net/if.h>
  59 #include <net/if_arp.h>
  60 #include <net/if_dl.h>
  61 #include <net/if_media.h>
  62 #include <net/if_poll.h>
  63 #include <net/if_types.h>
  64 #include <net/ifq_var.h>
  65 #include <net/toeplitz.h>
  66 #include <net/toeplitz2.h>
  67 #include <net/vlan/if_vlan_var.h>
  68 #include <net/vlan/if_vlan_ether.h>
  69
  70 #include <dev/netif/mii_layer/mii.h>
  71 #include <dev/netif/mii_layer/miivar.h>
  72 #include <dev/netif/mii_layer/brgphyreg.h>
  73
  74 #include <bus/pci/pcidevs.h>
  75 #include <bus/pci/pcireg.h>
  76 #include <bus/pci/pcivar.h>
  77
  78 #include <dev/netif/bge/if_bgereg.h>
  79 #include <dev/netif/bnx/if_bnxvar.h>
  80
  81 /* "device miibus" required.  See GENERIC if you get errors here. */
  82 #include "miibus_if.h"
  83
  84 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  85
  86 #define BNX_INTR_CKINTVL        ((10 * hz) / 1000)      /* 10ms */
  87
  88 #ifdef BNX_RSS_DEBUG
  89 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...) \
  90 do { \
  91         if (sc->bnx_rss_debug >= lvl) \
  92                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  93 } while (0)
  94 #else   /* !BNX_RSS_DEBUG */
  95 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  96 #endif  /* BNX_RSS_DEBUG */
  97
  98 static const struct bnx_type {
  99         uint16_t                bnx_vid;
 100         uint16_t                bnx_did;
 101         char                    *bnx_name;
 102 } bnx_devs[] = {
 103         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
 104                 "Broadcom BCM5717 Gigabit Ethernet" },
 105         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
 106                 "Broadcom BCM5717C Gigabit Ethernet" },
 107         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
 108                 "Broadcom BCM5718 Gigabit Ethernet" },
 109         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
 110                 "Broadcom BCM5719 Gigabit Ethernet" },
 111         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
 112                 "Broadcom BCM5720 Gigabit Ethernet" },
 113
 114         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
 115                 "Broadcom BCM5725 Gigabit Ethernet" },
 116         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
 117                 "Broadcom BCM5727 Gigabit Ethernet" },
 118         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
 119                 "Broadcom BCM5762 Gigabit Ethernet" },
 120
 121         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
 122                 "Broadcom BCM57761 Gigabit Ethernet" },
 123         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
 124                 "Broadcom BCM57762 Gigabit Ethernet" },
 125         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
 126                 "Broadcom BCM57765 Gigabit Ethernet" },
 127         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
 128                 "Broadcom BCM57766 Gigabit Ethernet" },
 129         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
 130                 "Broadcom BCM57781 Gigabit Ethernet" },
 131         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
 132                 "Broadcom BCM57782 Gigabit Ethernet" },
 133         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
 134                 "Broadcom BCM57785 Gigabit Ethernet" },
 135         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
 136                 "Broadcom BCM57786 Gigabit Ethernet" },
 137         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
 138                 "Broadcom BCM57791 Fast Ethernet" },
 139         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
 140                 "Broadcom BCM57795 Fast Ethernet" },
 141
 142         { 0, 0, NULL }
 143 };
 144
 145 static const int bnx_tx_mailbox[BNX_TX_RING_MAX] = {
 146         BGE_MBX_TX_HOST_PROD0_LO,
 147         BGE_MBX_TX_HOST_PROD0_HI,
 148         BGE_MBX_TX_HOST_PROD1_LO,
 149         BGE_MBX_TX_HOST_PROD1_HI
 150 };
 151
 152 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
 153 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
 154 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
 155 #define BNX_IS_57765_FAMILY(sc)  \
 156         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
 157
 158 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
 159
 160 static int      bnx_probe(device_t);
 161 static int      bnx_attach(device_t);
 162 static int      bnx_detach(device_t);
 163 static void     bnx_shutdown(device_t);
 164 static int      bnx_suspend(device_t);
 165 static int      bnx_resume(device_t);
 166 static int      bnx_miibus_readreg(device_t, int, int);
 167 static int      bnx_miibus_writereg(device_t, int, int, int);
 168 static void     bnx_miibus_statchg(device_t);
 169
 170 static void     bnx_handle_status(struct bnx_softc *);
 171 #ifdef IFPOLL_ENABLE
 172 static void     bnx_npoll(struct ifnet *, struct ifpoll_info *);
 173 static void     bnx_npoll_rx(struct ifnet *, void *, int);
 174 static void     bnx_npoll_tx(struct ifnet *, void *, int);
 175 static void     bnx_npoll_tx_notag(struct ifnet *, void *, int);
 176 static void     bnx_npoll_status(struct ifnet *);
 177 static void     bnx_npoll_status_notag(struct ifnet *);
 178 #endif
 179 static void     bnx_intr_legacy(void *);
 180 static void     bnx_msi(void *);
 181 static void     bnx_intr(struct bnx_softc *);
 182 static void     bnx_msix_status(void *);
 183 static void     bnx_msix_tx_status(void *);
 184 static void     bnx_msix_rx(void *);
 185 static void     bnx_msix_rxtx(void *);
 186 static void     bnx_enable_intr(struct bnx_softc *);
 187 static void     bnx_disable_intr(struct bnx_softc *);
 188 static void     bnx_txeof(struct bnx_tx_ring *, uint16_t);
 189 static void     bnx_rxeof(struct bnx_rx_ret_ring *, uint16_t, int);
 190 static int      bnx_alloc_intr(struct bnx_softc *);
 191 static int      bnx_setup_intr(struct bnx_softc *);
 192 static void     bnx_free_intr(struct bnx_softc *);
 193 static void     bnx_teardown_intr(struct bnx_softc *, int);
 194 static int      bnx_alloc_msix(struct bnx_softc *);
 195 static void     bnx_free_msix(struct bnx_softc *, boolean_t);
 196 static void     bnx_check_intr_rxtx(void *);
 197 static void     bnx_check_intr_rx(void *);
 198 static void     bnx_check_intr_tx(void *);
 199 static void     bnx_rx_std_refill_ithread(void *);
 200 static void     bnx_rx_std_refill(void *, void *);
 201 static void     bnx_rx_std_refill_sched_ipi(void *);
 202 static void     bnx_rx_std_refill_stop(void *);
 203 static void     bnx_rx_std_refill_sched(struct bnx_rx_ret_ring *,
 204                     struct bnx_rx_std_ring *);
 205
 206 static void     bnx_start(struct ifnet *, struct ifaltq_subque *);
 207 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 208 static void     bnx_init(void *);
 209 static void     bnx_stop(struct bnx_softc *);
 210 static void     bnx_watchdog(struct ifaltq_subque *);
 211 static int      bnx_ifmedia_upd(struct ifnet *);
 212 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 213 static void     bnx_tick(void *);
 214 static void     bnx_serialize(struct ifnet *, enum ifnet_serialize);
 215 static void     bnx_deserialize(struct ifnet *, enum ifnet_serialize);
 216 static int      bnx_tryserialize(struct ifnet *, enum ifnet_serialize);
 217 #ifdef INVARIANTS
 218 static void     bnx_serialize_assert(struct ifnet *, enum ifnet_serialize,
 219                     boolean_t);
 220 #endif
 221 static void     bnx_serialize_skipmain(struct bnx_softc *);
 222 static void     bnx_deserialize_skipmain(struct bnx_softc *sc);
 223
 224 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
 225 static void     bnx_free_jumbo_mem(struct bnx_softc *);
 226 static struct bnx_jslot
 227                 *bnx_jalloc(struct bnx_softc *);
 228 static void     bnx_jfree(void *);
 229 static void     bnx_jref(void *);
 230 static int      bnx_newbuf_std(struct bnx_rx_ret_ring *, int, int);
 231 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
 232 static void     bnx_setup_rxdesc_std(struct bnx_rx_std_ring *, int);
 233 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
 234 static int      bnx_init_rx_ring_std(struct bnx_rx_std_ring *);
 235 static void     bnx_free_rx_ring_std(struct bnx_rx_std_ring *);
 236 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
 237 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
 238 static void     bnx_free_tx_ring(struct bnx_tx_ring *);
 239 static int      bnx_init_tx_ring(struct bnx_tx_ring *);
 240 static int      bnx_create_tx_ring(struct bnx_tx_ring *);
 241 static void     bnx_destroy_tx_ring(struct bnx_tx_ring *);
 242 static int      bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *);
 243 static void     bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *);
 244 static int      bnx_dma_alloc(device_t);
 245 static void     bnx_dma_free(struct bnx_softc *);
 246 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
 247                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
 248 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 249 static struct mbuf *
 250                 bnx_defrag_shortdma(struct mbuf *);
 251 static int      bnx_encap(struct bnx_tx_ring *, struct mbuf **,
 252                     uint32_t *, int *);
 253 static int      bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **,
 254                     uint16_t *, uint16_t *);
 255 static void     bnx_setup_serialize(struct bnx_softc *);
 256 static void     bnx_set_tick_cpuid(struct bnx_softc *, boolean_t);
 257 static void     bnx_setup_ring_cnt(struct bnx_softc *);
 258
 259 static struct pktinfo *bnx_rss_info(struct pktinfo *,
 260                     const struct bge_rx_bd *);
 261 static void     bnx_init_rss(struct bnx_softc *);
 262 static void     bnx_reset(struct bnx_softc *);
 263 static int      bnx_chipinit(struct bnx_softc *);
 264 static int      bnx_blockinit(struct bnx_softc *);
 265 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
 266 static void     bnx_enable_msi(struct bnx_softc *, boolean_t);
 267 static void     bnx_setmulti(struct bnx_softc *);
 268 static void     bnx_setpromisc(struct bnx_softc *);
 269 static void     bnx_stats_update_regs(struct bnx_softc *);
 270 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
 271
 272 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
 273 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
 274 #ifdef notdef
 275 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
 276 #endif
 277 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
 278 static void     bnx_writembx(struct bnx_softc *, int, int);
 279 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
 280 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
 281 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
 282
 283 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
 284 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
 285 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
 286 static void     bnx_link_poll(struct bnx_softc *);
 287
 288 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
 289 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
 290 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
 291 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
 292
 293 static void     bnx_coal_change(struct bnx_softc *);
 294 static int      bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS);
 295 static int      bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS);
 296 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 297 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 298 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
 299 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
 300 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 301 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 302 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
 303                     int, int, uint32_t);
 304 #ifdef IFPOLL_ENABLE
 305 static int      bnx_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS);
 306 static int      bnx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
 307 static int      bnx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
 308 #endif
 309 static int      bnx_sysctl_std_refill(SYSCTL_HANDLER_ARGS);
 310
 311 static int      bnx_msi_enable = 1;
 312 static int      bnx_msix_enable = 1;
 313
 314 static int      bnx_rx_rings = 0; /* auto */
 315 static int      bnx_tx_rings = 0; /* auto */
 316
 317 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
 318 TUNABLE_INT("hw.bnx.msix.enable", &bnx_msix_enable);
 319 TUNABLE_INT("hw.bnx.rx_rings", &bnx_rx_rings);
 320 TUNABLE_INT("hw.bnx.tx_rings", &bnx_tx_rings);
 321
 322 static device_method_t bnx_methods[] = {
 323         /* Device interface */
 324         DEVMETHOD(device_probe,         bnx_probe),
 325         DEVMETHOD(device_attach,        bnx_attach),
 326         DEVMETHOD(device_detach,        bnx_detach),
 327         DEVMETHOD(device_shutdown,      bnx_shutdown),
 328         DEVMETHOD(device_suspend,       bnx_suspend),
 329         DEVMETHOD(device_resume,        bnx_resume),
 330
 331         /* bus interface */
 332         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 333         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 334
 335         /* MII interface */
 336         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
 337         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
 338         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
 339
 340         DEVMETHOD_END
 341 };
 342
 343 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
 344 static devclass_t bnx_devclass;
 345
 346 DECLARE_DUMMY_MODULE(if_bnx);
 347 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
 348 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
 349
 350 static uint32_t
 351 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
 352 {
 353         device_t dev = sc->bnx_dev;
 354         uint32_t val;
 355
 356         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 357         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 358         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 359         return (val);
 360 }
 361
 362 static void
 363 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 364 {
 365         device_t dev = sc->bnx_dev;
 366
 367         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 368         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 369         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 370 }
 371
 372 static void
 373 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
 374 {
 375         CSR_WRITE_4(sc, off, val);
 376 }
 377
 378 static void
 379 bnx_writembx(struct bnx_softc *sc, int off, int val)
 380 {
 381         CSR_WRITE_4(sc, off, val);
 382 }
 383
 384 /*
 385  * Read a sequence of bytes from NVRAM.
 386  */
 387 static int
 388 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
 389 {
 390         return (1);
 391 }
 392
 393 /*
 394  * Read a byte of data stored in the EEPROM at address 'addr.' The
 395  * BCM570x supports both the traditional bitbang interface and an
 396  * auto access interface for reading the EEPROM. We use the auto
 397  * access method.
 398  */
 399 static uint8_t
 400 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
 401 {
 402         int i;
 403         uint32_t byte = 0;
 404
 405         /*
 406          * Enable use of auto EEPROM access so we can avoid
 407          * having to use the bitbang method.
 408          */
 409         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 410
 411         /* Reset the EEPROM, load the clock period. */
 412         CSR_WRITE_4(sc, BGE_EE_ADDR,
 413             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 414         DELAY(20);
 415
 416         /* Issue the read EEPROM command. */
 417         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 418
 419         /* Wait for completion */
 420         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
 421                 DELAY(10);
 422                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 423                         break;
 424         }
 425
 426         if (i == BNX_TIMEOUT) {
 427                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 428                 return(1);
 429         }
 430
 431         /* Get result. */
 432         byte = CSR_READ_4(sc, BGE_EE_DATA);
 433
 434         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 435
 436         return(0);
 437 }
 438
 439 /*
 440  * Read a sequence of bytes from the EEPROM.
 441  */
 442 static int
 443 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
 444 {
 445         size_t i;
 446         int err;
 447         uint8_t byte;
 448
 449         for (byte = 0, err = 0, i = 0; i < len; i++) {
 450                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
 451                 if (err)
 452                         break;
 453                 *(dest + i) = byte;
 454         }
 455
 456         return(err ? 1 : 0);
 457 }
 458
 459 static int
 460 bnx_miibus_readreg(device_t dev, int phy, int reg)
 461 {
 462         struct bnx_softc *sc = device_get_softc(dev);
 463         uint32_t val;
 464         int i;
 465
 466         KASSERT(phy == sc->bnx_phyno,
 467             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 468
 469         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 470         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 471                 CSR_WRITE_4(sc, BGE_MI_MODE,
 472                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 473                 DELAY(80);
 474         }
 475
 476         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 477             BGE_MIPHY(phy) | BGE_MIREG(reg));
 478
 479         /* Poll for the PHY register access to complete. */
 480         for (i = 0; i < BNX_TIMEOUT; i++) {
 481                 DELAY(10);
 482                 val = CSR_READ_4(sc, BGE_MI_COMM);
 483                 if ((val & BGE_MICOMM_BUSY) == 0) {
 484                         DELAY(5);
 485                         val = CSR_READ_4(sc, BGE_MI_COMM);
 486                         break;
 487                 }
 488         }
 489         if (i == BNX_TIMEOUT) {
 490                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 491                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 492                 val = 0;
 493         }
 494
 495         /* Restore the autopoll bit if necessary. */
 496         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 497                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 498                 DELAY(80);
 499         }
 500
 501         if (val & BGE_MICOMM_READFAIL)
 502                 return 0;
 503
 504         return (val & 0xFFFF);
 505 }
 506
 507 static int
 508 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
 509 {
 510         struct bnx_softc *sc = device_get_softc(dev);
 511         int i;
 512
 513         KASSERT(phy == sc->bnx_phyno,
 514             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 515
 516         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 517         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 518                 CSR_WRITE_4(sc, BGE_MI_MODE,
 519                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 520                 DELAY(80);
 521         }
 522
 523         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 524             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 525
 526         for (i = 0; i < BNX_TIMEOUT; i++) {
 527                 DELAY(10);
 528                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 529                         DELAY(5);
 530                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 531                         break;
 532                 }
 533         }
 534         if (i == BNX_TIMEOUT) {
 535                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 536                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 537         }
 538
 539         /* Restore the autopoll bit if necessary. */
 540         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 541                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 542                 DELAY(80);
 543         }
 544
 545         return 0;
 546 }
 547
 548 static void
 549 bnx_miibus_statchg(device_t dev)
 550 {
 551         struct bnx_softc *sc;
 552         struct mii_data *mii;
 553
 554         sc = device_get_softc(dev);
 555         mii = device_get_softc(sc->bnx_miibus);
 556
 557         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 558             (IFM_ACTIVE | IFM_AVALID)) {
 559                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 560                 case IFM_10_T:
 561                 case IFM_100_TX:
 562                         sc->bnx_link = 1;
 563                         break;
 564                 case IFM_1000_T:
 565                 case IFM_1000_SX:
 566                 case IFM_2500_SX:
 567                         sc->bnx_link = 1;
 568                         break;
 569                 default:
 570                         sc->bnx_link = 0;
 571                         break;
 572                 }
 573         } else {
 574                 sc->bnx_link = 0;
 575         }
 576         if (sc->bnx_link == 0)
 577                 return;
 578
 579         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 580         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 581             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 582                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 583         } else {
 584                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 585         }
 586
 587         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 588                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 589         } else {
 590                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 591         }
 592 }
 593
 594 /*
 595  * Memory management for jumbo frames.
 596  */
 597 static int
 598 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
 599 {
 600         struct ifnet *ifp = &sc->arpcom.ac_if;
 601         struct bnx_jslot *entry;
 602         uint8_t *ptr;
 603         bus_addr_t paddr;
 604         int i, error;
 605
 606         /*
 607          * Create tag for jumbo mbufs.
 608          * This is really a bit of a kludge. We allocate a special
 609          * jumbo buffer pool which (thanks to the way our DMA
 610          * memory allocation works) will consist of contiguous
 611          * pages. This means that even though a jumbo buffer might
 612          * be larger than a page size, we don't really need to
 613          * map it into more than one DMA segment. However, the
 614          * default mbuf tag will result in multi-segment mappings,
 615          * so we have to create a special jumbo mbuf tag that
 616          * lets us get away with mapping the jumbo buffers as
 617          * a single segment. I think eventually the driver should
 618          * be changed so that it uses ordinary mbufs and cluster
 619          * buffers, i.e. jumbo frames can span multiple DMA
 620          * descriptors. But that's a project for another day.
 621          */
 622
 623         /*
 624          * Create DMA stuffs for jumbo RX ring.
 625          */
 626         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 627                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 628                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 629                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
 630                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
 631         if (error) {
 632                 if_printf(ifp, "could not create jumbo RX ring\n");
 633                 return error;
 634         }
 635
 636         /*
 637          * Create DMA stuffs for jumbo buffer block.
 638          */
 639         error = bnx_dma_block_alloc(sc, BNX_JMEM,
 640                                     &sc->bnx_cdata.bnx_jumbo_tag,
 641                                     &sc->bnx_cdata.bnx_jumbo_map,
 642                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
 643                                     &paddr);
 644         if (error) {
 645                 if_printf(ifp, "could not create jumbo buffer\n");
 646                 return error;
 647         }
 648
 649         SLIST_INIT(&sc->bnx_jfree_listhead);
 650
 651         /*
 652          * Now divide it up into 9K pieces and save the addresses
 653          * in an array. Note that we play an evil trick here by using
 654          * the first few bytes in the buffer to hold the the address
 655          * of the softc structure for this interface. This is because
 656          * bnx_jfree() needs it, but it is called by the mbuf management
 657          * code which will not pass it to us explicitly.
 658          */
 659         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
 660                 entry = &sc->bnx_cdata.bnx_jslots[i];
 661                 entry->bnx_sc = sc;
 662                 entry->bnx_buf = ptr;
 663                 entry->bnx_paddr = paddr;
 664                 entry->bnx_inuse = 0;
 665                 entry->bnx_slot = i;
 666                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
 667
 668                 ptr += BNX_JLEN;
 669                 paddr += BNX_JLEN;
 670         }
 671         return 0;
 672 }
 673
 674 static void
 675 bnx_free_jumbo_mem(struct bnx_softc *sc)
 676 {
 677         /* Destroy jumbo RX ring. */
 678         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 679                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 680                            sc->bnx_ldata.bnx_rx_jumbo_ring);
 681
 682         /* Destroy jumbo buffer block. */
 683         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
 684                            sc->bnx_cdata.bnx_jumbo_map,
 685                            sc->bnx_ldata.bnx_jumbo_buf);
 686 }
 687
 688 /*
 689  * Allocate a jumbo buffer.
 690  */
 691 static struct bnx_jslot *
 692 bnx_jalloc(struct bnx_softc *sc)
 693 {
 694         struct bnx_jslot *entry;
 695
 696         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 697         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
 698         if (entry) {
 699                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
 700                 entry->bnx_inuse = 1;
 701         } else {
 702                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 703         }
 704         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 705         return(entry);
 706 }
 707
 708 /*
 709  * Adjust usage count on a jumbo buffer.
 710  */
 711 static void
 712 bnx_jref(void *arg)
 713 {
 714         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 715         struct bnx_softc *sc = entry->bnx_sc;
 716
 717         if (sc == NULL)
 718                 panic("bnx_jref: can't find softc pointer!");
 719
 720         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 721                 panic("bnx_jref: asked to reference buffer "
 722                     "that we don't manage!");
 723         } else if (entry->bnx_inuse == 0) {
 724                 panic("bnx_jref: buffer already free!");
 725         } else {
 726                 atomic_add_int(&entry->bnx_inuse, 1);
 727         }
 728 }
 729
 730 /*
 731  * Release a jumbo buffer.
 732  */
 733 static void
 734 bnx_jfree(void *arg)
 735 {
 736         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 737         struct bnx_softc *sc = entry->bnx_sc;
 738
 739         if (sc == NULL)
 740                 panic("bnx_jfree: can't find softc pointer!");
 741
 742         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 743                 panic("bnx_jfree: asked to free buffer that we don't manage!");
 744         } else if (entry->bnx_inuse == 0) {
 745                 panic("bnx_jfree: buffer already free!");
 746         } else {
 747                 /*
 748                  * Possible MP race to 0, use the serializer.  The atomic insn
 749                  * is still needed for races against bnx_jref().
 750                  */
 751                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 752                 atomic_subtract_int(&entry->bnx_inuse, 1);
 753                 if (entry->bnx_inuse == 0) {
 754                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
 755                                           entry, jslot_link);
 756                 }
 757                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 758         }
 759 }
 760
 761
 762 /*
 763  * Intialize a standard receive ring descriptor.
 764  */
 765 static int
 766 bnx_newbuf_std(struct bnx_rx_ret_ring *ret, int i, int init)
 767 {
 768         struct mbuf *m_new = NULL;
 769         bus_dma_segment_t seg;
 770         bus_dmamap_t map;
 771         int error, nsegs;
 772         struct bnx_rx_buf *rb;
 773
 774         rb = &ret->bnx_std->bnx_rx_std_buf[i];
 775         KASSERT(!rb->bnx_rx_refilled, ("RX buf %dth has been refilled", i));
 776
 777         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 778         if (m_new == NULL) {
 779                 error = ENOBUFS;
 780                 goto back;
 781         }
 782         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 783         m_adj(m_new, ETHER_ALIGN);
 784
 785         error = bus_dmamap_load_mbuf_segment(ret->bnx_rx_mtag,
 786             ret->bnx_rx_tmpmap, m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 787         if (error) {
 788                 m_freem(m_new);
 789                 goto back;
 790         }
 791
 792         if (!init) {
 793                 bus_dmamap_sync(ret->bnx_rx_mtag, rb->bnx_rx_dmamap,
 794                     BUS_DMASYNC_POSTREAD);
 795                 bus_dmamap_unload(ret->bnx_rx_mtag, rb->bnx_rx_dmamap);
 796         }
 797
 798         map = ret->bnx_rx_tmpmap;
 799         ret->bnx_rx_tmpmap = rb->bnx_rx_dmamap;
 800
 801         rb->bnx_rx_dmamap = map;
 802         rb->bnx_rx_mbuf = m_new;
 803         rb->bnx_rx_paddr = seg.ds_addr;
 804         rb->bnx_rx_len = m_new->m_len;
 805 back:
 806         cpu_sfence();
 807         rb->bnx_rx_refilled = 1;
 808         return error;
 809 }
 810
 811 static void
 812 bnx_setup_rxdesc_std(struct bnx_rx_std_ring *std, int i)
 813 {
 814         struct bnx_rx_buf *rb;
 815         struct bge_rx_bd *r;
 816         bus_addr_t paddr;
 817         int len;
 818
 819         rb = &std->bnx_rx_std_buf[i];
 820         KASSERT(rb->bnx_rx_refilled, ("RX buf %dth is not refilled", i));
 821
 822         paddr = rb->bnx_rx_paddr;
 823         len = rb->bnx_rx_len;
 824
 825         cpu_mfence();
 826
 827         rb->bnx_rx_refilled = 0;
 828
 829         r = &std->bnx_rx_std_ring[i];
 830         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
 831         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
 832         r->bge_len = len;
 833         r->bge_idx = i;
 834         r->bge_flags = BGE_RXBDFLAG_END;
 835 }
 836
 837 /*
 838  * Initialize a jumbo receive ring descriptor. This allocates
 839  * a jumbo buffer from the pool managed internally by the driver.
 840  */
 841 static int
 842 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
 843 {
 844         struct mbuf *m_new = NULL;
 845         struct bnx_jslot *buf;
 846         bus_addr_t paddr;
 847
 848         /* Allocate the mbuf. */
 849         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 850         if (m_new == NULL)
 851                 return ENOBUFS;
 852
 853         /* Allocate the jumbo buffer */
 854         buf = bnx_jalloc(sc);
 855         if (buf == NULL) {
 856                 m_freem(m_new);
 857                 return ENOBUFS;
 858         }
 859
 860         /* Attach the buffer to the mbuf. */
 861         m_new->m_ext.ext_arg = buf;
 862         m_new->m_ext.ext_buf = buf->bnx_buf;
 863         m_new->m_ext.ext_free = bnx_jfree;
 864         m_new->m_ext.ext_ref = bnx_jref;
 865         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
 866
 867         m_new->m_flags |= M_EXT;
 868
 869         m_new->m_data = m_new->m_ext.ext_buf;
 870         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 871
 872         paddr = buf->bnx_paddr;
 873         m_adj(m_new, ETHER_ALIGN);
 874         paddr += ETHER_ALIGN;
 875
 876         /* Save necessary information */
 877         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_mbuf = m_new;
 878         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_paddr = paddr;
 879
 880         /* Set up the descriptor. */
 881         bnx_setup_rxdesc_jumbo(sc, i);
 882         return 0;
 883 }
 884
 885 static void
 886 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
 887 {
 888         struct bge_rx_bd *r;
 889         struct bnx_rx_buf *rc;
 890
 891         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
 892         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 893
 894         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_rx_paddr);
 895         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_rx_paddr);
 896         r->bge_len = rc->bnx_rx_mbuf->m_len;
 897         r->bge_idx = i;
 898         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 899 }
 900
 901 static int
 902 bnx_init_rx_ring_std(struct bnx_rx_std_ring *std)
 903 {
 904         int i, error;
 905
 906         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 907                 /* Use the first RX return ring's tmp RX mbuf DMA map */
 908                 error = bnx_newbuf_std(&std->bnx_sc->bnx_rx_ret_ring[0], i, 1);
 909                 if (error)
 910                         return error;
 911                 bnx_setup_rxdesc_std(std, i);
 912         }
 913
 914         std->bnx_rx_std_refill = 0;
 915         std->bnx_rx_std_running = 0;
 916         cpu_sfence();
 917         lwkt_serialize_handler_enable(&std->bnx_rx_std_serialize);
 918
 919         std->bnx_rx_std = BGE_STD_RX_RING_CNT - 1;
 920         bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO, std->bnx_rx_std);
 921
 922         return(0);
 923 }
 924
 925 static void
 926 bnx_free_rx_ring_std(struct bnx_rx_std_ring *std)
 927 {
 928         int i;
 929
 930         lwkt_serialize_handler_disable(&std->bnx_rx_std_serialize);
 931
 932         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 933                 struct bnx_rx_buf *rb = &std->bnx_rx_std_buf[i];
 934
 935                 rb->bnx_rx_refilled = 0;
 936                 if (rb->bnx_rx_mbuf != NULL) {
 937                         bus_dmamap_unload(std->bnx_rx_mtag, rb->bnx_rx_dmamap);
 938                         m_freem(rb->bnx_rx_mbuf);
 939                         rb->bnx_rx_mbuf = NULL;
 940                 }
 941                 bzero(&std->bnx_rx_std_ring[i], sizeof(struct bge_rx_bd));
 942         }
 943 }
 944
 945 static int
 946 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
 947 {
 948         struct bge_rcb *rcb;
 949         int i, error;
 950
 951         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 952                 error = bnx_newbuf_jumbo(sc, i, 1);
 953                 if (error)
 954                         return error;
 955         }
 956
 957         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
 958
 959         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
 960         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 961         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 962
 963         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
 964
 965         return(0);
 966 }
 967
 968 static void
 969 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
 970 {
 971         int i;
 972
 973         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 974                 struct bnx_rx_buf *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 975
 976                 if (rc->bnx_rx_mbuf != NULL) {
 977                         m_freem(rc->bnx_rx_mbuf);
 978                         rc->bnx_rx_mbuf = NULL;
 979                 }
 980                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
 981                     sizeof(struct bge_rx_bd));
 982         }
 983 }
 984
 985 static void
 986 bnx_free_tx_ring(struct bnx_tx_ring *txr)
 987 {
 988         int i;
 989
 990         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 991                 struct bnx_tx_buf *buf = &txr->bnx_tx_buf[i];
 992
 993                 if (buf->bnx_tx_mbuf != NULL) {
 994                         bus_dmamap_unload(txr->bnx_tx_mtag,
 995                             buf->bnx_tx_dmamap);
 996                         m_freem(buf->bnx_tx_mbuf);
 997                         buf->bnx_tx_mbuf = NULL;
 998                 }
 999                 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd));
1000         }
1001         txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
1002 }
1003
1004 static int
1005 bnx_init_tx_ring(struct bnx_tx_ring *txr)
1006 {
1007         txr->bnx_tx_cnt = 0;
1008         txr->bnx_tx_saved_considx = 0;
1009         txr->bnx_tx_prodidx = 0;
1010
1011         /* Initialize transmit producer index for host-memory send ring. */
1012         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, txr->bnx_tx_prodidx);
1013
1014         return(0);
1015 }
1016
1017 static void
1018 bnx_setmulti(struct bnx_softc *sc)
1019 {
1020         struct ifnet *ifp;
1021         struct ifmultiaddr *ifma;
1022         uint32_t hashes[4] = { 0, 0, 0, 0 };
1023         int h, i;
1024
1025         ifp = &sc->arpcom.ac_if;
1026
1027         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1028                 for (i = 0; i < 4; i++)
1029                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1030                 return;
1031         }
1032
1033         /* First, zot all the existing filters. */
1034         for (i = 0; i < 4; i++)
1035                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1036
1037         /* Now program new ones. */
1038         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1039                 if (ifma->ifma_addr->sa_family != AF_LINK)
1040                         continue;
1041                 h = ether_crc32_le(
1042                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1043                     ETHER_ADDR_LEN) & 0x7f;
1044                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1045         }
1046
1047         for (i = 0; i < 4; i++)
1048                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1049 }
1050
1051 /*
1052  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1053  * self-test results.
1054  */
1055 static int
1056 bnx_chipinit(struct bnx_softc *sc)
1057 {
1058         uint32_t dma_rw_ctl, mode_ctl;
1059         int i;
1060
1061         /* Set endian type before we access any non-PCI registers. */
1062         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
1063             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
1064
1065         /* Clear the MAC control register */
1066         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1067
1068         /*
1069          * Clear the MAC statistics block in the NIC's
1070          * internal memory.
1071          */
1072         for (i = BGE_STATS_BLOCK;
1073             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1074                 BNX_MEMWIN_WRITE(sc, i, 0);
1075
1076         for (i = BGE_STATUS_BLOCK;
1077             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1078                 BNX_MEMWIN_WRITE(sc, i, 0);
1079
1080         if (BNX_IS_57765_FAMILY(sc)) {
1081                 uint32_t val;
1082
1083                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
1084                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1085                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1086
1087                         /* Access the lower 1K of PL PCI-E block registers. */
1088                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1089                             val | BGE_MODECTL_PCIE_PL_SEL);
1090
1091                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
1092                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
1093                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
1094
1095                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1096                 }
1097                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1098                         /* Fix transmit hangs */
1099                         val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
1100                         val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1101                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1102
1103                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1104                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1105
1106                         /* Access the lower 1K of DL PCI-E block registers. */
1107                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1108                             val | BGE_MODECTL_PCIE_DL_SEL);
1109
1110                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1111                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1112                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1113                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1114
1115                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1116                 }
1117
1118                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1119                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1120                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1121                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1122         }
1123
1124         /*
1125          * Set up the PCI DMA control register.
1126          */
1127         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1128         /*
1129          * Disable 32bytes cache alignment for DMA write to host memory
1130          *
1131          * NOTE:
1132          * 64bytes cache alignment for DMA write to host memory is still
1133          * enabled.
1134          */
1135         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1136         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1137                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1138         /*
1139          * Enable HW workaround for controllers that misinterpret
1140          * a status tag update and leave interrupts permanently
1141          * disabled.
1142          */
1143         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1144             sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1145             !BNX_IS_57765_FAMILY(sc))
1146                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1147         if (bootverbose) {
1148                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1149                     dma_rw_ctl);
1150         }
1151         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1152
1153         /*
1154          * Set up general mode register.
1155          */
1156         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1157             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1158         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1159
1160         /*
1161          * Disable memory write invalidate.  Apparently it is not supported
1162          * properly by these devices.  Also ensure that INTx isn't disabled,
1163          * as these chips need it even when using MSI.
1164          */
1165         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1166             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1167
1168         /* Set the timer prescaler (always 66Mhz) */
1169         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1170
1171         return(0);
1172 }
1173
1174 static int
1175 bnx_blockinit(struct bnx_softc *sc)
1176 {
1177         struct bnx_intr_data *intr;
1178         struct bge_rcb *rcb;
1179         bus_size_t vrcb;
1180         bge_hostaddr taddr;
1181         uint32_t val;
1182         int i, limit;
1183
1184         /*
1185          * Initialize the memory window pointer register so that
1186          * we can access the first 32K of internal NIC RAM. This will
1187          * allow us to set up the TX send ring RCBs and the RX return
1188          * ring RCBs, plus other things which live in NIC memory.
1189          */
1190         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1191
1192         /* Configure mbuf pool watermarks */
1193         if (BNX_IS_57765_PLUS(sc)) {
1194                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1195                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1196                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1197                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1198                 } else {
1199                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1200                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1201                 }
1202         } else {
1203                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1204                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1205                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1206         }
1207
1208         /* Configure DMA resource watermarks */
1209         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1210         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1211
1212         /* Enable buffer manager */
1213         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1214         /*
1215          * Change the arbitration algorithm of TXMBUF read request to
1216          * round-robin instead of priority based for BCM5719.  When
1217          * TXFIFO is almost empty, RDMA will hold its request until
1218          * TXFIFO is not almost empty.
1219          */
1220         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1221                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1222         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1223             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1224             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1225                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1226         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1227
1228         /* Poll for buffer manager start indication */
1229         for (i = 0; i < BNX_TIMEOUT; i++) {
1230                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1231                         break;
1232                 DELAY(10);
1233         }
1234
1235         if (i == BNX_TIMEOUT) {
1236                 if_printf(&sc->arpcom.ac_if,
1237                           "buffer manager failed to start\n");
1238                 return(ENXIO);
1239         }
1240
1241         /* Enable flow-through queues */
1242         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1243         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1244
1245         /* Wait until queue initialization is complete */
1246         for (i = 0; i < BNX_TIMEOUT; i++) {
1247                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1248                         break;
1249                 DELAY(10);
1250         }
1251
1252         if (i == BNX_TIMEOUT) {
1253                 if_printf(&sc->arpcom.ac_if,
1254                           "flow-through queue init failed\n");
1255                 return(ENXIO);
1256         }
1257
1258         /*
1259          * Summary of rings supported by the controller:
1260          *
1261          * Standard Receive Producer Ring
1262          * - This ring is used to feed receive buffers for "standard"
1263          *   sized frames (typically 1536 bytes) to the controller.
1264          *
1265          * Jumbo Receive Producer Ring
1266          * - This ring is used to feed receive buffers for jumbo sized
1267          *   frames (i.e. anything bigger than the "standard" frames)
1268          *   to the controller.
1269          *
1270          * Mini Receive Producer Ring
1271          * - This ring is used to feed receive buffers for "mini"
1272          *   sized frames to the controller.
1273          * - This feature required external memory for the controller
1274          *   but was never used in a production system.  Should always
1275          *   be disabled.
1276          *
1277          * Receive Return Ring
1278          * - After the controller has placed an incoming frame into a
1279          *   receive buffer that buffer is moved into a receive return
1280          *   ring.  The driver is then responsible to passing the
1281          *   buffer up to the stack.  BCM5718/BCM57785 families support
1282          *   multiple receive return rings.
1283          *
1284          * Send Ring
1285          * - This ring is used for outgoing frames.  BCM5719/BCM5720
1286          *   support multiple send rings.
1287          */
1288
1289         /* Initialize the standard receive producer ring control block. */
1290         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1291         rcb->bge_hostaddr.bge_addr_lo =
1292             BGE_ADDR_LO(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1293         rcb->bge_hostaddr.bge_addr_hi =
1294             BGE_ADDR_HI(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1295         if (BNX_IS_57765_PLUS(sc)) {
1296                 /*
1297                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1298                  * Bits 15-2 : Maximum RX frame size
1299                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1300                  * Bit 0     : Reserved
1301                  */
1302                 rcb->bge_maxlen_flags =
1303                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1304         } else {
1305                 /*
1306                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1307                  * Bits 15-2 : Reserved (should be 0)
1308                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1309                  * Bit 0     : Reserved
1310                  */
1311                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1312         }
1313         if (BNX_IS_5717_PLUS(sc))
1314                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1315         else
1316                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1317         /* Write the standard receive producer ring control block. */
1318         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1319         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1320         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1321         if (!BNX_IS_5717_PLUS(sc))
1322                 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1323         /* Reset the standard receive producer ring producer index. */
1324         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1325
1326         /*
1327          * Initialize the jumbo RX producer ring control
1328          * block.  We set the 'ring disabled' bit in the
1329          * flags field until we're actually ready to start
1330          * using this ring (i.e. once we set the MTU
1331          * high enough to require it).
1332          */
1333         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1334                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1335                 /* Get the jumbo receive producer ring RCB parameters. */
1336                 rcb->bge_hostaddr.bge_addr_lo =
1337                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1338                 rcb->bge_hostaddr.bge_addr_hi =
1339                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1340                 rcb->bge_maxlen_flags =
1341                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1342                     BGE_RCB_FLAG_RING_DISABLED);
1343                 if (BNX_IS_5717_PLUS(sc))
1344                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1345                 else
1346                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1347                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1348                     rcb->bge_hostaddr.bge_addr_hi);
1349                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1350                     rcb->bge_hostaddr.bge_addr_lo);
1351                 /* Program the jumbo receive producer ring RCB parameters. */
1352                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1353                     rcb->bge_maxlen_flags);
1354                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1355                 /* Reset the jumbo receive producer ring producer index. */
1356                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1357         }
1358
1359         /*
1360          * The BD ring replenish thresholds control how often the
1361          * hardware fetches new BD's from the producer rings in host
1362          * memory.  Setting the value too low on a busy system can
1363          * starve the hardware and recue the throughpout.
1364          *
1365          * Set the BD ring replentish thresholds. The recommended
1366          * values are 1/8th the number of descriptors allocated to
1367          * each ring.
1368          */
1369         val = 8;
1370         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1371         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1372                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1373                     BGE_JUMBO_RX_RING_CNT/8);
1374         }
1375         if (BNX_IS_57765_PLUS(sc)) {
1376                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1377                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1378         }
1379
1380         /*
1381          * Disable all send rings by setting the 'ring disabled' bit
1382          * in the flags field of all the TX send ring control blocks,
1383          * located in NIC memory.
1384          */
1385         if (BNX_IS_5717_PLUS(sc))
1386                 limit = 4;
1387         else if (BNX_IS_57765_FAMILY(sc) ||
1388             sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1389                 limit = 2;
1390         else
1391                 limit = 1;
1392         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1393         for (i = 0; i < limit; i++) {
1394                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1395                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1396                 vrcb += sizeof(struct bge_rcb);
1397         }
1398
1399         /*
1400          * Configure send ring RCBs
1401          */
1402         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1403         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
1404                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
1405
1406                 BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr);
1407                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi,
1408                     taddr.bge_addr_hi);
1409                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo,
1410                     taddr.bge_addr_lo);
1411                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1412                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1413                 vrcb += sizeof(struct bge_rcb);
1414         }
1415
1416         /*
1417          * Disable all receive return rings by setting the
1418          * 'ring disabled' bit in the flags field of all the receive
1419          * return ring control blocks, located in NIC memory.
1420          */
1421         if (BNX_IS_5717_PLUS(sc)) {
1422                 /* Should be 17, use 16 until we get an SRAM map. */
1423                 limit = 16;
1424         } else if (BNX_IS_57765_FAMILY(sc) ||
1425             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1426                 limit = 4;
1427         } else {
1428                 limit = 1;
1429         }
1430         /* Disable all receive return rings. */
1431         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1432         for (i = 0; i < limit; i++) {
1433                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1434                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1435                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1436                     BGE_RCB_FLAG_RING_DISABLED);
1437                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1438                     (i * (sizeof(uint64_t))), 0);
1439                 vrcb += sizeof(struct bge_rcb);
1440         }
1441
1442         /*
1443          * Set up receive return rings.
1444          */
1445         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1446         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
1447                 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
1448
1449                 BGE_HOSTADDR(taddr, ret->bnx_rx_ret_ring_paddr);
1450                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi,
1451                     taddr.bge_addr_hi);
1452                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo,
1453                     taddr.bge_addr_lo);
1454                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1455                     BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0));
1456                 vrcb += sizeof(struct bge_rcb);
1457         }
1458
1459         /* Set random backoff seed for TX */
1460         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1461             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1462             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1463             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1464             BGE_TX_BACKOFF_SEED_MASK);
1465
1466         /* Set inter-packet gap */
1467         val = 0x2620;
1468         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1469             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1470                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1471                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1472         }
1473         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1474
1475         /*
1476          * Specify which ring to use for packets that don't match
1477          * any RX rules.
1478          */
1479         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1480
1481         /*
1482          * Configure number of RX lists. One interrupt distribution
1483          * list, sixteen active lists, one bad frames class.
1484          */
1485         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1486
1487         /* Inialize RX list placement stats mask. */
1488         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1489         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1490
1491         /* Disable host coalescing until we get it set up */
1492         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1493
1494         /* Poll to make sure it's shut down. */
1495         for (i = 0; i < BNX_TIMEOUT; i++) {
1496                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1497                         break;
1498                 DELAY(10);
1499         }
1500
1501         if (i == BNX_TIMEOUT) {
1502                 if_printf(&sc->arpcom.ac_if,
1503                           "host coalescing engine failed to idle\n");
1504                 return(ENXIO);
1505         }
1506
1507         /* Set up host coalescing defaults */
1508         sc->bnx_coal_chg = BNX_RX_COAL_TICKS_CHG |
1509             BNX_TX_COAL_TICKS_CHG |
1510             BNX_RX_COAL_BDS_CHG |
1511             BNX_TX_COAL_BDS_CHG |
1512             BNX_RX_COAL_BDS_INT_CHG |
1513             BNX_TX_COAL_BDS_INT_CHG;
1514         bnx_coal_change(sc);
1515
1516         /*
1517          * Set up addresses of status blocks
1518          */
1519         intr = &sc->bnx_intr_data[0];
1520         bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ);
1521         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1522             BGE_ADDR_HI(intr->bnx_status_block_paddr));
1523         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1524             BGE_ADDR_LO(intr->bnx_status_block_paddr));
1525         for (i = 1; i < sc->bnx_intr_cnt; ++i) {
1526                 intr = &sc->bnx_intr_data[i];
1527                 bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ);
1528                 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_HI + ((i - 1) * 8),
1529                     BGE_ADDR_HI(intr->bnx_status_block_paddr));
1530                 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_LO + ((i - 1) * 8),
1531                     BGE_ADDR_LO(intr->bnx_status_block_paddr));
1532         }
1533
1534         /* Set up status block partail update size. */
1535         val = BGE_STATBLKSZ_32BYTE;
1536 #if 0
1537         /*
1538          * Does not seem to have visible effect in both
1539          * bulk data (1472B UDP datagram) and tiny data
1540          * (18B UDP datagram) TX tests.
1541          */
1542         val |= BGE_HCCMODE_CLRTICK_TX;
1543 #endif
1544         /* Turn on host coalescing state machine */
1545         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1546
1547         /* Turn on RX BD completion state machine and enable attentions */
1548         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1549             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1550
1551         /* Turn on RX list placement state machine */
1552         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1553
1554         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1555             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1556             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1557             BGE_MACMODE_FRMHDR_DMA_ENB;
1558
1559         if (sc->bnx_flags & BNX_FLAG_TBI)
1560                 val |= BGE_PORTMODE_TBI;
1561         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1562                 val |= BGE_PORTMODE_GMII;
1563         else
1564                 val |= BGE_PORTMODE_MII;
1565
1566         /* Turn on DMA, clear stats */
1567         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1568
1569         /* Set misc. local control, enable interrupts on attentions */
1570         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1571
1572 #ifdef notdef
1573         /* Assert GPIO pins for PHY reset */
1574         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1575             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1576         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1577             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1578 #endif
1579
1580         if (sc->bnx_intr_type == PCI_INTR_TYPE_MSIX)
1581                 bnx_enable_msi(sc, TRUE);
1582
1583         /* Turn on write DMA state machine */
1584         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1585         /* Enable host coalescing bug fix. */
1586         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1587         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1588                 /* Request larger DMA burst size to get better performance. */
1589                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1590         }
1591         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1592         DELAY(40);
1593
1594         if (BNX_IS_57765_PLUS(sc)) {
1595                 uint32_t dmactl, dmactl_reg;
1596
1597                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1598                         dmactl_reg = BGE_RDMA_RSRVCTRL2;
1599                 else
1600                         dmactl_reg = BGE_RDMA_RSRVCTRL;
1601
1602                 dmactl = CSR_READ_4(sc, dmactl_reg);
1603                 /*
1604                  * Adjust tx margin to prevent TX data corruption and
1605                  * fix internal FIFO overflow.
1606                  */
1607                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1608                     sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1609                     sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1610                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1611                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1612                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1613                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1614                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1615                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1616                 }
1617                 /*
1618                  * Enable fix for read DMA FIFO overruns.
1619                  * The fix is to limit the number of RX BDs
1620                  * the hardware would fetch at a fime.
1621                  */
1622                 CSR_WRITE_4(sc, dmactl_reg,
1623                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1624         }
1625
1626         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1627                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1628                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1629                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1630                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1631         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1632             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1633                 uint32_t ctrl_reg;
1634
1635                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1636                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1637                 else
1638                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1639
1640                 /*
1641                  * Allow 4KB burst length reads for non-LSO frames.
1642                  * Enable 512B burst length reads for buffer descriptors.
1643                  */
1644                 CSR_WRITE_4(sc, ctrl_reg,
1645                     CSR_READ_4(sc, ctrl_reg) |
1646                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1647                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1648         }
1649
1650         /* Turn on read DMA state machine */
1651         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1652         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1653                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1654         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1655             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1656             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1657                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1658                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1659                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1660         }
1661         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1662             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1663                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1664                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1665                 /*
1666                  * Allow multiple outstanding read requests from
1667                  * non-LSO read DMA engine.
1668                  */
1669                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1670         }
1671         if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
1672                 val |= BGE_RDMAMODE_JMB_2K_MMRR;
1673         if (sc->bnx_flags & BNX_FLAG_TSO)
1674                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1675         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1676         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1677         DELAY(40);
1678
1679         /* Turn on RX data completion state machine */
1680         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1681
1682         /* Turn on RX BD initiator state machine */
1683         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1684
1685         /* Turn on RX data and RX BD initiator state machine */
1686         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1687
1688         /* Turn on send BD completion state machine */
1689         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1690
1691         /* Turn on send data completion state machine */
1692         val = BGE_SDCMODE_ENABLE;
1693         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1694                 val |= BGE_SDCMODE_CDELAY;
1695         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1696
1697         /* Turn on send data initiator state machine */
1698         if (sc->bnx_flags & BNX_FLAG_TSO) {
1699                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1700                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1701         } else {
1702                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1703         }
1704
1705         /* Turn on send BD initiator state machine */
1706         val = BGE_SBDIMODE_ENABLE;
1707         if (sc->bnx_tx_ringcnt > 1)
1708                 val |= BGE_SBDIMODE_MULTI_TXR;
1709         CSR_WRITE_4(sc, BGE_SBDI_MODE, val);
1710
1711         /* Turn on send BD selector state machine */
1712         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1713
1714         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1715         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1716             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1717
1718         /* ack/clear link change events */
1719         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1720             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1721             BGE_MACSTAT_LINK_CHANGED);
1722         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1723
1724         /*
1725          * Enable attention when the link has changed state for
1726          * devices that use auto polling.
1727          */
1728         if (sc->bnx_flags & BNX_FLAG_TBI) {
1729                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1730         } else {
1731                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1732                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1733                         DELAY(80);
1734                 }
1735         }
1736
1737         /*
1738          * Clear any pending link state attention.
1739          * Otherwise some link state change events may be lost until attention
1740          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1741          * It's not necessary on newer BCM chips - perhaps enabling link
1742          * state change attentions implies clearing pending attention.
1743          */
1744         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1745             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1746             BGE_MACSTAT_LINK_CHANGED);
1747
1748         /* Enable link state change attentions. */
1749         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1750
1751         return(0);
1752 }
1753
1754 /*
1755  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1756  * against our list and return its name if we find a match. Note
1757  * that since the Broadcom controller contains VPD support, we
1758  * can get the device name string from the controller itself instead
1759  * of the compiled-in string. This is a little slow, but it guarantees
1760  * we'll always announce the right product name.
1761  */
1762 static int
1763 bnx_probe(device_t dev)
1764 {
1765         const struct bnx_type *t;
1766         uint16_t product, vendor;
1767
1768         if (!pci_is_pcie(dev))
1769                 return ENXIO;
1770
1771         product = pci_get_device(dev);
1772         vendor = pci_get_vendor(dev);
1773
1774         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1775                 if (vendor == t->bnx_vid && product == t->bnx_did)
1776                         break;
1777         }
1778         if (t->bnx_name == NULL)
1779                 return ENXIO;
1780
1781         device_set_desc(dev, t->bnx_name);
1782         return 0;
1783 }
1784
1785 static int
1786 bnx_attach(device_t dev)
1787 {
1788         struct ifnet *ifp;
1789         struct bnx_softc *sc;
1790         struct bnx_rx_std_ring *std;
1791         uint32_t hwcfg = 0;
1792         int error = 0, rid, capmask, i, std_cpuid, std_cpuid_def;
1793         uint8_t ether_addr[ETHER_ADDR_LEN];
1794         uint16_t product;
1795         uintptr_t mii_priv = 0;
1796 #if defined(BNX_TSO_DEBUG) || defined(BNX_RSS_DEBUG) || defined(BNX_TSS_DEBUG)
1797         char desc[32];
1798 #endif
1799 #ifdef IFPOLL_ENABLE
1800         int offset, offset_def;
1801 #endif
1802
1803         sc = device_get_softc(dev);
1804         sc->bnx_dev = dev;
1805         callout_init_mp(&sc->bnx_tick_timer);
1806         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1807         lwkt_serialize_init(&sc->bnx_main_serialize);
1808
1809         /* Always setup interrupt mailboxes */
1810         for (i = 0; i < BNX_INTR_MAX; ++i) {
1811                 callout_init_mp(&sc->bnx_intr_data[i].bnx_intr_timer);
1812                 sc->bnx_intr_data[i].bnx_sc = sc;
1813                 sc->bnx_intr_data[i].bnx_intr_mbx = BGE_MBX_IRQ0_LO + (i * 8);
1814                 sc->bnx_intr_data[i].bnx_intr_rid = -1;
1815                 sc->bnx_intr_data[i].bnx_intr_cpuid = -1;
1816         }
1817
1818         product = pci_get_device(dev);
1819
1820 #ifndef BURN_BRIDGES
1821         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1822                 uint32_t irq, mem;
1823
1824                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1825                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1826
1827                 device_printf(dev, "chip is in D%d power mode "
1828                     "-- setting to D0\n", pci_get_powerstate(dev));
1829
1830                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1831
1832                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1833                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1834         }
1835 #endif  /* !BURN_BRIDGE */
1836
1837         /*
1838          * Map control/status registers.
1839          */
1840         pci_enable_busmaster(dev);
1841
1842         rid = BGE_PCI_BAR0;
1843         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1844             RF_ACTIVE);
1845
1846         if (sc->bnx_res == NULL) {
1847                 device_printf(dev, "couldn't map memory\n");
1848                 return ENXIO;
1849         }
1850
1851         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1852         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1853
1854         /* Save various chip information */
1855         sc->bnx_chipid =
1856             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1857             BGE_PCIMISCCTL_ASICREV_SHIFT;
1858         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1859                 /* All chips having dedicated ASICREV register have CPMU */
1860                 sc->bnx_flags |= BNX_FLAG_CPMU;
1861
1862                 switch (product) {
1863                 case PCI_PRODUCT_BROADCOM_BCM5717:
1864                 case PCI_PRODUCT_BROADCOM_BCM5717C:
1865                 case PCI_PRODUCT_BROADCOM_BCM5718:
1866                 case PCI_PRODUCT_BROADCOM_BCM5719:
1867                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1868                 case PCI_PRODUCT_BROADCOM_BCM5725:
1869                 case PCI_PRODUCT_BROADCOM_BCM5727:
1870                 case PCI_PRODUCT_BROADCOM_BCM5762:
1871                         sc->bnx_chipid = pci_read_config(dev,
1872                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1873                         break;
1874
1875                 case PCI_PRODUCT_BROADCOM_BCM57761:
1876                 case PCI_PRODUCT_BROADCOM_BCM57762:
1877                 case PCI_PRODUCT_BROADCOM_BCM57765:
1878                 case PCI_PRODUCT_BROADCOM_BCM57766:
1879                 case PCI_PRODUCT_BROADCOM_BCM57781:
1880                 case PCI_PRODUCT_BROADCOM_BCM57782:
1881                 case PCI_PRODUCT_BROADCOM_BCM57785:
1882                 case PCI_PRODUCT_BROADCOM_BCM57786:
1883                 case PCI_PRODUCT_BROADCOM_BCM57791:
1884                 case PCI_PRODUCT_BROADCOM_BCM57795:
1885                         sc->bnx_chipid = pci_read_config(dev,
1886                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1887                         break;
1888
1889                 default:
1890                         sc->bnx_chipid = pci_read_config(dev,
1891                             BGE_PCI_PRODID_ASICREV, 4);
1892                         break;
1893                 }
1894         }
1895         if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1896                 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1897
1898         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1899         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1900
1901         switch (sc->bnx_asicrev) {
1902         case BGE_ASICREV_BCM5717:
1903         case BGE_ASICREV_BCM5719:
1904         case BGE_ASICREV_BCM5720:
1905                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1906                 break;
1907
1908         case BGE_ASICREV_BCM5762:
1909                 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1910                 break;
1911
1912         case BGE_ASICREV_BCM57765:
1913         case BGE_ASICREV_BCM57766:
1914                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1915                 break;
1916         }
1917
1918         sc->bnx_flags |= BNX_FLAG_TSO;
1919         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1920             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1921                 sc->bnx_flags &= ~BNX_FLAG_TSO;
1922
1923         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1924             BNX_IS_57765_FAMILY(sc)) {
1925                 /*
1926                  * All BCM57785 and BCM5718 families chips have a bug that
1927                  * under certain situation interrupt will not be enabled
1928                  * even if status tag is written to interrupt mailbox.
1929                  *
1930                  * While BCM5719 and BCM5720 have a hardware workaround
1931                  * which could fix the above bug.
1932                  * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1933                  * bnx_chipinit().
1934                  *
1935                  * For the rest of the chips in these two families, we will
1936                  * have to poll the status block at high rate (10ms currently)
1937                  * to check whether the interrupt is hosed or not.
1938                  * See bnx_check_intr_*() for details.
1939                  */
1940                 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1941         }
1942
1943         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1944         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1945             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1946                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1947         else
1948                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1949         device_printf(dev, "CHIP ID 0x%08x; "
1950                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1951                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1952
1953         /*
1954          * Set various PHY quirk flags.
1955          */
1956
1957         capmask = MII_CAPMASK_DEFAULT;
1958         if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1959             product == PCI_PRODUCT_BROADCOM_BCM57795) {
1960                 /* 10/100 only */
1961                 capmask &= ~BMSR_EXTSTAT;
1962         }
1963
1964         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1965         if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1966                 mii_priv |= BRGPHY_FLAG_5762_A0;
1967
1968         /* Initialize if_name earlier, so if_printf could be used */
1969         ifp = &sc->arpcom.ac_if;
1970         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1971
1972         /* Try to reset the chip. */
1973         bnx_reset(sc);
1974
1975         if (bnx_chipinit(sc)) {
1976                 device_printf(dev, "chip initialization failed\n");
1977                 error = ENXIO;
1978                 goto fail;
1979         }
1980
1981         /*
1982          * Get station address
1983          */
1984         error = bnx_get_eaddr(sc, ether_addr);
1985         if (error) {
1986                 device_printf(dev, "failed to read station address\n");
1987                 goto fail;
1988         }
1989
1990         /* Setup RX/TX and interrupt count */
1991         bnx_setup_ring_cnt(sc);
1992
1993         if ((sc->bnx_rx_retcnt == 1 && sc->bnx_tx_ringcnt == 1) ||
1994             (sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt > 1)) {
1995                 /*
1996                  * The RX ring and the corresponding TX ring processing
1997                  * should be on the same CPU, since they share the same
1998                  * status block.
1999                  */
2000                 sc->bnx_flags |= BNX_FLAG_RXTX_BUNDLE;
2001                 if (bootverbose)
2002                         device_printf(dev, "RX/TX bundle\n");
2003                 if (sc->bnx_tx_ringcnt > 1) {
2004                         /*
2005                          * Multiple TX rings do not share status block
2006                          * with link status, so link status will have
2007                          * to save its own status_tag.
2008                          */
2009                         sc->bnx_flags |= BNX_FLAG_STATUS_HASTAG;
2010                         if (bootverbose)
2011                                 device_printf(dev, "status needs tag\n");
2012                 }
2013         } else {
2014                 KKASSERT(sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt == 1);
2015                 if (bootverbose)
2016                         device_printf(dev, "RX/TX not bundled\n");
2017         }
2018
2019         error = bnx_dma_alloc(dev);
2020         if (error)
2021                 goto fail;
2022
2023 #ifdef IFPOLL_ENABLE
2024         if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2025                 /*
2026                  * NPOLLING RX/TX CPU offset
2027                  */
2028                 if (sc->bnx_rx_retcnt == ncpus2) {
2029                         offset = 0;
2030                 } else {
2031                         offset_def =
2032                         (sc->bnx_rx_retcnt * device_get_unit(dev)) % ncpus2;
2033                         offset = device_getenv_int(dev, "npoll.offset",
2034                             offset_def);
2035                         if (offset >= ncpus2 ||
2036                             offset % sc->bnx_rx_retcnt != 0) {
2037                                 device_printf(dev, "invalid npoll.offset %d, "
2038                                     "use %d\n", offset, offset_def);
2039                                 offset = offset_def;
2040                         }
2041                 }
2042                 sc->bnx_npoll_rxoff = offset;
2043                 sc->bnx_npoll_txoff = offset;
2044         } else {
2045                 /*
2046                  * NPOLLING RX CPU offset
2047                  */
2048                 if (sc->bnx_rx_retcnt == ncpus2) {
2049                         offset = 0;
2050                 } else {
2051                         offset_def =
2052                         (sc->bnx_rx_retcnt * device_get_unit(dev)) % ncpus2;
2053                         offset = device_getenv_int(dev, "npoll.rxoff",
2054                             offset_def);
2055                         if (offset >= ncpus2 ||
2056                             offset % sc->bnx_rx_retcnt != 0) {
2057                                 device_printf(dev, "invalid npoll.rxoff %d, "
2058                                     "use %d\n", offset, offset_def);
2059                                 offset = offset_def;
2060                         }
2061                 }
2062                 sc->bnx_npoll_rxoff = offset;
2063
2064                 /*
2065                  * NPOLLING TX CPU offset
2066                  */
2067                 offset_def = device_get_unit(dev) % ncpus2;
2068                 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
2069                 if (offset >= ncpus2) {
2070                         device_printf(dev, "invalid npoll.txoff %d, use %d\n",
2071                             offset, offset_def);
2072                         offset = offset_def;
2073                 }
2074                 sc->bnx_npoll_txoff = offset;
2075         }
2076 #endif  /* IFPOLL_ENABLE */
2077
2078         /*
2079          * Allocate interrupt
2080          */
2081         error = bnx_alloc_intr(sc);
2082         if (error)
2083                 goto fail;
2084
2085         /* Setup serializers */
2086         bnx_setup_serialize(sc);
2087
2088         /* Set default tuneable values. */
2089         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
2090         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
2091         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
2092         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
2093         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
2094         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
2095
2096         /* Set up ifnet structure */
2097         ifp->if_softc = sc;
2098         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2099         ifp->if_ioctl = bnx_ioctl;
2100         ifp->if_start = bnx_start;
2101 #ifdef IFPOLL_ENABLE
2102         ifp->if_npoll = bnx_npoll;
2103 #endif
2104         ifp->if_init = bnx_init;
2105         ifp->if_serialize = bnx_serialize;
2106         ifp->if_deserialize = bnx_deserialize;
2107         ifp->if_tryserialize = bnx_tryserialize;
2108 #ifdef INVARIANTS
2109         ifp->if_serialize_assert = bnx_serialize_assert;
2110 #endif
2111         ifp->if_mtu = ETHERMTU;
2112         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2113
2114         ifp->if_capabilities |= IFCAP_HWCSUM;
2115         ifp->if_hwassist = BNX_CSUM_FEATURES;
2116         if (sc->bnx_flags & BNX_FLAG_TSO) {
2117                 ifp->if_capabilities |= IFCAP_TSO;
2118                 ifp->if_hwassist |= CSUM_TSO;
2119         }
2120         if (BNX_RSS_ENABLED(sc))
2121                 ifp->if_capabilities |= IFCAP_RSS;
2122         ifp->if_capenable = ifp->if_capabilities;
2123
2124         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2125         ifq_set_ready(&ifp->if_snd);
2126         ifq_set_subq_cnt(&ifp->if_snd, sc->bnx_tx_ringcnt);
2127
2128         if (sc->bnx_tx_ringcnt > 1) {
2129                 ifp->if_mapsubq = ifq_mapsubq_mask;
2130                 ifq_set_subq_mask(&ifp->if_snd, sc->bnx_tx_ringcnt - 1);
2131         }
2132
2133         /*
2134          * Figure out what sort of media we have by checking the
2135          * hardware config word in the first 32k of NIC internal memory,
2136          * or fall back to examining the EEPROM if necessary.
2137          * Note: on some BCM5700 cards, this value appears to be unset.
2138          * If that's the case, we have to rely on identifying the NIC
2139          * by its PCI subsystem ID, as we do below for the SysKonnect
2140          * SK-9D41.
2141          */
2142         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2143                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2144         } else {
2145                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2146                                     sizeof(hwcfg))) {
2147                         device_printf(dev, "failed to read EEPROM\n");
2148                         error = ENXIO;
2149                         goto fail;
2150                 }
2151                 hwcfg = ntohl(hwcfg);
2152         }
2153
2154         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2155         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2156             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2157                 sc->bnx_flags |= BNX_FLAG_TBI;
2158
2159         /* Setup MI MODE */
2160         if (sc->bnx_flags & BNX_FLAG_CPMU)
2161                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
2162         else
2163                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
2164
2165         /* Setup link status update stuffs */
2166         if (sc->bnx_flags & BNX_FLAG_TBI) {
2167                 sc->bnx_link_upd = bnx_tbi_link_upd;
2168                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2169         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
2170                 sc->bnx_link_upd = bnx_autopoll_link_upd;
2171                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2172         } else {
2173                 sc->bnx_link_upd = bnx_copper_link_upd;
2174                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2175         }
2176
2177         /* Set default PHY address */
2178         sc->bnx_phyno = 1;
2179
2180         /*
2181          * PHY address mapping for various devices.
2182          *
2183          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2184          * ---------+-------+-------+-------+-------+
2185          * BCM57XX  |   1   |   X   |   X   |   X   |
2186          * BCM5704  |   1   |   X   |   1   |   X   |
2187          * BCM5717  |   1   |   8   |   2   |   9   |
2188          * BCM5719  |   1   |   8   |   2   |   9   |
2189          * BCM5720  |   1   |   8   |   2   |   9   |
2190          *
2191          * Other addresses may respond but they are not
2192          * IEEE compliant PHYs and should be ignored.
2193          */
2194         if (BNX_IS_5717_PLUS(sc)) {
2195                 int f;
2196
2197                 f = pci_get_function(dev);
2198                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
2199                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2200                             BGE_SGDIGSTS_IS_SERDES)
2201                                 sc->bnx_phyno = f + 8;
2202                         else
2203                                 sc->bnx_phyno = f + 1;
2204                 } else {
2205                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2206                             BGE_CPMU_PHY_STRAP_IS_SERDES)
2207                                 sc->bnx_phyno = f + 8;
2208                         else
2209                                 sc->bnx_phyno = f + 1;
2210                 }
2211         }
2212
2213         if (sc->bnx_flags & BNX_FLAG_TBI) {
2214                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
2215                     bnx_ifmedia_upd, bnx_ifmedia_sts);
2216                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2217                 ifmedia_add(&sc->bnx_ifmedia,
2218                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2219                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2220                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2221                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2222         } else {
2223                 struct mii_probe_args mii_args;
2224
2225                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2226                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2227                 mii_args.mii_capmask = capmask;
2228                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2229                 mii_args.mii_priv = mii_priv;
2230
2231                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2232                 if (error) {
2233                         device_printf(dev, "MII without any PHY!\n");
2234                         goto fail;
2235                 }
2236         }
2237
2238         /*
2239          * Create sysctl nodes.
2240          */
2241         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2242         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2243                                               SYSCTL_STATIC_CHILDREN(_hw),
2244                                               OID_AUTO,
2245                                               device_get_nameunit(dev),
2246                                               CTLFLAG_RD, 0, "");
2247         if (sc->bnx_sysctl_tree == NULL) {
2248                 device_printf(dev, "can't add sysctl node\n");
2249                 error = ENXIO;
2250                 goto fail;
2251         }
2252
2253         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2254             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2255             "rx_rings", CTLFLAG_RD, &sc->bnx_rx_retcnt, 0, "# of RX rings");
2256         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2257             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2258             "tx_rings", CTLFLAG_RD, &sc->bnx_tx_ringcnt, 0, "# of TX rings");
2259
2260         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2261                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2262                         OID_AUTO, "rx_coal_ticks",
2263                         CTLTYPE_INT | CTLFLAG_RW,
2264                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2265                         "Receive coalescing ticks (usec).");
2266         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2267                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2268                         OID_AUTO, "tx_coal_ticks",
2269                         CTLTYPE_INT | CTLFLAG_RW,
2270                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2271                         "Transmit coalescing ticks (usec).");
2272         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2273                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2274                         OID_AUTO, "rx_coal_bds",
2275                         CTLTYPE_INT | CTLFLAG_RW,
2276                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2277                         "Receive max coalesced BD count.");
2278         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2279                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2280                         OID_AUTO, "tx_coal_bds",
2281                         CTLTYPE_INT | CTLFLAG_RW,
2282                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2283                         "Transmit max coalesced BD count.");
2284         /*
2285          * A common design characteristic for many Broadcom
2286          * client controllers is that they only support a
2287          * single outstanding DMA read operation on the PCIe
2288          * bus. This means that it will take twice as long to
2289          * fetch a TX frame that is split into header and
2290          * payload buffers as it does to fetch a single,
2291          * contiguous TX frame (2 reads vs. 1 read). For these
2292          * controllers, coalescing buffers to reduce the number
2293          * of memory reads is effective way to get maximum
2294          * performance(about 940Mbps).  Without collapsing TX
2295          * buffers the maximum TCP bulk transfer performance
2296          * is about 850Mbps. However forcing coalescing mbufs
2297          * consumes a lot of CPU cycles, so leave it off by
2298          * default.
2299          */
2300         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2301             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2302             "force_defrag", CTLTYPE_INT | CTLFLAG_RW,
2303             sc, 0, bnx_sysctl_force_defrag, "I",
2304             "Force defragment on TX path");
2305
2306         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2307             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2308             "tx_wreg", CTLTYPE_INT | CTLFLAG_RW,
2309             sc, 0, bnx_sysctl_tx_wreg, "I",
2310             "# of segments before writing to hardware register");
2311
2312         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2313             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2314             "std_refill", CTLTYPE_INT | CTLFLAG_RW,
2315             sc, 0, bnx_sysctl_std_refill, "I",
2316             "# of packets received before scheduling standard refilling");
2317
2318         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2319             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2320             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2321             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2322             "Receive max coalesced BD count during interrupt.");
2323         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2324             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2325             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2326             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2327             "Transmit max coalesced BD count during interrupt.");
2328
2329 #ifdef IFPOLL_ENABLE
2330         if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2331                 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2332                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2333                     "npoll_offset", CTLTYPE_INT | CTLFLAG_RW,
2334                     sc, 0, bnx_sysctl_npoll_offset, "I",
2335                     "NPOLLING cpu offset");
2336         } else {
2337                 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2338                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2339                     "npoll_rxoff", CTLTYPE_INT | CTLFLAG_RW,
2340                     sc, 0, bnx_sysctl_npoll_rxoff, "I",
2341                     "NPOLLING RX cpu offset");
2342                 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2343                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2344                     "npoll_txoff", CTLTYPE_INT | CTLFLAG_RW,
2345                     sc, 0, bnx_sysctl_npoll_txoff, "I",
2346                     "NPOLLING TX cpu offset");
2347         }
2348 #endif
2349
2350 #ifdef BNX_RSS_DEBUG
2351         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2352             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2353             "std_refill_mask", CTLFLAG_RD,
2354             &sc->bnx_rx_std_ring.bnx_rx_std_refill, 0, "");
2355         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2356             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2357             "rss_debug", CTLFLAG_RW, &sc->bnx_rss_debug, 0, "");
2358         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
2359                 ksnprintf(desc, sizeof(desc), "rx_pkt%d", i);
2360                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2361                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2362                     desc, CTLFLAG_RW, &sc->bnx_rx_ret_ring[i].bnx_rx_pkt, "");
2363         }
2364 #endif
2365 #ifdef BNX_TSS_DEBUG
2366         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2367                 ksnprintf(desc, sizeof(desc), "tx_pkt%d", i);
2368                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2369                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2370                     desc, CTLFLAG_RW, &sc->bnx_tx_ring[i].bnx_tx_pkt, "");
2371         }
2372 #endif
2373
2374         SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2375             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2376             "norxbds", CTLFLAG_RW, &sc->bnx_norxbds, "");
2377
2378         SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2379             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2380             "errors", CTLFLAG_RW, &sc->bnx_errors, "");
2381
2382 #ifdef BNX_TSO_DEBUG
2383         for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2384                 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2385                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2386                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2387                     desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2388         }
2389 #endif
2390
2391         /*
2392          * Call MI attach routine.
2393          */
2394         ether_ifattach(ifp, ether_addr, NULL);
2395
2396         /* Setup TX rings and subqueues */
2397         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2398                 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2399                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
2400
2401                 ifsq_set_cpuid(ifsq, txr->bnx_tx_cpuid);
2402                 ifsq_set_hw_serialize(ifsq, &txr->bnx_tx_serialize);
2403                 ifsq_set_priv(ifsq, txr);
2404                 txr->bnx_ifsq = ifsq;
2405
2406                 ifsq_watchdog_init(&txr->bnx_tx_watchdog, ifsq, bnx_watchdog);
2407
2408                 if (bootverbose) {
2409                         device_printf(dev, "txr %d -> cpu%d\n", i,
2410                             txr->bnx_tx_cpuid);
2411                 }
2412         }
2413
2414         error = bnx_setup_intr(sc);
2415         if (error) {
2416                 ether_ifdetach(ifp);
2417                 goto fail;
2418         }
2419         bnx_set_tick_cpuid(sc, FALSE);
2420
2421         /*
2422          * Create RX standard ring refilling thread
2423          */
2424         std_cpuid_def = device_get_unit(dev) % ncpus;
2425         std_cpuid = device_getenv_int(dev, "std.cpuid", std_cpuid_def);
2426         if (std_cpuid < 0 || std_cpuid >= ncpus) {
2427                 device_printf(dev, "invalid std.cpuid %d, use %d\n",
2428                     std_cpuid, std_cpuid_def);
2429                 std_cpuid = std_cpuid_def;
2430         }
2431
2432         std = &sc->bnx_rx_std_ring;
2433         lwkt_create(bnx_rx_std_refill_ithread, std, NULL,
2434             &std->bnx_rx_std_ithread, TDF_NOSTART | TDF_INTTHREAD, std_cpuid,
2435             "%s std", device_get_nameunit(dev));
2436         lwkt_setpri(&std->bnx_rx_std_ithread, TDPRI_INT_MED);
2437         std->bnx_rx_std_ithread.td_preemptable = lwkt_preempt;
2438         sc->bnx_flags |= BNX_FLAG_STD_THREAD;
2439
2440         return(0);
2441 fail:
2442         bnx_detach(dev);
2443         return(error);
2444 }
2445
2446 static int
2447 bnx_detach(device_t dev)
2448 {
2449         struct bnx_softc *sc = device_get_softc(dev);
2450
2451         if (device_is_attached(dev)) {
2452                 struct ifnet *ifp = &sc->arpcom.ac_if;
2453
2454                 ifnet_serialize_all(ifp);
2455                 bnx_stop(sc);
2456                 bnx_reset(sc);
2457                 bnx_teardown_intr(sc, sc->bnx_intr_cnt);
2458                 ifnet_deserialize_all(ifp);
2459
2460                 ether_ifdetach(ifp);
2461         }
2462
2463         if (sc->bnx_flags & BNX_FLAG_STD_THREAD) {
2464                 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
2465
2466                 tsleep_interlock(std, 0);
2467
2468                 if (std->bnx_rx_std_ithread.td_gd == mycpu) {
2469                         bnx_rx_std_refill_stop(std);
2470                 } else {
2471                         lwkt_send_ipiq(std->bnx_rx_std_ithread.td_gd,
2472                             bnx_rx_std_refill_stop, std);
2473                 }
2474
2475                 tsleep(std, PINTERLOCKED, "bnx_detach", 0);
2476                 if (bootverbose)
2477                         device_printf(dev, "RX std ithread exited\n");
2478
2479                 lwkt_synchronize_ipiqs("bnx_detach_ipiq");
2480         }
2481
2482         if (sc->bnx_flags & BNX_FLAG_TBI)
2483                 ifmedia_removeall(&sc->bnx_ifmedia);
2484         if (sc->bnx_miibus)
2485                 device_delete_child(dev, sc->bnx_miibus);
2486         bus_generic_detach(dev);
2487
2488         bnx_free_intr(sc);
2489
2490         if (sc->bnx_msix_mem_res != NULL) {
2491                 bus_release_resource(dev, SYS_RES_MEMORY, sc->bnx_msix_mem_rid,
2492                     sc->bnx_msix_mem_res);
2493         }
2494         if (sc->bnx_res != NULL) {
2495                 bus_release_resource(dev, SYS_RES_MEMORY,
2496                     BGE_PCI_BAR0, sc->bnx_res);
2497         }
2498
2499         if (sc->bnx_sysctl_tree != NULL)
2500                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2501
2502         bnx_dma_free(sc);
2503
2504         if (sc->bnx_serialize != NULL)
2505                 kfree(sc->bnx_serialize, M_DEVBUF);
2506
2507         return 0;
2508 }
2509
2510 static void
2511 bnx_reset(struct bnx_softc *sc)
2512 {
2513         device_t dev;
2514         uint32_t cachesize, command, pcistate, reset;
2515         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2516         int i, val = 0;
2517         uint16_t devctl;
2518
2519         dev = sc->bnx_dev;
2520
2521         write_op = bnx_writemem_direct;
2522
2523         /* Save some important PCI state. */
2524         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2525         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2526         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2527
2528         pci_write_config(dev, BGE_PCI_MISC_CTL,
2529             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2530             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2531             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2532
2533         /* Disable fastboot on controllers that support it. */
2534         if (bootverbose)
2535                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2536         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2537
2538         /*
2539          * Write the magic number to SRAM at offset 0xB50.
2540          * When firmware finishes its initialization it will
2541          * write ~BGE_MAGIC_NUMBER to the same location.
2542          */
2543         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2544
2545         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2546
2547         /* XXX: Broadcom Linux driver. */
2548         /* Force PCI-E 1.0a mode */
2549         if (!BNX_IS_57765_PLUS(sc) &&
2550             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2551             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2552              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2553                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2554                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2555         }
2556         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2557                 /* Prevent PCIE link training during global reset */
2558                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2559                 reset |= (1<<29);
2560         }
2561
2562         /*
2563          * Set GPHY Power Down Override to leave GPHY
2564          * powered up in D0 uninitialized.
2565          */
2566         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2567                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2568
2569         /* Issue global reset */
2570         write_op(sc, BGE_MISC_CFG, reset);
2571
2572         DELAY(1000);
2573
2574         /* XXX: Broadcom Linux driver. */
2575         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2576                 uint32_t v;
2577
2578                 DELAY(500000); /* wait for link training to complete */
2579                 v = pci_read_config(dev, 0xc4, 4);
2580                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2581         }
2582
2583         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2584
2585         /* Disable no snoop and disable relaxed ordering. */
2586         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2587
2588         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2589         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2590                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2591                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2592         }
2593
2594         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2595             devctl, 2);
2596
2597         /* Clear error status. */
2598         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2599             PCIEM_DEVSTS_CORR_ERR |
2600             PCIEM_DEVSTS_NFATAL_ERR |
2601             PCIEM_DEVSTS_FATAL_ERR |
2602             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2603
2604         /* Reset some of the PCI state that got zapped by reset */
2605         pci_write_config(dev, BGE_PCI_MISC_CTL,
2606             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2607             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2608             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2609         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2610         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2611         write_op(sc, BGE_MISC_CFG, (65 << 1));
2612
2613         /* Enable memory arbiter */
2614         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2615
2616         /*
2617          * Poll until we see the 1's complement of the magic number.
2618          * This indicates that the firmware initialization is complete.
2619          */
2620         for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2621                 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2622                 if (val == ~BGE_MAGIC_NUMBER)
2623                         break;
2624                 DELAY(10);
2625         }
2626         if (i == BNX_FIRMWARE_TIMEOUT) {
2627                 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2628                           "timed out, found 0x%08x\n", val);
2629         }
2630
2631         /* BCM57765 A0 needs additional time before accessing. */
2632         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2633                 DELAY(10 * 1000);
2634
2635         /*
2636          * XXX Wait for the value of the PCISTATE register to
2637          * return to its original pre-reset state. This is a
2638          * fairly good indicator of reset completion. If we don't
2639          * wait for the reset to fully complete, trying to read
2640          * from the device's non-PCI registers may yield garbage
2641          * results.
2642          */
2643         for (i = 0; i < BNX_TIMEOUT; i++) {
2644                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2645                         break;
2646                 DELAY(10);
2647         }
2648
2649         /* Fix up byte swapping */
2650         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2651
2652         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2653
2654         /*
2655          * The 5704 in TBI mode apparently needs some special
2656          * adjustment to insure the SERDES drive level is set
2657          * to 1.2V.
2658          */
2659         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2660             (sc->bnx_flags & BNX_FLAG_TBI)) {
2661                 uint32_t serdescfg;
2662
2663                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2664                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2665                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2666         }
2667
2668         CSR_WRITE_4(sc, BGE_MI_MODE,
2669             sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2670         DELAY(80);
2671
2672         /* XXX: Broadcom Linux driver. */
2673         if (!BNX_IS_57765_PLUS(sc)) {
2674                 uint32_t v;
2675
2676                 /* Enable Data FIFO protection. */
2677                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2678                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2679         }
2680
2681         DELAY(10000);
2682
2683         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2684                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2685                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2686         }
2687 }
2688
2689 /*
2690  * Frame reception handling. This is called if there's a frame
2691  * on the receive return list.
2692  *
2693  * Note: we have to be able to handle two possibilities here:
2694  * 1) the frame is from the jumbo recieve ring
2695  * 2) the frame is from the standard receive ring
2696  */
2697
2698 static void
2699 bnx_rxeof(struct bnx_rx_ret_ring *ret, uint16_t rx_prod, int count)
2700 {
2701         struct bnx_softc *sc = ret->bnx_sc;
2702         struct bnx_rx_std_ring *std = ret->bnx_std;
2703         struct ifnet *ifp = &sc->arpcom.ac_if;
2704
2705         while (ret->bnx_rx_saved_considx != rx_prod && count != 0) {
2706                 struct pktinfo pi0, *pi = NULL;
2707                 struct bge_rx_bd *cur_rx;
2708                 struct bnx_rx_buf *rb;
2709                 uint32_t rxidx;
2710                 struct mbuf *m = NULL;
2711                 uint16_t vlan_tag = 0;
2712                 int have_tag = 0;
2713
2714                 --count;
2715
2716                 cur_rx = &ret->bnx_rx_ret_ring[ret->bnx_rx_saved_considx];
2717
2718                 rxidx = cur_rx->bge_idx;
2719                 KKASSERT(rxidx < BGE_STD_RX_RING_CNT);
2720
2721                 BNX_INC(ret->bnx_rx_saved_considx, BNX_RETURN_RING_CNT);
2722 #ifdef BNX_RSS_DEBUG
2723                 ret->bnx_rx_pkt++;
2724 #endif
2725
2726                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2727                         have_tag = 1;
2728                         vlan_tag = cur_rx->bge_vlan_tag;
2729                 }
2730
2731                 if (ret->bnx_rx_cnt >= ret->bnx_rx_cntmax)
2732                         bnx_rx_std_refill_sched(ret, std);
2733                 ret->bnx_rx_cnt++;
2734
2735                 rb = &std->bnx_rx_std_buf[rxidx];
2736                 m = rb->bnx_rx_mbuf;
2737                 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2738                         IFNET_STAT_INC(ifp, ierrors, 1);
2739                         cpu_sfence();
2740                         rb->bnx_rx_refilled = 1;
2741                         continue;
2742                 }
2743                 if (bnx_newbuf_std(ret, rxidx, 0)) {
2744                         IFNET_STAT_INC(ifp, ierrors, 1);
2745                         continue;
2746                 }
2747
2748                 IFNET_STAT_INC(ifp, ipackets, 1);
2749                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2750                 m->m_pkthdr.rcvif = ifp;
2751
2752                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2753                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2754                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2755                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2756                                 if ((cur_rx->bge_error_flag &
2757                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2758                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2759                         }
2760                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2761                                 m->m_pkthdr.csum_data =
2762                                     cur_rx->bge_tcp_udp_csum;
2763                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2764                                     CSUM_PSEUDO_HDR;
2765                         }
2766                 }
2767                 if (ifp->if_capenable & IFCAP_RSS) {
2768                         pi = bnx_rss_info(&pi0, cur_rx);
2769                         if (pi != NULL &&
2770                             (cur_rx->bge_flags & BGE_RXBDFLAG_RSS_HASH)) {
2771                                 m->m_flags |= M_HASH;
2772                                 m->m_pkthdr.hash =
2773                                     toeplitz_hash(cur_rx->bge_hash);
2774                         }
2775                 }
2776
2777                 /*
2778                  * If we received a packet with a vlan tag, pass it
2779                  * to vlan_input() instead of ether_input().
2780                  */
2781                 if (have_tag) {
2782                         m->m_flags |= M_VLANTAG;
2783                         m->m_pkthdr.ether_vlantag = vlan_tag;
2784                 }
2785                 ether_input_pkt(ifp, m, pi);
2786         }
2787         bnx_writembx(sc, ret->bnx_rx_mbx, ret->bnx_rx_saved_considx);
2788
2789         if (ret->bnx_rx_cnt > 0)
2790                 bnx_rx_std_refill_sched(ret, std);
2791 }
2792
2793 static void
2794 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons)
2795 {
2796         struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if;
2797
2798         /*
2799          * Go through our tx ring and free mbufs for those
2800          * frames that have been sent.
2801          */
2802         while (txr->bnx_tx_saved_considx != tx_cons) {
2803                 struct bnx_tx_buf *buf;
2804                 uint32_t idx = 0;
2805
2806                 idx = txr->bnx_tx_saved_considx;
2807                 buf = &txr->bnx_tx_buf[idx];
2808                 if (buf->bnx_tx_mbuf != NULL) {
2809                         IFNET_STAT_INC(ifp, opackets, 1);
2810 #ifdef BNX_TSS_DEBUG
2811                         txr->bnx_tx_pkt++;
2812 #endif
2813                         bus_dmamap_unload(txr->bnx_tx_mtag,
2814                             buf->bnx_tx_dmamap);
2815                         m_freem(buf->bnx_tx_mbuf);
2816                         buf->bnx_tx_mbuf = NULL;
2817                 }
2818                 txr->bnx_tx_cnt--;
2819                 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2820         }
2821
2822         if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) >=
2823             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2824                 ifsq_clr_oactive(txr->bnx_ifsq);
2825
2826         if (txr->bnx_tx_cnt == 0)
2827                 txr->bnx_tx_watchdog.wd_timer = 0;
2828
2829         if (!ifsq_is_empty(txr->bnx_ifsq))
2830                 ifsq_devstart(txr->bnx_ifsq);
2831 }
2832
2833 static void
2834 bnx_handle_status(struct bnx_softc *sc)
2835 {
2836         uint32_t status;
2837
2838         status = *sc->bnx_hw_status;
2839
2840         if (status & BGE_STATFLAG_ERROR) {
2841                 uint32_t val;
2842                 int reset = 0;
2843
2844                 sc->bnx_errors++;
2845
2846                 val = CSR_READ_4(sc, BGE_FLOW_ATTN);
2847                 if (val & ~BGE_FLOWATTN_MB_LOWAT) {
2848                         if_printf(&sc->arpcom.ac_if,
2849                             "flow attn 0x%08x\n", val);
2850                         reset = 1;
2851                 }
2852
2853                 val = CSR_READ_4(sc, BGE_MSI_STATUS);
2854                 if (val & ~BGE_MSISTAT_MSI_PCI_REQ) {
2855                         if_printf(&sc->arpcom.ac_if,
2856                             "msi status 0x%08x\n", val);
2857                         reset = 1;
2858                 }
2859
2860                 val = CSR_READ_4(sc, BGE_RDMA_STATUS);
2861                 if (val) {
2862                         if_printf(&sc->arpcom.ac_if,
2863                             "rmda status 0x%08x\n", val);
2864                         reset = 1;
2865                 }
2866
2867                 val = CSR_READ_4(sc, BGE_WDMA_STATUS);
2868                 if (val) {
2869                         if_printf(&sc->arpcom.ac_if,
2870                             "wdma status 0x%08x\n", val);
2871                         reset = 1;
2872                 }
2873
2874                 if (reset) {
2875                         bnx_serialize_skipmain(sc);
2876                         bnx_init(sc);
2877                         bnx_deserialize_skipmain(sc);
2878                 }
2879         }
2880
2881         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2882                 bnx_link_poll(sc);
2883 }
2884
2885 #ifdef IFPOLL_ENABLE
2886
2887 static void
2888 bnx_npoll_rx(struct ifnet *ifp __unused, void *xret, int cycle)
2889 {
2890         struct bnx_rx_ret_ring *ret = xret;
2891         uint16_t rx_prod;
2892
2893         ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
2894
2895         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
2896         cpu_lfence();
2897
2898         rx_prod = *ret->bnx_rx_considx;
2899         if (ret->bnx_rx_saved_considx != rx_prod)
2900                 bnx_rxeof(ret, rx_prod, cycle);
2901 }
2902
2903 static void
2904 bnx_npoll_tx_notag(struct ifnet *ifp __unused, void *xtxr, int cycle __unused)
2905 {
2906         struct bnx_tx_ring *txr = xtxr;
2907         uint16_t tx_cons;
2908
2909         ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
2910
2911         tx_cons = *txr->bnx_tx_considx;
2912         if (txr->bnx_tx_saved_considx != tx_cons)
2913                 bnx_txeof(txr, tx_cons);
2914 }
2915
2916 static void
2917 bnx_npoll_tx(struct ifnet *ifp, void *xtxr, int cycle)
2918 {
2919         struct bnx_tx_ring *txr = xtxr;
2920
2921         ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
2922
2923         txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag;
2924         cpu_lfence();
2925         bnx_npoll_tx_notag(ifp, txr, cycle);
2926 }
2927
2928 static void
2929 bnx_npoll_status_notag(struct ifnet *ifp)
2930 {
2931         struct bnx_softc *sc = ifp->if_softc;
2932
2933         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
2934
2935         bnx_handle_status(sc);
2936 }
2937
2938 static void
2939 bnx_npoll_status(struct ifnet *ifp)
2940 {
2941         struct bnx_softc *sc = ifp->if_softc;
2942
2943         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
2944
2945         sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag;
2946         cpu_lfence();
2947         bnx_npoll_status_notag(ifp);
2948 }
2949
2950 static void
2951 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2952 {
2953         struct bnx_softc *sc = ifp->if_softc;
2954         int i;
2955
2956         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2957
2958         if (info != NULL) {
2959                 if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG)
2960                         info->ifpi_status.status_func = bnx_npoll_status;
2961                 else
2962                         info->ifpi_status.status_func = bnx_npoll_status_notag;
2963                 info->ifpi_status.serializer = &sc->bnx_main_serialize;
2964
2965                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2966                         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
2967                         int idx = i + sc->bnx_npoll_txoff;
2968
2969                         KKASSERT(idx < ncpus2);
2970                         if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2971                                 info->ifpi_tx[idx].poll_func =
2972                                     bnx_npoll_tx_notag;
2973                         } else {
2974                                 info->ifpi_tx[idx].poll_func = bnx_npoll_tx;
2975                         }
2976                         info->ifpi_tx[idx].arg = txr;
2977                         info->ifpi_tx[idx].serializer = &txr->bnx_tx_serialize;
2978                         ifsq_set_cpuid(txr->bnx_ifsq, idx);
2979                 }
2980
2981                 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
2982                         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
2983                         int idx = i + sc->bnx_npoll_rxoff;
2984
2985                         KKASSERT(idx < ncpus2);
2986                         info->ifpi_rx[idx].poll_func = bnx_npoll_rx;
2987                         info->ifpi_rx[idx].arg = ret;
2988                         info->ifpi_rx[idx].serializer =
2989                             &ret->bnx_rx_ret_serialize;
2990                 }
2991
2992                 if (ifp->if_flags & IFF_RUNNING) {
2993                         bnx_disable_intr(sc);
2994                         bnx_set_tick_cpuid(sc, TRUE);
2995                 }
2996         } else {
2997                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2998                         ifsq_set_cpuid(sc->bnx_tx_ring[i].bnx_ifsq,
2999                             sc->bnx_tx_ring[i].bnx_tx_cpuid);
3000                 }
3001                 if (ifp->if_flags & IFF_RUNNING) {
3002                         bnx_enable_intr(sc);
3003                         bnx_set_tick_cpuid(sc, FALSE);
3004                 }
3005         }
3006 }
3007
3008 #endif  /* IFPOLL_ENABLE */
3009
3010 static void
3011 bnx_intr_legacy(void *xsc)
3012 {
3013         struct bnx_softc *sc = xsc;
3014         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
3015
3016         if (ret->bnx_saved_status_tag == *ret->bnx_hw_status_tag) {
3017                 uint32_t val;
3018
3019                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
3020                 if (val & BGE_PCISTAT_INTR_NOTACT)
3021                         return;
3022         }
3023
3024         /*
3025          * NOTE:
3026          * Interrupt will have to be disabled if tagged status
3027          * is used, else interrupt will always be asserted on
3028          * certain chips (at least on BCM5750 AX/BX).
3029          */
3030         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3031
3032         bnx_intr(sc);
3033 }
3034
3035 static void
3036 bnx_msi(void *xsc)
3037 {
3038         bnx_intr(xsc);
3039 }
3040
3041 static void
3042 bnx_intr(struct bnx_softc *sc)
3043 {
3044         struct ifnet *ifp = &sc->arpcom.ac_if;
3045         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
3046
3047         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3048
3049         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3050         /*
3051          * Use a load fence to ensure that status_tag is saved
3052          * before rx_prod, tx_cons and status.
3053          */
3054         cpu_lfence();
3055
3056         bnx_handle_status(sc);
3057
3058         if (ifp->if_flags & IFF_RUNNING) {
3059                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
3060                 uint16_t rx_prod, tx_cons;
3061
3062                 lwkt_serialize_enter(&ret->bnx_rx_ret_serialize);
3063                 rx_prod = *ret->bnx_rx_considx;
3064                 if (ret->bnx_rx_saved_considx != rx_prod)
3065                         bnx_rxeof(ret, rx_prod, -1);
3066                 lwkt_serialize_exit(&ret->bnx_rx_ret_serialize);
3067
3068                 lwkt_serialize_enter(&txr->bnx_tx_serialize);
3069                 tx_cons = *txr->bnx_tx_considx;
3070                 if (txr->bnx_tx_saved_considx != tx_cons)
3071                         bnx_txeof(txr, tx_cons);
3072                 lwkt_serialize_exit(&txr->bnx_tx_serialize);
3073         }
3074
3075         bnx_writembx(sc, BGE_MBX_IRQ0_LO, ret->bnx_saved_status_tag << 24);
3076 }
3077
3078 static void
3079 bnx_msix_tx_status(void *xtxr)
3080 {
3081         struct bnx_tx_ring *txr = xtxr;
3082         struct bnx_softc *sc = txr->bnx_sc;
3083         struct ifnet *ifp = &sc->arpcom.ac_if;
3084
3085         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3086
3087         txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag;
3088         /*
3089          * Use a load fence to ensure that status_tag is saved
3090          * before tx_cons and status.
3091          */
3092         cpu_lfence();
3093
3094         bnx_handle_status(sc);
3095
3096         if (ifp->if_flags & IFF_RUNNING) {
3097                 uint16_t tx_cons;
3098
3099                 lwkt_serialize_enter(&txr->bnx_tx_serialize);
3100                 tx_cons = *txr->bnx_tx_considx;
3101                 if (txr->bnx_tx_saved_considx != tx_cons)
3102                         bnx_txeof(txr, tx_cons);
3103                 lwkt_serialize_exit(&txr->bnx_tx_serialize);
3104         }
3105
3106         bnx_writembx(sc, BGE_MBX_IRQ0_LO, txr->bnx_saved_status_tag << 24);
3107 }
3108
3109 static void
3110 bnx_msix_rx(void *xret)
3111 {
3112         struct bnx_rx_ret_ring *ret = xret;
3113         uint16_t rx_prod;
3114
3115         ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
3116
3117         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3118         /*
3119          * Use a load fence to ensure that status_tag is saved
3120          * before rx_prod.
3121          */
3122         cpu_lfence();
3123
3124         rx_prod = *ret->bnx_rx_considx;
3125         if (ret->bnx_rx_saved_considx != rx_prod)
3126                 bnx_rxeof(ret, rx_prod, -1);
3127
3128         bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx,
3129             ret->bnx_saved_status_tag << 24);
3130 }
3131
3132 static void
3133 bnx_msix_rxtx(void *xret)
3134 {
3135         struct bnx_rx_ret_ring *ret = xret;
3136         struct bnx_tx_ring *txr = ret->bnx_txr;
3137         uint16_t rx_prod, tx_cons;
3138
3139         ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
3140
3141         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3142         /*
3143          * Use a load fence to ensure that status_tag is saved
3144          * before rx_prod and tx_cons.
3145          */
3146         cpu_lfence();
3147
3148         rx_prod = *ret->bnx_rx_considx;
3149         if (ret->bnx_rx_saved_considx != rx_prod)
3150                 bnx_rxeof(ret, rx_prod, -1);
3151
3152         lwkt_serialize_enter(&txr->bnx_tx_serialize);
3153         tx_cons = *txr->bnx_tx_considx;
3154         if (txr->bnx_tx_saved_considx != tx_cons)
3155                 bnx_txeof(txr, tx_cons);
3156         lwkt_serialize_exit(&txr->bnx_tx_serialize);
3157
3158         bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx,
3159             ret->bnx_saved_status_tag << 24);
3160 }
3161
3162 static void
3163 bnx_msix_status(void *xsc)
3164 {
3165         struct bnx_softc *sc = xsc;
3166
3167         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3168
3169         sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag;
3170         /*
3171          * Use a load fence to ensure that status_tag is saved
3172          * before status.
3173          */
3174         cpu_lfence();
3175
3176         bnx_handle_status(sc);
3177
3178         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_saved_status_tag << 24);
3179 }
3180
3181 static void
3182 bnx_tick(void *xsc)
3183 {
3184         struct bnx_softc *sc = xsc;
3185
3186         lwkt_serialize_enter(&sc->bnx_main_serialize);
3187
3188         bnx_stats_update_regs(sc);
3189
3190         if (sc->bnx_flags & BNX_FLAG_TBI) {
3191                 /*
3192                  * Since in TBI mode auto-polling can't be used we should poll
3193                  * link status manually. Here we register pending link event
3194                  * and trigger interrupt.
3195                  */
3196                 sc->bnx_link_evt++;
3197                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3198         } else if (!sc->bnx_link) {
3199                 mii_tick(device_get_softc(sc->bnx_miibus));
3200         }
3201
3202         callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc,
3203             sc->bnx_tick_cpuid);
3204
3205         lwkt_serialize_exit(&sc->bnx_main_serialize);
3206 }
3207
3208 static void
3209 bnx_stats_update_regs(struct bnx_softc *sc)
3210 {
3211         struct ifnet *ifp = &sc->arpcom.ac_if;
3212         struct bge_mac_stats_regs stats;
3213         uint32_t *s, val;
3214         int i;
3215
3216         s = (uint32_t *)&stats;
3217         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3218                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3219                 s++;
3220         }
3221
3222         IFNET_STAT_SET(ifp, collisions,
3223            (stats.dot3StatsSingleCollisionFrames +
3224            stats.dot3StatsMultipleCollisionFrames +
3225            stats.dot3StatsExcessiveCollisions +
3226            stats.dot3StatsLateCollisions));
3227
3228         val = CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3229         sc->bnx_norxbds += val;
3230 }
3231
3232 /*
3233  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3234  * pointers to descriptors.
3235  */
3236 static int
3237 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx,
3238     int *segs_used)
3239 {
3240         struct bge_tx_bd *d = NULL;
3241         uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
3242         bus_dma_segment_t segs[BNX_NSEG_NEW];
3243         bus_dmamap_t map;
3244         int error, maxsegs, nsegs, idx, i;
3245         struct mbuf *m_head = *m_head0, *m_new;
3246
3247         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3248 #ifdef BNX_TSO_DEBUG
3249                 int tso_nsegs;
3250 #endif
3251
3252                 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags);
3253                 if (error)
3254                         return error;
3255                 m_head = *m_head0;
3256
3257 #ifdef BNX_TSO_DEBUG
3258                 tso_nsegs = (m_head->m_pkthdr.len /
3259                     m_head->m_pkthdr.tso_segsz) - 1;
3260                 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
3261                         tso_nsegs = BNX_TSO_NSTATS - 1;
3262                 else if (tso_nsegs < 0)
3263                         tso_nsegs = 0;
3264                 txr->bnx_sc->bnx_tsosegs[tso_nsegs]++;
3265 #endif
3266         } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
3267                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3268                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3269                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3270                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3271                 if (m_head->m_flags & M_LASTFRAG)
3272                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3273                 else if (m_head->m_flags & M_FRAG)
3274                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3275         }
3276         if (m_head->m_flags & M_VLANTAG) {
3277                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3278                 vlan_tag = m_head->m_pkthdr.ether_vlantag;
3279         }
3280
3281         idx = *txidx;
3282         map = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
3283
3284         maxsegs = (BGE_TX_RING_CNT - txr->bnx_tx_cnt) - BNX_NSEG_RSVD;
3285         KASSERT(maxsegs >= BNX_NSEG_SPARE,
3286                 ("not enough segments %d", maxsegs));
3287
3288         if (maxsegs > BNX_NSEG_NEW)
3289                 maxsegs = BNX_NSEG_NEW;
3290
3291         /*
3292          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
3293          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
3294          * but when such padded frames employ the bge IP/TCP checksum
3295          * offload, the hardware checksum assist gives incorrect results
3296          * (possibly from incorporating its own padding into the UDP/TCP
3297          * checksum; who knows).  If we pad such runts with zeros, the
3298          * onboard checksum comes out correct.
3299          */
3300         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3301             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
3302                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
3303                 if (error)
3304                         goto back;
3305         }
3306
3307         if ((txr->bnx_tx_flags & BNX_TX_FLAG_SHORTDMA) &&
3308             m_head->m_next != NULL) {
3309                 m_new = bnx_defrag_shortdma(m_head);
3310                 if (m_new == NULL) {
3311                         error = ENOBUFS;
3312                         goto back;
3313                 }
3314                 *m_head0 = m_head = m_new;
3315         }
3316         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3317             (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) &&
3318             m_head->m_next != NULL) {
3319                 /*
3320                  * Forcefully defragment mbuf chain to overcome hardware
3321                  * limitation which only support a single outstanding
3322                  * DMA read operation.  If it fails, keep moving on using
3323                  * the original mbuf chain.
3324                  */
3325                 m_new = m_defrag(m_head, MB_DONTWAIT);
3326                 if (m_new != NULL)
3327                         *m_head0 = m_head = m_new;
3328         }
3329
3330         error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map,
3331             m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3332         if (error)
3333                 goto back;
3334         *segs_used += nsegs;
3335
3336         m_head = *m_head0;
3337         bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3338
3339         for (i = 0; ; i++) {
3340                 d = &txr->bnx_tx_ring[idx];
3341
3342                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3343                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3344                 d->bge_len = segs[i].ds_len;
3345                 d->bge_flags = csum_flags;
3346                 d->bge_vlan_tag = vlan_tag;
3347                 d->bge_mss = mss;
3348
3349                 if (i == nsegs - 1)
3350                         break;
3351                 BNX_INC(idx, BGE_TX_RING_CNT);
3352         }
3353         /* Mark the last segment as end of packet... */
3354         d->bge_flags |= BGE_TXBDFLAG_END;
3355
3356         /*
3357          * Insure that the map for this transmission is placed at
3358          * the array index of the last descriptor in this chain.
3359          */
3360         txr->bnx_tx_buf[*txidx].bnx_tx_dmamap = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
3361         txr->bnx_tx_buf[idx].bnx_tx_dmamap = map;
3362         txr->bnx_tx_buf[idx].bnx_tx_mbuf = m_head;
3363         txr->bnx_tx_cnt += nsegs;
3364
3365         BNX_INC(idx, BGE_TX_RING_CNT);
3366         *txidx = idx;
3367 back:
3368         if (error) {
3369                 m_freem(*m_head0);
3370                 *m_head0 = NULL;
3371         }
3372         return error;
3373 }
3374
3375 /*
3376  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3377  * to the mbuf data regions directly in the transmit descriptors.
3378  */
3379 static void
3380 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3381 {
3382         struct bnx_tx_ring *txr = ifsq_get_priv(ifsq);
3383         struct mbuf *m_head = NULL;
3384         uint32_t prodidx;
3385         int nsegs = 0;
3386
3387         KKASSERT(txr->bnx_ifsq == ifsq);
3388         ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
3389
3390         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3391                 return;
3392
3393         prodidx = txr->bnx_tx_prodidx;
3394
3395         while (txr->bnx_tx_buf[prodidx].bnx_tx_mbuf == NULL) {
3396                 /*
3397                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3398                  * descriptors of the end of the ring.  Also make
3399                  * sure there are BGE_NSEG_SPARE descriptors for
3400                  * jumbo buffers' or TSO segments' defragmentation.
3401                  */
3402                 if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) <
3403                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
3404                         ifsq_set_oactive(ifsq);
3405                         break;
3406                 }
3407
3408                 m_head = ifsq_dequeue(ifsq, NULL);
3409                 if (m_head == NULL)
3410                         break;
3411
3412                 /*
3413                  * Pack the data into the transmit ring. If we
3414                  * don't have room, set the OACTIVE flag and wait
3415                  * for the NIC to drain the ring.
3416                  */
3417                 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) {
3418                         ifsq_set_oactive(ifsq);
3419                         IFNET_STAT_INC(ifp, oerrors, 1);
3420                         break;
3421                 }
3422
3423                 if (nsegs >= txr->bnx_tx_wreg) {
3424                         /* Transmit */
3425                         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
3426                         nsegs = 0;
3427                 }
3428
3429                 ETHER_BPF_MTAP(ifp, m_head);
3430
3431                 /*
3432                  * Set a timeout in case the chip goes out to lunch.
3433                  */
3434                 txr->bnx_tx_watchdog.wd_timer = 5;
3435         }
3436
3437         if (nsegs > 0) {
3438                 /* Transmit */
3439                 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
3440         }
3441         txr->bnx_tx_prodidx = prodidx;
3442 }
3443
3444 static void
3445 bnx_init(void *xsc)
3446 {
3447         struct bnx_softc *sc = xsc;
3448         struct ifnet *ifp = &sc->arpcom.ac_if;
3449         uint16_t *m;
3450         uint32_t mode;
3451         int i;
3452         boolean_t polling;
3453
3454         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3455
3456         /* Cancel pending I/O and flush buffers. */
3457         bnx_stop(sc);
3458         bnx_reset(sc);
3459         bnx_chipinit(sc);
3460
3461         /*
3462          * Init the various state machines, ring
3463          * control blocks and firmware.
3464          */
3465         if (bnx_blockinit(sc)) {
3466                 if_printf(ifp, "initialization failure\n");
3467                 bnx_stop(sc);
3468                 return;
3469         }
3470
3471         /* Specify MTU. */
3472         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3473             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3474
3475         /* Load our MAC address. */
3476         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3477         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3478         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3479
3480         /* Enable or disable promiscuous mode as needed. */
3481         bnx_setpromisc(sc);
3482
3483         /* Program multicast filter. */
3484         bnx_setmulti(sc);
3485
3486         /* Init RX ring. */
3487         if (bnx_init_rx_ring_std(&sc->bnx_rx_std_ring)) {
3488                 if_printf(ifp, "RX ring initialization failed\n");
3489                 bnx_stop(sc);
3490                 return;
3491         }
3492
3493         /* Init jumbo RX ring. */
3494         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3495                 if (bnx_init_rx_ring_jumbo(sc)) {
3496                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3497                         bnx_stop(sc);
3498                         return;
3499                 }
3500         }
3501
3502         /* Init our RX return ring index */
3503         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
3504                 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
3505
3506                 ret->bnx_rx_saved_considx = 0;
3507                 ret->bnx_rx_cnt = 0;
3508         }
3509
3510         /* Init TX ring. */
3511         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3512                 bnx_init_tx_ring(&sc->bnx_tx_ring[i]);
3513
3514         /* Enable TX MAC state machine lockup fix. */
3515         mode = CSR_READ_4(sc, BGE_TX_MODE);
3516         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3517         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
3518             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
3519                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3520                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3521                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3522         }
3523         /* Turn on transmitter */
3524         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3525
3526         /* Initialize RSS */
3527         mode = BGE_RXMODE_ENABLE;
3528         if (BNX_RSS_ENABLED(sc)) {
3529                 bnx_init_rss(sc);
3530                 mode |= BGE_RXMODE_RSS_ENABLE |
3531                     BGE_RXMODE_RSS_HASH_MASK_BITS |
3532                     BGE_RXMODE_RSS_IPV4_HASH |
3533                     BGE_RXMODE_RSS_TCP_IPV4_HASH;
3534         }
3535         /* Turn on receiver */
3536         BNX_SETBIT(sc, BGE_RX_MODE, mode);
3537
3538         /*
3539          * Set the number of good frames to receive after RX MBUF
3540          * Low Watermark has been reached.  After the RX MAC receives
3541          * this number of frames, it will drop subsequent incoming
3542          * frames until the MBUF High Watermark is reached.
3543          */
3544         if (BNX_IS_57765_FAMILY(sc))
3545                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3546         else
3547                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3548
3549         if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI ||
3550             sc->bnx_intr_type == PCI_INTR_TYPE_MSIX) {
3551                 if (bootverbose) {
3552                         if_printf(ifp, "MSI_MODE: %#x\n",
3553                             CSR_READ_4(sc, BGE_MSI_MODE));
3554                 }
3555         }
3556
3557         /* Tell firmware we're alive. */
3558         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3559
3560         /* Enable host interrupts if polling(4) is not enabled. */
3561         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3562
3563         polling = FALSE;
3564 #ifdef IFPOLL_ENABLE
3565         if (ifp->if_flags & IFF_NPOLLING)
3566                 polling = TRUE;
3567 #endif
3568         if (polling)
3569                 bnx_disable_intr(sc);
3570         else
3571                 bnx_enable_intr(sc);
3572         bnx_set_tick_cpuid(sc, polling);
3573
3574         bnx_ifmedia_upd(ifp);
3575
3576         ifp->if_flags |= IFF_RUNNING;
3577         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3578                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3579
3580                 ifsq_clr_oactive(txr->bnx_ifsq);
3581                 ifsq_watchdog_start(&txr->bnx_tx_watchdog);
3582         }
3583
3584         callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc,
3585             sc->bnx_tick_cpuid);
3586 }
3587
3588 /*
3589  * Set media options.
3590  */
3591 static int
3592 bnx_ifmedia_upd(struct ifnet *ifp)
3593 {
3594         struct bnx_softc *sc = ifp->if_softc;
3595
3596         /* If this is a 1000baseX NIC, enable the TBI port. */
3597         if (sc->bnx_flags & BNX_FLAG_TBI) {
3598                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3599
3600                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3601                         return(EINVAL);
3602
3603                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3604                 case IFM_AUTO:
3605                         break;
3606
3607                 case IFM_1000_SX:
3608                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3609                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3610                                     BGE_MACMODE_HALF_DUPLEX);
3611                         } else {
3612                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3613                                     BGE_MACMODE_HALF_DUPLEX);
3614                         }
3615                         break;
3616                 default:
3617                         return(EINVAL);
3618                 }
3619         } else {
3620                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3621
3622                 sc->bnx_link_evt++;
3623                 sc->bnx_link = 0;
3624                 if (mii->mii_instance) {
3625                         struct mii_softc *miisc;
3626
3627                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3628                                 mii_phy_reset(miisc);
3629                 }
3630                 mii_mediachg(mii);
3631
3632                 /*
3633                  * Force an interrupt so that we will call bnx_link_upd
3634                  * if needed and clear any pending link state attention.
3635                  * Without this we are not getting any further interrupts
3636                  * for link state changes and thus will not UP the link and
3637                  * not be able to send in bnx_start.  The only way to get
3638                  * things working was to receive a packet and get an RX
3639                  * intr.
3640                  *
3641                  * bnx_tick should help for fiber cards and we might not
3642                  * need to do this here if BNX_FLAG_TBI is set but as
3643                  * we poll for fiber anyway it should not harm.
3644                  */
3645                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3646         }
3647         return(0);
3648 }
3649
3650 /*
3651  * Report current media status.
3652  */
3653 static void
3654 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3655 {
3656         struct bnx_softc *sc = ifp->if_softc;
3657
3658         if (sc->bnx_flags & BNX_FLAG_TBI) {
3659                 ifmr->ifm_status = IFM_AVALID;
3660                 ifmr->ifm_active = IFM_ETHER;
3661                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3662                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3663                         ifmr->ifm_status |= IFM_ACTIVE;
3664                 } else {
3665                         ifmr->ifm_active |= IFM_NONE;
3666                         return;
3667                 }
3668
3669                 ifmr->ifm_active |= IFM_1000_SX;
3670                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3671                         ifmr->ifm_active |= IFM_HDX;
3672                 else
3673                         ifmr->ifm_active |= IFM_FDX;
3674         } else {
3675                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3676
3677                 mii_pollstat(mii);
3678                 ifmr->ifm_active = mii->mii_media_active;
3679                 ifmr->ifm_status = mii->mii_media_status;
3680         }
3681 }
3682
3683 static int
3684 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3685 {
3686         struct bnx_softc *sc = ifp->if_softc;
3687         struct ifreq *ifr = (struct ifreq *)data;
3688         int mask, error = 0;
3689
3690         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3691
3692         switch (command) {
3693         case SIOCSIFMTU:
3694                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3695                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3696                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3697                         error = EINVAL;
3698                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3699                         ifp->if_mtu = ifr->ifr_mtu;
3700                         if (ifp->if_flags & IFF_RUNNING)
3701                                 bnx_init(sc);
3702                 }
3703                 break;
3704         case SIOCSIFFLAGS:
3705                 if (ifp->if_flags & IFF_UP) {
3706                         if (ifp->if_flags & IFF_RUNNING) {
3707                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3708
3709                                 /*
3710                                  * If only the state of the PROMISC flag
3711                                  * changed, then just use the 'set promisc
3712                                  * mode' command instead of reinitializing
3713                                  * the entire NIC. Doing a full re-init
3714                                  * means reloading the firmware and waiting
3715                                  * for it to start up, which may take a
3716                                  * second or two.  Similarly for ALLMULTI.
3717                                  */
3718                                 if (mask & IFF_PROMISC)
3719                                         bnx_setpromisc(sc);
3720                                 if (mask & IFF_ALLMULTI)
3721                                         bnx_setmulti(sc);
3722                         } else {
3723                                 bnx_init(sc);
3724                         }
3725                 } else if (ifp->if_flags & IFF_RUNNING) {
3726                         bnx_stop(sc);
3727                 }
3728                 sc->bnx_if_flags = ifp->if_flags;
3729                 break;
3730         case SIOCADDMULTI:
3731         case SIOCDELMULTI:
3732                 if (ifp->if_flags & IFF_RUNNING)
3733                         bnx_setmulti(sc);
3734                 break;
3735         case SIOCSIFMEDIA:
3736         case SIOCGIFMEDIA:
3737                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3738                         error = ifmedia_ioctl(ifp, ifr,
3739                             &sc->bnx_ifmedia, command);
3740                 } else {
3741                         struct mii_data *mii;
3742
3743                         mii = device_get_softc(sc->bnx_miibus);
3744                         error = ifmedia_ioctl(ifp, ifr,
3745                                               &mii->mii_media, command);
3746                 }
3747                 break;
3748         case SIOCSIFCAP:
3749                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3750                 if (mask & IFCAP_HWCSUM) {
3751                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3752                         if (ifp->if_capenable & IFCAP_TXCSUM)
3753                                 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3754                         else
3755                                 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3756                 }
3757                 if (mask & IFCAP_TSO) {
3758                         ifp->if_capenable ^= (mask & IFCAP_TSO);
3759                         if (ifp->if_capenable & IFCAP_TSO)
3760                                 ifp->if_hwassist |= CSUM_TSO;
3761                         else
3762                                 ifp->if_hwassist &= ~CSUM_TSO;
3763                 }
3764                 if (mask & IFCAP_RSS)
3765                         ifp->if_capenable ^= IFCAP_RSS;
3766                 break;
3767         default:
3768                 error = ether_ioctl(ifp, command, data);
3769                 break;
3770         }
3771         return error;
3772 }
3773
3774 static void
3775 bnx_watchdog(struct ifaltq_subque *ifsq)
3776 {
3777         struct ifnet *ifp = ifsq_get_ifp(ifsq);
3778         struct bnx_softc *sc = ifp->if_softc;
3779         int i;
3780
3781         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3782
3783         if_printf(ifp, "watchdog timeout -- resetting\n");
3784
3785         bnx_init(sc);
3786
3787         IFNET_STAT_INC(ifp, oerrors, 1);
3788
3789         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3790                 ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq);
3791 }
3792
3793 /*
3794  * Stop the adapter and free any mbufs allocated to the
3795  * RX and TX lists.
3796  */
3797 static void
3798 bnx_stop(struct bnx_softc *sc)
3799 {
3800         struct ifnet *ifp = &sc->arpcom.ac_if;
3801         int i;
3802
3803         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3804
3805         callout_stop(&sc->bnx_tick_timer);
3806
3807         /*
3808          * Disable all of the receiver blocks
3809          */
3810         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3811         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3812         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3813         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3814         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3815         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3816
3817         /*
3818          * Disable all of the transmit blocks
3819          */
3820         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3821         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3822         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3823         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3824         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3825         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3826
3827         /*
3828          * Shut down all of the memory managers and related
3829          * state machines.
3830          */
3831         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3832         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3833         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3834         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3835
3836         /* Disable host interrupts. */
3837         bnx_disable_intr(sc);
3838
3839         /*
3840          * Tell firmware we're shutting down.
3841          */
3842         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3843
3844         /* Free the RX lists. */
3845         bnx_free_rx_ring_std(&sc->bnx_rx_std_ring);
3846
3847         /* Free jumbo RX list. */
3848         if (BNX_IS_JUMBO_CAPABLE(sc))
3849                 bnx_free_rx_ring_jumbo(sc);
3850
3851         /* Free TX buffers. */
3852         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3853                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3854
3855                 txr->bnx_saved_status_tag = 0;
3856                 bnx_free_tx_ring(txr);
3857         }
3858
3859         /* Clear saved status tag */
3860         for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3861                 sc->bnx_rx_ret_ring[i].bnx_saved_status_tag = 0;
3862
3863         sc->bnx_link = 0;
3864         sc->bnx_coal_chg = 0;
3865
3866         ifp->if_flags &= ~IFF_RUNNING;
3867         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3868                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3869
3870                 ifsq_clr_oactive(txr->bnx_ifsq);
3871                 ifsq_watchdog_stop(&txr->bnx_tx_watchdog);
3872         }
3873 }
3874
3875 /*
3876  * Stop all chip I/O so that the kernel's probe routines don't
3877  * get confused by errant DMAs when rebooting.
3878  */
3879 static void
3880 bnx_shutdown(device_t dev)
3881 {
3882         struct bnx_softc *sc = device_get_softc(dev);
3883         struct ifnet *ifp = &sc->arpcom.ac_if;
3884
3885         ifnet_serialize_all(ifp);
3886         bnx_stop(sc);
3887         bnx_reset(sc);
3888         ifnet_deserialize_all(ifp);
3889 }
3890
3891 static int
3892 bnx_suspend(device_t dev)
3893 {
3894         struct bnx_softc *sc = device_get_softc(dev);
3895         struct ifnet *ifp = &sc->arpcom.ac_if;
3896
3897         ifnet_serialize_all(ifp);
3898         bnx_stop(sc);
3899         ifnet_deserialize_all(ifp);
3900
3901         return 0;
3902 }
3903
3904 static int
3905 bnx_resume(device_t dev)
3906 {
3907         struct bnx_softc *sc = device_get_softc(dev);
3908         struct ifnet *ifp = &sc->arpcom.ac_if;
3909
3910         ifnet_serialize_all(ifp);
3911
3912         if (ifp->if_flags & IFF_UP) {
3913                 int i;
3914
3915                 bnx_init(sc);
3916                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3917                         ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq);
3918         }
3919
3920         ifnet_deserialize_all(ifp);
3921
3922         return 0;
3923 }
3924
3925 static void
3926 bnx_setpromisc(struct bnx_softc *sc)
3927 {
3928         struct ifnet *ifp = &sc->arpcom.ac_if;
3929
3930         if (ifp->if_flags & IFF_PROMISC)
3931                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3932         else
3933                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3934 }
3935
3936 static void
3937 bnx_dma_free(struct bnx_softc *sc)
3938 {
3939         struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3940         int i;
3941
3942         /* Destroy RX return rings */
3943         if (sc->bnx_rx_ret_ring != NULL) {
3944                 for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3945                         bnx_destroy_rx_ret_ring(&sc->bnx_rx_ret_ring[i]);
3946                 kfree(sc->bnx_rx_ret_ring, M_DEVBUF);
3947         }
3948
3949         /* Destroy RX mbuf DMA stuffs. */
3950         if (std->bnx_rx_mtag != NULL) {
3951                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3952                         KKASSERT(std->bnx_rx_std_buf[i].bnx_rx_mbuf == NULL);
3953                         bus_dmamap_destroy(std->bnx_rx_mtag,
3954                             std->bnx_rx_std_buf[i].bnx_rx_dmamap);
3955                 }
3956                 bus_dma_tag_destroy(std->bnx_rx_mtag);
3957         }
3958
3959         /* Destroy standard RX ring */
3960         bnx_dma_block_free(std->bnx_rx_std_ring_tag,
3961             std->bnx_rx_std_ring_map, std->bnx_rx_std_ring);
3962
3963         /* Destroy TX rings */
3964         if (sc->bnx_tx_ring != NULL) {
3965                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3966                         bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]);
3967                 kfree(sc->bnx_tx_ring, M_DEVBUF);
3968         }
3969
3970         if (BNX_IS_JUMBO_CAPABLE(sc))
3971                 bnx_free_jumbo_mem(sc);
3972
3973         /* Destroy status blocks */
3974         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
3975                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
3976
3977                 bnx_dma_block_free(intr->bnx_status_tag,
3978                     intr->bnx_status_map, intr->bnx_status_block);
3979         }
3980
3981         /* Destroy the parent tag */
3982         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3983                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3984 }
3985
3986 static int
3987 bnx_dma_alloc(device_t dev)
3988 {
3989         struct bnx_softc *sc = device_get_softc(dev);
3990         struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3991         int i, error, mbx;
3992
3993         /*
3994          * Allocate the parent bus DMA tag appropriate for PCI.
3995          *
3996          * All of the NetExtreme/NetLink controllers have 4GB boundary
3997          * DMA bug.
3998          * Whenever an address crosses a multiple of the 4GB boundary
3999          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
4000          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
4001          * state machine will lockup and cause the device to hang.
4002          */
4003         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
4004             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
4005             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
4006             0, &sc->bnx_cdata.bnx_parent_tag);
4007         if (error) {
4008                 device_printf(dev, "could not create parent DMA tag\n");
4009                 return error;
4010         }
4011
4012         /*
4013          * Create DMA stuffs for status blocks.
4014          */
4015         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4016                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4017
4018                 error = bnx_dma_block_alloc(sc,
4019                     __VM_CACHELINE_ALIGN(BGE_STATUS_BLK_SZ),
4020                     &intr->bnx_status_tag, &intr->bnx_status_map,
4021                     (void *)&intr->bnx_status_block,
4022                     &intr->bnx_status_block_paddr);
4023                 if (error) {
4024                         device_printf(dev,
4025                             "could not create %dth status block\n", i);
4026                         return error;
4027                 }
4028         }
4029         sc->bnx_hw_status = &sc->bnx_intr_data[0].bnx_status_block->bge_status;
4030         if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG) {
4031                 sc->bnx_hw_status_tag =
4032                     &sc->bnx_intr_data[0].bnx_status_block->bge_status_tag;
4033         }
4034
4035         /*
4036          * Create DMA tag and maps for RX mbufs.
4037          */
4038         std->bnx_sc = sc;
4039         lwkt_serialize_init(&std->bnx_rx_std_serialize);
4040         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
4041             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4042             NULL, NULL, MCLBYTES, 1, MCLBYTES,
4043             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, &std->bnx_rx_mtag);
4044         if (error) {
4045                 device_printf(dev, "could not create RX mbuf DMA tag\n");
4046                 return error;
4047         }
4048
4049         for (i = 0; i < BGE_STD_RX_RING_CNT; ++i) {
4050                 error = bus_dmamap_create(std->bnx_rx_mtag, BUS_DMA_WAITOK,
4051                     &std->bnx_rx_std_buf[i].bnx_rx_dmamap);
4052                 if (error) {
4053                         int j;
4054
4055                         for (j = 0; j < i; ++j) {
4056                                 bus_dmamap_destroy(std->bnx_rx_mtag,
4057                                     std->bnx_rx_std_buf[j].bnx_rx_dmamap);
4058                         }
4059                         bus_dma_tag_destroy(std->bnx_rx_mtag);
4060                         std->bnx_rx_mtag = NULL;
4061
4062                         device_printf(dev,
4063                             "could not create %dth RX mbuf DMA map\n", i);
4064                         return error;
4065                 }
4066         }
4067
4068         /*
4069          * Create DMA stuffs for standard RX ring.
4070          */
4071         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
4072             &std->bnx_rx_std_ring_tag,
4073             &std->bnx_rx_std_ring_map,
4074             (void *)&std->bnx_rx_std_ring,
4075             &std->bnx_rx_std_ring_paddr);
4076         if (error) {
4077                 device_printf(dev, "could not create std RX ring\n");
4078                 return error;
4079         }
4080
4081         /*
4082          * Create RX return rings
4083          */
4084         mbx = BGE_MBX_RX_CONS0_LO;
4085         sc->bnx_rx_ret_ring = kmalloc_cachealign(
4086             sizeof(struct bnx_rx_ret_ring) * sc->bnx_rx_retcnt, M_DEVBUF,
4087             M_WAITOK | M_ZERO);
4088         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4089                 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
4090                 struct bnx_intr_data *intr;
4091
4092                 ret->bnx_sc = sc;
4093                 ret->bnx_std = std;
4094                 ret->bnx_rx_mbx = mbx;
4095                 ret->bnx_rx_cntmax = (BGE_STD_RX_RING_CNT / 4) /
4096                     sc->bnx_rx_retcnt;
4097                 ret->bnx_rx_mask = 1 << i;
4098
4099                 if (!BNX_RSS_ENABLED(sc)) {
4100                         intr = &sc->bnx_intr_data[0];
4101                 } else {
4102                         KKASSERT(i + 1 < sc->bnx_intr_cnt);
4103                         intr = &sc->bnx_intr_data[i + 1];
4104                 }
4105
4106                 if (i == 0) {
4107                         ret->bnx_rx_considx =
4108                             &intr->bnx_status_block->bge_idx[0].bge_rx_prod_idx;
4109                 } else if (i == 1) {
4110                         ret->bnx_rx_considx =
4111                             &intr->bnx_status_block->bge_rx_jumbo_cons_idx;
4112                 } else if (i == 2) {
4113                         ret->bnx_rx_considx =
4114                             &intr->bnx_status_block->bge_rsvd1;
4115                 } else if (i == 3) {
4116                         ret->bnx_rx_considx =
4117                             &intr->bnx_status_block->bge_rx_mini_cons_idx;
4118                 } else {
4119                         panic("unknown RX return ring %d\n", i);
4120                 }
4121                 ret->bnx_hw_status_tag =
4122                     &intr->bnx_status_block->bge_status_tag;
4123
4124                 error = bnx_create_rx_ret_ring(ret);
4125                 if (error) {
4126                         device_printf(dev,
4127                             "could not create %dth RX ret ring\n", i);
4128                         return error;
4129                 }
4130                 mbx += 8;
4131         }
4132
4133         /*
4134          * Create TX rings
4135          */
4136         sc->bnx_tx_ring = kmalloc_cachealign(
4137             sizeof(struct bnx_tx_ring) * sc->bnx_tx_ringcnt, M_DEVBUF,
4138             M_WAITOK | M_ZERO);
4139         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4140                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
4141                 struct bnx_intr_data *intr;
4142
4143                 txr->bnx_sc = sc;
4144                 txr->bnx_tx_mbx = bnx_tx_mailbox[i];
4145
4146                 if (sc->bnx_tx_ringcnt == 1) {
4147                         intr = &sc->bnx_intr_data[0];
4148                 } else {
4149                         KKASSERT(i + 1 < sc->bnx_intr_cnt);
4150                         intr = &sc->bnx_intr_data[i + 1];
4151                 }
4152
4153                 if ((sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) == 0) {
4154                         txr->bnx_hw_status_tag =
4155                             &intr->bnx_status_block->bge_status_tag;
4156                 }
4157                 txr->bnx_tx_considx =
4158                     &intr->bnx_status_block->bge_idx[0].bge_tx_cons_idx;
4159
4160                 error = bnx_create_tx_ring(txr);
4161                 if (error) {
4162                         device_printf(dev,
4163                             "could not create %dth TX ring\n", i);
4164                         return error;
4165                 }
4166         }
4167
4168         /*
4169          * Create jumbo buffer pool.
4170          */
4171         if (BNX_IS_JUMBO_CAPABLE(sc)) {
4172                 error = bnx_alloc_jumbo_mem(sc);
4173                 if (error) {
4174                         device_printf(dev,
4175                             "could not create jumbo buffer pool\n");
4176                         return error;
4177                 }
4178         }
4179
4180         return 0;
4181 }
4182
4183 static int
4184 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
4185                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
4186 {
4187         bus_dmamem_t dmem;
4188         int error;
4189
4190         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
4191                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4192                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4193         if (error)
4194                 return error;
4195
4196         *tag = dmem.dmem_tag;
4197         *map = dmem.dmem_map;
4198         *addr = dmem.dmem_addr;
4199         *paddr = dmem.dmem_busaddr;
4200
4201         return 0;
4202 }
4203
4204 static void
4205 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
4206 {
4207         if (tag != NULL) {
4208                 bus_dmamap_unload(tag, map);
4209                 bus_dmamem_free(tag, addr, map);
4210                 bus_dma_tag_destroy(tag);
4211         }
4212 }
4213
4214 static void
4215 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
4216 {
4217         struct ifnet *ifp = &sc->arpcom.ac_if;
4218
4219 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
4220
4221         /*
4222          * Sometimes PCS encoding errors are detected in
4223          * TBI mode (on fiber NICs), and for some reason
4224          * the chip will signal them as link changes.
4225          * If we get a link change event, but the 'PCS
4226          * encoding error' bit in the MAC status register
4227          * is set, don't bother doing a link check.
4228          * This avoids spurious "gigabit link up" messages
4229          * that sometimes appear on fiber NICs during
4230          * periods of heavy traffic.
4231          */
4232         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4233                 if (!sc->bnx_link) {
4234                         sc->bnx_link++;
4235                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
4236                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
4237                                     BGE_MACMODE_TBI_SEND_CFGS);
4238                         }
4239                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4240
4241                         if (bootverbose)
4242                                 if_printf(ifp, "link UP\n");
4243
4244                         ifp->if_link_state = LINK_STATE_UP;
4245                         if_link_state_change(ifp);
4246                 }
4247         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
4248                 if (sc->bnx_link) {
4249                         sc->bnx_link = 0;
4250
4251                         if (bootverbose)
4252                                 if_printf(ifp, "link DOWN\n");
4253
4254                         ifp->if_link_state = LINK_STATE_DOWN;
4255                         if_link_state_change(ifp);
4256                 }
4257         }
4258
4259 #undef PCS_ENCODE_ERR
4260
4261         /* Clear the attention. */
4262         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4263             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4264             BGE_MACSTAT_LINK_CHANGED);
4265 }
4266
4267 static void
4268 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
4269 {
4270         struct ifnet *ifp = &sc->arpcom.ac_if;
4271         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
4272
4273         mii_pollstat(mii);
4274         bnx_miibus_statchg(sc->bnx_dev);
4275
4276         if (bootverbose) {
4277                 if (sc->bnx_link)
4278                         if_printf(ifp, "link UP\n");
4279                 else
4280                         if_printf(ifp, "link DOWN\n");
4281         }
4282
4283         /* Clear the attention. */
4284         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4285             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4286             BGE_MACSTAT_LINK_CHANGED);
4287 }
4288
4289 static void
4290 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
4291 {
4292         struct ifnet *ifp = &sc->arpcom.ac_if;
4293         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
4294
4295         mii_pollstat(mii);
4296
4297         if (!sc->bnx_link &&
4298             (mii->mii_media_status & IFM_ACTIVE) &&
4299             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4300                 sc->bnx_link++;
4301                 if (bootverbose)
4302                         if_printf(ifp, "link UP\n");
4303         } else if (sc->bnx_link &&
4304             (!(mii->mii_media_status & IFM_ACTIVE) ||
4305             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4306                 sc->bnx_link = 0;
4307                 if (bootverbose)
4308                         if_printf(ifp, "link DOWN\n");
4309         }
4310
4311         /* Clear the attention. */
4312         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4313             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4314             BGE_MACSTAT_LINK_CHANGED);
4315 }
4316
4317 static int
4318 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
4319 {
4320         struct bnx_softc *sc = arg1;
4321
4322         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4323             &sc->bnx_rx_coal_ticks,
4324             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
4325             BNX_RX_COAL_TICKS_CHG);
4326 }
4327
4328 static int
4329 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
4330 {
4331         struct bnx_softc *sc = arg1;
4332
4333         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4334             &sc->bnx_tx_coal_ticks,
4335             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
4336             BNX_TX_COAL_TICKS_CHG);
4337 }
4338
4339 static int
4340 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
4341 {
4342         struct bnx_softc *sc = arg1;
4343
4344         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4345             &sc->bnx_rx_coal_bds,
4346             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
4347             BNX_RX_COAL_BDS_CHG);
4348 }
4349
4350 static int
4351 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
4352 {
4353         struct bnx_softc *sc = arg1;
4354
4355         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4356             &sc->bnx_tx_coal_bds,
4357             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
4358             BNX_TX_COAL_BDS_CHG);
4359 }
4360
4361 static int
4362 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4363 {
4364         struct bnx_softc *sc = arg1;
4365
4366         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4367             &sc->bnx_rx_coal_bds_int,
4368             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
4369             BNX_RX_COAL_BDS_INT_CHG);
4370 }
4371
4372 static int
4373 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4374 {
4375         struct bnx_softc *sc = arg1;
4376
4377         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4378             &sc->bnx_tx_coal_bds_int,
4379             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
4380             BNX_TX_COAL_BDS_INT_CHG);
4381 }
4382
4383 static int
4384 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
4385     int coal_min, int coal_max, uint32_t coal_chg_mask)
4386 {
4387         struct bnx_softc *sc = arg1;
4388         struct ifnet *ifp = &sc->arpcom.ac_if;
4389         int error = 0, v;
4390
4391         ifnet_serialize_all(ifp);
4392
4393         v = *coal;
4394         error = sysctl_handle_int(oidp, &v, 0, req);
4395         if (!error && req->newptr != NULL) {
4396                 if (v < coal_min || v > coal_max) {
4397                         error = EINVAL;
4398                 } else {
4399                         *coal = v;
4400                         sc->bnx_coal_chg |= coal_chg_mask;
4401
4402                         /* Commit changes */
4403                         bnx_coal_change(sc);
4404                 }
4405         }
4406
4407         ifnet_deserialize_all(ifp);
4408         return error;
4409 }
4410
4411 static void
4412 bnx_coal_change(struct bnx_softc *sc)
4413 {
4414         struct ifnet *ifp = &sc->arpcom.ac_if;
4415         int i;
4416
4417         ASSERT_IFNET_SERIALIZED_ALL(ifp);
4418
4419         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
4420                 if (sc->bnx_rx_retcnt == 1) {
4421                         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
4422                             sc->bnx_rx_coal_ticks);
4423                         i = 0;
4424                 } else {
4425                         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, 0);
4426                         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4427                                 CSR_WRITE_4(sc, BGE_VEC1_RX_COAL_TICKS +
4428                                     (i * BGE_VEC_COALSET_SIZE),
4429                                     sc->bnx_rx_coal_ticks);
4430                         }
4431                 }
4432                 for (; i < BNX_INTR_MAX - 1; ++i) {
4433                         CSR_WRITE_4(sc, BGE_VEC1_RX_COAL_TICKS +
4434                             (i * BGE_VEC_COALSET_SIZE), 0);
4435                 }
4436                 if (bootverbose) {
4437                         if_printf(ifp, "rx_coal_ticks -> %u\n",
4438                             sc->bnx_rx_coal_ticks);
4439                 }
4440         }
4441
4442         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
4443                 if (sc->bnx_tx_ringcnt == 1) {
4444                         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4445                             sc->bnx_tx_coal_ticks);
4446                         i = 0;
4447                 } else {
4448                         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, 0);
4449                         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4450                                 CSR_WRITE_4(sc, BGE_VEC1_TX_COAL_TICKS +
4451                                     (i * BGE_VEC_COALSET_SIZE),
4452                                     sc->bnx_tx_coal_ticks);
4453                         }
4454                 }
4455                 for (; i < BNX_INTR_MAX - 1; ++i) {
4456                         CSR_WRITE_4(sc, BGE_VEC1_TX_COAL_TICKS +
4457                             (i * BGE_VEC_COALSET_SIZE), 0);
4458                 }
4459                 if (bootverbose) {
4460                         if_printf(ifp, "tx_coal_ticks -> %u\n",
4461                             sc->bnx_tx_coal_ticks);
4462                 }
4463         }
4464
4465         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
4466                 if (sc->bnx_rx_retcnt == 1) {
4467                         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4468                             sc->bnx_rx_coal_bds);
4469                         i = 0;
4470                 } else {
4471                         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, 0);
4472                         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4473                                 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS +
4474                                     (i * BGE_VEC_COALSET_SIZE),
4475                                     sc->bnx_rx_coal_bds);
4476                         }
4477                 }
4478                 for (; i < BNX_INTR_MAX - 1; ++i) {
4479                         CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS +
4480                             (i * BGE_VEC_COALSET_SIZE), 0);
4481                 }
4482                 if (bootverbose) {
4483                         if_printf(ifp, "rx_coal_bds -> %u\n",
4484                             sc->bnx_rx_coal_bds);
4485                 }
4486         }
4487
4488         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
4489                 if (sc->bnx_tx_ringcnt == 1) {
4490                         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4491                             sc->bnx_tx_coal_bds);
4492                         i = 0;
4493                 } else {
4494                         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, 0);
4495                         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4496                                 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS +
4497                                     (i * BGE_VEC_COALSET_SIZE),
4498                                     sc->bnx_tx_coal_bds);
4499                         }
4500                 }
4501                 for (; i < BNX_INTR_MAX - 1; ++i) {
4502                         CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS +
4503                             (i * BGE_VEC_COALSET_SIZE), 0);
4504                 }
4505                 if (bootverbose) {
4506                         if_printf(ifp, "tx_coal_bds -> %u\n",
4507                             sc->bnx_tx_coal_bds);
4508                 }
4509         }
4510
4511         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
4512                 if (sc->bnx_rx_retcnt == 1) {
4513                         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
4514                             sc->bnx_rx_coal_bds_int);
4515                         i = 0;
4516                 } else {
4517                         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
4518                         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4519                                 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS_INT +
4520                                     (i * BGE_VEC_COALSET_SIZE),
4521                                     sc->bnx_rx_coal_bds_int);
4522                         }
4523                 }
4524                 for (; i < BNX_INTR_MAX - 1; ++i) {
4525                         CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS_INT +
4526                             (i * BGE_VEC_COALSET_SIZE), 0);
4527                 }
4528                 if (bootverbose) {
4529                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
4530                             sc->bnx_rx_coal_bds_int);
4531                 }
4532         }
4533
4534         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
4535                 if (sc->bnx_tx_ringcnt == 1) {
4536                         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
4537                             sc->bnx_tx_coal_bds_int);
4538                         i = 0;
4539                 } else {
4540                         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
4541                         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4542                                 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS_INT +
4543                                     (i * BGE_VEC_COALSET_SIZE),
4544                                     sc->bnx_tx_coal_bds_int);
4545                         }
4546                 }
4547                 for (; i < BNX_INTR_MAX - 1; ++i) {
4548                         CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS_INT +
4549                             (i * BGE_VEC_COALSET_SIZE), 0);
4550                 }
4551                 if (bootverbose) {
4552                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
4553                             sc->bnx_tx_coal_bds_int);
4554                 }
4555         }
4556
4557         sc->bnx_coal_chg = 0;
4558 }
4559
4560 static void
4561 bnx_check_intr_rxtx(void *xintr)
4562 {
4563         struct bnx_intr_data *intr = xintr;
4564         struct bnx_rx_ret_ring *ret;
4565         struct bnx_tx_ring *txr;
4566         struct ifnet *ifp;
4567
4568         lwkt_serialize_enter(intr->bnx_intr_serialize);
4569
4570         KKASSERT(mycpuid == intr->bnx_intr_cpuid);
4571
4572         ifp = &intr->bnx_sc->arpcom.ac_if;
4573         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4574                 lwkt_serialize_exit(intr->bnx_intr_serialize);
4575                 return;
4576         }
4577
4578         txr = intr->bnx_txr;
4579         ret = intr->bnx_ret;
4580
4581         if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx ||
4582             *txr->bnx_tx_considx != txr->bnx_tx_saved_considx) {
4583                 if (intr->bnx_rx_check_considx == ret->bnx_rx_saved_considx &&
4584                     intr->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
4585                         if (!intr->bnx_intr_maylose) {
4586                                 intr->bnx_intr_maylose = TRUE;
4587                                 goto done;
4588                         }
4589                         if (bootverbose)
4590                                 if_printf(ifp, "lost interrupt\n");
4591                         intr->bnx_intr_func(intr->bnx_intr_arg);
4592                 }
4593         }
4594         intr->bnx_intr_maylose = FALSE;
4595         intr->bnx_rx_check_considx = ret->bnx_rx_saved_considx;
4596         intr->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
4597
4598 done:
4599         callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL,
4600             intr->bnx_intr_check, intr);
4601         lwkt_serialize_exit(intr->bnx_intr_serialize);
4602 }
4603
4604 static void
4605 bnx_check_intr_tx(void *xintr)
4606 {
4607         struct bnx_intr_data *intr = xintr;
4608         struct bnx_tx_ring *txr;
4609         struct ifnet *ifp;
4610
4611         lwkt_serialize_enter(intr->bnx_intr_serialize);
4612
4613         KKASSERT(mycpuid == intr->bnx_intr_cpuid);
4614
4615         ifp = &intr->bnx_sc->arpcom.ac_if;
4616         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4617                 lwkt_serialize_exit(intr->bnx_intr_serialize);
4618                 return;
4619         }
4620
4621         txr = intr->bnx_txr;
4622
4623         if (*txr->bnx_tx_considx != txr->bnx_tx_saved_considx) {
4624                 if (intr->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
4625                         if (!intr->bnx_intr_maylose) {
4626                                 intr->bnx_intr_maylose = TRUE;
4627                                 goto done;
4628                         }
4629                         if (bootverbose)
4630                                 if_printf(ifp, "lost interrupt\n");
4631                         intr->bnx_intr_func(intr->bnx_intr_arg);
4632                 }
4633         }
4634         intr->bnx_intr_maylose = FALSE;
4635         intr->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
4636
4637 done:
4638         callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL,
4639             intr->bnx_intr_check, intr);
4640         lwkt_serialize_exit(intr->bnx_intr_serialize);
4641 }
4642
4643 static void
4644 bnx_check_intr_rx(void *xintr)
4645 {
4646         struct bnx_intr_data *intr = xintr;
4647         struct bnx_rx_ret_ring *ret;
4648         struct ifnet *ifp;
4649
4650         lwkt_serialize_enter(intr->bnx_intr_serialize);
4651
4652         KKASSERT(mycpuid == intr->bnx_intr_cpuid);
4653
4654         ifp = &intr->bnx_sc->arpcom.ac_if;
4655         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4656                 lwkt_serialize_exit(intr->bnx_intr_serialize);
4657                 return;
4658         }
4659
4660         ret = intr->bnx_ret;
4661
4662         if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx) {
4663                 if (intr->bnx_rx_check_considx == ret->bnx_rx_saved_considx) {
4664                         if (!intr->bnx_intr_maylose) {
4665                                 intr->bnx_intr_maylose = TRUE;
4666                                 goto done;
4667                         }
4668                         if (bootverbose)
4669                                 if_printf(ifp, "lost interrupt\n");
4670                         intr->bnx_intr_func(intr->bnx_intr_arg);
4671                 }
4672         }
4673         intr->bnx_intr_maylose = FALSE;
4674         intr->bnx_rx_check_considx = ret->bnx_rx_saved_considx;
4675
4676 done:
4677         callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL,
4678             intr->bnx_intr_check, intr);
4679         lwkt_serialize_exit(intr->bnx_intr_serialize);
4680 }
4681
4682 static void
4683 bnx_enable_intr(struct bnx_softc *sc)
4684 {
4685         struct ifnet *ifp = &sc->arpcom.ac_if;
4686         int i;
4687
4688         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4689                 lwkt_serialize_handler_enable(
4690                     sc->bnx_intr_data[i].bnx_intr_serialize);
4691         }
4692
4693         /*
4694          * Enable interrupt.
4695          */
4696         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4697                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4698
4699                 bnx_writembx(sc, intr->bnx_intr_mbx,
4700                     (*intr->bnx_saved_status_tag) << 24);
4701                 /* XXX Linux driver */
4702                 bnx_writembx(sc, intr->bnx_intr_mbx,
4703                     (*intr->bnx_saved_status_tag) << 24);
4704         }
4705
4706         /*
4707          * Unmask the interrupt when we stop polling.
4708          */
4709         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4710             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4711
4712         /*
4713          * Trigger another interrupt, since above writing
4714          * to interrupt mailbox0 may acknowledge pending
4715          * interrupt.
4716          */
4717         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4718
4719         if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
4720                 if (bootverbose)
4721                         if_printf(ifp, "status tag bug workaround\n");
4722
4723                 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4724                         struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4725
4726                         if (intr->bnx_intr_check == NULL)
4727                                 continue;
4728                         intr->bnx_intr_maylose = FALSE;
4729                         intr->bnx_rx_check_considx = 0;
4730                         intr->bnx_tx_check_considx = 0;
4731                         callout_reset_bycpu(&intr->bnx_intr_timer,
4732                             BNX_INTR_CKINTVL, intr->bnx_intr_check, intr,
4733                             intr->bnx_intr_cpuid);
4734                 }
4735         }
4736 }
4737
4738 static void
4739 bnx_disable_intr(struct bnx_softc *sc)
4740 {
4741         int i;
4742
4743         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4744                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4745
4746                 callout_stop(&intr->bnx_intr_timer);
4747                 intr->bnx_intr_maylose = FALSE;
4748                 intr->bnx_rx_check_considx = 0;
4749                 intr->bnx_tx_check_considx = 0;
4750         }
4751
4752         /*
4753          * Mask the interrupt when we start polling.
4754          */
4755         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4756             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4757
4758         /*
4759          * Acknowledge possible asserted interrupt.
4760          */
4761         for (i = 0; i < BNX_INTR_MAX; ++i)
4762                 bnx_writembx(sc, sc->bnx_intr_data[i].bnx_intr_mbx, 1);
4763
4764         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4765                 lwkt_serialize_handler_disable(
4766                     sc->bnx_intr_data[i].bnx_intr_serialize);
4767         }
4768 }
4769
4770 static int
4771 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
4772 {
4773         uint32_t mac_addr;
4774         int ret = 1;
4775
4776         mac_addr = bnx_readmem_ind(sc, 0x0c14);
4777         if ((mac_addr >> 16) == 0x484b) {
4778                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4779                 ether_addr[1] = (uint8_t)mac_addr;
4780                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
4781                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4782                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4783                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4784                 ether_addr[5] = (uint8_t)mac_addr;
4785                 ret = 0;
4786         }
4787         return ret;
4788 }
4789
4790 static int
4791 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4792 {
4793         int mac_offset = BGE_EE_MAC_OFFSET;
4794
4795         if (BNX_IS_5717_PLUS(sc)) {
4796                 int f;
4797
4798                 f = pci_get_function(sc->bnx_dev);
4799                 if (f & 1)
4800                         mac_offset = BGE_EE_MAC_OFFSET_5717;
4801                 if (f > 1)
4802                         mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
4803         }
4804
4805         return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4806 }
4807
4808 static int
4809 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4810 {
4811         if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4812                 return 1;
4813
4814         return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4815                                ETHER_ADDR_LEN);
4816 }
4817
4818 static int
4819 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4820 {
4821         static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4822                 /* NOTE: Order is critical */
4823                 bnx_get_eaddr_mem,
4824                 bnx_get_eaddr_nvram,
4825                 bnx_get_eaddr_eeprom,
4826                 NULL
4827         };
4828         const bnx_eaddr_fcn_t *func;
4829
4830         for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4831                 if ((*func)(sc, eaddr) == 0)
4832                         break;
4833         }
4834         return (*func == NULL ? ENXIO : 0);
4835 }
4836
4837 /*
4838  * NOTE: 'm' is not freed upon failure
4839  */
4840 struct mbuf *
4841 bnx_defrag_shortdma(struct mbuf *m)
4842 {
4843         struct mbuf *n;
4844         int found;
4845
4846         /*
4847          * If device receive two back-to-back send BDs with less than
4848          * or equal to 8 total bytes then the device may hang.  The two
4849          * back-to-back send BDs must in the same frame for this failure
4850          * to occur.  Scan mbuf chains and see whether two back-to-back
4851          * send BDs are there.  If this is the case, allocate new mbuf
4852          * and copy the frame to workaround the silicon bug.
4853          */
4854         for (n = m, found = 0; n != NULL; n = n->m_next) {
4855                 if (n->m_len < 8) {
4856                         found++;
4857                         if (found > 1)
4858                                 break;
4859                         continue;
4860                 }
4861                 found = 0;
4862         }
4863
4864         if (found > 1)
4865                 n = m_defrag(m, MB_DONTWAIT);
4866         else
4867                 n = m;
4868         return n;
4869 }
4870
4871 static void
4872 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4873 {
4874         int i;
4875
4876         BNX_CLRBIT(sc, reg, bit);
4877         for (i = 0; i < BNX_TIMEOUT; i++) {
4878                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4879                         return;
4880                 DELAY(100);
4881         }
4882 }
4883
4884 static void
4885 bnx_link_poll(struct bnx_softc *sc)
4886 {
4887         uint32_t status;
4888
4889         status = CSR_READ_4(sc, BGE_MAC_STS);
4890         if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4891                 sc->bnx_link_evt = 0;
4892                 sc->bnx_link_upd(sc, status);
4893         }
4894 }
4895
4896 static void
4897 bnx_enable_msi(struct bnx_softc *sc, boolean_t is_msix)
4898 {
4899         uint32_t msi_mode;
4900
4901         msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4902         msi_mode |= BGE_MSIMODE_ENABLE;
4903         /*
4904          * NOTE:
4905          * 5718-PG105-R says that "one shot" mode does not work
4906          * if MSI is used, however, it obviously works.
4907          */
4908         msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4909         if (is_msix)
4910                 msi_mode |= BGE_MSIMODE_MSIX_MULTIMODE;
4911         else
4912                 msi_mode &= ~BGE_MSIMODE_MSIX_MULTIMODE;
4913         CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4914 }
4915
4916 static uint32_t
4917 bnx_dma_swap_options(struct bnx_softc *sc)
4918 {
4919         uint32_t dma_options;
4920
4921         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4922             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4923 #if BYTE_ORDER == BIG_ENDIAN
4924         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4925 #endif
4926         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
4927             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
4928                 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4929                     BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4930                     BGE_MODECTL_HTX2B_ENABLE;
4931         }
4932         return dma_options;
4933 }
4934
4935 static int
4936 bnx_setup_tso(struct bnx_tx_ring *txr, struct mbuf **mp,
4937     uint16_t *mss0, uint16_t *flags0)
4938 {
4939         struct mbuf *m;
4940         struct ip *ip;
4941         struct tcphdr *th;
4942         int thoff, iphlen, hoff, hlen;
4943         uint16_t flags, mss;
4944
4945         m = *mp;
4946         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4947
4948         hoff = m->m_pkthdr.csum_lhlen;
4949         iphlen = m->m_pkthdr.csum_iphlen;
4950         thoff = m->m_pkthdr.csum_thlen;
4951
4952         KASSERT(hoff > 0, ("invalid ether header len"));
4953         KASSERT(iphlen > 0, ("invalid ip header len"));
4954         KASSERT(thoff > 0, ("invalid tcp header len"));
4955
4956         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4957                 m = m_pullup(m, hoff + iphlen + thoff);
4958                 if (m == NULL) {
4959                         *mp = NULL;
4960                         return ENOBUFS;
4961                 }
4962                 *mp = m;
4963         }
4964         ip = mtodoff(m, struct ip *, hoff);
4965         th = mtodoff(m, struct tcphdr *, hoff + iphlen);
4966
4967         mss = m->m_pkthdr.tso_segsz;
4968         flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
4969
4970         ip->ip_len = htons(mss + iphlen + thoff);
4971         th->th_sum = 0;
4972
4973         hlen = (iphlen + thoff) >> 2;
4974         mss |= ((hlen & 0x3) << 14);
4975         flags |= ((hlen & 0xf8) << 7) | ((hlen & 0x4) << 2);
4976
4977         *mss0 = mss;
4978         *flags0 = flags;
4979
4980         return 0;
4981 }
4982
4983 static int
4984 bnx_create_tx_ring(struct bnx_tx_ring *txr)
4985 {
4986         bus_size_t txmaxsz, txmaxsegsz;
4987         int i, error;
4988
4989         lwkt_serialize_init(&txr->bnx_tx_serialize);
4990
4991         /*
4992          * Create DMA tag and maps for TX mbufs.
4993          */
4994         if (txr->bnx_sc->bnx_flags & BNX_FLAG_TSO)
4995                 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
4996         else
4997                 txmaxsz = BNX_JUMBO_FRAMELEN;
4998         if (txr->bnx_sc->bnx_asicrev == BGE_ASICREV_BCM57766)
4999                 txmaxsegsz = MCLBYTES;
5000         else
5001                 txmaxsegsz = PAGE_SIZE;
5002         error = bus_dma_tag_create(txr->bnx_sc->bnx_cdata.bnx_parent_tag,
5003             1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
5004             txmaxsz, BNX_NSEG_NEW, txmaxsegsz,
5005             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
5006             &txr->bnx_tx_mtag);
5007         if (error) {
5008                 device_printf(txr->bnx_sc->bnx_dev,
5009                     "could not create TX mbuf DMA tag\n");
5010                 return error;
5011         }
5012
5013         for (i = 0; i < BGE_TX_RING_CNT; i++) {
5014                 error = bus_dmamap_create(txr->bnx_tx_mtag,
5015                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
5016                     &txr->bnx_tx_buf[i].bnx_tx_dmamap);
5017                 if (error) {
5018                         int j;
5019
5020                         for (j = 0; j < i; ++j) {
5021                                 bus_dmamap_destroy(txr->bnx_tx_mtag,
5022                                     txr->bnx_tx_buf[j].bnx_tx_dmamap);
5023                         }
5024                         bus_dma_tag_destroy(txr->bnx_tx_mtag);
5025                         txr->bnx_tx_mtag = NULL;
5026
5027                         device_printf(txr->bnx_sc->bnx_dev,
5028                             "could not create TX mbuf DMA map\n");
5029                         return error;
5030                 }
5031         }
5032
5033         /*
5034          * Create DMA stuffs for TX ring.
5035          */
5036         error = bnx_dma_block_alloc(txr->bnx_sc, BGE_TX_RING_SZ,
5037             &txr->bnx_tx_ring_tag,
5038             &txr->bnx_tx_ring_map,
5039             (void *)&txr->bnx_tx_ring,
5040             &txr->bnx_tx_ring_paddr);
5041         if (error) {
5042                 device_printf(txr->bnx_sc->bnx_dev,
5043                     "could not create TX ring\n");
5044                 return error;
5045         }
5046
5047         txr->bnx_tx_flags |= BNX_TX_FLAG_SHORTDMA;
5048         txr->bnx_tx_wreg = BNX_TX_WREG_NSEGS;
5049
5050         return 0;
5051 }
5052
5053 static void
5054 bnx_destroy_tx_ring(struct bnx_tx_ring *txr)
5055 {
5056         /* Destroy TX mbuf DMA stuffs. */
5057         if (txr->bnx_tx_mtag != NULL) {
5058                 int i;
5059
5060                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
5061                         KKASSERT(txr->bnx_tx_buf[i].bnx_tx_mbuf == NULL);
5062                         bus_dmamap_destroy(txr->bnx_tx_mtag,
5063                             txr->bnx_tx_buf[i].bnx_tx_dmamap);
5064                 }
5065                 bus_dma_tag_destroy(txr->bnx_tx_mtag);
5066         }
5067
5068         /* Destroy TX ring */
5069         bnx_dma_block_free(txr->bnx_tx_ring_tag,
5070             txr->bnx_tx_ring_map, txr->bnx_tx_ring);
5071 }
5072
5073 static int
5074 bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS)
5075 {
5076         struct bnx_softc *sc = (void *)arg1;
5077         struct ifnet *ifp = &sc->arpcom.ac_if;
5078         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
5079         int error, defrag, i;
5080
5081         if (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG)
5082                 defrag = 1;
5083         else
5084                 defrag = 0;
5085
5086         error = sysctl_handle_int(oidp, &defrag, 0, req);
5087         if (error || req->newptr == NULL)
5088                 return error;
5089
5090         ifnet_serialize_all(ifp);
5091         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
5092                 txr = &sc->bnx_tx_ring[i];
5093                 if (defrag)
5094                         txr->bnx_tx_flags |= BNX_TX_FLAG_FORCE_DEFRAG;
5095                 else
5096                         txr->bnx_tx_flags &= ~BNX_TX_FLAG_FORCE_DEFRAG;
5097         }
5098         ifnet_deserialize_all(ifp);
5099
5100         return 0;
5101 }
5102
5103 static int
5104 bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS)
5105 {
5106         struct bnx_softc *sc = (void *)arg1;
5107         struct ifnet *ifp = &sc->arpcom.ac_if;
5108         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
5109         int error, tx_wreg, i;
5110
5111         tx_wreg = txr->bnx_tx_wreg;
5112         error = sysctl_handle_int(oidp, &tx_wreg, 0, req);
5113         if (error || req->newptr == NULL)
5114                 return error;
5115
5116         ifnet_serialize_all(ifp);
5117         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
5118                 sc->bnx_tx_ring[i].bnx_tx_wreg = tx_wreg;
5119         ifnet_deserialize_all(ifp);
5120
5121         return 0;
5122 }
5123
5124 static int
5125 bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *ret)
5126 {
5127         int error;
5128
5129         lwkt_serialize_init(&ret->bnx_rx_ret_serialize);
5130
5131         /*
5132          * Create DMA stuffs for RX return ring.
5133          */
5134         error = bnx_dma_block_alloc(ret->bnx_sc,
5135             BGE_RX_RTN_RING_SZ(BNX_RETURN_RING_CNT),
5136             &ret->bnx_rx_ret_ring_tag,
5137             &ret->bnx_rx_ret_ring_map,
5138             (void *)&ret->bnx_rx_ret_ring,
5139             &ret->bnx_rx_ret_ring_paddr);
5140         if (error) {
5141                 device_printf(ret->bnx_sc->bnx_dev,
5142                     "could not create RX ret ring\n");
5143                 return error;
5144         }
5145
5146         /* Shadow standard ring's RX mbuf DMA tag */
5147         ret->bnx_rx_mtag = ret->bnx_std->bnx_rx_mtag;
5148
5149         /*
5150          * Create tmp DMA map for RX mbufs.
5151          */
5152         error = bus_dmamap_create(ret->bnx_rx_mtag, BUS_DMA_WAITOK,
5153             &ret->bnx_rx_tmpmap);
5154         if (error) {
5155                 device_printf(ret->bnx_sc->bnx_dev,
5156                     "could not create tmp RX mbuf DMA map\n");
5157                 ret->bnx_rx_mtag = NULL;
5158                 return error;
5159         }
5160         return 0;
5161 }
5162
5163 static void
5164 bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *ret)
5165 {
5166         /* Destroy tmp RX mbuf DMA map */
5167         if (ret->bnx_rx_mtag != NULL)
5168                 bus_dmamap_destroy(ret->bnx_rx_mtag, ret->bnx_rx_tmpmap);
5169
5170         /* Destroy RX return ring */
5171         bnx_dma_block_free(ret->bnx_rx_ret_ring_tag,
5172             ret->bnx_rx_ret_ring_map, ret->bnx_rx_ret_ring);
5173 }
5174
5175 static int
5176 bnx_alloc_intr(struct bnx_softc *sc)
5177 {
5178         struct bnx_intr_data *intr;
5179         u_int intr_flags;
5180         int error;
5181
5182         if (sc->bnx_intr_cnt > 1) {
5183                 error = bnx_alloc_msix(sc);
5184                 if (error)
5185                         return error;
5186                 KKASSERT(sc->bnx_intr_type == PCI_INTR_TYPE_MSIX);
5187                 return 0;
5188         }
5189
5190         KKASSERT(sc->bnx_intr_cnt == 1);
5191
5192         intr = &sc->bnx_intr_data[0];
5193         intr->bnx_ret = &sc->bnx_rx_ret_ring[0];
5194         intr->bnx_txr = &sc->bnx_tx_ring[0];
5195         intr->bnx_intr_serialize = &sc->bnx_main_serialize;
5196         intr->bnx_intr_check = bnx_check_intr_rxtx;
5197         intr->bnx_saved_status_tag = &intr->bnx_ret->bnx_saved_status_tag;
5198
5199         sc->bnx_intr_type = pci_alloc_1intr(sc->bnx_dev, bnx_msi_enable,
5200             &intr->bnx_intr_rid, &intr_flags);
5201
5202         intr->bnx_intr_res = bus_alloc_resource_any(sc->bnx_dev, SYS_RES_IRQ,
5203             &intr->bnx_intr_rid, intr_flags);
5204         if (intr->bnx_intr_res == NULL) {
5205                 device_printf(sc->bnx_dev, "could not alloc interrupt\n");
5206                 return ENXIO;
5207         }
5208
5209         if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI) {
5210                 bnx_enable_msi(sc, FALSE);
5211                 intr->bnx_intr_func = bnx_msi;
5212                 if (bootverbose)
5213                         device_printf(sc->bnx_dev, "oneshot MSI\n");
5214         } else {
5215                 intr->bnx_intr_func = bnx_intr_legacy;
5216         }
5217         intr->bnx_intr_arg = sc;
5218         intr->bnx_intr_cpuid = rman_get_cpuid(intr->bnx_intr_res);
5219
5220         intr->bnx_txr->bnx_tx_cpuid = intr->bnx_intr_cpuid;
5221
5222         return 0;
5223 }
5224
5225 static int
5226 bnx_setup_intr(struct bnx_softc *sc)
5227 {
5228         int error, i;
5229
5230         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
5231                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
5232
5233                 error = bus_setup_intr_descr(sc->bnx_dev, intr->bnx_intr_res,
5234                     INTR_MPSAFE, intr->bnx_intr_func, intr->bnx_intr_arg,
5235                     &intr->bnx_intr_hand, intr->bnx_intr_serialize,
5236                     intr->bnx_intr_desc);
5237                 if (error) {
5238                         device_printf(sc->bnx_dev,
5239                             "could not set up %dth intr\n", i);
5240                         bnx_teardown_intr(sc, i);
5241                         return error;
5242                 }
5243         }
5244         return 0;
5245 }
5246
5247 static void
5248 bnx_teardown_intr(struct bnx_softc *sc, int cnt)
5249 {
5250         int i;
5251
5252         for (i = 0; i < cnt; ++i) {
5253                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
5254
5255                 bus_teardown_intr(sc->bnx_dev, intr->bnx_intr_res,
5256                     intr->bnx_intr_hand);
5257         }
5258 }
5259
5260 static void
5261 bnx_free_intr(struct bnx_softc *sc)
5262 {
5263         if (sc->bnx_intr_type != PCI_INTR_TYPE_MSIX) {
5264                 struct bnx_intr_data *intr;
5265
5266                 KKASSERT(sc->bnx_intr_cnt <= 1);
5267                 intr = &sc->bnx_intr_data[0];
5268
5269                 if (intr->bnx_intr_res != NULL) {
5270                         bus_release_resource(sc->bnx_dev, SYS_RES_IRQ,
5271                             intr->bnx_intr_rid, intr->bnx_intr_res);
5272                 }
5273                 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI)
5274                         pci_release_msi(sc->bnx_dev);
5275         } else {
5276                 bnx_free_msix(sc, TRUE);
5277         }
5278 }
5279
5280 static void
5281 bnx_setup_serialize(struct bnx_softc *sc)
5282 {
5283         int i, j;
5284
5285         /*
5286          * Allocate serializer array
5287          */
5288
5289         /* Main + RX STD + TX + RX RET */
5290         sc->bnx_serialize_cnt = 1 + 1 + sc->bnx_tx_ringcnt + sc->bnx_rx_retcnt;
5291
5292         sc->bnx_serialize =
5293             kmalloc(sc->bnx_serialize_cnt * sizeof(struct lwkt_serialize *),
5294                 M_DEVBUF, M_WAITOK | M_ZERO);
5295
5296         /*
5297          * Setup serializers
5298          *
5299          * NOTE: Order is critical
5300          */
5301
5302         i = 0;
5303
5304         KKASSERT(i < sc->bnx_serialize_cnt);
5305         sc->bnx_serialize[i++] = &sc->bnx_main_serialize;
5306
5307         KKASSERT(i < sc->bnx_serialize_cnt);
5308         sc->bnx_serialize[i++] = &sc->bnx_rx_std_ring.bnx_rx_std_serialize;
5309
5310         for (j = 0; j < sc->bnx_rx_retcnt; ++j) {
5311                 KKASSERT(i < sc->bnx_serialize_cnt);
5312                 sc->bnx_serialize[i++] =
5313                     &sc->bnx_rx_ret_ring[j].bnx_rx_ret_serialize;
5314         }
5315
5316         for (j = 0; j < sc->bnx_tx_ringcnt; ++j) {
5317                 KKASSERT(i < sc->bnx_serialize_cnt);
5318                 sc->bnx_serialize[i++] =
5319                     &sc->bnx_tx_ring[j].bnx_tx_serialize;
5320         }
5321
5322         KKASSERT(i == sc->bnx_serialize_cnt);
5323 }
5324
5325 static void
5326 bnx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
5327 {
5328         struct bnx_softc *sc = ifp->if_softc;
5329
5330         ifnet_serialize_array_enter(sc->bnx_serialize,
5331             sc->bnx_serialize_cnt, slz);
5332 }
5333
5334 static void
5335 bnx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
5336 {
5337         struct bnx_softc *sc = ifp->if_softc;
5338
5339         ifnet_serialize_array_exit(sc->bnx_serialize,
5340             sc->bnx_serialize_cnt, slz);
5341 }
5342
5343 static int
5344 bnx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
5345 {
5346         struct bnx_softc *sc = ifp->if_softc;
5347
5348         return ifnet_serialize_array_try(sc->bnx_serialize,
5349             sc->bnx_serialize_cnt, slz);
5350 }
5351
5352 #ifdef INVARIANTS
5353
5354 static void
5355 bnx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
5356     boolean_t serialized)
5357 {
5358         struct bnx_softc *sc = ifp->if_softc;
5359
5360         ifnet_serialize_array_assert(sc->bnx_serialize, sc->bnx_serialize_cnt,
5361             slz, serialized);
5362 }
5363
5364 #endif  /* INVARIANTS */
5365
5366 #ifdef IFPOLL_ENABLE
5367
5368 static int
5369 bnx_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS)
5370 {
5371         struct bnx_softc *sc = (void *)arg1;
5372         struct ifnet *ifp = &sc->arpcom.ac_if;
5373         int error, off;
5374
5375         off = sc->bnx_npoll_rxoff;
5376         error = sysctl_handle_int(oidp, &off, 0, req);
5377         if (error || req->newptr == NULL)
5378                 return error;
5379         if (off < 0)
5380                 return EINVAL;
5381
5382         ifnet_serialize_all(ifp);
5383         if (off >= ncpus2 || off % sc->bnx_rx_retcnt != 0) {
5384                 error = EINVAL;
5385         } else {
5386                 error = 0;
5387                 sc->bnx_npoll_txoff = off;
5388                 sc->bnx_npoll_rxoff = off;
5389         }
5390         ifnet_deserialize_all(ifp);
5391
5392         return error;
5393 }
5394
5395 static int
5396 bnx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
5397 {
5398         struct bnx_softc *sc = (void *)arg1;
5399         struct ifnet *ifp = &sc->arpcom.ac_if;
5400         int error, off;
5401
5402         off = sc->bnx_npoll_rxoff;
5403         error = sysctl_handle_int(oidp, &off, 0, req);
5404         if (error || req->newptr == NULL)
5405                 return error;
5406         if (off < 0)
5407                 return EINVAL;
5408
5409         ifnet_serialize_all(ifp);
5410         if (off >= ncpus2 || off % sc->bnx_rx_retcnt != 0) {
5411                 error = EINVAL;
5412         } else {
5413                 error = 0;
5414                 sc->bnx_npoll_rxoff = off;
5415         }
5416         ifnet_deserialize_all(ifp);
5417
5418         return error;
5419 }
5420
5421 static int
5422 bnx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
5423 {
5424         struct bnx_softc *sc = (void *)arg1;
5425         struct ifnet *ifp = &sc->arpcom.ac_if;
5426         int error, off;
5427
5428         off = sc->bnx_npoll_txoff;
5429         error = sysctl_handle_int(oidp, &off, 0, req);
5430         if (error || req->newptr == NULL)
5431                 return error;
5432         if (off < 0)
5433                 return EINVAL;
5434
5435         ifnet_serialize_all(ifp);
5436         if (off >= ncpus2) {
5437                 error = EINVAL;
5438         } else {
5439                 error = 0;
5440                 sc->bnx_npoll_txoff = off;
5441         }
5442         ifnet_deserialize_all(ifp);
5443
5444         return error;
5445 }
5446
5447 #endif  /* IFPOLL_ENABLE */
5448
5449 static void
5450 bnx_set_tick_cpuid(struct bnx_softc *sc, boolean_t polling)
5451 {
5452         if (polling)
5453                 sc->bnx_tick_cpuid = 0; /* XXX */
5454         else
5455                 sc->bnx_tick_cpuid = sc->bnx_intr_data[0].bnx_intr_cpuid;
5456 }
5457
5458 static void
5459 bnx_rx_std_refill_ithread(void *xstd)
5460 {
5461         struct bnx_rx_std_ring *std = xstd;
5462         struct globaldata *gd = mycpu;
5463
5464         crit_enter_gd(gd);
5465
5466         while (!std->bnx_rx_std_stop) {
5467                 if (std->bnx_rx_std_refill) {
5468                         lwkt_serialize_handler_call(
5469                             &std->bnx_rx_std_serialize,
5470                             bnx_rx_std_refill, std, NULL);
5471                 }
5472
5473                 crit_exit_gd(gd);
5474                 crit_enter_gd(gd);
5475
5476                 atomic_poll_release_int(&std->bnx_rx_std_running);
5477                 cpu_mfence();
5478
5479                 if (!std->bnx_rx_std_refill && !std->bnx_rx_std_stop) {
5480                         lwkt_deschedule_self(gd->gd_curthread);
5481                         lwkt_switch();
5482                 }
5483         }
5484
5485         crit_exit_gd(gd);
5486
5487         wakeup(std);
5488
5489         lwkt_exit();
5490 }
5491
5492 static void
5493 bnx_rx_std_refill(void *xstd, void *frame __unused)
5494 {
5495         struct bnx_rx_std_ring *std = xstd;
5496         int cnt, refill_mask;
5497
5498 again:
5499         cnt = 0;
5500
5501         cpu_lfence();
5502         refill_mask = std->bnx_rx_std_refill;
5503         atomic_clear_int(&std->bnx_rx_std_refill, refill_mask);
5504
5505         while (refill_mask) {
5506                 uint16_t check_idx = std->bnx_rx_std;
5507                 int ret_idx;
5508
5509                 ret_idx = bsfl(refill_mask);
5510                 for (;;) {
5511                         struct bnx_rx_buf *rb;
5512                         int refilled;
5513
5514                         BNX_INC(check_idx, BGE_STD_RX_RING_CNT);
5515                         rb = &std->bnx_rx_std_buf[check_idx];
5516                         refilled = rb->bnx_rx_refilled;
5517                         cpu_lfence();
5518                         if (refilled) {
5519                                 bnx_setup_rxdesc_std(std, check_idx);
5520                                 std->bnx_rx_std = check_idx;
5521                                 ++cnt;
5522                                 if (cnt >= 8) {
5523                                         bnx_writembx(std->bnx_sc,
5524                                             BGE_MBX_RX_STD_PROD_LO,
5525                                             std->bnx_rx_std);
5526                                         cnt = 0;
5527                                 }
5528                         } else {
5529                                 break;
5530                         }
5531                 }
5532                 refill_mask &= ~(1 << ret_idx);
5533         }
5534
5535         if (cnt) {
5536                 bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO,
5537                     std->bnx_rx_std);
5538         }
5539
5540         if (std->bnx_rx_std_refill)
5541                 goto again;
5542
5543         atomic_poll_release_int(&std->bnx_rx_std_running);
5544         cpu_mfence();
5545
5546         if (std->bnx_rx_std_refill)
5547                 goto again;
5548 }
5549
5550 static int
5551 bnx_sysctl_std_refill(SYSCTL_HANDLER_ARGS)
5552 {
5553         struct bnx_softc *sc = (void *)arg1;
5554         struct ifnet *ifp = &sc->arpcom.ac_if;
5555         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
5556         int error, cntmax, i;
5557
5558         cntmax = ret->bnx_rx_cntmax;
5559         error = sysctl_handle_int(oidp, &cntmax, 0, req);
5560         if (error || req->newptr == NULL)
5561                 return error;
5562
5563         ifnet_serialize_all(ifp);
5564
5565         if ((cntmax * sc->bnx_rx_retcnt) > BGE_STD_RX_RING_CNT / 2) {
5566                 error = EINVAL;
5567                 goto back;
5568         }
5569
5570         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
5571                 sc->bnx_rx_ret_ring[i].bnx_rx_cntmax = cntmax;
5572         error = 0;
5573
5574 back:
5575         ifnet_deserialize_all(ifp);
5576
5577         return error;
5578 }
5579
5580 static void
5581 bnx_init_rss(struct bnx_softc *sc)
5582 {
5583         uint8_t key[BGE_RSS_KEYREG_CNT * BGE_RSS_KEYREG_SIZE];
5584         int i, j, r;
5585
5586         KKASSERT(BNX_RSS_ENABLED(sc));
5587
5588         r = 0;
5589         for (j = 0; j < BGE_RSS_INDIR_TBL_CNT; ++j) {
5590                 uint32_t tbl = 0;
5591
5592                 for (i = 0; i < BGE_RSS_INDIR_TBLENT_CNT; ++i) {
5593                         uint32_t q;
5594
5595                         q = r % sc->bnx_rx_retcnt;
5596                         tbl |= q << (BGE_RSS_INDIR_TBLENT_SHIFT *
5597                             (BGE_RSS_INDIR_TBLENT_CNT - i - 1));
5598                         ++r;
5599                 }
5600
5601                 BNX_RSS_DPRINTF(sc, 1, "tbl%d %08x\n", j, tbl);
5602                 CSR_WRITE_4(sc, BGE_RSS_INDIR_TBL(j), tbl);
5603         }
5604
5605         toeplitz_get_key(key, sizeof(key));
5606         for (i = 0; i < BGE_RSS_KEYREG_CNT; ++i) {
5607                 uint32_t keyreg;
5608
5609                 keyreg = BGE_RSS_KEYREG_VAL(key, i);
5610
5611                 BNX_RSS_DPRINTF(sc, 1, "key%d %08x\n", i, keyreg);
5612                 CSR_WRITE_4(sc, BGE_RSS_KEYREG(i), keyreg);
5613         }
5614 }
5615
5616 static void
5617 bnx_setup_ring_cnt(struct bnx_softc *sc)
5618 {
5619         int msix_enable, i, msix_cnt, msix_cnt2, ring_max;
5620
5621         sc->bnx_tx_ringcnt = 1;
5622         sc->bnx_rx_retcnt = 1;
5623         sc->bnx_intr_cnt = 1;
5624
5625         msix_enable = device_getenv_int(sc->bnx_dev, "msix.enable",
5626             bnx_msix_enable);
5627         if (!msix_enable)
5628                 return;
5629
5630         if (ncpus2 == 1)
5631                 return;
5632
5633         msix_cnt = pci_msix_count(sc->bnx_dev);
5634         if (msix_cnt <= 1)
5635                 return;
5636
5637         i = 0;
5638         while ((1 << (i + 1)) <= msix_cnt)
5639                 ++i;
5640         msix_cnt2 = 1 << i;
5641
5642         /*
5643          * One MSI-X vector is dedicated to status or single TX queue,
5644          * so make sure that there are enough MSI-X vectors.
5645          */
5646         if (msix_cnt == msix_cnt2) {
5647                 /*
5648                  * XXX
5649                  * This probably will not happen; 57785/5718 families
5650                  * come with at least 5 MSI-X vectors.
5651                  */
5652                 msix_cnt2 >>= 1;
5653                 if (msix_cnt2 <= 1) {
5654                         device_printf(sc->bnx_dev,
5655                             "MSI-X count %d could not be used\n", msix_cnt);
5656                         return;
5657                 }
5658                 device_printf(sc->bnx_dev, "MSI-X count %d is power of 2\n",
5659                     msix_cnt);
5660         }
5661
5662         /*
5663          * Setup RX ring count
5664          */
5665         ring_max = BNX_RX_RING_MAX;
5666         if (ring_max > msix_cnt2)
5667                 ring_max = msix_cnt2;
5668         sc->bnx_rx_retcnt = device_getenv_int(sc->bnx_dev, "rx_rings",
5669             bnx_rx_rings);
5670         sc->bnx_rx_retcnt = if_ring_count2(sc->bnx_rx_retcnt, ring_max);
5671
5672         if (sc->bnx_rx_retcnt == 1)
5673                 return;
5674
5675         /*
5676          * We need one extra MSI-X vector for link status or
5677          * TX ring (if only one TX ring is enabled).
5678          */
5679         sc->bnx_intr_cnt = sc->bnx_rx_retcnt + 1;
5680
5681         /*
5682          * Setup TX ring count
5683          *
5684          * Currently only BCM5719 and BCM5720 support multiple TX rings
5685          * and the TX ring count must be less than the RX ring count.
5686          */
5687         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
5688             sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
5689                 ring_max = BNX_TX_RING_MAX;
5690                 if (ring_max > msix_cnt2)
5691                         ring_max = msix_cnt2;
5692                 if (ring_max > sc->bnx_rx_retcnt)
5693                         ring_max = sc->bnx_rx_retcnt;
5694                 sc->bnx_tx_ringcnt = device_getenv_int(sc->bnx_dev, "tx_rings",
5695                     bnx_tx_rings);
5696                 sc->bnx_tx_ringcnt = if_ring_count2(sc->bnx_tx_ringcnt,
5697                     ring_max);
5698         }
5699 }
5700
5701 static int
5702 bnx_alloc_msix(struct bnx_softc *sc)
5703 {
5704         struct bnx_intr_data *intr;
5705         boolean_t setup = FALSE;
5706         int error, i, offset, offset_def;
5707
5708         KKASSERT(sc->bnx_intr_cnt > 1);
5709         KKASSERT(sc->bnx_intr_cnt == sc->bnx_rx_retcnt + 1);
5710
5711         if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
5712                 /*
5713                  * Link status
5714                  */
5715                 intr = &sc->bnx_intr_data[0];
5716
5717                 intr->bnx_intr_serialize = &sc->bnx_main_serialize;
5718                 intr->bnx_saved_status_tag = &sc->bnx_saved_status_tag;
5719
5720                 intr->bnx_intr_func = bnx_msix_status;
5721                 intr->bnx_intr_arg = sc;
5722                 intr->bnx_intr_cpuid = 0; /* XXX */
5723
5724                 ksnprintf(intr->bnx_intr_desc0, sizeof(intr->bnx_intr_desc0),
5725                     "%s sts", device_get_nameunit(sc->bnx_dev));
5726                 intr->bnx_intr_desc = intr->bnx_intr_desc0;
5727
5728                 /*
5729                  * RX/TX rings
5730                  */
5731                 if (sc->bnx_rx_retcnt == ncpus2) {
5732                         offset = 0;
5733                 } else {
5734                         offset_def = (sc->bnx_rx_retcnt *
5735                             device_get_unit(sc->bnx_dev)) % ncpus2;
5736
5737                         offset = device_getenv_int(sc->bnx_dev,
5738                             "msix.offset", offset_def);
5739                         if (offset >= ncpus2 ||
5740                             offset % sc->bnx_rx_retcnt != 0) {
5741                                 device_printf(sc->bnx_dev,
5742                                     "invalid msix.offset %d, use %d\n",
5743                                     offset, offset_def);
5744                                 offset = offset_def;
5745                         }
5746                 }
5747
5748                 for (i = 1; i < sc->bnx_intr_cnt; ++i) {
5749                         int idx = i - 1;
5750
5751                         intr = &sc->bnx_intr_data[i];
5752
5753                         KKASSERT(idx < sc->bnx_rx_retcnt);
5754                         intr->bnx_ret = &sc->bnx_rx_ret_ring[idx];
5755                         if (idx < sc->bnx_tx_ringcnt) {
5756                                 intr->bnx_txr = &sc->bnx_tx_ring[idx];
5757                                 intr->bnx_ret->bnx_txr = intr->bnx_txr;
5758                         }
5759
5760                         intr->bnx_intr_serialize =
5761                             &intr->bnx_ret->bnx_rx_ret_serialize;
5762                         intr->bnx_saved_status_tag =
5763                             &intr->bnx_ret->bnx_saved_status_tag;
5764
5765                         intr->bnx_intr_arg = intr->bnx_ret;
5766                         KKASSERT(idx + offset < ncpus2);
5767                         intr->bnx_intr_cpuid = idx + offset;
5768
5769                         if (intr->bnx_txr == NULL) {
5770                                 intr->bnx_intr_check = bnx_check_intr_rx;
5771                                 intr->bnx_intr_func = bnx_msix_rx;
5772                                 ksnprintf(intr->bnx_intr_desc0,
5773                                     sizeof(intr->bnx_intr_desc0), "%s rx%d",
5774                                     device_get_nameunit(sc->bnx_dev), idx);
5775                         } else {
5776                                 intr->bnx_intr_check = bnx_check_intr_rxtx;
5777                                 intr->bnx_intr_func = bnx_msix_rxtx;
5778                                 ksnprintf(intr->bnx_intr_desc0,
5779                                     sizeof(intr->bnx_intr_desc0), "%s rxtx%d",
5780                                     device_get_nameunit(sc->bnx_dev), idx);
5781
5782                                 intr->bnx_txr->bnx_tx_cpuid =
5783                                     intr->bnx_intr_cpuid;
5784                         }
5785                         intr->bnx_intr_desc = intr->bnx_intr_desc0;
5786
5787                         intr->bnx_ret->bnx_msix_mbx = intr->bnx_intr_mbx;
5788                 }
5789         } else {
5790                 /*
5791                  * TX ring and link status
5792                  */
5793                 offset_def = device_get_unit(sc->bnx_dev) % ncpus2;
5794                 offset = device_getenv_int(sc->bnx_dev, "msix.txoff",
5795                     offset_def);
5796                 if (offset >= ncpus2) {
5797                         device_printf(sc->bnx_dev,
5798                             "invalid msix.txoff %d, use %d\n",
5799                             offset, offset_def);
5800                         offset = offset_def;
5801                 }
5802
5803                 intr = &sc->bnx_intr_data[0];
5804
5805                 intr->bnx_txr = &sc->bnx_tx_ring[0];
5806                 intr->bnx_intr_serialize = &sc->bnx_main_serialize;
5807                 intr->bnx_intr_check = bnx_check_intr_tx;
5808                 intr->bnx_saved_status_tag =
5809                     &intr->bnx_txr->bnx_saved_status_tag;
5810
5811                 intr->bnx_intr_func = bnx_msix_tx_status;
5812                 intr->bnx_intr_arg = intr->bnx_txr;
5813                 intr->bnx_intr_cpuid = offset;
5814
5815                 ksnprintf(intr->bnx_intr_desc0, sizeof(intr->bnx_intr_desc0),
5816                     "%s ststx", device_get_nameunit(sc->bnx_dev));
5817                 intr->bnx_intr_desc = intr->bnx_intr_desc0;
5818
5819                 intr->bnx_txr->bnx_tx_cpuid = intr->bnx_intr_cpuid;
5820
5821                 /*
5822                  * RX rings
5823                  */
5824                 if (sc->bnx_rx_retcnt == ncpus2) {
5825                         offset = 0;
5826                 } else {
5827                         offset_def = (sc->bnx_rx_retcnt *
5828                             device_get_unit(sc->bnx_dev)) % ncpus2;
5829
5830                         offset = device_getenv_int(sc->bnx_dev,
5831                             "msix.rxoff", offset_def);
5832                         if (offset >= ncpus2 ||
5833                             offset % sc->bnx_rx_retcnt != 0) {
5834                                 device_printf(sc->bnx_dev,
5835                                     "invalid msix.rxoff %d, use %d\n",
5836                                     offset, offset_def);
5837                                 offset = offset_def;
5838                         }
5839                 }
5840
5841                 for (i = 1; i < sc->bnx_intr_cnt; ++i) {
5842                         int idx = i - 1;
5843
5844                         intr = &sc->bnx_intr_data[i];
5845
5846                         KKASSERT(idx < sc->bnx_rx_retcnt);
5847                         intr->bnx_ret = &sc->bnx_rx_ret_ring[idx];
5848                         intr->bnx_intr_serialize =
5849                             &intr->bnx_ret->bnx_rx_ret_serialize;
5850                         intr->bnx_intr_check = bnx_check_intr_rx;
5851                         intr->bnx_saved_status_tag =
5852                             &intr->bnx_ret->bnx_saved_status_tag;
5853
5854                         intr->bnx_intr_func = bnx_msix_rx;
5855                         intr->bnx_intr_arg = intr->bnx_ret;
5856                         KKASSERT(idx + offset < ncpus2);
5857                         intr->bnx_intr_cpuid = idx + offset;
5858
5859                         ksnprintf(intr->bnx_intr_desc0,
5860                             sizeof(intr->bnx_intr_desc0), "%s rx%d",
5861                             device_get_nameunit(sc->bnx_dev), idx);
5862                         intr->bnx_intr_desc = intr->bnx_intr_desc0;
5863
5864                         intr->bnx_ret->bnx_msix_mbx = intr->bnx_intr_mbx;
5865                 }
5866         }
5867
5868         sc->bnx_msix_mem_rid = PCIR_BAR(4);
5869         sc->bnx_msix_mem_res = bus_alloc_resource_any(sc->bnx_dev,
5870             SYS_RES_MEMORY, &sc->bnx_msix_mem_rid, RF_ACTIVE);
5871         if (sc->bnx_msix_mem_res == NULL) {
5872                 device_printf(sc->bnx_dev, "could not alloc MSI-X table\n");
5873                 return ENXIO;
5874         }
5875
5876         bnx_enable_msi(sc, TRUE);
5877
5878         error = pci_setup_msix(sc->bnx_dev);
5879         if (error) {
5880                 device_printf(sc->bnx_dev, "could not setup MSI-X\n");
5881                 goto back;
5882         }
5883         setup = TRUE;
5884
5885         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
5886                 intr = &sc->bnx_intr_data[i];
5887
5888                 error = pci_alloc_msix_vector(sc->bnx_dev, i,
5889                     &intr->bnx_intr_rid, intr->bnx_intr_cpuid);
5890                 if (error) {
5891                         device_printf(sc->bnx_dev,
5892                             "could not alloc MSI-X %d on cpu%d\n",
5893                             i, intr->bnx_intr_cpuid);
5894                         goto back;
5895                 }
5896
5897                 intr->bnx_intr_res = bus_alloc_resource_any(sc->bnx_dev,
5898                     SYS_RES_IRQ, &intr->bnx_intr_rid, RF_ACTIVE);
5899                 if (intr->bnx_intr_res == NULL) {
5900                         device_printf(sc->bnx_dev,
5901                             "could not alloc MSI-X %d resource\n", i);
5902                         error = ENXIO;
5903                         goto back;
5904                 }
5905         }
5906
5907         pci_enable_msix(sc->bnx_dev);
5908         sc->bnx_intr_type = PCI_INTR_TYPE_MSIX;
5909 back:
5910         if (error)
5911                 bnx_free_msix(sc, setup);
5912         return error;
5913 }
5914
5915 static void
5916 bnx_free_msix(struct bnx_softc *sc, boolean_t setup)
5917 {
5918         int i;
5919
5920         KKASSERT(sc->bnx_intr_cnt > 1);
5921
5922         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
5923                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
5924
5925                 if (intr->bnx_intr_res != NULL) {
5926                         bus_release_resource(sc->bnx_dev, SYS_RES_IRQ,
5927                             intr->bnx_intr_rid, intr->bnx_intr_res);
5928                 }
5929                 if (intr->bnx_intr_rid >= 0) {
5930                         pci_release_msix_vector(sc->bnx_dev,
5931                             intr->bnx_intr_rid);
5932                 }
5933         }
5934         if (setup)
5935                 pci_teardown_msix(sc->bnx_dev);
5936 }
5937
5938 static void
5939 bnx_rx_std_refill_sched_ipi(void *xret)
5940 {
5941         struct bnx_rx_ret_ring *ret = xret;
5942         struct bnx_rx_std_ring *std = ret->bnx_std;
5943         struct globaldata *gd = mycpu;
5944
5945         crit_enter_gd(gd);
5946
5947         atomic_set_int(&std->bnx_rx_std_refill, ret->bnx_rx_mask);
5948         cpu_sfence();
5949
5950         KKASSERT(std->bnx_rx_std_ithread.td_gd == gd);
5951         lwkt_schedule(&std->bnx_rx_std_ithread);
5952
5953         crit_exit_gd(gd);
5954 }
5955
5956 static void
5957 bnx_rx_std_refill_stop(void *xstd)
5958 {
5959         struct bnx_rx_std_ring *std = xstd;
5960         struct globaldata *gd = mycpu;
5961
5962         crit_enter_gd(gd);
5963
5964         std->bnx_rx_std_stop = 1;
5965         cpu_sfence();
5966
5967         KKASSERT(std->bnx_rx_std_ithread.td_gd == gd);
5968         lwkt_schedule(&std->bnx_rx_std_ithread);
5969
5970         crit_exit_gd(gd);
5971 }
5972
5973 static void
5974 bnx_serialize_skipmain(struct bnx_softc *sc)
5975 {
5976         lwkt_serialize_array_enter(sc->bnx_serialize,
5977             sc->bnx_serialize_cnt, 1);
5978 }
5979
5980 static void
5981 bnx_deserialize_skipmain(struct bnx_softc *sc)
5982 {
5983         lwkt_serialize_array_exit(sc->bnx_serialize,
5984             sc->bnx_serialize_cnt, 1);
5985 }
5986
5987 static void
5988 bnx_rx_std_refill_sched(struct bnx_rx_ret_ring *ret,
5989     struct bnx_rx_std_ring *std)
5990 {
5991         struct globaldata *gd = mycpu;
5992
5993         ret->bnx_rx_cnt = 0;
5994         cpu_sfence();
5995
5996         crit_enter_gd(gd);
5997
5998         atomic_set_int(&std->bnx_rx_std_refill, ret->bnx_rx_mask);
5999         cpu_sfence();
6000         if (atomic_poll_acquire_int(&std->bnx_rx_std_running)) {
6001                 if (std->bnx_rx_std_ithread.td_gd == gd) {
6002                         lwkt_schedule(&std->bnx_rx_std_ithread);
6003                 } else {
6004                         lwkt_send_ipiq(
6005                             std->bnx_rx_std_ithread.td_gd,
6006                             bnx_rx_std_refill_sched_ipi, ret);
6007                 }
6008         }
6009
6010         crit_exit_gd(gd);
6011 }
6012
6013 static struct pktinfo *
6014 bnx_rss_info(struct pktinfo *pi, const struct bge_rx_bd *cur_rx)
6015 {
6016         /* Don't pick up IPv6 packet */
6017         if (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6)
6018                 return NULL;
6019
6020         /* Don't pick up IP packet w/o IP checksum */
6021         if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) == 0 ||
6022             (cur_rx->bge_error_flag & BGE_RXERRFLAG_IP_CSUM_NOK))
6023                 return NULL;
6024
6025         /* Don't pick up IP packet w/o TCP/UDP checksum */
6026         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) == 0)
6027                 return NULL;
6028
6029         /* May be IP fragment */
6030         if (cur_rx->bge_tcp_udp_csum != 0xffff)
6031                 return NULL;
6032
6033         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_IS_TCP)
6034                 pi->pi_l3proto = IPPROTO_TCP;
6035         else
6036                 pi->pi_l3proto = IPPROTO_UDP;
6037         pi->pi_netisr = NETISR_IP;
6038         pi->pi_flags = 0;
6039
6040         return pi;
6041 }