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40 #define IX_MAX_MSIX 64
41 #define IX_MAX_MSIX_82598 16
46 #define IX_MAX_RXRING 16
47 #define IX_MIN_RXRING_RSS 2
52 #define IX_MAX_TXRING_82598 32
53 #define IX_MAX_TXRING_82599 64
54 #define IX_MAX_TXRING_X540 64
57 * Default number of segments received before writing to RX related registers
59 #define IX_DEF_RXWREG_NSEGS 32
62 * Default number of segments sent before writing to TX related registers
64 #define IX_DEF_TXWREG_NSEGS 8
67 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
68 * number of transmit descriptors allocated by the driver. Increasing this
69 * value allows the driver to queue more transmits. Each descriptor is 16
70 * bytes. Performance tests have show the 2K value to be optimal for top
73 #define IX_DEF_TXD 1024
74 #define IX_PERF_TXD 2048
75 #define IX_MAX_TXD 4096
79 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
80 * number of receive descriptors allocated for each RX queue. Increasing this
81 * value allows the driver to buffer more incoming packets. Each descriptor
82 * is 16 bytes. A receive buffer is also allocated for each descriptor.
84 * Note: with 8 rings and a dual port card, it is possible to bump up
85 * against the system mbuf pool limit, you can tune nmbclusters
88 #define IX_DEF_RXD 1024
89 #define IX_PERF_RXD 2048
90 #define IX_MAX_RXD 4096
93 /* Alignment for rings */
94 #define IX_DBA_ALIGN 128
96 #define IX_MAX_FRAME_SIZE 0x3F00
98 /* Flow control constants */
99 #define IX_FC_PAUSE 0xFFFF
100 #define IX_FC_HI 0x20000
101 #define IX_FC_LO 0x10000
104 * RSS related registers
107 #define IX_RSSRK_SIZE 4
108 #define IX_RSSRK_VAL(key, i) (key[(i) * IX_RSSRK_SIZE] | \
109 key[(i) * IX_RSSRK_SIZE + 1] << 8 | \
110 key[(i) * IX_RSSRK_SIZE + 2] << 16 | \
111 key[(i) * IX_RSSRK_SIZE + 3] << 24)
113 #define IX_RETA_SIZE 4
118 #define IX_EITR_INTVL_MASK_82598 0xffff
119 #define IX_EITR_INTVL_MASK 0x0fff
120 #define IX_EITR_INTVL_RSVD_MASK 0x0007
121 #define IX_EITR_INTVL_MIN IXGBE_MIN_EITR
122 #define IX_EITR_INTVL_MAX IXGBE_MAX_EITR
125 * Used for optimizing small rx mbufs. Effort is made to keep the copy
126 * small and aligned for the CPU L1 cache.
128 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting
129 * 32 byte alignment needed for the fast bcopy results in 8 bytes being
130 * wasted. Getting 64 byte alignment, which _should_ be ideal for
131 * modern Intel CPUs, results in 40 bytes wasted and a significant drop
132 * in observed efficiency of the optimization, 97.9% -> 81.8%.
134 #define IX_RX_COPY_LEN 160
135 #define IX_RX_COPY_ALIGN (MHLEN - IX_RX_COPY_LEN)
137 #define IX_MAX_MCASTADDR 128
139 #define IX_MSIX_BAR_82598 3
140 #define IX_MSIX_BAR_82599 4
142 #define IX_TSO_SIZE (IP_MAXPACKET + \
143 sizeof(struct ether_vlan_header))
146 * MUST be less than 38. Though 82598 does not have this limit,
147 * we don't want long TX chain. 33 should be large enough even
148 * for 64K TSO (32 x 2K mbuf cluster and 1 x mbuf header).
151 * - 82599 datasheet 7.2.1.1
152 * - X540 datasheet 7.2.1.1
154 #define IX_MAX_SCATTER 33
155 #define IX_TX_RESERVED 3 /* 1 for TX ctx, 2 reserved */
157 /* MSI and legacy interrupt */
158 #define IX_TX_INTR_VEC 0
159 #define IX_TX_INTR_MASK (1 << IX_TX_INTR_VEC)
160 #define IX_RX0_INTR_VEC 1
161 #define IX_RX0_INTR_MASK (1 << IX_RX0_INTR_VEC)
162 #define IX_RX1_INTR_VEC 2
163 #define IX_RX1_INTR_MASK (1 << IX_RX1_INTR_VEC)
165 #define IX_INTR_RATE 8000
166 #define IX_MSIX_RX_RATE 8000
167 #define IX_MSIX_TX_RATE 6000
169 /* IOCTL define to gather SFP+ Diagnostic data */
170 #define SIOCGI2C SIOCGIFGENERIC
172 /* TX checksum offload */
173 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP)
175 #define IX_EICR_STATUS (IXGBE_EICR_LSC | IXGBE_EICR_ECC | \
176 IXGBE_EICR_GPI_SDP1 | IXGBE_EICR_GPI_SDP2 | \
179 /* This is used to get SFP+ module data */
199 #define IX_RX_COPY 0x1
205 struct lwkt_serialize tx_serialize;
206 struct ifaltq_subque *tx_ifsq;
207 struct ix_softc *tx_sc;
208 volatile uint32_t *tx_hdr;
209 union ixgbe_adv_tx_desc *tx_base;
210 struct ix_tx_buf *tx_buf;
211 bus_dma_tag_t tx_tag;
213 #define IX_TXFLAG_ENABLED 0x1
217 uint16_t tx_next_avail;
218 uint16_t tx_next_clean;
220 uint16_t tx_wreg_nsegs;
221 uint16_t tx_intr_nsegs;
226 uint32_t tx_eims_val;
227 struct ifsubq_watchdog tx_watchdog;
229 bus_dma_tag_t tx_base_dtag;
230 bus_dmamap_t tx_base_map;
231 bus_addr_t tx_base_paddr;
233 bus_dma_tag_t tx_hdr_dtag;
234 bus_dmamap_t tx_hdr_map;
235 bus_addr_t tx_hdr_paddr;
239 struct lwkt_serialize rx_serialize;
240 struct ix_softc *rx_sc;
241 union ixgbe_adv_rx_desc *rx_base;
242 struct ix_rx_buf *rx_buf;
243 bus_dma_tag_t rx_tag;
244 bus_dmamap_t rx_sparemap;
247 #define IX_RXRING_FLAG_LRO 0x01
248 #define IX_RXRING_FLAG_DISC 0x02
249 uint16_t rx_next_check;
252 uint16_t rx_wreg_nsegs;
255 uint32_t rx_eims_val;
256 struct ix_tx_ring *rx_txr; /* piggybacked TX ring */
262 bus_dma_tag_t rx_base_dtag;
263 bus_dmamap_t rx_base_map;
264 bus_addr_t rx_base_paddr;
267 struct ix_intr_data {
268 struct lwkt_serialize *intr_serialize;
269 driver_intr_t *intr_func;
271 struct resource *intr_res;
277 #define IX_INTR_USE_RXTX 0
278 #define IX_INTR_USE_STATUS 1
279 #define IX_INTR_USE_RX 2
280 #define IX_INTR_USE_TX 3
281 const char *intr_desc;
286 struct arpcom arpcom;
289 struct ixgbe_osdep osdep;
291 struct lwkt_serialize main_serialize;
294 boolean_t link_active;
299 struct ix_rx_ring *rx_rings;
300 struct ix_tx_ring *tx_rings;
302 struct callout timer;
306 uint32_t fc; /* local flow ctrl setting */
309 boolean_t sfp_probe; /* plyggable optics */
311 struct ixgbe_hw_stats stats;
321 struct ix_intr_data *intr_data;
324 bus_dma_tag_t parent_tag;
325 struct ifmedia media;
327 struct resource *mem_res;
330 struct resource *msix_mem_res;
334 struct lwkt_serialize **serializes;
336 uint8_t *mta; /* Multicast array memory */
339 int advspeed; /* advertised link speeds */
340 uint16_t max_frame_size;
341 int16_t sts_msix_vec; /* status MSI-X vector */
351 #define IX_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1)
352 #define IX_ENABLE_HWTSS(sc) ((sc)->tx_ring_cnt > 1)
354 #endif /* _IF_IX_H_ */