sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_ringbuffer.h"
  34 #include <linux/workqueue.h>
  35
  36 extern struct drm_i915_private *i915_mch_dev;
  37
  38 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  39
  40 #define BEGIN_LP_RING(n) \
  41         intel_ring_begin(LP_RING(dev_priv), (n))
  42
  43 #define OUT_RING(x) \
  44         intel_ring_emit(LP_RING(dev_priv), x)
  45
  46 #define ADVANCE_LP_RING() \
  47         intel_ring_advance(LP_RING(dev_priv))
  48
  49 /**
  50  * Lock test for when it's just for synchronization of ring access.
  51  *
  52  * In that case, we don't need to do it when GEM is initialized as nobody else
  53  * has access to the ring.
  54  */
  55 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  56         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  57                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  58 } while (0)
  59
  60 static inline u32
  61 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  62 {
  63         if (I915_NEED_GFX_HWS(dev_priv->dev))
  64                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  65         else
  66                 return intel_read_status_page(LP_RING(dev_priv), reg);
  67 }
  68
  69 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  70 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  71 #define I915_BREADCRUMB_INDEX           0x21
  72
  73 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  74 {
  75         /*
  76          * The dri breadcrumb update races against the drm master disappearing.
  77          * Instead of trying to fix this (this is by far not the only ums issue)
  78          * just don't do the update in kms mode.
  79          */
  80         if (drm_core_check_feature(dev, DRIVER_MODESET))
  81                 return;
  82
  83         /* XXX: don't do it at all actually */
  84         return;
  85 }
  86
  87 static void i915_write_hws_pga(struct drm_device *dev)
  88 {
  89         drm_i915_private_t *dev_priv = dev->dev_private;
  90         u32 addr;
  91
  92         addr = dev_priv->status_page_dmah->busaddr;
  93         if (INTEL_INFO(dev)->gen >= 4)
  94                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  95         I915_WRITE(HWS_PGA, addr);
  96 }
  97
  98 /**
  99  * Sets up the hardware status page for devices that need a physical address
 100  * in the register.
 101  */
 102 static int i915_init_phys_hws(struct drm_device *dev)
 103 {
 104         drm_i915_private_t *dev_priv = dev->dev_private;
 105         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 106
 107         /*
 108          * Program Hardware Status Page
 109          * XXXKIB Keep 4GB limit for allocation for now.  This method
 110          * of allocation is used on <= 965 hardware, that has several
 111          * erratas regarding the use of physical memory > 4 GB.
 112          */
 113         DRM_UNLOCK(dev);
 114         dev_priv->status_page_dmah =
 115                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 116         DRM_LOCK(dev);
 117         if (!dev_priv->status_page_dmah) {
 118                 DRM_ERROR("Can not allocate hardware status page\n");
 119                 return -ENOMEM;
 120         }
 121         ring->status_page.page_addr = dev_priv->hw_status_page =
 122             dev_priv->status_page_dmah->vaddr;
 123         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 124
 125         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 126
 127         i915_write_hws_pga(dev);
 128         DRM_DEBUG("Enabled hardware status page, phys %jx\n",
 129             (uintmax_t)dev_priv->dma_status_page);
 130         return 0;
 131 }
 132
 133 /**
 134  * Frees the hardware status page, whether it's a physical address or a virtual
 135  * address set up by the X Server.
 136  */
 137 static void i915_free_hws(struct drm_device *dev)
 138 {
 139         drm_i915_private_t *dev_priv = dev->dev_private;
 140         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 141
 142         if (dev_priv->status_page_dmah) {
 143                 drm_pci_free(dev, dev_priv->status_page_dmah);
 144                 dev_priv->status_page_dmah = NULL;
 145         }
 146
 147         if (dev_priv->status_gfx_addr) {
 148                 dev_priv->status_gfx_addr = 0;
 149                 ring->status_page.gfx_addr = 0;
 150                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 151         }
 152
 153         /* Need to rewrite hardware status page */
 154         I915_WRITE(HWS_PGA, 0x1ffff000);
 155 }
 156
 157 void i915_kernel_lost_context(struct drm_device * dev)
 158 {
 159         drm_i915_private_t *dev_priv = dev->dev_private;
 160         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 161
 162         /*
 163          * We should never lose context on the ring with modesetting
 164          * as we don't expose it to userspace
 165          */
 166         if (drm_core_check_feature(dev, DRIVER_MODESET))
 167                 return;
 168
 169         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 170         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 171         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 172         if (ring->space < 0)
 173                 ring->space += ring->size;
 174
 175 #if 1
 176         KIB_NOTYET();
 177 #else
 178         if (!dev->primary->master)
 179                 return;
 180 #endif
 181
 182         if (ring->head == ring->tail && dev_priv->sarea_priv)
 183                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 184 }
 185
 186 static int i915_dma_cleanup(struct drm_device * dev)
 187 {
 188         drm_i915_private_t *dev_priv = dev->dev_private;
 189         int i;
 190
 191
 192         /* Make sure interrupts are disabled here because the uninstall ioctl
 193          * may not have been called from userspace and after dev_private
 194          * is freed, it's too late.
 195          */
 196         if (dev->irq_enabled)
 197                 drm_irq_uninstall(dev);
 198
 199         DRM_LOCK(dev);
 200         for (i = 0; i < I915_NUM_RINGS; i++)
 201                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 202         DRM_UNLOCK(dev);
 203
 204         /* Clear the HWS virtual address at teardown */
 205         if (I915_NEED_GFX_HWS(dev))
 206                 i915_free_hws(dev);
 207
 208         return 0;
 209 }
 210
 211 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 212 {
 213         drm_i915_private_t *dev_priv = dev->dev_private;
 214         int ret;
 215
 216         dev_priv->sarea = drm_getsarea(dev);
 217         if (!dev_priv->sarea) {
 218                 DRM_ERROR("can not find sarea!\n");
 219                 i915_dma_cleanup(dev);
 220                 return -EINVAL;
 221         }
 222
 223         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 224             ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
 225
 226         if (init->ring_size != 0) {
 227                 if (LP_RING(dev_priv)->obj != NULL) {
 228                         i915_dma_cleanup(dev);
 229                         DRM_ERROR("Client tried to initialize ringbuffer in "
 230                                   "GEM mode\n");
 231                         return -EINVAL;
 232                 }
 233
 234                 ret = intel_render_ring_init_dri(dev,
 235                                                  init->ring_start,
 236                                                  init->ring_size);
 237                 if (ret) {
 238                         i915_dma_cleanup(dev);
 239                         return ret;
 240                 }
 241         }
 242
 243         dev_priv->cpp = init->cpp;
 244         dev_priv->back_offset = init->back_offset;
 245         dev_priv->front_offset = init->front_offset;
 246         dev_priv->current_page = 0;
 247         dev_priv->sarea_priv->pf_current_page = 0;
 248
 249         /* Allow hardware batchbuffers unless told otherwise.
 250          */
 251         dev_priv->dri1.allow_batchbuffer = 1;
 252
 253         return 0;
 254 }
 255
 256 static int i915_dma_resume(struct drm_device * dev)
 257 {
 258         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 259         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 260
 261         DRM_DEBUG("\n");
 262
 263         if (ring->virtual_start == NULL) {
 264                 DRM_ERROR("can not ioremap virtual address for"
 265                           " ring buffer\n");
 266                 return -ENOMEM;
 267         }
 268
 269         /* Program Hardware Status Page */
 270         if (!ring->status_page.page_addr) {
 271                 DRM_ERROR("Can not find hardware status page\n");
 272                 return -EINVAL;
 273         }
 274         DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
 275         if (ring->status_page.gfx_addr != 0)
 276                 intel_ring_setup_status_page(ring);
 277         else
 278                 i915_write_hws_pga(dev);
 279
 280         DRM_DEBUG("Enabled hardware status page\n");
 281
 282         return 0;
 283 }
 284
 285 static int i915_dma_init(struct drm_device *dev, void *data,
 286                          struct drm_file *file_priv)
 287 {
 288         drm_i915_init_t *init = data;
 289         int retcode = 0;
 290
 291         switch (init->func) {
 292         case I915_INIT_DMA:
 293                 retcode = i915_initialize(dev, init);
 294                 break;
 295         case I915_CLEANUP_DMA:
 296                 retcode = i915_dma_cleanup(dev);
 297                 break;
 298         case I915_RESUME_DMA:
 299                 retcode = i915_dma_resume(dev);
 300                 break;
 301         default:
 302                 retcode = -EINVAL;
 303                 break;
 304         }
 305
 306         return retcode;
 307 }
 308
 309 /* Implement basically the same security restrictions as hardware does
 310  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 311  *
 312  * Most of the calculations below involve calculating the size of a
 313  * particular instruction.  It's important to get the size right as
 314  * that tells us where the next instruction to check is.  Any illegal
 315  * instruction detected will be given a size of zero, which is a
 316  * signal to abort the rest of the buffer.
 317  */
 318 static int do_validate_cmd(int cmd)
 319 {
 320         switch (((cmd >> 29) & 0x7)) {
 321         case 0x0:
 322                 switch ((cmd >> 23) & 0x3f) {
 323                 case 0x0:
 324                         return 1;       /* MI_NOOP */
 325                 case 0x4:
 326                         return 1;       /* MI_FLUSH */
 327                 default:
 328                         return 0;       /* disallow everything else */
 329                 }
 330                 break;
 331         case 0x1:
 332                 return 0;       /* reserved */
 333         case 0x2:
 334                 return (cmd & 0xff) + 2;        /* 2d commands */
 335         case 0x3:
 336                 if (((cmd >> 24) & 0x1f) <= 0x18)
 337                         return 1;
 338
 339                 switch ((cmd >> 24) & 0x1f) {
 340                 case 0x1c:
 341                         return 1;
 342                 case 0x1d:
 343                         switch ((cmd >> 16) & 0xff) {
 344                         case 0x3:
 345                                 return (cmd & 0x1f) + 2;
 346                         case 0x4:
 347                                 return (cmd & 0xf) + 2;
 348                         default:
 349                                 return (cmd & 0xffff) + 2;
 350                         }
 351                 case 0x1e:
 352                         if (cmd & (1 << 23))
 353                                 return (cmd & 0xffff) + 1;
 354                         else
 355                                 return 1;
 356                 case 0x1f:
 357                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 358                                 return (cmd & 0x1ffff) + 2;
 359                         else if (cmd & (1 << 17))       /* indirect random */
 360                                 if ((cmd & 0xffff) == 0)
 361                                         return 0;       /* unknown length, too hard */
 362                                 else
 363                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 364                         else
 365                                 return 2;       /* indirect sequential */
 366                 default:
 367                         return 0;
 368                 }
 369         default:
 370                 return 0;
 371         }
 372
 373         return 0;
 374 }
 375
 376 static int validate_cmd(int cmd)
 377 {
 378         int ret = do_validate_cmd(cmd);
 379
 380 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 381
 382         return ret;
 383 }
 384
 385 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 386                           int dwords)
 387 {
 388         drm_i915_private_t *dev_priv = dev->dev_private;
 389         int i, ret;
 390
 391         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 392                 return -EINVAL;
 393
 394         ret = BEGIN_LP_RING((dwords+1)&~1);
 395         if (ret)
 396                 return ret;
 397
 398         for (i = 0; i < dwords;) {
 399                 int cmd, sz;
 400
 401                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 402                         return -EINVAL;
 403
 404                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 405                         return -EINVAL;
 406
 407                 OUT_RING(cmd);
 408
 409                 while (++i, --sz) {
 410                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 411                                                          sizeof(cmd))) {
 412                                 return -EINVAL;
 413                         }
 414                         OUT_RING(cmd);
 415                 }
 416         }
 417
 418         if (dwords & 1)
 419                 OUT_RING(0);
 420
 421         ADVANCE_LP_RING();
 422
 423         return 0;
 424 }
 425
 426 int
 427 i915_emit_box(struct drm_device *dev,
 428               struct drm_clip_rect *box,
 429               int DR1, int DR4)
 430 {
 431         struct drm_i915_private *dev_priv = dev->dev_private;
 432         int ret;
 433
 434         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 435             box->y2 <= 0 || box->x2 <= 0) {
 436                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 437                           box->x1, box->y1, box->x2, box->y2);
 438                 return -EINVAL;
 439         }
 440
 441         if (INTEL_INFO(dev)->gen >= 4) {
 442                 ret = BEGIN_LP_RING(4);
 443                 if (ret)
 444                         return ret;
 445
 446                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 447                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 448                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 449                 OUT_RING(DR4);
 450         } else {
 451                 ret = BEGIN_LP_RING(6);
 452                 if (ret)
 453                         return ret;
 454
 455                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 456                 OUT_RING(DR1);
 457                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 458                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 459                 OUT_RING(DR4);
 460                 OUT_RING(0);
 461         }
 462         ADVANCE_LP_RING();
 463
 464         return 0;
 465 }
 466
 467 /* XXX: Emitting the counter should really be moved to part of the IRQ
 468  * emit. For now, do it in both places:
 469  */
 470
 471 static void i915_emit_breadcrumb(struct drm_device *dev)
 472 {
 473         drm_i915_private_t *dev_priv = dev->dev_private;
 474
 475         dev_priv->dri1.counter++;
 476         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 477                 dev_priv->dri1.counter = 0;
 478         if (dev_priv->sarea_priv)
 479                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 480
 481         if (BEGIN_LP_RING(4) == 0) {
 482                 OUT_RING(MI_STORE_DWORD_INDEX);
 483                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 484                 OUT_RING(dev_priv->dri1.counter);
 485                 OUT_RING(0);
 486                 ADVANCE_LP_RING();
 487         }
 488 }
 489
 490 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 491                                    drm_i915_cmdbuffer_t *cmd,
 492                                    struct drm_clip_rect *cliprects,
 493                                    void *cmdbuf)
 494 {
 495         int nbox = cmd->num_cliprects;
 496         int i = 0, count, ret;
 497
 498         if (cmd->sz & 0x3) {
 499                 DRM_ERROR("alignment");
 500                 return -EINVAL;
 501         }
 502
 503         i915_kernel_lost_context(dev);
 504
 505         count = nbox ? nbox : 1;
 506
 507         for (i = 0; i < count; i++) {
 508                 if (i < nbox) {
 509                         ret = i915_emit_box(dev, &cliprects[i],
 510                                             cmd->DR1, cmd->DR4);
 511                         if (ret)
 512                                 return ret;
 513                 }
 514
 515                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 516                 if (ret)
 517                         return ret;
 518         }
 519
 520         i915_emit_breadcrumb(dev);
 521         return 0;
 522 }
 523
 524 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 525                                      drm_i915_batchbuffer_t * batch,
 526                                      struct drm_clip_rect *cliprects)
 527 {
 528         struct drm_i915_private *dev_priv = dev->dev_private;
 529         int nbox = batch->num_cliprects;
 530         int i, count, ret;
 531
 532         if ((batch->start | batch->used) & 0x7) {
 533                 DRM_ERROR("alignment");
 534                 return -EINVAL;
 535         }
 536
 537         i915_kernel_lost_context(dev);
 538
 539         count = nbox ? nbox : 1;
 540         for (i = 0; i < count; i++) {
 541                 if (i < nbox) {
 542                         ret = i915_emit_box(dev, &cliprects[i],
 543                                             batch->DR1, batch->DR4);
 544                         if (ret)
 545                                 return ret;
 546                 }
 547
 548                 if (!IS_I830(dev) && !IS_845G(dev)) {
 549                         ret = BEGIN_LP_RING(2);
 550                         if (ret)
 551                                 return ret;
 552
 553                         if (INTEL_INFO(dev)->gen >= 4) {
 554                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 555                                 OUT_RING(batch->start);
 556                         } else {
 557                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 558                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 559                         }
 560                 } else {
 561                         ret = BEGIN_LP_RING(4);
 562                         if (ret)
 563                                 return ret;
 564
 565                         OUT_RING(MI_BATCH_BUFFER);
 566                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 567                         OUT_RING(batch->start + batch->used - 4);
 568                         OUT_RING(0);
 569                 }
 570                 ADVANCE_LP_RING();
 571         }
 572
 573
 574         if (IS_G4X(dev) || IS_GEN5(dev)) {
 575                 if (BEGIN_LP_RING(2) == 0) {
 576                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 577                         OUT_RING(MI_NOOP);
 578                         ADVANCE_LP_RING();
 579                 }
 580         }
 581
 582         i915_emit_breadcrumb(dev);
 583         return 0;
 584 }
 585
 586 static int i915_dispatch_flip(struct drm_device * dev)
 587 {
 588         drm_i915_private_t *dev_priv = dev->dev_private;
 589         int ret;
 590
 591         if (!dev_priv->sarea_priv)
 592                 return -EINVAL;
 593
 594         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 595                           __func__,
 596                          dev_priv->dri1.current_page,
 597                          dev_priv->sarea_priv->pf_current_page);
 598
 599         i915_kernel_lost_context(dev);
 600
 601         ret = BEGIN_LP_RING(10);
 602         if (ret)
 603                 return ret;
 604
 605         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 606         OUT_RING(0);
 607
 608         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 609         OUT_RING(0);
 610         if (dev_priv->dri1.current_page == 0) {
 611                 OUT_RING(dev_priv->dri1.back_offset);
 612                 dev_priv->dri1.current_page = 1;
 613         } else {
 614                 OUT_RING(dev_priv->dri1.front_offset);
 615                 dev_priv->dri1.current_page = 0;
 616         }
 617         OUT_RING(0);
 618
 619         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 620         OUT_RING(0);
 621
 622         ADVANCE_LP_RING();
 623
 624         dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 625
 626         if (BEGIN_LP_RING(4) == 0) {
 627                 OUT_RING(MI_STORE_DWORD_INDEX);
 628                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 629                 OUT_RING(dev_priv->dri1.counter);
 630                 OUT_RING(0);
 631                 ADVANCE_LP_RING();
 632         }
 633
 634         dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 635         return 0;
 636 }
 637
 638 static int i915_quiescent(struct drm_device *dev)
 639 {
 640         i915_kernel_lost_context(dev);
 641         return intel_ring_idle(LP_RING(dev->dev_private));
 642 }
 643
 644 static int
 645 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
 646 {
 647         int ret;
 648
 649         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 650
 651         DRM_LOCK(dev);
 652         ret = i915_quiescent(dev);
 653         DRM_UNLOCK(dev);
 654
 655         return (ret);
 656 }
 657
 658 static int i915_batchbuffer(struct drm_device *dev, void *data,
 659                             struct drm_file *file_priv)
 660 {
 661         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 662         drm_i915_sarea_t *sarea_priv;
 663         drm_i915_batchbuffer_t *batch = data;
 664         struct drm_clip_rect *cliprects;
 665         size_t cliplen;
 666         int ret;
 667
 668         if (!dev_priv->dri1.allow_batchbuffer) {
 669                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 670                 return -EINVAL;
 671         }
 672
 673         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 674                   batch->start, batch->used, batch->num_cliprects);
 675
 676         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 677
 678         cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
 679         if (batch->num_cliprects < 0)
 680                 return -EFAULT;
 681         if (batch->num_cliprects != 0) {
 682                 cliprects = kmalloc(batch->num_cliprects *
 683                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 684                     M_WAITOK | M_ZERO);
 685
 686                 ret = -copyin(batch->cliprects, cliprects,
 687                     batch->num_cliprects * sizeof(struct drm_clip_rect));
 688                 if (ret != 0) {
 689                         ret = -EFAULT;
 690                         goto fail_free;
 691                 }
 692         } else
 693                 cliprects = NULL;
 694
 695         DRM_LOCK(dev);
 696         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 697         DRM_UNLOCK(dev);
 698
 699         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 700         if (sarea_priv)
 701                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 702
 703 fail_free:
 704         drm_free(cliprects, DRM_MEM_DMA);
 705         return ret;
 706 }
 707
 708 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 709                           struct drm_file *file_priv)
 710 {
 711         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 712         drm_i915_sarea_t *sarea_priv;
 713         drm_i915_cmdbuffer_t *cmdbuf = data;
 714         struct drm_clip_rect *cliprects = NULL;
 715         void *batch_data;
 716         int ret;
 717
 718         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 719                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 720
 721         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 722
 723         if (cmdbuf->num_cliprects < 0)
 724                 return -EINVAL;
 725
 726         batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
 727
 728         ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
 729         if (ret != 0) {
 730                 ret = -EFAULT;
 731                 goto fail_batch_free;
 732         }
 733
 734         if (cmdbuf->num_cliprects) {
 735                 cliprects = kmalloc(cmdbuf->num_cliprects *
 736                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 737                     M_WAITOK | M_ZERO);
 738                 ret = -copyin(cmdbuf->cliprects, cliprects,
 739                     cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
 740
 741                 if (ret != 0) {
 742                         ret = -EFAULT;
 743                         goto fail_clip_free;
 744                 }
 745         }
 746
 747         DRM_LOCK(dev);
 748         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 749         DRM_UNLOCK(dev);
 750         if (ret) {
 751                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 752                 goto fail_clip_free;
 753         }
 754
 755         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 756         if (sarea_priv)
 757                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 758
 759 fail_clip_free:
 760         drm_free(cliprects, DRM_MEM_DMA);
 761 fail_batch_free:
 762         drm_free(batch_data, DRM_MEM_DMA);
 763         return ret;
 764 }
 765
 766 static int i915_emit_irq(struct drm_device * dev)
 767 {
 768         drm_i915_private_t *dev_priv = dev->dev_private;
 769 #if 0
 770         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 771 #endif
 772
 773         i915_kernel_lost_context(dev);
 774
 775         DRM_DEBUG_DRIVER("\n");
 776
 777         dev_priv->dri1.counter++;
 778         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 779                 dev_priv->dri1.counter = 1;
 780         if (dev_priv->sarea_priv)
 781                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 782
 783         if (BEGIN_LP_RING(4) == 0) {
 784                 OUT_RING(MI_STORE_DWORD_INDEX);
 785                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 786                 OUT_RING(dev_priv->dri1.counter);
 787                 OUT_RING(MI_USER_INTERRUPT);
 788                 ADVANCE_LP_RING();
 789         }
 790
 791         return dev_priv->dri1.counter;
 792 }
 793
 794 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 795 {
 796         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 797 #if 0
 798         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 799 #endif
 800         int ret = 0;
 801         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 802
 803         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 804                   READ_BREADCRUMB(dev_priv));
 805
 806 #if 0
 807         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 808                 if (master_priv->sarea_priv)
 809                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 810                 return 0;
 811         }
 812
 813         if (master_priv->sarea_priv)
 814                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 815 #else
 816         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 817                 if (dev_priv->sarea_priv) {
 818                         dev_priv->sarea_priv->last_dispatch =
 819                                 READ_BREADCRUMB(dev_priv);
 820                 }
 821                 return 0;
 822         }
 823
 824         if (dev_priv->sarea_priv)
 825                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 826 #endif
 827
 828         if (ring->irq_get(ring)) {
 829                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 830                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 831                 ring->irq_put(ring);
 832         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 833                 ret = -EBUSY;
 834
 835         if (ret == -EBUSY) {
 836                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 837                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 838         }
 839
 840         return ret;
 841 }
 842
 843 /* Needs the lock as it touches the ring.
 844  */
 845 int i915_irq_emit(struct drm_device *dev, void *data,
 846                          struct drm_file *file_priv)
 847 {
 848         drm_i915_private_t *dev_priv = dev->dev_private;
 849         drm_i915_irq_emit_t *emit = data;
 850         int result;
 851
 852         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 853                 DRM_ERROR("called with no initialization\n");
 854                 return -EINVAL;
 855         }
 856
 857         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 858
 859         DRM_LOCK(dev);
 860         result = i915_emit_irq(dev);
 861         DRM_UNLOCK(dev);
 862
 863         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 864                 DRM_ERROR("copy_to_user\n");
 865                 return -EFAULT;
 866         }
 867
 868         return 0;
 869 }
 870
 871 /* Doesn't need the hardware lock.
 872  */
 873 int i915_irq_wait(struct drm_device *dev, void *data,
 874                          struct drm_file *file_priv)
 875 {
 876         drm_i915_private_t *dev_priv = dev->dev_private;
 877         drm_i915_irq_wait_t *irqwait = data;
 878
 879         if (!dev_priv) {
 880                 DRM_ERROR("called with no initialization\n");
 881                 return -EINVAL;
 882         }
 883
 884         return i915_wait_irq(dev, irqwait->irq_seq);
 885 }
 886
 887 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 888                          struct drm_file *file_priv)
 889 {
 890         drm_i915_private_t *dev_priv = dev->dev_private;
 891         drm_i915_vblank_pipe_t *pipe = data;
 892
 893         if (drm_core_check_feature(dev, DRIVER_MODESET))
 894                 return -ENODEV;
 895
 896         if (!dev_priv) {
 897                 DRM_ERROR("called with no initialization\n");
 898                 return -EINVAL;
 899         }
 900
 901         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 902
 903         return 0;
 904 }
 905
 906 /**
 907  * Schedule buffer swap at given vertical blank.
 908  */
 909 static int i915_vblank_swap(struct drm_device *dev, void *data,
 910                      struct drm_file *file_priv)
 911 {
 912         /* The delayed swap mechanism was fundamentally racy, and has been
 913          * removed.  The model was that the client requested a delayed flip/swap
 914          * from the kernel, then waited for vblank before continuing to perform
 915          * rendering.  The problem was that the kernel might wake the client
 916          * up before it dispatched the vblank swap (since the lock has to be
 917          * held while touching the ringbuffer), in which case the client would
 918          * clear and start the next frame before the swap occurred, and
 919          * flicker would occur in addition to likely missing the vblank.
 920          *
 921          * In the absence of this ioctl, userland falls back to a correct path
 922          * of waiting for a vblank, then dispatching the swap on its own.
 923          * Context switching to userland and back is plenty fast enough for
 924          * meeting the requirements of vblank swapping.
 925          */
 926         return -EINVAL;
 927 }
 928
 929 static int i915_flip_bufs(struct drm_device *dev, void *data,
 930                           struct drm_file *file_priv)
 931 {
 932         int ret;
 933
 934         DRM_DEBUG("%s\n", __func__);
 935
 936         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 937
 938         DRM_LOCK(dev);
 939         ret = i915_dispatch_flip(dev);
 940         DRM_UNLOCK(dev);
 941
 942         return ret;
 943 }
 944
 945 static int i915_getparam(struct drm_device *dev, void *data,
 946                          struct drm_file *file_priv)
 947 {
 948         drm_i915_private_t *dev_priv = dev->dev_private;
 949         drm_i915_getparam_t *param = data;
 950         int value;
 951
 952         if (!dev_priv) {
 953                 DRM_ERROR("called with no initialization\n");
 954                 return -EINVAL;
 955         }
 956
 957         switch (param->param) {
 958         case I915_PARAM_IRQ_ACTIVE:
 959                 value = dev->irq_enabled ? 1 : 0;
 960                 break;
 961         case I915_PARAM_ALLOW_BATCHBUFFER:
 962                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 963                 break;
 964         case I915_PARAM_LAST_DISPATCH:
 965                 value = READ_BREADCRUMB(dev_priv);
 966                 break;
 967         case I915_PARAM_CHIPSET_ID:
 968                 value = dev->pci_device;
 969                 break;
 970         case I915_PARAM_HAS_GEM:
 971                 value = 1;
 972                 break;
 973         case I915_PARAM_NUM_FENCES_AVAIL:
 974                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 975                 break;
 976         case I915_PARAM_HAS_OVERLAY:
 977                 value = dev_priv->overlay ? 1 : 0;
 978                 break;
 979         case I915_PARAM_HAS_PAGEFLIPPING:
 980                 value = 1;
 981                 break;
 982         case I915_PARAM_HAS_EXECBUF2:
 983                 /* depends on GEM */
 984                 value = 1;
 985                 break;
 986         case I915_PARAM_HAS_BSD:
 987                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 988                 break;
 989         case I915_PARAM_HAS_BLT:
 990                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 991                 break;
 992         case I915_PARAM_HAS_RELAXED_FENCING:
 993                 value = 1;
 994                 break;
 995         case I915_PARAM_HAS_COHERENT_RINGS:
 996                 value = 1;
 997                 break;
 998         case I915_PARAM_HAS_EXEC_CONSTANTS:
 999                 value = INTEL_INFO(dev)->gen >= 4;
1000                 break;
1001         case I915_PARAM_HAS_RELAXED_DELTA:
1002                 value = 1;
1003                 break;
1004         case I915_PARAM_HAS_GEN7_SOL_RESET:
1005                 value = 1;
1006                 break;
1007         case I915_PARAM_HAS_LLC:
1008                 value = HAS_LLC(dev);
1009                 break;
1010         case I915_PARAM_HAS_ALIASING_PPGTT:
1011                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
1012                 break;
1013         case I915_PARAM_HAS_PINNED_BATCHES:
1014                 value = 1;
1015                 break;
1016         default:
1017                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1018                                  param->param);
1019                 return -EINVAL;
1020         }
1021
1022         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1023                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1024                 return -EFAULT;
1025         }
1026
1027         return 0;
1028 }
1029
1030 static int i915_setparam(struct drm_device *dev, void *data,
1031                          struct drm_file *file_priv)
1032 {
1033         drm_i915_private_t *dev_priv = dev->dev_private;
1034         drm_i915_setparam_t *param = data;
1035
1036         if (!dev_priv) {
1037                 DRM_ERROR("called with no initialization\n");
1038                 return -EINVAL;
1039         }
1040
1041         switch (param->param) {
1042         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1043                 break;
1044         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1045                 break;
1046         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1047                 dev_priv->dri1.allow_batchbuffer = param->value;
1048                 break;
1049         case I915_SETPARAM_NUM_USED_FENCES:
1050                 if (param->value > dev_priv->num_fence_regs ||
1051                     param->value < 0)
1052                         return -EINVAL;
1053                 /* Userspace can use first N regs */
1054                 dev_priv->fence_reg_start = param->value;
1055                 break;
1056         default:
1057                 DRM_DEBUG("unknown parameter %d\n", param->param);
1058                 return -EINVAL;
1059         }
1060
1061         return 0;
1062 }
1063
1064 static int i915_set_status_page(struct drm_device *dev, void *data,
1065                                 struct drm_file *file_priv)
1066 {
1067         drm_i915_private_t *dev_priv = dev->dev_private;
1068         drm_i915_hws_addr_t *hws = data;
1069         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1070
1071         if (!I915_NEED_GFX_HWS(dev))
1072                 return -EINVAL;
1073
1074         if (!dev_priv) {
1075                 DRM_ERROR("called with no initialization\n");
1076                 return -EINVAL;
1077         }
1078
1079         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1080         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1081                 DRM_ERROR("tried to set status page when mode setting active\n");
1082                 return 0;
1083         }
1084
1085         ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
1086             hws->addr & (0x1ffff<<12);
1087
1088         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1089         dev_priv->hws_map.size = 4*1024;
1090         dev_priv->hws_map.type = 0;
1091         dev_priv->hws_map.flags = 0;
1092         dev_priv->hws_map.mtrr = 0;
1093
1094         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
1095         if (dev_priv->hws_map.virtual == NULL) {
1096                 i915_dma_cleanup(dev);
1097                 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
1098                 DRM_ERROR("can not ioremap virtual address for"
1099                                 " G33 hw status page\n");
1100                 return -ENOMEM;
1101         }
1102         ring->status_page.page_addr = dev_priv->hw_status_page =
1103             dev_priv->hws_map.virtual;
1104
1105         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1106         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
1107         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
1108                         dev_priv->status_gfx_addr);
1109         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1110         return 0;
1111 }
1112
1113 static int i915_load_modeset_init(struct drm_device *dev)
1114 {
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         int ret;
1117
1118         ret = intel_parse_bios(dev);
1119         if (ret)
1120                 DRM_INFO("failed to find VBIOS tables\n");
1121
1122 #if 0
1123         /* If we have > 1 VGA cards, then we need to arbitrate access
1124          * to the common VGA resources.
1125          *
1126          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1127          * then we do not take part in VGA arbitration and the
1128          * vga_client_register() fails with -ENODEV.
1129          */
1130         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1131         if (ret && ret != -ENODEV)
1132                 goto out;
1133
1134         intel_register_dsm_handler();
1135
1136         ret = vga_switcheroo_register_client(dev->pdev,
1137                                              i915_switcheroo_set_state,
1138                                              NULL,
1139                                              i915_switcheroo_can_switch);
1140         if (ret)
1141                 goto cleanup_vga_client;
1142
1143         /* Initialise stolen first so that we may reserve preallocated
1144          * objects for the BIOS to KMS transition.
1145          */
1146         ret = i915_gem_init_stolen(dev);
1147         if (ret)
1148                 goto cleanup_vga_switcheroo;
1149 #endif
1150
1151         intel_modeset_init(dev);
1152
1153         ret = i915_gem_init(dev);
1154         if (ret)
1155                 goto cleanup_gem_stolen;
1156
1157         intel_modeset_gem_init(dev);
1158
1159         ret = drm_irq_install(dev);
1160         if (ret)
1161                 goto cleanup_gem;
1162
1163         /* Always safe in the mode setting case. */
1164         /* FIXME: do pre/post-mode set stuff in core KMS code */
1165         dev->vblank_disable_allowed = 1;
1166
1167         ret = intel_fbdev_init(dev);
1168         if (ret)
1169                 goto cleanup_irq;
1170
1171         drm_kms_helper_poll_init(dev);
1172
1173         /* We're off and running w/KMS */
1174         dev_priv->mm.suspended = 0;
1175
1176         return 0;
1177
1178 cleanup_irq:
1179         drm_irq_uninstall(dev);
1180 cleanup_gem:
1181         DRM_LOCK(dev);
1182         i915_gem_cleanup_ringbuffer(dev);
1183         DRM_UNLOCK(dev);
1184         i915_gem_cleanup_aliasing_ppgtt(dev);
1185 cleanup_gem_stolen:
1186 #if 0
1187         i915_gem_cleanup_stolen(dev);
1188 cleanup_vga_switcheroo:
1189         vga_switcheroo_unregister_client(dev->pdev);
1190 cleanup_vga_client:
1191         vga_client_register(dev->pdev, NULL, NULL, NULL);
1192 out:
1193 #endif
1194         return ret;
1195 }
1196
1197 static int i915_get_bridge_dev(struct drm_device *dev)
1198 {
1199         struct drm_i915_private *dev_priv = dev->dev_private;
1200
1201         dev_priv->bridge_dev = pci_find_dbsf(0, 0, 0, 0);
1202         if (!dev_priv->bridge_dev) {
1203                 DRM_ERROR("bridge device not found\n");
1204                 return -1;
1205         }
1206         return 0;
1207 }
1208
1209 #define MCHBAR_I915 0x44
1210 #define MCHBAR_I965 0x48
1211 #define MCHBAR_SIZE (4*4096)
1212
1213 #define DEVEN_REG 0x54
1214 #define   DEVEN_MCHBAR_EN (1 << 28)
1215
1216 /* Allocate space for the MCH regs if needed, return nonzero on error */
1217 static int
1218 intel_alloc_mchbar_resource(struct drm_device *dev)
1219 {
1220         drm_i915_private_t *dev_priv;
1221         device_t vga;
1222         int reg;
1223         u32 temp_lo, temp_hi;
1224         u64 mchbar_addr, temp;
1225
1226         dev_priv = dev->dev_private;
1227         reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1228
1229         if (INTEL_INFO(dev)->gen >= 4)
1230                 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1231         else
1232                 temp_hi = 0;
1233         temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1234         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1235
1236         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1237 #ifdef XXX_CONFIG_PNP
1238         if (mchbar_addr &&
1239             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1240                 return 0;
1241 #endif
1242
1243         /* Get some space for it */
1244         vga = device_get_parent(dev->dev);
1245         dev_priv->mch_res_rid = 0x100;
1246         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1247             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1248             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1249         if (dev_priv->mch_res == NULL) {
1250                 DRM_ERROR("failed mchbar resource alloc\n");
1251                 return (-ENOMEM);
1252         }
1253
1254         if (INTEL_INFO(dev)->gen >= 4) {
1255                 temp = rman_get_start(dev_priv->mch_res);
1256                 temp >>= 32;
1257                 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1258         }
1259         pci_write_config(dev_priv->bridge_dev, reg,
1260             rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1261         return (0);
1262 }
1263
1264 static void
1265 intel_setup_mchbar(struct drm_device *dev)
1266 {
1267         drm_i915_private_t *dev_priv;
1268         int mchbar_reg;
1269         u32 temp;
1270         bool enabled;
1271
1272         dev_priv = dev->dev_private;
1273         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1274
1275         dev_priv->mchbar_need_disable = false;
1276
1277         if (IS_I915G(dev) || IS_I915GM(dev)) {
1278                 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1279                 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1280         } else {
1281                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1282                 enabled = temp & 1;
1283         }
1284
1285         /* If it's already enabled, don't have to do anything */
1286         if (enabled) {
1287                 DRM_DEBUG("mchbar already enabled\n");
1288                 return;
1289         }
1290
1291         if (intel_alloc_mchbar_resource(dev))
1292                 return;
1293
1294         dev_priv->mchbar_need_disable = true;
1295
1296         /* Space is allocated or reserved, so enable it. */
1297         if (IS_I915G(dev) || IS_I915GM(dev)) {
1298                 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1299                     temp | DEVEN_MCHBAR_EN, 4);
1300         } else {
1301                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1302                 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1303         }
1304 }
1305
1306 static void
1307 intel_teardown_mchbar(struct drm_device *dev)
1308 {
1309         drm_i915_private_t *dev_priv;
1310         device_t vga;
1311         int mchbar_reg;
1312         u32 temp;
1313
1314         dev_priv = dev->dev_private;
1315         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1316
1317         if (dev_priv->mchbar_need_disable) {
1318                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1319                         temp = pci_read_config(dev_priv->bridge_dev,
1320                             DEVEN_REG, 4);
1321                         temp &= ~DEVEN_MCHBAR_EN;
1322                         pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1323                             temp, 4);
1324                 } else {
1325                         temp = pci_read_config(dev_priv->bridge_dev,
1326                             mchbar_reg, 4);
1327                         temp &= ~1;
1328                         pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1329                             temp, 4);
1330                 }
1331         }
1332
1333         if (dev_priv->mch_res != NULL) {
1334                 vga = device_get_parent(dev->dev);
1335                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1336                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1337                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1338                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1339                 dev_priv->mch_res = NULL;
1340         }
1341 }
1342
1343 /**
1344  * i915_driver_load - setup chip and create an initial config
1345  * @dev: DRM device
1346  * @flags: startup flags
1347  *
1348  * The driver load routine has to do several things:
1349  *   - drive output discovery via intel_modeset_init()
1350  *   - initialize the memory manager
1351  *   - allocate initial config memory
1352  *   - setup the DRM framebuffer with the allocated memory
1353  */
1354 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1355 {
1356         struct drm_i915_private *dev_priv = dev->dev_private;
1357         unsigned long base, size;
1358         int mmio_bar, ret;
1359
1360         ret = 0;
1361
1362         /* i915 has 4 more counters */
1363         dev->counters += 4;
1364         dev->types[6] = _DRM_STAT_IRQ;
1365         dev->types[7] = _DRM_STAT_PRIMARY;
1366         dev->types[8] = _DRM_STAT_SECONDARY;
1367         dev->types[9] = _DRM_STAT_DMA;
1368
1369         dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1370             M_ZERO | M_WAITOK);
1371         if (dev_priv == NULL)
1372                 return -ENOMEM;
1373
1374         dev->dev_private = (void *)dev_priv;
1375         dev_priv->dev = dev;
1376         dev_priv->info = i915_get_device_id(dev->pci_device);
1377
1378         if (i915_get_bridge_dev(dev)) {
1379                 drm_free(dev_priv, DRM_MEM_DRIVER);
1380                 return (-EIO);
1381         }
1382         dev_priv->mm.gtt = intel_gtt_get();
1383
1384         /* Add register map (needed for suspend/resume) */
1385         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1386         base = drm_get_resource_start(dev, mmio_bar);
1387         size = drm_get_resource_len(dev, mmio_bar);
1388
1389         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1390             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1391
1392         /* The i915 workqueue is primarily used for batched retirement of
1393          * requests (and thus managing bo) once the task has been completed
1394          * by the GPU. i915_gem_retire_requests() is called directly when we
1395          * need high-priority retirement, such as waiting for an explicit
1396          * bo.
1397          *
1398          * It is also used for periodic low-priority events, such as
1399          * idle-timers and recording error state.
1400          *
1401          * All tasks on the workqueue are expected to acquire the dev mutex
1402          * so there is no point in running more than one instance of the
1403          * workqueue at any time.  Use an ordered one.
1404          */
1405         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1406         if (dev_priv->wq == NULL) {
1407                 DRM_ERROR("Failed to create our workqueue.\n");
1408                 ret = -ENOMEM;
1409                 goto out_mtrrfree;
1410         }
1411
1412         /* This must be called before any calls to HAS_PCH_* */
1413         intel_detect_pch(dev);
1414
1415         intel_irq_init(dev);
1416         intel_gt_init(dev);
1417
1418         /* Try to make sure MCHBAR is enabled before poking at it */
1419         intel_setup_mchbar(dev);
1420         intel_setup_gmbus(dev);
1421         intel_opregion_setup(dev);
1422
1423         intel_setup_bios(dev);
1424
1425         i915_gem_load(dev);
1426
1427         /* On the 945G/GM, the chipset reports the MSI capability on the
1428          * integrated graphics even though the support isn't actually there
1429          * according to the published specs.  It doesn't appear to function
1430          * correctly in testing on 945G.
1431          * This may be a side effect of MSI having been made available for PEG
1432          * and the registers being closely associated.
1433          *
1434          * According to chipset errata, on the 965GM, MSI interrupts may
1435          * be lost or delayed, but we use them anyways to avoid
1436          * stuck interrupts on some machines.
1437          */
1438
1439         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1440         lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1441         spin_init(&dev_priv->rps.lock);
1442         spin_init(&dev_priv->dpio_lock);
1443
1444         lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1445
1446         /* Init HWS */
1447         if (!I915_NEED_GFX_HWS(dev)) {
1448                 ret = i915_init_phys_hws(dev);
1449                 if (ret != 0) {
1450                         drm_rmmap(dev, dev_priv->mmio_map);
1451                         drm_free(dev_priv, DRM_MEM_DRIVER);
1452                         return ret;
1453                 }
1454         }
1455
1456         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1457                 dev_priv->num_pipe = 3;
1458         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1459                 dev_priv->num_pipe = 2;
1460         else
1461                 dev_priv->num_pipe = 1;
1462
1463         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1464         if (ret)
1465                 goto out_gem_unload;
1466
1467         /* Start out suspended */
1468         dev_priv->mm.suspended = 1;
1469
1470         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1471                 ret = i915_load_modeset_init(dev);
1472                 if (ret < 0) {
1473                         DRM_ERROR("failed to init modeset\n");
1474                         goto out_gem_unload;
1475                 }
1476         }
1477
1478         /* Must be done after probing outputs */
1479         intel_opregion_init(dev);
1480
1481         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1482                     (unsigned long) dev);
1483
1484         if (IS_GEN5(dev))
1485                 intel_gpu_ips_init(dev_priv);
1486
1487         return 0;
1488
1489 out_gem_unload:
1490         intel_teardown_gmbus(dev);
1491         intel_teardown_mchbar(dev);
1492         destroy_workqueue(dev_priv->wq);
1493 out_mtrrfree:
1494         return ret;
1495 }
1496
1497 int i915_driver_unload(struct drm_device *dev)
1498 {
1499         struct drm_i915_private *dev_priv = dev->dev_private;
1500         int ret;
1501
1502         intel_gpu_ips_teardown();
1503
1504         DRM_LOCK(dev);
1505         ret = i915_gpu_idle(dev);
1506         if (ret)
1507                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1508         i915_gem_retire_requests(dev);
1509         DRM_UNLOCK(dev);
1510
1511         /* Cancel the retire work handler, which should be idle now. */
1512         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1513
1514         i915_free_hws(dev);
1515
1516         intel_teardown_mchbar(dev);
1517
1518         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1519                 intel_fbdev_fini(dev);
1520                 intel_modeset_cleanup(dev);
1521         }
1522
1523         /* Free error state after interrupts are fully disabled. */
1524         del_timer_sync(&dev_priv->hangcheck_timer);
1525         cancel_work_sync(&dev_priv->error_work);
1526         i915_destroy_error_state(dev);
1527
1528         intel_opregion_fini(dev);
1529
1530         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1531                 /* Flush any outstanding unpin_work. */
1532                 flush_workqueue(dev_priv->wq);
1533
1534                 DRM_LOCK(dev);
1535                 i915_gem_free_all_phys_object(dev);
1536                 i915_gem_cleanup_ringbuffer(dev);
1537                 DRM_UNLOCK(dev);
1538                 i915_gem_cleanup_aliasing_ppgtt(dev);
1539                 drm_mm_takedown(&dev_priv->mm.stolen);
1540
1541                 intel_cleanup_overlay(dev);
1542
1543                 if (!I915_NEED_GFX_HWS(dev))
1544                         i915_free_hws(dev);
1545         }
1546
1547         i915_gem_unload(dev);
1548
1549         bus_generic_detach(dev->dev);
1550         drm_rmmap(dev, dev_priv->mmio_map);
1551         intel_teardown_gmbus(dev);
1552
1553         destroy_workqueue(dev_priv->wq);
1554
1555         drm_free(dev->dev_private, DRM_MEM_DRIVER);
1556
1557         return 0;
1558 }
1559
1560 int
1561 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1562 {
1563         struct drm_i915_file_private *i915_file_priv;
1564
1565         i915_file_priv = kmalloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1566             M_WAITOK | M_ZERO);
1567
1568         spin_init(&i915_file_priv->mm.lock);
1569         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1570         file_priv->driver_priv = i915_file_priv;
1571
1572         return (0);
1573 }
1574
1575 void
1576 i915_driver_lastclose(struct drm_device * dev)
1577 {
1578         drm_i915_private_t *dev_priv = dev->dev_private;
1579
1580         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1581 #if 1
1582                 KIB_NOTYET();
1583 #else
1584                 drm_fb_helper_restore();
1585                 vga_switcheroo_process_delayed_switch();
1586 #endif
1587                 return;
1588         }
1589         i915_gem_lastclose(dev);
1590         i915_dma_cleanup(dev);
1591 }
1592
1593 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1594 {
1595
1596         i915_gem_release(dev, file_priv);
1597 }
1598
1599 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1600 {
1601         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1602
1603         spin_uninit(&i915_file_priv->mm.lock);
1604         drm_free(i915_file_priv, DRM_MEM_FILES);
1605 }
1606
1607 struct drm_ioctl_desc i915_ioctls[] = {
1608         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1609         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1610         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1611         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1612         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1613         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1614         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1615         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1616         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1617         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1618         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1619         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1620         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1621         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1622         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1623         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1624         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1625         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1626         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1627         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1628         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1629         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1630         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1631         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1632         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1633         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1634         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1635         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1636         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1637         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1638         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1639         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1640         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1641         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1642         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1643         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1644         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1645         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1646         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1647         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1648         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1649         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1650 };
1651
1652 struct drm_driver i915_driver_info = {
1653         .driver_features =   DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1654             DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1655             DRIVER_GEM /*| DRIVER_MODESET*/,
1656
1657         .buf_priv_size  = sizeof(drm_i915_private_t),
1658         .load           = i915_driver_load,
1659         .open           = i915_driver_open,
1660         .unload         = i915_driver_unload,
1661         .preclose       = i915_driver_preclose,
1662         .lastclose      = i915_driver_lastclose,
1663         .postclose      = i915_driver_postclose,
1664         .device_is_agp  = i915_driver_device_is_agp,
1665         .gem_init_object = i915_gem_init_object,
1666         .gem_free_object = i915_gem_free_object,
1667         .gem_pager_ops  = &i915_gem_pager_ops,
1668         .dumb_create    = i915_gem_dumb_create,
1669         .dumb_map_offset = i915_gem_mmap_gtt,
1670         .dumb_destroy   = i915_gem_dumb_destroy,
1671
1672         .ioctls         = i915_ioctls,
1673         .max_ioctl      = DRM_ARRAY_SIZE(i915_ioctls),
1674
1675         .name           = DRIVER_NAME,
1676         .desc           = DRIVER_DESC,
1677         .date           = DRIVER_DATE,
1678         .major          = DRIVER_MAJOR,
1679         .minor          = DRIVER_MINOR,
1680         .patchlevel     = DRIVER_PATCHLEVEL,
1681 };
1682
1683 /**
1684  * Determine if the device really is AGP or not.
1685  *
1686  * All Intel graphics chipsets are treated as AGP, even if they are really
1687  * built-in.
1688  *
1689  * \param dev   The device to be tested.
1690  *
1691  * \returns
1692  * A value of 1 is always retured to indictate every i9x5 is AGP.
1693  */
1694 int i915_driver_device_is_agp(struct drm_device * dev)
1695 {
1696         return 1;
1697 }