sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_ringbuffer.h"
  34 #include <linux/workqueue.h>
  35
  36 extern struct drm_i915_private *i915_mch_dev;
  37
  38 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  39
  40 #define BEGIN_LP_RING(n) \
  41         intel_ring_begin(LP_RING(dev_priv), (n))
  42
  43 #define OUT_RING(x) \
  44         intel_ring_emit(LP_RING(dev_priv), x)
  45
  46 #define ADVANCE_LP_RING() \
  47         intel_ring_advance(LP_RING(dev_priv))
  48
  49 /**
  50  * Lock test for when it's just for synchronization of ring access.
  51  *
  52  * In that case, we don't need to do it when GEM is initialized as nobody else
  53  * has access to the ring.
  54  */
  55 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  56         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  57                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  58 } while (0)
  59
  60 static inline u32
  61 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  62 {
  63         if (I915_NEED_GFX_HWS(dev_priv->dev))
  64                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  65         else
  66                 return intel_read_status_page(LP_RING(dev_priv), reg);
  67 }
  68
  69 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  70 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  71 #define I915_BREADCRUMB_INDEX           0x21
  72
  73 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  74 {
  75         /* XXX: We don't care about dri1 */
  76         return;
  77 }
  78
  79 static void i915_write_hws_pga(struct drm_device *dev)
  80 {
  81         drm_i915_private_t *dev_priv = dev->dev_private;
  82         u32 addr;
  83
  84         addr = dev_priv->status_page_dmah->busaddr;
  85         if (INTEL_INFO(dev)->gen >= 4)
  86                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  87         I915_WRITE(HWS_PGA, addr);
  88 }
  89
  90 /**
  91  * Frees the hardware status page, whether it's a physical address or a virtual
  92  * address set up by the X Server.
  93  */
  94 static void i915_free_hws(struct drm_device *dev)
  95 {
  96         drm_i915_private_t *dev_priv = dev->dev_private;
  97         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  98
  99         if (dev_priv->status_page_dmah) {
 100                 drm_pci_free(dev, dev_priv->status_page_dmah);
 101                 dev_priv->status_page_dmah = NULL;
 102         }
 103
 104         if (ring->status_page.gfx_addr) {
 105                 ring->status_page.gfx_addr = 0;
 106 #if 0   /* We don't care about dri1 */
 107                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 108 #endif
 109         }
 110
 111         /* Need to rewrite hardware status page */
 112         I915_WRITE(HWS_PGA, 0x1ffff000);
 113 }
 114
 115 void i915_kernel_lost_context(struct drm_device * dev)
 116 {
 117         drm_i915_private_t *dev_priv = dev->dev_private;
 118         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 119
 120         /*
 121          * We should never lose context on the ring with modesetting
 122          * as we don't expose it to userspace
 123          */
 124         if (drm_core_check_feature(dev, DRIVER_MODESET))
 125                 return;
 126
 127         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 128         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 129         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 130         if (ring->space < 0)
 131                 ring->space += ring->size;
 132
 133 #if 0
 134         if (!dev->primary->master)
 135                 return;
 136 #endif
 137
 138         if (ring->head == ring->tail && dev_priv->sarea_priv)
 139                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 140 }
 141
 142 static int i915_dma_cleanup(struct drm_device * dev)
 143 {
 144         drm_i915_private_t *dev_priv = dev->dev_private;
 145         int i;
 146
 147         /* Make sure interrupts are disabled here because the uninstall ioctl
 148          * may not have been called from userspace and after dev_private
 149          * is freed, it's too late.
 150          */
 151         if (dev->irq_enabled)
 152                 drm_irq_uninstall(dev);
 153
 154         mutex_lock(&dev->struct_mutex);
 155         for (i = 0; i < I915_NUM_RINGS; i++)
 156                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 157         mutex_unlock(&dev->struct_mutex);
 158
 159         /* Clear the HWS virtual address at teardown */
 160         if (I915_NEED_GFX_HWS(dev))
 161                 i915_free_hws(dev);
 162
 163         return 0;
 164 }
 165
 166 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 167 {
 168         drm_i915_private_t *dev_priv = dev->dev_private;
 169         int ret;
 170
 171         dev_priv->sarea = drm_getsarea(dev);
 172         if (!dev_priv->sarea) {
 173                 DRM_ERROR("can not find sarea!\n");
 174                 i915_dma_cleanup(dev);
 175                 return -EINVAL;
 176         }
 177
 178         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 179             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 180
 181         if (init->ring_size != 0) {
 182                 if (LP_RING(dev_priv)->obj != NULL) {
 183                         i915_dma_cleanup(dev);
 184                         DRM_ERROR("Client tried to initialize ringbuffer in "
 185                                   "GEM mode\n");
 186                         return -EINVAL;
 187                 }
 188
 189                 ret = intel_render_ring_init_dri(dev,
 190                                                  init->ring_start,
 191                                                  init->ring_size);
 192                 if (ret) {
 193                         i915_dma_cleanup(dev);
 194                         return ret;
 195                 }
 196         }
 197
 198         dev_priv->dri1.cpp = init->cpp;
 199         dev_priv->dri1.back_offset = init->back_offset;
 200         dev_priv->dri1.front_offset = init->front_offset;
 201         dev_priv->dri1.current_page = 0;
 202         dev_priv->sarea_priv->pf_current_page = 0;
 203
 204
 205         /* Allow hardware batchbuffers unless told otherwise.
 206          */
 207         dev_priv->dri1.allow_batchbuffer = 1;
 208
 209         return 0;
 210 }
 211
 212 static int i915_dma_resume(struct drm_device * dev)
 213 {
 214         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 215         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 216
 217         DRM_DEBUG_DRIVER("%s\n", __func__);
 218
 219         if (ring->virtual_start == NULL) {
 220                 DRM_ERROR("can not ioremap virtual address for"
 221                           " ring buffer\n");
 222                 return -ENOMEM;
 223         }
 224
 225         /* Program Hardware Status Page */
 226         if (!ring->status_page.page_addr) {
 227                 DRM_ERROR("Can not find hardware status page\n");
 228                 return -EINVAL;
 229         }
 230         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 231                                 ring->status_page.page_addr);
 232         if (ring->status_page.gfx_addr != 0)
 233                 intel_ring_setup_status_page(ring);
 234         else
 235                 i915_write_hws_pga(dev);
 236
 237         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 238
 239         return 0;
 240 }
 241
 242 static int i915_dma_init(struct drm_device *dev, void *data,
 243                          struct drm_file *file_priv)
 244 {
 245         drm_i915_init_t *init = data;
 246         int retcode = 0;
 247
 248         if (drm_core_check_feature(dev, DRIVER_MODESET))
 249                 return -ENODEV;
 250
 251         switch (init->func) {
 252         case I915_INIT_DMA:
 253                 retcode = i915_initialize(dev, init);
 254                 break;
 255         case I915_CLEANUP_DMA:
 256                 retcode = i915_dma_cleanup(dev);
 257                 break;
 258         case I915_RESUME_DMA:
 259                 retcode = i915_dma_resume(dev);
 260                 break;
 261         default:
 262                 retcode = -EINVAL;
 263                 break;
 264         }
 265
 266         return retcode;
 267 }
 268
 269 /* Implement basically the same security restrictions as hardware does
 270  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 271  *
 272  * Most of the calculations below involve calculating the size of a
 273  * particular instruction.  It's important to get the size right as
 274  * that tells us where the next instruction to check is.  Any illegal
 275  * instruction detected will be given a size of zero, which is a
 276  * signal to abort the rest of the buffer.
 277  */
 278 static int validate_cmd(int cmd)
 279 {
 280         switch (((cmd >> 29) & 0x7)) {
 281         case 0x0:
 282                 switch ((cmd >> 23) & 0x3f) {
 283                 case 0x0:
 284                         return 1;       /* MI_NOOP */
 285                 case 0x4:
 286                         return 1;       /* MI_FLUSH */
 287                 default:
 288                         return 0;       /* disallow everything else */
 289                 }
 290                 break;
 291         case 0x1:
 292                 return 0;       /* reserved */
 293         case 0x2:
 294                 return (cmd & 0xff) + 2;        /* 2d commands */
 295         case 0x3:
 296                 if (((cmd >> 24) & 0x1f) <= 0x18)
 297                         return 1;
 298
 299                 switch ((cmd >> 24) & 0x1f) {
 300                 case 0x1c:
 301                         return 1;
 302                 case 0x1d:
 303                         switch ((cmd >> 16) & 0xff) {
 304                         case 0x3:
 305                                 return (cmd & 0x1f) + 2;
 306                         case 0x4:
 307                                 return (cmd & 0xf) + 2;
 308                         default:
 309                                 return (cmd & 0xffff) + 2;
 310                         }
 311                 case 0x1e:
 312                         if (cmd & (1 << 23))
 313                                 return (cmd & 0xffff) + 1;
 314                         else
 315                                 return 1;
 316                 case 0x1f:
 317                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 318                                 return (cmd & 0x1ffff) + 2;
 319                         else if (cmd & (1 << 17))       /* indirect random */
 320                                 if ((cmd & 0xffff) == 0)
 321                                         return 0;       /* unknown length, too hard */
 322                                 else
 323                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 324                         else
 325                                 return 2;       /* indirect sequential */
 326                 default:
 327                         return 0;
 328                 }
 329         default:
 330                 return 0;
 331         }
 332
 333         return 0;
 334 }
 335
 336 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 337 {
 338         drm_i915_private_t *dev_priv = dev->dev_private;
 339         int i, ret;
 340
 341         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 342                 return -EINVAL;
 343
 344         for (i = 0; i < dwords;) {
 345                 int sz = validate_cmd(buffer[i]);
 346                 if (sz == 0 || i + sz > dwords)
 347                         return -EINVAL;
 348                 i += sz;
 349         }
 350
 351         ret = BEGIN_LP_RING((dwords+1)&~1);
 352         if (ret)
 353                 return ret;
 354
 355         for (i = 0; i < dwords; i++)
 356                 OUT_RING(buffer[i]);
 357         if (dwords & 1)
 358                 OUT_RING(0);
 359
 360         ADVANCE_LP_RING();
 361
 362         return 0;
 363 }
 364
 365 int
 366 i915_emit_box(struct drm_device *dev,
 367               struct drm_clip_rect *box,
 368               int DR1, int DR4)
 369 {
 370         struct drm_i915_private *dev_priv = dev->dev_private;
 371         int ret;
 372
 373         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 374             box->y2 <= 0 || box->x2 <= 0) {
 375                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 376                           box->x1, box->y1, box->x2, box->y2);
 377                 return -EINVAL;
 378         }
 379
 380         if (INTEL_INFO(dev)->gen >= 4) {
 381                 ret = BEGIN_LP_RING(4);
 382                 if (ret)
 383                         return ret;
 384
 385                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 386                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 387                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 388                 OUT_RING(DR4);
 389         } else {
 390                 ret = BEGIN_LP_RING(6);
 391                 if (ret)
 392                         return ret;
 393
 394                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 395                 OUT_RING(DR1);
 396                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 397                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 398                 OUT_RING(DR4);
 399                 OUT_RING(0);
 400         }
 401         ADVANCE_LP_RING();
 402
 403         return 0;
 404 }
 405
 406 /* XXX: Emitting the counter should really be moved to part of the IRQ
 407  * emit. For now, do it in both places:
 408  */
 409
 410 static void i915_emit_breadcrumb(struct drm_device *dev)
 411 {
 412         drm_i915_private_t *dev_priv = dev->dev_private;
 413
 414         dev_priv->dri1.counter++;
 415         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 416                 dev_priv->dri1.counter = 0;
 417         if (dev_priv->sarea_priv)
 418                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 419
 420         if (BEGIN_LP_RING(4) == 0) {
 421                 OUT_RING(MI_STORE_DWORD_INDEX);
 422                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 423                 OUT_RING(dev_priv->dri1.counter);
 424                 OUT_RING(0);
 425                 ADVANCE_LP_RING();
 426         }
 427 }
 428
 429 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 430                                    drm_i915_cmdbuffer_t *cmd,
 431                                    struct drm_clip_rect *cliprects,
 432                                    void *cmdbuf)
 433 {
 434         int nbox = cmd->num_cliprects;
 435         int i = 0, count, ret;
 436
 437         if (cmd->sz & 0x3) {
 438                 DRM_ERROR("alignment");
 439                 return -EINVAL;
 440         }
 441
 442         i915_kernel_lost_context(dev);
 443
 444         count = nbox ? nbox : 1;
 445
 446         for (i = 0; i < count; i++) {
 447                 if (i < nbox) {
 448                         ret = i915_emit_box(dev, &cliprects[i],
 449                                             cmd->DR1, cmd->DR4);
 450                         if (ret)
 451                                 return ret;
 452                 }
 453
 454                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 455                 if (ret)
 456                         return ret;
 457         }
 458
 459         i915_emit_breadcrumb(dev);
 460         return 0;
 461 }
 462
 463 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 464                                      drm_i915_batchbuffer_t * batch,
 465                                      struct drm_clip_rect *cliprects)
 466 {
 467         struct drm_i915_private *dev_priv = dev->dev_private;
 468         int nbox = batch->num_cliprects;
 469         int i, count, ret;
 470
 471         if ((batch->start | batch->used) & 0x7) {
 472                 DRM_ERROR("alignment");
 473                 return -EINVAL;
 474         }
 475
 476         i915_kernel_lost_context(dev);
 477
 478         count = nbox ? nbox : 1;
 479         for (i = 0; i < count; i++) {
 480                 if (i < nbox) {
 481                         ret = i915_emit_box(dev, &cliprects[i],
 482                                             batch->DR1, batch->DR4);
 483                         if (ret)
 484                                 return ret;
 485                 }
 486
 487                 if (!IS_I830(dev) && !IS_845G(dev)) {
 488                         ret = BEGIN_LP_RING(2);
 489                         if (ret)
 490                                 return ret;
 491
 492                         if (INTEL_INFO(dev)->gen >= 4) {
 493                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 494                                 OUT_RING(batch->start);
 495                         } else {
 496                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 497                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 498                         }
 499                 } else {
 500                         ret = BEGIN_LP_RING(4);
 501                         if (ret)
 502                                 return ret;
 503
 504                         OUT_RING(MI_BATCH_BUFFER);
 505                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 506                         OUT_RING(batch->start + batch->used - 4);
 507                         OUT_RING(0);
 508                 }
 509                 ADVANCE_LP_RING();
 510         }
 511
 512
 513         if (IS_G4X(dev) || IS_GEN5(dev)) {
 514                 if (BEGIN_LP_RING(2) == 0) {
 515                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 516                         OUT_RING(MI_NOOP);
 517                         ADVANCE_LP_RING();
 518                 }
 519         }
 520
 521         i915_emit_breadcrumb(dev);
 522         return 0;
 523 }
 524
 525 static int i915_dispatch_flip(struct drm_device * dev)
 526 {
 527         drm_i915_private_t *dev_priv = dev->dev_private;
 528         int ret;
 529
 530         if (!dev_priv->sarea_priv)
 531                 return -EINVAL;
 532
 533         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 534                           __func__,
 535                          dev_priv->dri1.current_page,
 536                          dev_priv->sarea_priv->pf_current_page);
 537
 538         i915_kernel_lost_context(dev);
 539
 540         ret = BEGIN_LP_RING(10);
 541         if (ret)
 542                 return ret;
 543
 544         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 545         OUT_RING(0);
 546
 547         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 548         OUT_RING(0);
 549         if (dev_priv->dri1.current_page == 0) {
 550                 OUT_RING(dev_priv->dri1.back_offset);
 551                 dev_priv->dri1.current_page = 1;
 552         } else {
 553                 OUT_RING(dev_priv->dri1.front_offset);
 554                 dev_priv->dri1.current_page = 0;
 555         }
 556         OUT_RING(0);
 557
 558         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 559         OUT_RING(0);
 560
 561         ADVANCE_LP_RING();
 562
 563         dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 564
 565         if (BEGIN_LP_RING(4) == 0) {
 566                 OUT_RING(MI_STORE_DWORD_INDEX);
 567                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 568                 OUT_RING(dev_priv->dri1.counter);
 569                 OUT_RING(0);
 570                 ADVANCE_LP_RING();
 571         }
 572
 573         dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 574         return 0;
 575 }
 576
 577 static int i915_quiescent(struct drm_device *dev)
 578 {
 579         i915_kernel_lost_context(dev);
 580         return intel_ring_idle(LP_RING(dev->dev_private));
 581 }
 582
 583 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 584                             struct drm_file *file_priv)
 585 {
 586         int ret;
 587
 588         if (drm_core_check_feature(dev, DRIVER_MODESET))
 589                 return -ENODEV;
 590
 591         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 592
 593         mutex_lock(&dev->struct_mutex);
 594         ret = i915_quiescent(dev);
 595         mutex_unlock(&dev->struct_mutex);
 596
 597         return ret;
 598 }
 599
 600 static int i915_batchbuffer(struct drm_device *dev, void *data,
 601                             struct drm_file *file_priv)
 602 {
 603         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 604         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 605         drm_i915_batchbuffer_t *batch = data;
 606         int ret;
 607         struct drm_clip_rect *cliprects = NULL;
 608
 609         if (drm_core_check_feature(dev, DRIVER_MODESET))
 610                 return -ENODEV;
 611
 612         if (!dev_priv->dri1.allow_batchbuffer) {
 613                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 614                 return -EINVAL;
 615         }
 616
 617         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 618                         batch->start, batch->used, batch->num_cliprects);
 619
 620         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 621
 622         if (batch->num_cliprects < 0)
 623                 return -EINVAL;
 624
 625         if (batch->num_cliprects) {
 626                 cliprects = kmalloc(batch->num_cliprects *
 627                                     sizeof(struct drm_clip_rect), M_DRM,
 628                                     M_WAITOK | M_ZERO);
 629                 if (cliprects == NULL)
 630                         return -ENOMEM;
 631
 632                 ret = copy_from_user(cliprects, batch->cliprects,
 633                                      batch->num_cliprects *
 634                                      sizeof(struct drm_clip_rect));
 635                 if (ret != 0) {
 636                         ret = -EFAULT;
 637                         goto fail_free;
 638                 }
 639         }
 640
 641         mutex_lock(&dev->struct_mutex);
 642         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 643         mutex_unlock(&dev->struct_mutex);
 644
 645         if (sarea_priv)
 646                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 647
 648 fail_free:
 649         kfree(cliprects);
 650
 651         return ret;
 652 }
 653
 654 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 655                           struct drm_file *file_priv)
 656 {
 657         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 658         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 659         drm_i915_cmdbuffer_t *cmdbuf = data;
 660         struct drm_clip_rect *cliprects = NULL;
 661         void *batch_data;
 662         int ret;
 663
 664         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 665                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 666
 667         if (drm_core_check_feature(dev, DRIVER_MODESET))
 668                 return -ENODEV;
 669
 670         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 671
 672         if (cmdbuf->num_cliprects < 0)
 673                 return -EINVAL;
 674
 675         batch_data = kmalloc(cmdbuf->sz, M_DRM, M_WAITOK);
 676         if (batch_data == NULL)
 677                 return -ENOMEM;
 678
 679         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 680         if (ret != 0) {
 681                 ret = -EFAULT;
 682                 goto fail_batch_free;
 683         }
 684
 685         if (cmdbuf->num_cliprects) {
 686                 cliprects = kmalloc(cmdbuf->num_cliprects *
 687                                     sizeof(struct drm_clip_rect), M_DRM,
 688                                     M_WAITOK | M_ZERO);
 689                 if (cliprects == NULL) {
 690                         ret = -ENOMEM;
 691                         goto fail_batch_free;
 692                 }
 693
 694                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 695                                      cmdbuf->num_cliprects *
 696                                      sizeof(struct drm_clip_rect));
 697                 if (ret != 0) {
 698                         ret = -EFAULT;
 699                         goto fail_clip_free;
 700                 }
 701         }
 702
 703         mutex_lock(&dev->struct_mutex);
 704         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 705         mutex_unlock(&dev->struct_mutex);
 706         if (ret) {
 707                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 708                 goto fail_clip_free;
 709         }
 710
 711         if (sarea_priv)
 712                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 713
 714 fail_clip_free:
 715         kfree(cliprects);
 716 fail_batch_free:
 717         kfree(batch_data);
 718         return ret;
 719 }
 720
 721 static int i915_emit_irq(struct drm_device * dev)
 722 {
 723         drm_i915_private_t *dev_priv = dev->dev_private;
 724 #if 0
 725         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 726 #endif
 727
 728         i915_kernel_lost_context(dev);
 729
 730         DRM_DEBUG_DRIVER("\n");
 731
 732         dev_priv->dri1.counter++;
 733         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 734                 dev_priv->dri1.counter = 1;
 735         if (dev_priv->sarea_priv)
 736                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 737
 738         if (BEGIN_LP_RING(4) == 0) {
 739                 OUT_RING(MI_STORE_DWORD_INDEX);
 740                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 741                 OUT_RING(dev_priv->dri1.counter);
 742                 OUT_RING(MI_USER_INTERRUPT);
 743                 ADVANCE_LP_RING();
 744         }
 745
 746         return dev_priv->dri1.counter;
 747 }
 748
 749 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 750 {
 751         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 752 #if 0
 753         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 754 #endif
 755         int ret = 0;
 756         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 757
 758         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 759                   READ_BREADCRUMB(dev_priv));
 760
 761 #if 0
 762         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 763                 if (master_priv->sarea_priv)
 764                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 765                 return 0;
 766         }
 767
 768         if (master_priv->sarea_priv)
 769                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 770 #else
 771         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 772                 if (dev_priv->sarea_priv) {
 773                         dev_priv->sarea_priv->last_dispatch =
 774                                 READ_BREADCRUMB(dev_priv);
 775                 }
 776                 return 0;
 777         }
 778
 779         if (dev_priv->sarea_priv)
 780                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 781 #endif
 782
 783         if (ring->irq_get(ring)) {
 784                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 785                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 786                 ring->irq_put(ring);
 787         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 788                 ret = -EBUSY;
 789
 790         if (ret == -EBUSY) {
 791                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 792                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 793         }
 794
 795         return ret;
 796 }
 797
 798 /* Needs the lock as it touches the ring.
 799  */
 800 static int i915_irq_emit(struct drm_device *dev, void *data,
 801                          struct drm_file *file_priv)
 802 {
 803         drm_i915_private_t *dev_priv = dev->dev_private;
 804         drm_i915_irq_emit_t *emit = data;
 805         int result;
 806
 807         if (drm_core_check_feature(dev, DRIVER_MODESET))
 808                 return -ENODEV;
 809
 810         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 811                 DRM_ERROR("called with no initialization\n");
 812                 return -EINVAL;
 813         }
 814
 815         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 816
 817         mutex_lock(&dev->struct_mutex);
 818         result = i915_emit_irq(dev);
 819         mutex_unlock(&dev->struct_mutex);
 820
 821         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 822                 DRM_ERROR("copy_to_user\n");
 823                 return -EFAULT;
 824         }
 825
 826         return 0;
 827 }
 828
 829 /* Doesn't need the hardware lock.
 830  */
 831 static int i915_irq_wait(struct drm_device *dev, void *data,
 832                          struct drm_file *file_priv)
 833 {
 834         drm_i915_private_t *dev_priv = dev->dev_private;
 835         drm_i915_irq_wait_t *irqwait = data;
 836
 837         if (drm_core_check_feature(dev, DRIVER_MODESET))
 838                 return -ENODEV;
 839
 840         if (!dev_priv) {
 841                 DRM_ERROR("called with no initialization\n");
 842                 return -EINVAL;
 843         }
 844
 845         return i915_wait_irq(dev, irqwait->irq_seq);
 846 }
 847
 848 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 849                          struct drm_file *file_priv)
 850 {
 851         drm_i915_private_t *dev_priv = dev->dev_private;
 852         drm_i915_vblank_pipe_t *pipe = data;
 853
 854         if (drm_core_check_feature(dev, DRIVER_MODESET))
 855                 return -ENODEV;
 856
 857         if (!dev_priv) {
 858                 DRM_ERROR("called with no initialization\n");
 859                 return -EINVAL;
 860         }
 861
 862         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 863
 864         return 0;
 865 }
 866
 867 /**
 868  * Schedule buffer swap at given vertical blank.
 869  */
 870 static int i915_vblank_swap(struct drm_device *dev, void *data,
 871                      struct drm_file *file_priv)
 872 {
 873         /* The delayed swap mechanism was fundamentally racy, and has been
 874          * removed.  The model was that the client requested a delayed flip/swap
 875          * from the kernel, then waited for vblank before continuing to perform
 876          * rendering.  The problem was that the kernel might wake the client
 877          * up before it dispatched the vblank swap (since the lock has to be
 878          * held while touching the ringbuffer), in which case the client would
 879          * clear and start the next frame before the swap occurred, and
 880          * flicker would occur in addition to likely missing the vblank.
 881          *
 882          * In the absence of this ioctl, userland falls back to a correct path
 883          * of waiting for a vblank, then dispatching the swap on its own.
 884          * Context switching to userland and back is plenty fast enough for
 885          * meeting the requirements of vblank swapping.
 886          */
 887         return -EINVAL;
 888 }
 889
 890 static int i915_flip_bufs(struct drm_device *dev, void *data,
 891                           struct drm_file *file_priv)
 892 {
 893         int ret;
 894
 895         if (drm_core_check_feature(dev, DRIVER_MODESET))
 896                 return -ENODEV;
 897
 898         DRM_DEBUG_DRIVER("%s\n", __func__);
 899
 900         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 901
 902         mutex_lock(&dev->struct_mutex);
 903         ret = i915_dispatch_flip(dev);
 904         mutex_unlock(&dev->struct_mutex);
 905
 906         return ret;
 907 }
 908
 909 static int i915_getparam(struct drm_device *dev, void *data,
 910                          struct drm_file *file_priv)
 911 {
 912         drm_i915_private_t *dev_priv = dev->dev_private;
 913         drm_i915_getparam_t *param = data;
 914         int value;
 915
 916         if (!dev_priv) {
 917                 DRM_ERROR("called with no initialization\n");
 918                 return -EINVAL;
 919         }
 920
 921         switch (param->param) {
 922         case I915_PARAM_IRQ_ACTIVE:
 923                 value = dev->irq_enabled ? 1 : 0;
 924                 break;
 925         case I915_PARAM_ALLOW_BATCHBUFFER:
 926                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 927                 break;
 928         case I915_PARAM_LAST_DISPATCH:
 929                 value = READ_BREADCRUMB(dev_priv);
 930                 break;
 931         case I915_PARAM_CHIPSET_ID:
 932                 value = dev->pci_device;
 933                 break;
 934         case I915_PARAM_HAS_GEM:
 935                 value = 1;
 936                 break;
 937         case I915_PARAM_NUM_FENCES_AVAIL:
 938                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 939                 break;
 940         case I915_PARAM_HAS_OVERLAY:
 941                 value = dev_priv->overlay ? 1 : 0;
 942                 break;
 943         case I915_PARAM_HAS_PAGEFLIPPING:
 944                 value = 1;
 945                 break;
 946         case I915_PARAM_HAS_EXECBUF2:
 947                 /* depends on GEM */
 948                 value = 1;
 949                 break;
 950         case I915_PARAM_HAS_BSD:
 951                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 952                 break;
 953         case I915_PARAM_HAS_BLT:
 954                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 955                 break;
 956         case I915_PARAM_HAS_RELAXED_FENCING:
 957                 value = 1;
 958                 break;
 959         case I915_PARAM_HAS_COHERENT_RINGS:
 960                 value = 1;
 961                 break;
 962         case I915_PARAM_HAS_EXEC_CONSTANTS:
 963                 value = INTEL_INFO(dev)->gen >= 4;
 964                 break;
 965         case I915_PARAM_HAS_RELAXED_DELTA:
 966                 value = 1;
 967                 break;
 968         case I915_PARAM_HAS_GEN7_SOL_RESET:
 969                 value = 1;
 970                 break;
 971         case I915_PARAM_HAS_LLC:
 972                 value = HAS_LLC(dev);
 973                 break;
 974         case I915_PARAM_HAS_ALIASING_PPGTT:
 975                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 976                 break;
 977         case I915_PARAM_HAS_WAIT_TIMEOUT:
 978                 value = 1;
 979                 break;
 980         case I915_PARAM_HAS_SEMAPHORES:
 981                 value = i915_semaphore_is_enabled(dev);
 982                 break;
 983         case I915_PARAM_HAS_PINNED_BATCHES:
 984                 value = 1;
 985                 break;
 986         case I915_PARAM_HAS_EXEC_NO_RELOC:
 987                 value = 1;
 988                 break;
 989         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 990                 value = 1;
 991                 break;
 992         default:
 993                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 994                 return -EINVAL;
 995         }
 996
 997         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 998                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 999                 return -EFAULT;
1000         }
1001
1002         return 0;
1003 }
1004
1005 static int i915_setparam(struct drm_device *dev, void *data,
1006                          struct drm_file *file_priv)
1007 {
1008         drm_i915_private_t *dev_priv = dev->dev_private;
1009         drm_i915_setparam_t *param = data;
1010
1011         if (!dev_priv) {
1012                 DRM_ERROR("called with no initialization\n");
1013                 return -EINVAL;
1014         }
1015
1016         switch (param->param) {
1017         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1018                 break;
1019         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1020                 break;
1021         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1022                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1023                 break;
1024         case I915_SETPARAM_NUM_USED_FENCES:
1025                 if (param->value > dev_priv->num_fence_regs ||
1026                     param->value < 0)
1027                         return -EINVAL;
1028                 /* Userspace can use first N regs */
1029                 dev_priv->fence_reg_start = param->value;
1030                 break;
1031         default:
1032                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1033                                         param->param);
1034                 return -EINVAL;
1035         }
1036
1037         return 0;
1038 }
1039
1040 static int i915_set_status_page(struct drm_device *dev, void *data,
1041                                 struct drm_file *file_priv)
1042 {
1043 #if 0   /* We don't care about dri1 */
1044         drm_i915_private_t *dev_priv = dev->dev_private;
1045         drm_i915_hws_addr_t *hws = data;
1046         struct intel_ring_buffer *ring;
1047
1048         if (drm_core_check_feature(dev, DRIVER_MODESET))
1049                 return -ENODEV;
1050
1051         if (!I915_NEED_GFX_HWS(dev))
1052                 return -EINVAL;
1053
1054         if (!dev_priv) {
1055                 DRM_ERROR("called with no initialization\n");
1056                 return -EINVAL;
1057         }
1058
1059         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1060                 WARN(1, "tried to set status page when mode setting active\n");
1061                 return 0;
1062         }
1063
1064         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1065
1066         ring = LP_RING(dev_priv);
1067         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1068
1069         dev_priv->dri1.gfx_hws_cpu_addr =
1070                 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1071         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1072                 i915_dma_cleanup(dev);
1073                 ring->status_page.gfx_addr = 0;
1074                 DRM_ERROR("can not ioremap virtual address for"
1075                                 " G33 hw status page\n");
1076                 return -ENOMEM;
1077         }
1078
1079         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1080         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1081
1082         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1083                          ring->status_page.gfx_addr);
1084         DRM_DEBUG_DRIVER("load hws at %p\n",
1085                          ring->status_page.page_addr);
1086         return 0;
1087 #endif
1088         return -EINVAL;
1089 }
1090
1091 static int i915_get_bridge_dev(struct drm_device *dev)
1092 {
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094         static struct pci_dev i915_bridge_dev;
1095
1096         i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
1097         if (!i915_bridge_dev.dev) {
1098                 DRM_ERROR("bridge device not found\n");
1099                 return -1;
1100         }
1101
1102         dev_priv->bridge_dev = &i915_bridge_dev;
1103         return 0;
1104 }
1105
1106 #define MCHBAR_I915 0x44
1107 #define MCHBAR_I965 0x48
1108 #define MCHBAR_SIZE (4*4096)
1109
1110 #define DEVEN_REG 0x54
1111 #define   DEVEN_MCHBAR_EN (1 << 28)
1112
1113 /* Allocate space for the MCH regs if needed, return nonzero on error */
1114 static int
1115 intel_alloc_mchbar_resource(struct drm_device *dev)
1116 {
1117         drm_i915_private_t *dev_priv = dev->dev_private;
1118         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1119         device_t vga;
1120         u32 temp_lo, temp_hi = 0;
1121         u64 mchbar_addr;
1122
1123         if (INTEL_INFO(dev)->gen >= 4)
1124                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1125         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1126         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1127
1128         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1129 #ifdef CONFIG_PNP
1130         if (mchbar_addr &&
1131             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1132                 return 0;
1133 #endif
1134
1135         /* Get some space for it */
1136         vga = device_get_parent(dev->dev);
1137         dev_priv->mch_res_rid = 0x100;
1138         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1139             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1140             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1141         if (dev_priv->mch_res == NULL) {
1142                 DRM_ERROR("failed mchbar resource alloc\n");
1143                 return (-ENOMEM);
1144         }
1145
1146         if (INTEL_INFO(dev)->gen >= 4)
1147                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1148                                        upper_32_bits(rman_get_start(dev_priv->mch_res)));
1149
1150         pci_write_config_dword(dev_priv->bridge_dev, reg,
1151                                lower_32_bits(rman_get_start(dev_priv->mch_res)));
1152         return 0;
1153 }
1154
1155 /* Setup MCHBAR if possible, return true if we should disable it again */
1156 static void
1157 intel_setup_mchbar(struct drm_device *dev)
1158 {
1159         drm_i915_private_t *dev_priv = dev->dev_private;
1160         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1161         u32 temp;
1162         bool enabled;
1163
1164         dev_priv->mchbar_need_disable = false;
1165
1166         if (IS_I915G(dev) || IS_I915GM(dev)) {
1167                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1168                 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1169         } else {
1170                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1171                 enabled = temp & 1;
1172         }
1173
1174         /* If it's already enabled, don't have to do anything */
1175         if (enabled)
1176                 return;
1177
1178         if (intel_alloc_mchbar_resource(dev))
1179                 return;
1180
1181         dev_priv->mchbar_need_disable = true;
1182
1183         /* Space is allocated or reserved, so enable it. */
1184         if (IS_I915G(dev) || IS_I915GM(dev)) {
1185                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1186                                        temp | DEVEN_MCHBAR_EN);
1187         } else {
1188                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1189                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1190         }
1191 }
1192
1193 static void
1194 intel_teardown_mchbar(struct drm_device *dev)
1195 {
1196         drm_i915_private_t *dev_priv = dev->dev_private;
1197         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1198         device_t vga;
1199         u32 temp;
1200
1201         if (dev_priv->mchbar_need_disable) {
1202                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1204                         temp &= ~DEVEN_MCHBAR_EN;
1205                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1206                 } else {
1207                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1208                         temp &= ~1;
1209                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1210                 }
1211         }
1212
1213         if (dev_priv->mch_res != NULL) {
1214                 vga = device_get_parent(dev->dev);
1215                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1216                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1217                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1218                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1219                 dev_priv->mch_res = NULL;
1220         }
1221 }
1222
1223 static int i915_load_modeset_init(struct drm_device *dev)
1224 {
1225         struct drm_i915_private *dev_priv = dev->dev_private;
1226         int ret;
1227
1228         ret = intel_parse_bios(dev);
1229         if (ret)
1230                 DRM_INFO("failed to find VBIOS tables\n");
1231
1232 #if 0
1233         /* If we have > 1 VGA cards, then we need to arbitrate access
1234          * to the common VGA resources.
1235          *
1236          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1237          * then we do not take part in VGA arbitration and the
1238          * vga_client_register() fails with -ENODEV.
1239          */
1240         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1241         if (ret && ret != -ENODEV)
1242                 goto out;
1243
1244         intel_register_dsm_handler();
1245
1246         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1247         if (ret)
1248                 goto cleanup_vga_client;
1249
1250         /* Initialise stolen first so that we may reserve preallocated
1251          * objects for the BIOS to KMS transition.
1252          */
1253         ret = i915_gem_init_stolen(dev);
1254         if (ret)
1255                 goto cleanup_vga_switcheroo;
1256 #endif
1257
1258         ret = drm_irq_install(dev);
1259         if (ret)
1260                 goto cleanup_gem_stolen;
1261
1262         /* Important: The output setup functions called by modeset_init need
1263          * working irqs for e.g. gmbus and dp aux transfers. */
1264         intel_modeset_init(dev);
1265
1266         ret = i915_gem_init(dev);
1267         if (ret)
1268                 goto cleanup_irq;
1269
1270 #if 0
1271         INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1272 #endif
1273
1274         intel_modeset_gem_init(dev);
1275
1276         /* Always safe in the mode setting case. */
1277         /* FIXME: do pre/post-mode set stuff in core KMS code */
1278         dev->vblank_disable_allowed = 1;
1279         if (INTEL_INFO(dev)->num_pipes == 0) {
1280                 dev_priv->mm.suspended = 0;
1281                 return 0;
1282         }
1283
1284         ret = intel_fbdev_init(dev);
1285         if (ret)
1286                 goto cleanup_gem;
1287
1288         /* Only enable hotplug handling once the fbdev is fully set up. */
1289         intel_hpd_init(dev);
1290
1291         /*
1292          * Some ports require correctly set-up hpd registers for detection to
1293          * work properly (leading to ghost connected connector status), e.g. VGA
1294          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1295          * irqs are fully enabled. Now we should scan for the initial config
1296          * only once hotplug handling is enabled, but due to screwed-up locking
1297          * around kms/fbdev init we can't protect the fdbev initial config
1298          * scanning against hotplug events. Hence do this first and ignore the
1299          * tiny window where we will loose hotplug notifactions.
1300          */
1301         intel_fbdev_initial_config(dev);
1302
1303         /* Only enable hotplug handling once the fbdev is fully set up. */
1304         dev_priv->enable_hotplug_processing = true;
1305
1306         drm_kms_helper_poll_init(dev);
1307
1308         /* We're off and running w/KMS */
1309         dev_priv->mm.suspended = 0;
1310
1311         return 0;
1312
1313 cleanup_gem:
1314         mutex_lock(&dev->struct_mutex);
1315         i915_gem_cleanup_ringbuffer(dev);
1316         i915_gem_context_fini(dev);
1317         mutex_unlock(&dev->struct_mutex);
1318         i915_gem_cleanup_aliasing_ppgtt(dev);
1319         drm_mm_takedown(&dev_priv->mm.gtt_space);
1320 cleanup_irq:
1321         drm_irq_uninstall(dev);
1322 cleanup_gem_stolen:
1323 #if 0
1324         i915_gem_cleanup_stolen(dev);
1325 cleanup_vga_switcheroo:
1326         vga_switcheroo_unregister_client(dev->pdev);
1327 cleanup_vga_client:
1328         vga_client_register(dev->pdev, NULL, NULL, NULL);
1329 out:
1330 #endif
1331         return ret;
1332 }
1333
1334 #if 0
1335 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1336 {
1337         struct apertures_struct *ap;
1338         struct pci_dev *pdev = dev_priv->dev->pdev;
1339         bool primary;
1340
1341         ap = alloc_apertures(1);
1342         if (!ap)
1343                 return;
1344
1345         ap->ranges[0].base = dev_priv->gtt.mappable_base;
1346         ap->ranges[0].size = dev_priv->gtt.mappable_end;
1347
1348         primary =
1349                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1350
1351         remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1352
1353         kfree(ap);
1354 }
1355 #endif
1356
1357 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1358 {
1359 #if 0
1360         const struct intel_device_info *info = dev_priv->info;
1361
1362 #define PRINT_S(name) "%s"
1363 #define SEP_EMPTY
1364 #define PRINT_FLAG(name) info->name ? #name "," : ""
1365 #define SEP_COMMA ,
1366         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1367                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1368                          info->gen,
1369                          dev_priv->dev->pdev->device,
1370                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1371 #undef PRINT_S
1372 #undef SEP_EMPTY
1373 #undef PRINT_FLAG
1374 #undef SEP_COMMA
1375 #endif
1376 }
1377
1378 #if 0
1379 /**
1380  * intel_early_sanitize_regs - clean up BIOS state
1381  * @dev: DRM device
1382  *
1383  * This function must be called before we do any I915_READ or I915_WRITE. Its
1384  * purpose is to clean up any state left by the BIOS that may affect us when
1385  * reading and/or writing registers.
1386  */
1387 static void intel_early_sanitize_regs(struct drm_device *dev)
1388 {
1389         struct drm_i915_private *dev_priv = dev->dev_private;
1390
1391         if (HAS_FPGA_DBG_UNCLAIMED(dev))
1392                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1393 }
1394 #endif
1395
1396 /**
1397  * i915_driver_load - setup chip and create an initial config
1398  * @dev: DRM device
1399  * @flags: startup flags
1400  *
1401  * The driver load routine has to do several things:
1402  *   - drive output discovery via intel_modeset_init()
1403  *   - initialize the memory manager
1404  *   - allocate initial config memory
1405  *   - setup the DRM framebuffer with the allocated memory
1406  */
1407 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1408 {
1409         struct drm_i915_private *dev_priv = dev->dev_private;
1410         const struct intel_device_info *info;
1411         unsigned long base, size;
1412         int ret = 0, mmio_bar, mmio_size;
1413         uint32_t aperture_size;
1414         static struct pci_dev i915_pdev;
1415
1416         /* XXX: struct pci_dev */
1417         i915_pdev.dev = dev->dev;
1418         dev->pdev = &i915_pdev;
1419
1420         info = i915_get_device_id(dev->pci_device);
1421
1422         /* Refuse to load on gen6+ without kms enabled. */
1423         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1424                 return -ENODEV;
1425
1426         /* i915 has 4 more counters */
1427         dev->counters += 4;
1428         dev->types[6] = _DRM_STAT_IRQ;
1429         dev->types[7] = _DRM_STAT_PRIMARY;
1430         dev->types[8] = _DRM_STAT_SECONDARY;
1431         dev->types[9] = _DRM_STAT_DMA;
1432
1433         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1434         if (dev_priv == NULL)
1435                 return -ENOMEM;
1436
1437         dev->dev_private = (void *)dev_priv;
1438         dev_priv->dev = dev;
1439         dev_priv->info = info;
1440
1441         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1442         lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
1443         lockinit(&dev_priv->rps.lock, "rps.l", 0, LK_CANRECURSE);
1444         lockinit(&dev_priv->gt_lock, "915gt", 0, LK_CANRECURSE);
1445         spin_init(&dev_priv->backlight.lock, "i915bl");
1446         lockinit(&dev_priv->dpio_lock, "i915dpio", 0, LK_CANRECURSE);
1447         lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1448         lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
1449
1450         i915_dump_device_info(dev_priv);
1451
1452         if (i915_get_bridge_dev(dev)) {
1453                 ret = -EIO;
1454                 goto free_priv;
1455         }
1456
1457         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1458         /* Before gen4, the registers and the GTT are behind different BARs.
1459          * However, from gen4 onwards, the registers and the GTT are shared
1460          * in the same BAR, so we want to restrict this ioremap from
1461          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1462          * the register BAR remains the same size for all the earlier
1463          * generations up to Ironlake.
1464          */
1465         if (info->gen < 5)
1466                 mmio_size = 512*1024;
1467         else
1468                 mmio_size = 2*1024*1024;
1469
1470 #if 0
1471         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1472         if (!dev_priv->regs) {
1473                 DRM_ERROR("failed to map registers\n");
1474                 ret = -EIO;
1475                 goto put_bridge;
1476         }
1477
1478         intel_early_sanitize_regs(dev);
1479 #endif
1480
1481         ret = i915_gem_gtt_init(dev);
1482         if (ret)
1483                 goto put_bridge;
1484
1485 #if 0
1486         if (drm_core_check_feature(dev, DRIVER_MODESET))
1487                 i915_kick_out_firmware_fb(dev_priv);
1488
1489         pci_set_master(dev->pdev);
1490
1491         /* overlay on gen2 is broken and can't address above 1G */
1492         if (IS_GEN2(dev))
1493                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1494
1495         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1496          * using 32bit addressing, overwriting memory if HWS is located
1497          * above 4GB.
1498          *
1499          * The documentation also mentions an issue with undefined
1500          * behaviour if any general state is accessed within a page above 4GB,
1501          * which also needs to be handled carefully.
1502          */
1503         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1504                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1505 #endif
1506
1507         aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1508
1509 #if 0
1510         dev_priv->gtt.mappable =
1511                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1512                                      aperture_size);
1513         if (dev_priv->gtt.mappable == NULL) {
1514                 ret = -EIO;
1515                 goto out_rmmap;
1516         }
1517 #endif
1518         dev_priv->mm.gtt_mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1519                                                  aperture_size);
1520
1521         base = drm_get_resource_start(dev, mmio_bar);
1522         size = drm_get_resource_len(dev, mmio_bar);
1523
1524         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1525             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1526
1527         /* The i915 workqueue is primarily used for batched retirement of
1528          * requests (and thus managing bo) once the task has been completed
1529          * by the GPU. i915_gem_retire_requests() is called directly when we
1530          * need high-priority retirement, such as waiting for an explicit
1531          * bo.
1532          *
1533          * It is also used for periodic low-priority events, such as
1534          * idle-timers and recording error state.
1535          *
1536          * All tasks on the workqueue are expected to acquire the dev mutex
1537          * so there is no point in running more than one instance of the
1538          * workqueue at any time.  Use an ordered one.
1539          */
1540         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1541         if (dev_priv->wq == NULL) {
1542                 DRM_ERROR("Failed to create our workqueue.\n");
1543                 ret = -ENOMEM;
1544                 goto out_mtrrfree;
1545         }
1546
1547         /* This must be called before any calls to HAS_PCH_* */
1548         intel_detect_pch(dev);
1549
1550         intel_irq_init(dev);
1551         intel_pm_init(dev);
1552         intel_gt_sanitize(dev);
1553         intel_gt_init(dev);
1554
1555         /* Try to make sure MCHBAR is enabled before poking at it */
1556         intel_setup_mchbar(dev);
1557         intel_setup_gmbus(dev);
1558         intel_opregion_setup(dev);
1559
1560         intel_setup_bios(dev);
1561
1562         i915_gem_load(dev);
1563
1564         /* On the 945G/GM, the chipset reports the MSI capability on the
1565          * integrated graphics even though the support isn't actually there
1566          * according to the published specs.  It doesn't appear to function
1567          * correctly in testing on 945G.
1568          * This may be a side effect of MSI having been made available for PEG
1569          * and the registers being closely associated.
1570          *
1571          * According to chipset errata, on the 965GM, MSI interrupts may
1572          * be lost or delayed, but we use them anyways to avoid
1573          * stuck interrupts on some machines.
1574          */
1575 #if 0
1576         if (!IS_I945G(dev) && !IS_I945GM(dev))
1577                 pci_enable_msi(dev->pdev);
1578 #endif
1579
1580         dev_priv->num_plane = 1;
1581         if (IS_VALLEYVIEW(dev))
1582                 dev_priv->num_plane = 2;
1583
1584         if (INTEL_INFO(dev)->num_pipes) {
1585                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1586                 if (ret)
1587                         goto out_gem_unload;
1588         }
1589
1590         /* Start out suspended */
1591         dev_priv->mm.suspended = 1;
1592
1593         if (HAS_POWER_WELL(dev))
1594                 i915_init_power_well(dev);
1595
1596         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1597                 ret = i915_load_modeset_init(dev);
1598                 if (ret < 0) {
1599                         DRM_ERROR("failed to init modeset\n");
1600                         goto out_gem_unload;
1601                 }
1602         }
1603
1604 #if 0
1605         i915_setup_sysfs(dev);
1606 #endif
1607
1608         if (INTEL_INFO(dev)->num_pipes) {
1609                 /* Must be done after probing outputs */
1610                 intel_opregion_init(dev);
1611 #if 0
1612                 acpi_video_register();
1613 #endif
1614         }
1615
1616         if (IS_GEN5(dev))
1617                 intel_gpu_ips_init(dev_priv);
1618
1619         return 0;
1620
1621 out_gem_unload:
1622
1623         intel_teardown_gmbus(dev);
1624         intel_teardown_mchbar(dev);
1625         destroy_workqueue(dev_priv->wq);
1626 out_mtrrfree:
1627         arch_phys_wc_del(dev_priv->mm.gtt_mtrr);
1628 #if 0
1629         io_mapping_free(dev_priv->gtt.mappable);
1630 #endif
1631         dev_priv->gtt.gtt_remove(dev);
1632 put_bridge:
1633 free_priv:
1634         kfree(dev_priv);
1635         return ret;
1636 }
1637
1638 int i915_driver_unload(struct drm_device *dev)
1639 {
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         int ret;
1642
1643         intel_gpu_ips_teardown();
1644
1645         if (HAS_POWER_WELL(dev))
1646                 i915_remove_power_well(dev);
1647
1648 #if 0
1649         i915_teardown_sysfs(dev);
1650
1651         if (dev_priv->mm.inactive_shrinker.shrink)
1652                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1653 #endif
1654
1655         mutex_lock(&dev->struct_mutex);
1656         ret = i915_gpu_idle(dev);
1657         if (ret)
1658                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1659         i915_gem_retire_requests(dev);
1660         mutex_unlock(&dev->struct_mutex);
1661
1662         /* Cancel the retire work handler, which should be idle now. */
1663         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1664
1665 #if 0
1666         io_mapping_free(dev_priv->gtt.mappable);
1667 #endif
1668         arch_phys_wc_del(dev_priv->mm.gtt_mtrr);
1669
1670 #if 0
1671         acpi_video_unregister();
1672 #endif
1673
1674         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1675                 intel_fbdev_fini(dev);
1676                 intel_modeset_cleanup(dev);
1677 #if 0
1678                 cancel_work_sync(&dev_priv->console_resume_work);
1679 #endif
1680
1681                 /*
1682                  * free the memory space allocated for the child device
1683                  * config parsed from VBT
1684                  */
1685                 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1686                         kfree(dev_priv->vbt.child_dev);
1687                         dev_priv->vbt.child_dev = NULL;
1688                         dev_priv->vbt.child_dev_num = 0;
1689                 }
1690
1691         }
1692
1693         /* Free error state after interrupts are fully disabled. */
1694         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1695         cancel_work_sync(&dev_priv->gpu_error.work);
1696         i915_destroy_error_state(dev);
1697
1698         intel_opregion_fini(dev);
1699
1700         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1701                 /* Flush any outstanding unpin_work. */
1702                 flush_workqueue(dev_priv->wq);
1703
1704                 mutex_lock(&dev->struct_mutex);
1705                 i915_gem_free_all_phys_object(dev);
1706                 i915_gem_cleanup_ringbuffer(dev);
1707                 i915_gem_context_fini(dev);
1708                 mutex_unlock(&dev->struct_mutex);
1709                 i915_gem_cleanup_aliasing_ppgtt(dev);
1710 #if 0
1711                 i915_gem_cleanup_stolen(dev);
1712 #endif
1713
1714                 if (!I915_NEED_GFX_HWS(dev))
1715                         i915_free_hws(dev);
1716         }
1717
1718         drm_mm_takedown(&dev_priv->mm.gtt_space);
1719 #if 0
1720         if (dev_priv->regs != NULL)
1721                 pci_iounmap(dev->pdev, dev_priv->regs);
1722 #endif
1723
1724         intel_teardown_gmbus(dev);
1725         intel_teardown_mchbar(dev);
1726
1727         bus_generic_detach(dev->dev);
1728         drm_rmmap(dev, dev_priv->mmio_map);
1729         intel_teardown_gmbus(dev);
1730
1731         destroy_workqueue(dev_priv->wq);
1732         pm_qos_remove_request(&dev_priv->pm_qos);
1733
1734         dev_priv->gtt.gtt_remove(dev);
1735
1736         pci_dev_put(dev_priv->bridge_dev);
1737         drm_free(dev->dev_private, M_DRM);
1738
1739         return 0;
1740 }
1741
1742 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1743 {
1744         struct drm_i915_file_private *file_priv;
1745
1746         DRM_DEBUG_DRIVER("\n");
1747         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
1748         if (!file_priv)
1749                 return -ENOMEM;
1750
1751         file->driver_priv = file_priv;
1752
1753         spin_init(&file_priv->mm.lock, "i915_priv");
1754         INIT_LIST_HEAD(&file_priv->mm.request_list);
1755
1756         idr_init(&file_priv->context_idr);
1757
1758         return 0;
1759 }
1760
1761 /**
1762  * i915_driver_lastclose - clean up after all DRM clients have exited
1763  * @dev: DRM device
1764  *
1765  * Take care of cleaning up after all DRM clients have exited.  In the
1766  * mode setting case, we want to restore the kernel's initial mode (just
1767  * in case the last client left us in a bad state).
1768  *
1769  * Additionally, in the non-mode setting case, we'll tear down the GTT
1770  * and DMA structures, since the kernel won't be using them, and clea
1771  * up any GEM state.
1772  */
1773 void i915_driver_lastclose(struct drm_device * dev)
1774 {
1775         drm_i915_private_t *dev_priv = dev->dev_private;
1776
1777         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1778          * goes right around and calls lastclose. Check for this and don't clean
1779          * up anything. */
1780         if (!dev_priv)
1781                 return;
1782
1783         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1784 #if 0
1785                 intel_fb_restore_mode(dev);
1786                 vga_switcheroo_process_delayed_switch();
1787 #endif
1788                 return;
1789         }
1790
1791         i915_gem_lastclose(dev);
1792
1793         i915_dma_cleanup(dev);
1794 }
1795
1796 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1797 {
1798         i915_gem_context_close(dev, file_priv);
1799         i915_gem_release(dev, file_priv);
1800 }
1801
1802 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1803 {
1804         struct drm_i915_file_private *file_priv = file->driver_priv;
1805
1806         kfree(file_priv);
1807 }
1808
1809 struct drm_ioctl_desc i915_ioctls[] = {
1810         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1811         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1812         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1813         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1814         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1815         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1816         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1817         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1818         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1819         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1820         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1821         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1822         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1823         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1824         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1825         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1826         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1827         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1828         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1829         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1830         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1831         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1832         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1833         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1834         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1835         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1836         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1837         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1838         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1839         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1840         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1841         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1842         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1843         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1844         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1845         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1846         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1847         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1848         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1849         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1850         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1851         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1852         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1853         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1854         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1855         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1856         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1857         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1858 };
1859
1860 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1861
1862 /*
1863  * This is really ugly: Because old userspace abused the linux agp interface to
1864  * manage the gtt, we need to claim that all intel devices are agp.  For
1865  * otherwise the drm core refuses to initialize the agp support code.
1866  */
1867 int i915_driver_device_is_agp(struct drm_device * dev)
1868 {
1869         return 1;
1870 }