sys/dev/drm2/i915/i915_gem.c

   1 /*-
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  * Copyright (c) 2011 The FreeBSD Foundation
  27  * All rights reserved.
  28  *
  29  * This software was developed by Konstantin Belousov under sponsorship from
  30  * the FreeBSD Foundation.
  31  *
  32  * Redistribution and use in source and binary forms, with or without
  33  * modification, are permitted provided that the following conditions
  34  * are met:
  35  * 1. Redistributions of source code must retain the above copyright
  36  *    notice, this list of conditions and the following disclaimer.
  37  * 2. Redistributions in binary form must reproduce the above copyright
  38  *    notice, this list of conditions and the following disclaimer in the
  39  *    documentation and/or other materials provided with the distribution.
  40  *
  41  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  42  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  43  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  44  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  45  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  46  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  47  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  48  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  49  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  50  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  51  * SUCH DAMAGE.
  52  *
  53  * $FreeBSD: src/sys/dev/drm2/i915/i915_gem.c,v 1.2 2012/05/28 21:15:54 alc Exp $
  54  */
  55
  56 #include <dev/drm2/drmP.h>
  57 #include <dev/drm2/drm.h>
  58 #include <dev/drm2/i915/i915_drm.h>
  59 #include <dev/drm2/i915/i915_drv.h>
  60 #include <dev/drm2/i915/intel_drv.h>
  61 #include <dev/drm2/i915/intel_ringbuffer.h>
  62 #include <sys/resourcevar.h>
  63 #include <sys/sched.h>
  64 #include <sys/sf_buf.h>
  65
  66 static void i915_gem_object_flush_cpu_write_domain(
  67     struct drm_i915_gem_object *obj);
  68 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
  69     int tiling_mode);
  70 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
  71     uint32_t size, int tiling_mode);
  72 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  73     unsigned alignment, bool map_and_fenceable);
  74 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
  75     int flags);
  76 static void i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj);
  77 static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  78     bool write);
  79 static void i915_gem_object_set_to_full_cpu_read_domain(
  80     struct drm_i915_gem_object *obj);
  81 static int i915_gem_object_set_cpu_read_domain_range(
  82     struct drm_i915_gem_object *obj, uint64_t offset, uint64_t size);
  83 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
  84 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  85 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
  86 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
  87 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
  88 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
  89 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
  90     uint32_t flush_domains);
  91 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  92     struct drm_i915_fence_reg *reg);
  93 static void i915_gem_reset_fences(struct drm_device *dev);
  94 static void i915_gem_retire_task_handler(void *arg, int pending);
  95 static int i915_gem_phys_pwrite(struct drm_device *dev,
  96     struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
  97     uint64_t size, struct drm_file *file_priv);
  98 static void i915_gem_lowmem(void *arg);
  99
 100 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
 101 long i915_gem_wired_pages_cnt;
 102
 103 static void
 104 i915_gem_info_add_obj(struct drm_i915_private *dev_priv, size_t size)
 105 {
 106
 107         dev_priv->mm.object_count++;
 108         dev_priv->mm.object_memory += size;
 109 }
 110
 111 static void
 112 i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, size_t size)
 113 {
 114
 115         dev_priv->mm.object_count--;
 116         dev_priv->mm.object_memory -= size;
 117 }
 118
 119 static int
 120 i915_gem_wait_for_error(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv;
 123         int ret;
 124
 125         dev_priv = dev->dev_private;
 126         if (!atomic_load_acq_int(&dev_priv->mm.wedged))
 127                 return (0);
 128
 129         lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
 130         while (dev_priv->error_completion == 0) {
 131                 ret = -lksleep(&dev_priv->error_completion,
 132                     &dev_priv->error_completion_lock, PCATCH, "915wco", 0);
 133                 if (ret != 0) {
 134                         lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 135                         return (ret);
 136                 }
 137         }
 138         lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 139
 140         if (atomic_read(&dev_priv->mm.wedged)) {
 141                 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
 142                 dev_priv->error_completion++;
 143                 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 144         }
 145         return (0);
 146 }
 147
 148 int
 149 i915_mutex_lock_interruptible(struct drm_device *dev)
 150 {
 151         struct drm_i915_private *dev_priv;
 152         int ret;
 153
 154         dev_priv = dev->dev_private;
 155         ret = i915_gem_wait_for_error(dev);
 156         if (ret != 0)
 157                 return (ret);
 158
 159         /*
 160          * interruptible shall it be. might indeed be if dev_lock is
 161          * changed to sx
 162          */
 163         ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
 164         if (ret != 0)
 165                 return (-ret);
 166
 167         return (0);
 168 }
 169
 170
 171 static void
 172 i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
 173 {
 174         struct drm_device *dev;
 175         drm_i915_private_t *dev_priv;
 176         int ret;
 177
 178         dev = obj->base.dev;
 179         dev_priv = dev->dev_private;
 180
 181         ret = i915_gem_object_unbind(obj);
 182         if (ret == -ERESTART) {
 183                 list_move(&obj->mm_list, &dev_priv->mm.deferred_free_list);
 184                 return;
 185         }
 186
 187         drm_gem_free_mmap_offset(&obj->base);
 188         drm_gem_object_release(&obj->base);
 189         i915_gem_info_remove_obj(dev_priv, obj->base.size);
 190
 191         kfree(obj->page_cpu_valid, DRM_I915_GEM);
 192         kfree(obj->bit_17, DRM_I915_GEM);
 193         kfree(obj, DRM_I915_GEM);
 194 }
 195
 196 void
 197 i915_gem_free_object(struct drm_gem_object *gem_obj)
 198 {
 199         struct drm_i915_gem_object *obj;
 200         struct drm_device *dev;
 201
 202         obj = to_intel_bo(gem_obj);
 203         dev = obj->base.dev;
 204
 205         while (obj->pin_count > 0)
 206                 i915_gem_object_unpin(obj);
 207
 208         if (obj->phys_obj != NULL)
 209                 i915_gem_detach_phys_object(dev, obj);
 210
 211         i915_gem_free_object_tail(obj);
 212 }
 213
 214 static void
 215 init_ring_lists(struct intel_ring_buffer *ring)
 216 {
 217
 218         INIT_LIST_HEAD(&ring->active_list);
 219         INIT_LIST_HEAD(&ring->request_list);
 220         INIT_LIST_HEAD(&ring->gpu_write_list);
 221 }
 222
 223 void
 224 i915_gem_load(struct drm_device *dev)
 225 {
 226         drm_i915_private_t *dev_priv;
 227         int i;
 228
 229         dev_priv = dev->dev_private;
 230
 231         INIT_LIST_HEAD(&dev_priv->mm.active_list);
 232         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
 233         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
 234         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
 235         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
 236         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
 237         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
 238         for (i = 0; i < I915_NUM_RINGS; i++)
 239                 init_ring_lists(&dev_priv->rings[i]);
 240         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
 241                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
 242         TIMEOUT_TASK_INIT(dev_priv->tq, &dev_priv->mm.retire_task, 0,
 243             i915_gem_retire_task_handler, dev_priv);
 244         dev_priv->error_completion = 0;
 245
 246         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
 247         if (IS_GEN3(dev)) {
 248                 u32 tmp = I915_READ(MI_ARB_STATE);
 249                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
 250                         /*
 251                          * arb state is a masked write, so set bit +
 252                          * bit in mask.
 253                          */
 254                         tmp = MI_ARB_C3_LP_WRITE_ENABLE |
 255                             (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
 256                         I915_WRITE(MI_ARB_STATE, tmp);
 257                 }
 258         }
 259
 260         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
 261
 262         /* Old X drivers will take 0-2 for front, back, depth buffers */
 263         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 264                 dev_priv->fence_reg_start = 3;
 265
 266         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) ||
 267             IS_G33(dev))
 268                 dev_priv->num_fence_regs = 16;
 269         else
 270                 dev_priv->num_fence_regs = 8;
 271
 272         /* Initialize fence registers to zero */
 273         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 274                 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
 275         }
 276         i915_gem_detect_bit_6_swizzle(dev);
 277         dev_priv->mm.interruptible = true;
 278
 279         dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
 280             i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
 281 }
 282
 283 int
 284 i915_gem_do_init(struct drm_device *dev, unsigned long start,
 285     unsigned long mappable_end, unsigned long end)
 286 {
 287         drm_i915_private_t *dev_priv;
 288         unsigned long mappable;
 289         int error;
 290
 291         dev_priv = dev->dev_private;
 292         mappable = min(end, mappable_end) - start;
 293
 294         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 295
 296         dev_priv->mm.gtt_start = start;
 297         dev_priv->mm.gtt_mappable_end = mappable_end;
 298         dev_priv->mm.gtt_end = end;
 299         dev_priv->mm.gtt_total = end - start;
 300         dev_priv->mm.mappable_gtt_total = mappable;
 301
 302         /* Take over this portion of the GTT */
 303         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 304         device_printf(dev->device,
 305             "taking over the fictitious range 0x%lx-0x%lx\n",
 306             dev->agp->base + start, dev->agp->base + start + mappable);
 307         error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
 308             dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
 309         return (error);
 310 }
 311
 312 int
 313 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 314     struct drm_file *file)
 315 {
 316         struct drm_i915_gem_init *args;
 317         drm_i915_private_t *dev_priv;
 318
 319         dev_priv = dev->dev_private;
 320         args = data;
 321
 322         if (args->gtt_start >= args->gtt_end ||
 323             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 324                 return (-EINVAL);
 325
 326         if (mtx_initialized(&dev_priv->mm.gtt_space.unused_lock))
 327                 return (-EBUSY);
 328         /*
 329          * XXXKIB. The second-time initialization should be guarded
 330          * against.
 331          */
 332         return (i915_gem_do_init(dev, args->gtt_start, args->gtt_end,
 333             args->gtt_end));
 334 }
 335
 336 int
 337 i915_gem_idle(struct drm_device *dev)
 338 {
 339         drm_i915_private_t *dev_priv;
 340         int ret;
 341
 342         dev_priv = dev->dev_private;
 343         if (dev_priv->mm.suspended)
 344                 return (0);
 345
 346         ret = i915_gpu_idle(dev, true);
 347         if (ret != 0)
 348                 return (ret);
 349
 350         /* Under UMS, be paranoid and evict. */
 351         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 352                 ret = i915_gem_evict_inactive(dev, false);
 353                 if (ret != 0)
 354                         return ret;
 355         }
 356
 357         i915_gem_reset_fences(dev);
 358
 359         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
 360          * We need to replace this with a semaphore, or something.
 361          * And not confound mm.suspended!
 362          */
 363         dev_priv->mm.suspended = 1;
 364         callout_stop(&dev_priv->hangcheck_timer);
 365
 366         i915_kernel_lost_context(dev);
 367         i915_gem_cleanup_ringbuffer(dev);
 368
 369         /* Cancel the retire work handler, which should be idle now. */
 370         taskqueue_cancel_timeout(dev_priv->tq, &dev_priv->mm.retire_task, NULL);
 371         return (ret);
 372 }
 373
 374 void
 375 i915_gem_init_swizzling(struct drm_device *dev)
 376 {
 377         drm_i915_private_t *dev_priv;
 378
 379         dev_priv = dev->dev_private;
 380
 381         if (INTEL_INFO(dev)->gen < 5 ||
 382             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
 383                 return;
 384
 385         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
 386                                  DISP_TILE_SURFACE_SWIZZLING);
 387
 388         if (IS_GEN5(dev))
 389                 return;
 390
 391         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
 392         if (IS_GEN6(dev))
 393                 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB));
 394         else
 395                 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB));
 396 }
 397
 398 void
 399 i915_gem_init_ppgtt(struct drm_device *dev)
 400 {
 401         drm_i915_private_t *dev_priv;
 402         struct i915_hw_ppgtt *ppgtt;
 403         uint32_t pd_offset, pd_entry;
 404         vm_paddr_t pt_addr;
 405         struct intel_ring_buffer *ring;
 406         u_int first_pd_entry_in_global_pt, i;
 407
 408         dev_priv = dev->dev_private;
 409         ppgtt = dev_priv->mm.aliasing_ppgtt;
 410         if (ppgtt == NULL)
 411                 return;
 412
 413         first_pd_entry_in_global_pt = 512 * 1024 - I915_PPGTT_PD_ENTRIES;
 414         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 415                 pt_addr = VM_PAGE_TO_PHYS(ppgtt->pt_pages[i]);
 416                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 417                 pd_entry |= GEN6_PDE_VALID;
 418                 intel_gtt_write(first_pd_entry_in_global_pt + i, pd_entry);
 419         }
 420         intel_gtt_read_pte(first_pd_entry_in_global_pt);
 421
 422         pd_offset = ppgtt->pd_offset;
 423         pd_offset /= 64; /* in cachelines, */
 424         pd_offset <<= 16;
 425
 426         if (INTEL_INFO(dev)->gen == 6) {
 427                 uint32_t ecochk = I915_READ(GAM_ECOCHK);
 428                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 429                                        ECOCHK_PPGTT_CACHE64B);
 430                 I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
 431         } else if (INTEL_INFO(dev)->gen >= 7) {
 432                 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
 433                 /* GFX_MODE is per-ring on gen7+ */
 434         }
 435
 436         for (i = 0; i < I915_NUM_RINGS; i++) {
 437                 ring = &dev_priv->rings[i];
 438
 439                 if (INTEL_INFO(dev)->gen >= 7)
 440                         I915_WRITE(RING_MODE_GEN7(ring),
 441                                    GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
 442
 443                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 444                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 445         }
 446 }
 447
 448 int
 449 i915_gem_init_hw(struct drm_device *dev)
 450 {
 451         drm_i915_private_t *dev_priv;
 452         int ret;
 453
 454         dev_priv = dev->dev_private;
 455
 456         i915_gem_init_swizzling(dev);
 457
 458         ret = intel_init_render_ring_buffer(dev);
 459         if (ret != 0)
 460                 return (ret);
 461
 462         if (HAS_BSD(dev)) {
 463                 ret = intel_init_bsd_ring_buffer(dev);
 464                 if (ret != 0)
 465                         goto cleanup_render_ring;
 466         }
 467
 468         if (HAS_BLT(dev)) {
 469                 ret = intel_init_blt_ring_buffer(dev);
 470                 if (ret != 0)
 471                         goto cleanup_bsd_ring;
 472         }
 473
 474         dev_priv->next_seqno = 1;
 475         i915_gem_init_ppgtt(dev);
 476         return (0);
 477
 478 cleanup_bsd_ring:
 479         intel_cleanup_ring_buffer(&dev_priv->rings[VCS]);
 480 cleanup_render_ring:
 481         intel_cleanup_ring_buffer(&dev_priv->rings[RCS]);
 482         return (ret);
 483 }
 484
 485 int
 486 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 487     struct drm_file *file)
 488 {
 489         struct drm_i915_private *dev_priv;
 490         struct drm_i915_gem_get_aperture *args;
 491         struct drm_i915_gem_object *obj;
 492         size_t pinned;
 493
 494         dev_priv = dev->dev_private;
 495         args = data;
 496
 497         if (!(dev->driver->driver_features & DRIVER_GEM))
 498                 return (-ENODEV);
 499
 500         pinned = 0;
 501         DRM_LOCK(dev);
 502         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 503                 pinned += obj->gtt_space->size;
 504         DRM_UNLOCK(dev);
 505
 506         args->aper_size = dev_priv->mm.gtt_total;
 507         args->aper_available_size = args->aper_size - pinned;
 508
 509         return (0);
 510 }
 511
 512 int
 513 i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
 514      bool map_and_fenceable)
 515 {
 516         struct drm_device *dev;
 517         struct drm_i915_private *dev_priv;
 518         int ret;
 519
 520         dev = obj->base.dev;
 521         dev_priv = dev->dev_private;
 522
 523         KASSERT(obj->pin_count != DRM_I915_GEM_OBJECT_MAX_PIN_COUNT,
 524             ("Max pin count"));
 525
 526         if (obj->gtt_space != NULL) {
 527                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
 528                     (map_and_fenceable && !obj->map_and_fenceable)) {
 529                         DRM_DEBUG("bo is already pinned with incorrect alignment:"
 530                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
 531                              " obj->map_and_fenceable=%d\n",
 532                              obj->gtt_offset, alignment,
 533                              map_and_fenceable,
 534                              obj->map_and_fenceable);
 535                         ret = i915_gem_object_unbind(obj);
 536                         if (ret != 0)
 537                                 return (ret);
 538                 }
 539         }
 540
 541         if (obj->gtt_space == NULL) {
 542                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
 543                     map_and_fenceable);
 544                 if (ret)
 545                         return (ret);
 546         }
 547
 548         if (obj->pin_count++ == 0 && !obj->active)
 549                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
 550         obj->pin_mappable |= map_and_fenceable;
 551
 552 #if 1
 553         KIB_NOTYET();
 554 #else
 555         WARN_ON(i915_verify_lists(dev));
 556 #endif
 557         return (0);
 558 }
 559
 560 void
 561 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
 562 {
 563         struct drm_device *dev;
 564         drm_i915_private_t *dev_priv;
 565
 566         dev = obj->base.dev;
 567         dev_priv = dev->dev_private;
 568
 569 #if 1
 570         KIB_NOTYET();
 571 #else
 572         WARN_ON(i915_verify_lists(dev));
 573 #endif
 574
 575         KASSERT(obj->pin_count != 0, ("zero pin count"));
 576         KASSERT(obj->gtt_space != NULL, ("No gtt mapping"));
 577
 578         if (--obj->pin_count == 0) {
 579                 if (!obj->active)
 580                         list_move_tail(&obj->mm_list,
 581                             &dev_priv->mm.inactive_list);
 582                 obj->pin_mappable = false;
 583         }
 584 #if 1
 585         KIB_NOTYET();
 586 #else
 587         WARN_ON(i915_verify_lists(dev));
 588 #endif
 589 }
 590
 591 int
 592 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 593     struct drm_file *file)
 594 {
 595         struct drm_i915_gem_pin *args;
 596         struct drm_i915_gem_object *obj;
 597         struct drm_gem_object *gobj;
 598         int ret;
 599
 600         args = data;
 601
 602         ret = i915_mutex_lock_interruptible(dev);
 603         if (ret != 0)
 604                 return ret;
 605
 606         gobj = drm_gem_object_lookup(dev, file, args->handle);
 607         if (gobj == NULL) {
 608                 ret = -ENOENT;
 609                 goto unlock;
 610         }
 611         obj = to_intel_bo(gobj);
 612
 613         if (obj->madv != I915_MADV_WILLNEED) {
 614                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
 615                 ret = -EINVAL;
 616                 goto out;
 617         }
 618
 619         if (obj->pin_filp != NULL && obj->pin_filp != file) {
 620                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
 621                     args->handle);
 622                 ret = -EINVAL;
 623                 goto out;
 624         }
 625
 626         obj->user_pin_count++;
 627         obj->pin_filp = file;
 628         if (obj->user_pin_count == 1) {
 629                 ret = i915_gem_object_pin(obj, args->alignment, true);
 630                 if (ret != 0)
 631                         goto out;
 632         }
 633
 634         /* XXX - flush the CPU caches for pinned objects
 635          * as the X server doesn't manage domains yet
 636          */
 637         i915_gem_object_flush_cpu_write_domain(obj);
 638         args->offset = obj->gtt_offset;
 639 out:
 640         drm_gem_object_unreference(&obj->base);
 641 unlock:
 642         DRM_UNLOCK(dev);
 643         return (ret);
 644 }
 645
 646 int
 647 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 648     struct drm_file *file)
 649 {
 650         struct drm_i915_gem_pin *args;
 651         struct drm_i915_gem_object *obj;
 652         int ret;
 653
 654         args = data;
 655         ret = i915_mutex_lock_interruptible(dev);
 656         if (ret != 0)
 657                 return (ret);
 658
 659         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 660         if (&obj->base == NULL) {
 661                 ret = -ENOENT;
 662                 goto unlock;
 663         }
 664
 665         if (obj->pin_filp != file) {
 666                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
 667                     args->handle);
 668                 ret = -EINVAL;
 669                 goto out;
 670         }
 671         obj->user_pin_count--;
 672         if (obj->user_pin_count == 0) {
 673                 obj->pin_filp = NULL;
 674                 i915_gem_object_unpin(obj);
 675         }
 676
 677 out:
 678         drm_gem_object_unreference(&obj->base);
 679 unlock:
 680         DRM_UNLOCK(dev);
 681         return (ret);
 682 }
 683
 684 int
 685 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 686     struct drm_file *file)
 687 {
 688         struct drm_i915_gem_busy *args;
 689         struct drm_i915_gem_object *obj;
 690         struct drm_i915_gem_request *request;
 691         int ret;
 692
 693         args = data;
 694
 695         ret = i915_mutex_lock_interruptible(dev);
 696         if (ret != 0)
 697                 return ret;
 698
 699         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 700         if (&obj->base == NULL) {
 701                 ret = -ENOENT;
 702                 goto unlock;
 703         }
 704
 705         args->busy = obj->active;
 706         if (args->busy) {
 707                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
 708                         ret = i915_gem_flush_ring(obj->ring,
 709                             0, obj->base.write_domain);
 710                 } else if (obj->ring->outstanding_lazy_request ==
 711                     obj->last_rendering_seqno) {
 712                         request = kmalloc(sizeof(*request), DRM_I915_GEM,
 713                             M_WAITOK | M_ZERO);
 714                         ret = i915_add_request(obj->ring, NULL, request);
 715                         if (ret != 0)
 716                                 kfree(request, DRM_I915_GEM);
 717                 }
 718
 719                 i915_gem_retire_requests_ring(obj->ring);
 720                 args->busy = obj->active;
 721         }
 722
 723         drm_gem_object_unreference(&obj->base);
 724 unlock:
 725         DRM_UNLOCK(dev);
 726         return (ret);
 727 }
 728
 729 static int
 730 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
 731 {
 732         struct drm_i915_private *dev_priv;
 733         struct drm_i915_file_private *file_priv;
 734         unsigned long recent_enough;
 735         struct drm_i915_gem_request *request;
 736         struct intel_ring_buffer *ring;
 737         u32 seqno;
 738         int ret;
 739
 740         dev_priv = dev->dev_private;
 741         if (atomic_read(&dev_priv->mm.wedged))
 742                 return (-EIO);
 743
 744         file_priv = file->driver_priv;
 745         recent_enough = ticks - (20 * hz / 1000);
 746         ring = NULL;
 747         seqno = 0;
 748
 749         lockmgr(&file_priv->mm.lck, LK_EXCLUSIVE);
 750         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
 751                 if (time_after_eq(request->emitted_jiffies, recent_enough))
 752                         break;
 753                 ring = request->ring;
 754                 seqno = request->seqno;
 755         }
 756         lockmgr(&file_priv->mm.lck, LK_RELEASE);
 757         if (seqno == 0)
 758                 return (0);
 759
 760         ret = 0;
 761         lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
 762         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
 763                 if (ring->irq_get(ring)) {
 764                         while (ret == 0 &&
 765                             !(i915_seqno_passed(ring->get_seqno(ring), seqno) ||
 766                             atomic_read(&dev_priv->mm.wedged)))
 767                                 ret = -lksleep(ring, &ring->irq_lock, PCATCH,
 768                                     "915thr", 0);
 769                         ring->irq_put(ring);
 770                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
 771                                 ret = -EIO;
 772                 } else if (_intel_wait_for(dev,
 773                     i915_seqno_passed(ring->get_seqno(ring), seqno) ||
 774                     atomic_read(&dev_priv->mm.wedged), 3000, 0, "915rtr")) {
 775                         ret = -EBUSY;
 776                 }
 777         }
 778         lockmgr(&ring->irq_lock, LK_RELEASE);
 779
 780         if (ret == 0)
 781                 taskqueue_enqueue_timeout(dev_priv->tq,
 782                     &dev_priv->mm.retire_task, 0);
 783
 784         return (ret);
 785 }
 786
 787 int
 788 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 789     struct drm_file *file_priv)
 790 {
 791
 792         return (i915_gem_ring_throttle(dev, file_priv));
 793 }
 794
 795 int
 796 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 797     struct drm_file *file_priv)
 798 {
 799         struct drm_i915_gem_madvise *args;
 800         struct drm_i915_gem_object *obj;
 801         int ret;
 802
 803         args = data;
 804         switch (args->madv) {
 805         case I915_MADV_DONTNEED:
 806         case I915_MADV_WILLNEED:
 807                 break;
 808         default:
 809                 return (-EINVAL);
 810         }
 811
 812         ret = i915_mutex_lock_interruptible(dev);
 813         if (ret != 0)
 814                 return (ret);
 815
 816         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
 817         if (&obj->base == NULL) {
 818                 ret = -ENOENT;
 819                 goto unlock;
 820         }
 821
 822         if (obj->pin_count != 0) {
 823                 ret = -EINVAL;
 824                 goto out;
 825         }
 826
 827         if (obj->madv != I915_MADV_PURGED_INTERNAL)
 828                 obj->madv = args->madv;
 829         if (i915_gem_object_is_purgeable(obj) && obj->gtt_space == NULL)
 830                 i915_gem_object_truncate(obj);
 831         args->retained = obj->madv != I915_MADV_PURGED_INTERNAL;
 832
 833 out:
 834         drm_gem_object_unreference(&obj->base);
 835 unlock:
 836         DRM_UNLOCK(dev);
 837         return (ret);
 838 }
 839
 840 void
 841 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
 842 {
 843         drm_i915_private_t *dev_priv;
 844         int i;
 845
 846         dev_priv = dev->dev_private;
 847         for (i = 0; i < I915_NUM_RINGS; i++)
 848                 intel_cleanup_ring_buffer(&dev_priv->rings[i]);
 849 }
 850
 851 int
 852 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 853     struct drm_file *file_priv)
 854 {
 855         drm_i915_private_t *dev_priv;
 856         int ret, i;
 857
 858         if (drm_core_check_feature(dev, DRIVER_MODESET))
 859                 return (0);
 860         dev_priv = dev->dev_private;
 861         if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
 862                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
 863                 atomic_store_rel_int(&dev_priv->mm.wedged, 0);
 864         }
 865
 866         dev_priv->mm.suspended = 0;
 867
 868         ret = i915_gem_init_hw(dev);
 869         if (ret != 0) {
 870                 return (ret);
 871         }
 872
 873         KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
 874         KASSERT(list_empty(&dev_priv->mm.flushing_list), ("flushing list"));
 875         KASSERT(list_empty(&dev_priv->mm.inactive_list), ("inactive list"));
 876         for (i = 0; i < I915_NUM_RINGS; i++) {
 877                 KASSERT(list_empty(&dev_priv->rings[i].active_list),
 878                     ("ring %d active list", i));
 879                 KASSERT(list_empty(&dev_priv->rings[i].request_list),
 880                     ("ring %d request list", i));
 881         }
 882
 883         DRM_UNLOCK(dev);
 884         ret = drm_irq_install(dev);
 885         DRM_LOCK(dev);
 886         if (ret)
 887                 goto cleanup_ringbuffer;
 888
 889         return (0);
 890
 891 cleanup_ringbuffer:
 892         i915_gem_cleanup_ringbuffer(dev);
 893         dev_priv->mm.suspended = 1;
 894
 895         return (ret);
 896 }
 897
 898 int
 899 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 900     struct drm_file *file_priv)
 901 {
 902
 903         if (drm_core_check_feature(dev, DRIVER_MODESET))
 904                 return 0;
 905
 906         drm_irq_uninstall(dev);
 907         return (i915_gem_idle(dev));
 908 }
 909
 910 int
 911 i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size,
 912     uint32_t *handle_p)
 913 {
 914         struct drm_i915_gem_object *obj;
 915         uint32_t handle;
 916         int ret;
 917
 918         size = roundup(size, PAGE_SIZE);
 919         if (size == 0)
 920                 return (-EINVAL);
 921
 922         obj = i915_gem_alloc_object(dev, size);
 923         if (obj == NULL)
 924                 return (-ENOMEM);
 925
 926         handle = 0;
 927         ret = drm_gem_handle_create(file, &obj->base, &handle);
 928         if (ret != 0) {
 929                 drm_gem_object_release(&obj->base);
 930                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 931                 kfree(obj, DRM_I915_GEM);
 932                 return (-ret);
 933         }
 934
 935         /* drop reference from allocate - handle holds it now */
 936         drm_gem_object_unreference(&obj->base);
 937         *handle_p = handle;
 938         return (0);
 939 }
 940
 941 int
 942 i915_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 943     struct drm_mode_create_dumb *args)
 944 {
 945
 946         /* have to work out size/pitch and return them */
 947         args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
 948         args->size = args->pitch * args->height;
 949         return (i915_gem_create(file, dev, args->size, &args->handle));
 950 }
 951
 952 int
 953 i915_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
 954     uint32_t handle)
 955 {
 956
 957         return (drm_gem_handle_delete(file, handle));
 958 }
 959
 960 int
 961 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 962     struct drm_file *file)
 963 {
 964         struct drm_i915_gem_create *args = data;
 965
 966         return (i915_gem_create(file, dev, args->size, &args->handle));
 967 }
 968
 969 static int
 970 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
 971     uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
 972     struct drm_file *file)
 973 {
 974         vm_object_t vm_obj;
 975         vm_page_t m;
 976         struct sf_buf *sf;
 977         vm_offset_t mkva;
 978         vm_pindex_t obj_pi;
 979         int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
 980
 981         if (obj->gtt_offset != 0 && rw == UIO_READ)
 982                 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 983         else
 984                 do_bit17_swizzling = 0;
 985
 986         obj->dirty = 1;
 987         vm_obj = obj->base.vm_obj;
 988         ret = 0;
 989
 990         VM_OBJECT_LOCK(vm_obj);
 991         vm_object_pip_add(vm_obj, 1);
 992         while (size > 0) {
 993                 obj_pi = OFF_TO_IDX(offset);
 994                 obj_po = offset & PAGE_MASK;
 995
 996                 m = i915_gem_wire_page(vm_obj, obj_pi);
 997                 VM_OBJECT_UNLOCK(vm_obj);
 998
 999                 sched_pin();
1000                 sf = sf_buf_alloc(m, SFB_CPUPRIVATE);
1001                 mkva = sf_buf_kva(sf);
1002                 length = min(size, PAGE_SIZE - obj_po);
1003                 while (length > 0) {
1004                         if (do_bit17_swizzling &&
1005                             (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
1006                                 cnt = roundup2(obj_po + 1, 64);
1007                                 cnt = min(cnt - obj_po, length);
1008                                 swizzled_po = obj_po ^ 64;
1009                         } else {
1010                                 cnt = length;
1011                                 swizzled_po = obj_po;
1012                         }
1013                         if (rw == UIO_READ)
1014                                 ret = -copyout_nofault(
1015                                     (char *)mkva + swizzled_po,
1016                                     (void *)(uintptr_t)data_ptr, cnt);
1017                         else
1018                                 ret = -copyin_nofault(
1019                                     (void *)(uintptr_t)data_ptr,
1020                                     (char *)mkva + swizzled_po, cnt);
1021                         if (ret != 0)
1022                                 break;
1023                         data_ptr += cnt;
1024                         size -= cnt;
1025                         length -= cnt;
1026                         offset += cnt;
1027                         obj_po += cnt;
1028                 }
1029                 sf_buf_free(sf);
1030                 sched_unpin();
1031                 VM_OBJECT_LOCK(vm_obj);
1032                 if (rw == UIO_WRITE)
1033                         vm_page_dirty(m);
1034                 vm_page_reference(m);
1035                 vm_page_lock(m);
1036                 vm_page_unwire(m, 1);
1037                 vm_page_unlock(m);
1038                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
1039
1040                 if (ret != 0)
1041                         break;
1042         }
1043         vm_object_pip_wakeup(vm_obj);
1044         VM_OBJECT_UNLOCK(vm_obj);
1045
1046         return (ret);
1047 }
1048
1049 static int
1050 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
1051     uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
1052 {
1053         vm_offset_t mkva;
1054         vm_pindex_t obj_pi;
1055         int obj_po, ret;
1056
1057         obj_pi = OFF_TO_IDX(offset);
1058         obj_po = offset & PAGE_MASK;
1059
1060         mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
1061             IDX_TO_OFF(obj_pi), size, PAT_WRITE_COMBINING);
1062         ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva +
1063             obj_po, size);
1064         pmap_unmapdev(mkva, size);
1065         return (ret);
1066 }
1067
1068 static int
1069 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
1070     uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
1071 {
1072         struct drm_i915_gem_object *obj;
1073         vm_page_t *ma;
1074         vm_offset_t start, end;
1075         int npages, ret;
1076
1077         if (size == 0)
1078                 return (0);
1079         start = trunc_page(data_ptr);
1080         end = round_page(data_ptr + size);
1081         npages = howmany(end - start, PAGE_SIZE);
1082         ma = kmalloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
1083             M_ZERO);
1084         npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
1085             (vm_offset_t)data_ptr, size,
1086             (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
1087         if (npages == -1) {
1088                 ret = -EFAULT;
1089                 goto free_ma;
1090         }
1091
1092         ret = i915_mutex_lock_interruptible(dev);
1093         if (ret != 0)
1094                 goto unlocked;
1095
1096         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1097         if (&obj->base == NULL) {
1098                 ret = -ENOENT;
1099                 goto unlock;
1100         }
1101         if (offset > obj->base.size || size > obj->base.size - offset) {
1102                 ret = -EINVAL;
1103                 goto out;
1104         }
1105
1106         if (rw == UIO_READ) {
1107                 ret = i915_gem_object_set_cpu_read_domain_range(obj,
1108                     offset, size);
1109                 if (ret != 0)
1110                         goto out;
1111                 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1112                     UIO_READ, file);
1113         } else {
1114                 if (obj->phys_obj) {
1115                         ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
1116                             size, file);
1117                 } else if (obj->gtt_space &&
1118                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1119                         ret = i915_gem_object_pin(obj, 0, true);
1120                         if (ret != 0)
1121                                 goto out;
1122                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1123                         if (ret != 0)
1124                                 goto out_unpin;
1125                         ret = i915_gem_object_put_fence(obj);
1126                         if (ret != 0)
1127                                 goto out_unpin;
1128                         ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
1129                             offset, file);
1130 out_unpin:
1131                         i915_gem_object_unpin(obj);
1132                 } else {
1133                         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1134                         if (ret != 0)
1135                                 goto out;
1136                         ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1137                             UIO_WRITE, file);
1138                 }
1139         }
1140 out:
1141         drm_gem_object_unreference(&obj->base);
1142 unlock:
1143         DRM_UNLOCK(dev);
1144 unlocked:
1145         vm_page_unhold_pages(ma, npages);
1146 free_ma:
1147         kfree(ma, DRM_I915_GEM);
1148         return (ret);
1149 }
1150
1151 int
1152 i915_gem_pread_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1153 {
1154         struct drm_i915_gem_pread *args;
1155
1156         args = data;
1157         return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1158             args->offset, UIO_READ, file));
1159 }
1160
1161 int
1162 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1163 {
1164         struct drm_i915_gem_pwrite *args;
1165
1166         args = data;
1167         return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1168             args->offset, UIO_WRITE, file));
1169 }
1170
1171 int
1172 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1173     struct drm_file *file)
1174 {
1175         struct drm_i915_gem_set_domain *args;
1176         struct drm_i915_gem_object *obj;
1177         uint32_t read_domains;
1178         uint32_t write_domain;
1179         int ret;
1180
1181         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1182                 return (-ENODEV);
1183
1184         args = data;
1185         read_domains = args->read_domains;
1186         write_domain = args->write_domain;
1187
1188         if ((write_domain & I915_GEM_GPU_DOMAINS) != 0 ||
1189             (read_domains & I915_GEM_GPU_DOMAINS) != 0 ||
1190             (write_domain != 0 && read_domains != write_domain))
1191                 return (-EINVAL);
1192
1193         ret = i915_mutex_lock_interruptible(dev);
1194         if (ret != 0)
1195                 return (ret);
1196
1197         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1198         if (&obj->base == NULL) {
1199                 ret = -ENOENT;
1200                 goto unlock;
1201         }
1202
1203         if ((read_domains & I915_GEM_DOMAIN_GTT) != 0) {
1204                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1205                 if (ret == -EINVAL)
1206                         ret = 0;
1207         } else
1208                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1209
1210         drm_gem_object_unreference(&obj->base);
1211 unlock:
1212         DRM_UNLOCK(dev);
1213         return (ret);
1214 }
1215
1216 int
1217 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1218     struct drm_file *file)
1219 {
1220         struct drm_i915_gem_sw_finish *args;
1221         struct drm_i915_gem_object *obj;
1222         int ret;
1223
1224         args = data;
1225         ret = 0;
1226         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1227                 return (ENODEV);
1228         ret = i915_mutex_lock_interruptible(dev);
1229         if (ret != 0)
1230                 return (ret);
1231         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1232         if (&obj->base == NULL) {
1233                 ret = -ENOENT;
1234                 goto unlock;
1235         }
1236         if (obj->pin_count != 0)
1237                 i915_gem_object_flush_cpu_write_domain(obj);
1238         drm_gem_object_unreference(&obj->base);
1239 unlock:
1240         DRM_UNLOCK(dev);
1241         return (ret);
1242 }
1243
1244 #define PROC_LOCK(p)
1245 #define PROC_UNLOCK(p)
1246
1247 int
1248 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1249     struct drm_file *file)
1250 {
1251         struct drm_i915_gem_mmap *args;
1252         struct drm_gem_object *obj;
1253         struct proc *p;
1254         vm_map_t map;
1255         vm_offset_t addr;
1256         vm_size_t size;
1257         int error, rv;
1258
1259         args = data;
1260
1261         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1262                 return (-ENODEV);
1263
1264         obj = drm_gem_object_lookup(dev, file, args->handle);
1265         if (obj == NULL)
1266                 return (-ENOENT);
1267         error = 0;
1268         if (args->size == 0)
1269                 goto out;
1270         p = curproc;
1271         map = &p->p_vmspace->vm_map;
1272         size = round_page(args->size);
1273         PROC_LOCK(p);
1274         if (map->size + size > lim_cur(p, RLIMIT_VMEM)) {
1275                 PROC_UNLOCK(p);
1276                 error = ENOMEM;
1277                 goto out;
1278         }
1279         PROC_UNLOCK(p);
1280
1281         addr = 0;
1282         vm_object_reference(obj->vm_obj);
1283         DRM_UNLOCK(dev);
1284         rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size,
1285             VMFS_ANY_SPACE, VM_PROT_READ | VM_PROT_WRITE,
1286             VM_PROT_READ | VM_PROT_WRITE, MAP_SHARED);
1287         if (rv != KERN_SUCCESS) {
1288                 vm_object_deallocate(obj->vm_obj);
1289                 error = -vm_mmap_to_errno(rv);
1290         } else {
1291                 args->addr_ptr = (uint64_t)addr;
1292         }
1293         DRM_LOCK(dev);
1294 out:
1295         drm_gem_object_unreference(obj);
1296         return (error);
1297 }
1298
1299 static int
1300 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
1301     vm_ooffset_t foff, struct ucred *cred, u_short *color)
1302 {
1303
1304         *color = 0; /* XXXKIB */
1305         return (0);
1306 }
1307
1308 int i915_intr_pf;
1309
1310 static int
1311 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1312     vm_page_t *mres)
1313 {
1314         struct drm_gem_object *gem_obj;
1315         struct drm_i915_gem_object *obj;
1316         struct drm_device *dev;
1317         drm_i915_private_t *dev_priv;
1318         vm_page_t m, oldm;
1319         int cause, ret;
1320         bool write;
1321
1322         gem_obj = vm_obj->handle;
1323         obj = to_intel_bo(gem_obj);
1324         dev = obj->base.dev;
1325         dev_priv = dev->dev_private;
1326 #if 0
1327         write = (prot & VM_PROT_WRITE) != 0;
1328 #else
1329         write = true;
1330 #endif
1331         vm_object_pip_add(vm_obj, 1);
1332
1333         /*
1334          * Remove the placeholder page inserted by vm_fault() from the
1335          * object before dropping the object lock. If
1336          * i915_gem_release_mmap() is active in parallel on this gem
1337          * object, then it owns the drm device sx and might find the
1338          * placeholder already. Then, since the page is busy,
1339          * i915_gem_release_mmap() sleeps waiting for the busy state
1340          * of the page cleared. We will be not able to acquire drm
1341          * device lock until i915_gem_release_mmap() is able to make a
1342          * progress.
1343          */
1344         if (*mres != NULL) {
1345                 oldm = *mres;
1346                 vm_page_lock(oldm);
1347                 vm_page_remove(oldm);
1348                 vm_page_unlock(oldm);
1349                 *mres = NULL;
1350         } else
1351                 oldm = NULL;
1352 retry:
1353         VM_OBJECT_UNLOCK(vm_obj);
1354 unlocked_vmobj:
1355         cause = ret = 0;
1356         m = NULL;
1357
1358
1359         if (i915_intr_pf) {
1360                 ret = i915_mutex_lock_interruptible(dev);
1361                 if (ret != 0) {
1362                         cause = 10;
1363                         goto out;
1364                 }
1365         } else
1366                 DRM_LOCK(dev);
1367
1368         /* Now bind it into the GTT if needed */
1369         if (!obj->map_and_fenceable) {
1370                 ret = i915_gem_object_unbind(obj);
1371                 if (ret != 0) {
1372                         cause = 20;
1373                         goto unlock;
1374                 }
1375         }
1376         if (!obj->gtt_space) {
1377                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1378                 if (ret != 0) {
1379                         cause = 30;
1380                         goto unlock;
1381                 }
1382
1383                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1384                 if (ret != 0) {
1385                         cause = 40;
1386                         goto unlock;
1387                 }
1388         }
1389
1390         if (obj->tiling_mode == I915_TILING_NONE)
1391                 ret = i915_gem_object_put_fence(obj);
1392         else
1393                 ret = i915_gem_object_get_fence(obj, NULL);
1394         if (ret != 0) {
1395                 cause = 50;
1396                 goto unlock;
1397         }
1398
1399         if (i915_gem_object_is_inactive(obj))
1400                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1401
1402         obj->fault_mappable = true;
1403         VM_OBJECT_LOCK(vm_obj);
1404         m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
1405             offset);
1406         if (m == NULL) {
1407                 cause = 60;
1408                 ret = -EFAULT;
1409                 goto unlock;
1410         }
1411         KASSERT((m->flags & PG_FICTITIOUS) != 0,
1412             ("not fictitious %p", m));
1413         KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1414
1415         if ((m->flags & VPO_BUSY) != 0) {
1416                 DRM_UNLOCK(dev);
1417                 vm_page_sleep(m, "915pbs");
1418                 goto retry;
1419         }
1420         m->valid = VM_PAGE_BITS_ALL;
1421         *mres = m;
1422         vm_page_lock(m);
1423         vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1424         vm_page_unlock(m);
1425         vm_page_busy(m);
1426
1427         DRM_UNLOCK(dev);
1428         if (oldm != NULL) {
1429                 vm_page_lock(oldm);
1430                 vm_page_free(oldm);
1431                 vm_page_unlock(oldm);
1432         }
1433         vm_object_pip_wakeup(vm_obj);
1434         return (VM_PAGER_OK);
1435
1436 unlock:
1437         DRM_UNLOCK(dev);
1438 out:
1439         KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1440         if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1441                 kern_yield(PRI_USER);
1442                 goto unlocked_vmobj;
1443         }
1444         VM_OBJECT_LOCK(vm_obj);
1445         vm_object_pip_wakeup(vm_obj);
1446         return (VM_PAGER_ERROR);
1447 }
1448
1449 static void
1450 i915_gem_pager_dtor(void *handle)
1451 {
1452         struct drm_gem_object *obj;
1453         struct drm_device *dev;
1454
1455         obj = handle;
1456         dev = obj->dev;
1457
1458         DRM_LOCK(dev);
1459         drm_gem_free_mmap_offset(obj);
1460         i915_gem_release_mmap(to_intel_bo(obj));
1461         drm_gem_object_unreference(obj);
1462         DRM_UNLOCK(dev);
1463 }
1464
1465 struct cdev_pager_ops i915_gem_pager_ops = {
1466         .cdev_pg_fault  = i915_gem_pager_fault,
1467         .cdev_pg_ctor   = i915_gem_pager_ctor,
1468         .cdev_pg_dtor   = i915_gem_pager_dtor
1469 };
1470
1471 int
1472 i915_gem_mmap_gtt(struct drm_file *file, struct drm_device *dev,
1473     uint32_t handle, uint64_t *offset)
1474 {
1475         struct drm_i915_private *dev_priv;
1476         struct drm_i915_gem_object *obj;
1477         int ret;
1478
1479         if (!(dev->driver->driver_features & DRIVER_GEM))
1480                 return (-ENODEV);
1481
1482         dev_priv = dev->dev_private;
1483
1484         ret = i915_mutex_lock_interruptible(dev);
1485         if (ret != 0)
1486                 return (ret);
1487
1488         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1489         if (&obj->base == NULL) {
1490                 ret = -ENOENT;
1491                 goto unlock;
1492         }
1493
1494         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1495                 ret = -E2BIG;
1496                 goto out;
1497         }
1498
1499         if (obj->madv != I915_MADV_WILLNEED) {
1500                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1501                 ret = -EINVAL;
1502                 goto out;
1503         }
1504
1505         ret = drm_gem_create_mmap_offset(&obj->base);
1506         if (ret != 0)
1507                 goto out;
1508
1509         *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1510             DRM_GEM_MAPPING_KEY;
1511 out:
1512         drm_gem_object_unreference(&obj->base);
1513 unlock:
1514         DRM_UNLOCK(dev);
1515         return (ret);
1516 }
1517
1518 int
1519 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1520     struct drm_file *file)
1521 {
1522         struct drm_i915_private *dev_priv;
1523         struct drm_i915_gem_mmap_gtt *args;
1524
1525         dev_priv = dev->dev_private;
1526         args = data;
1527
1528         return (i915_gem_mmap_gtt(file, dev, args->handle, &args->offset));
1529 }
1530
1531 struct drm_i915_gem_object *
1532 i915_gem_alloc_object(struct drm_device *dev, size_t size)
1533 {
1534         struct drm_i915_private *dev_priv;
1535         struct drm_i915_gem_object *obj;
1536
1537         dev_priv = dev->dev_private;
1538
1539         obj = kmalloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
1540
1541         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
1542                 kfree(obj, DRM_I915_GEM);
1543                 return (NULL);
1544         }
1545
1546         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1547         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1548
1549         if (HAS_LLC(dev))
1550                 obj->cache_level = I915_CACHE_LLC;
1551         else
1552                 obj->cache_level = I915_CACHE_NONE;
1553         obj->base.driver_private = NULL;
1554         obj->fence_reg = I915_FENCE_REG_NONE;
1555         INIT_LIST_HEAD(&obj->mm_list);
1556         INIT_LIST_HEAD(&obj->gtt_list);
1557         INIT_LIST_HEAD(&obj->ring_list);
1558         INIT_LIST_HEAD(&obj->exec_list);
1559         INIT_LIST_HEAD(&obj->gpu_write_list);
1560         obj->madv = I915_MADV_WILLNEED;
1561         /* Avoid an unnecessary call to unbind on the first bind. */
1562         obj->map_and_fenceable = true;
1563
1564         i915_gem_info_add_obj(dev_priv, size);
1565
1566         return (obj);
1567 }
1568
1569 void
1570 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
1571 {
1572
1573         /* If we don't have a page list set up, then we're not pinned
1574          * to GPU, and we can ignore the cache flush because it'll happen
1575          * again at bind time.
1576          */
1577         if (obj->pages == NULL)
1578                 return;
1579
1580         /* If the GPU is snooping the contents of the CPU cache,
1581          * we do not need to manually clear the CPU cache lines.  However,
1582          * the caches are only snooped when the render cache is
1583          * flushed/invalidated.  As we always have to emit invalidations
1584          * and flushes when moving into and out of the RENDER domain, correct
1585          * snooping behaviour occurs naturally as the result of our domain
1586          * tracking.
1587          */
1588         if (obj->cache_level != I915_CACHE_NONE)
1589                 return;
1590
1591         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
1592 }
1593
1594 static void
1595 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
1596 {
1597         uint32_t old_write_domain;
1598
1599         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
1600                 return;
1601
1602         i915_gem_clflush_object(obj);
1603         intel_gtt_chipset_flush();
1604         old_write_domain = obj->base.write_domain;
1605         obj->base.write_domain = 0;
1606 }
1607
1608 static int
1609 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
1610 {
1611
1612         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
1613                 return (0);
1614         return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
1615 }
1616
1617 static void
1618 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
1619 {
1620         uint32_t old_write_domain;
1621
1622         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
1623                 return;
1624
1625         wmb();
1626
1627         old_write_domain = obj->base.write_domain;
1628         obj->base.write_domain = 0;
1629 }
1630
1631 int
1632 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
1633 {
1634         uint32_t old_write_domain, old_read_domains;
1635         int ret;
1636
1637         if (obj->gtt_space == NULL)
1638                 return (-EINVAL);
1639
1640         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
1641                 return 0;
1642
1643         ret = i915_gem_object_flush_gpu_write_domain(obj);
1644         if (ret != 0)
1645                 return (ret);
1646
1647         if (obj->pending_gpu_write || write) {
1648                 ret = i915_gem_object_wait_rendering(obj);
1649                 if (ret != 0)
1650                         return (ret);
1651         }
1652
1653         i915_gem_object_flush_cpu_write_domain(obj);
1654
1655         old_write_domain = obj->base.write_domain;
1656         old_read_domains = obj->base.read_domains;
1657
1658         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1659             ("In GTT write domain"));
1660         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1661         if (write) {
1662                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
1663                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
1664                 obj->dirty = 1;
1665         }
1666
1667         return (0);
1668 }
1669
1670 int
1671 i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1672     enum i915_cache_level cache_level)
1673 {
1674         struct drm_device *dev;
1675         drm_i915_private_t *dev_priv;
1676         int ret;
1677
1678         if (obj->cache_level == cache_level)
1679                 return 0;
1680
1681         if (obj->pin_count) {
1682                 DRM_DEBUG("can not change the cache level of pinned objects\n");
1683                 return (-EBUSY);
1684         }
1685
1686         dev = obj->base.dev;
1687         dev_priv = dev->dev_private;
1688         if (obj->gtt_space) {
1689                 ret = i915_gem_object_finish_gpu(obj);
1690                 if (ret != 0)
1691                         return (ret);
1692
1693                 i915_gem_object_finish_gtt(obj);
1694
1695                 /* Before SandyBridge, you could not use tiling or fence
1696                  * registers with snooped memory, so relinquish any fences
1697                  * currently pointing to our region in the aperture.
1698                  */
1699                 if (INTEL_INFO(obj->base.dev)->gen < 6) {
1700                         ret = i915_gem_object_put_fence(obj);
1701                         if (ret != 0)
1702                                 return (ret);
1703                 }
1704
1705                 i915_gem_gtt_rebind_object(obj, cache_level);
1706                 if (obj->has_aliasing_ppgtt_mapping)
1707                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
1708                             obj, cache_level);
1709         }
1710
1711         if (cache_level == I915_CACHE_NONE) {
1712                 u32 old_read_domains, old_write_domain;
1713
1714                 /* If we're coming from LLC cached, then we haven't
1715                  * actually been tracking whether the data is in the
1716                  * CPU cache or not, since we only allow one bit set
1717                  * in obj->write_domain and have been skipping the clflushes.
1718                  * Just set it to the CPU cache for now.
1719                  */
1720                 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1721                     ("obj %p in CPU write domain", obj));
1722                 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
1723                     ("obj %p in CPU read domain", obj));
1724
1725                 old_read_domains = obj->base.read_domains;
1726                 old_write_domain = obj->base.write_domain;
1727
1728                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1729                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1730
1731         }
1732
1733         obj->cache_level = cache_level;
1734         return (0);
1735 }
1736
1737 int
1738 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1739     u32 alignment, struct intel_ring_buffer *pipelined)
1740 {
1741         u32 old_read_domains, old_write_domain;
1742         int ret;
1743
1744         ret = i915_gem_object_flush_gpu_write_domain(obj);
1745         if (ret != 0)
1746                 return (ret);
1747
1748         if (pipelined != obj->ring) {
1749                 ret = i915_gem_object_wait_rendering(obj);
1750                 if (ret == -ERESTART || ret == -EINTR)
1751                         return (ret);
1752         }
1753
1754         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
1755         if (ret != 0)
1756                 return (ret);
1757
1758         ret = i915_gem_object_pin(obj, alignment, true);
1759         if (ret != 0)
1760                 return (ret);
1761
1762         i915_gem_object_flush_cpu_write_domain(obj);
1763
1764         old_write_domain = obj->base.write_domain;
1765         old_read_domains = obj->base.read_domains;
1766
1767         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1768             ("obj %p in GTT write domain", obj));
1769         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1770
1771         return (0);
1772 }
1773
1774 int
1775 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
1776 {
1777         int ret;
1778
1779         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
1780                 return (0);
1781
1782         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1783                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
1784                 if (ret != 0)
1785                         return (ret);
1786         }
1787
1788         ret = i915_gem_object_wait_rendering(obj);
1789         if (ret != 0)
1790                 return (ret);
1791
1792         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1793
1794         return (0);
1795 }
1796
1797 static int
1798 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
1799 {
1800         uint32_t old_write_domain, old_read_domains;
1801         int ret;
1802
1803         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
1804                 return 0;
1805
1806         ret = i915_gem_object_flush_gpu_write_domain(obj);
1807         if (ret != 0)
1808                 return (ret);
1809
1810         ret = i915_gem_object_wait_rendering(obj);
1811         if (ret != 0)
1812                 return (ret);
1813
1814         i915_gem_object_flush_gtt_write_domain(obj);
1815         i915_gem_object_set_to_full_cpu_read_domain(obj);
1816
1817         old_write_domain = obj->base.write_domain;
1818         old_read_domains = obj->base.read_domains;
1819
1820         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1821                 i915_gem_clflush_object(obj);
1822                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
1823         }
1824
1825         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1826             ("In cpu write domain"));
1827
1828         if (write) {
1829                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1830                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1831         }
1832
1833         return (0);
1834 }
1835
1836 static void
1837 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
1838 {
1839         int i;
1840
1841         if (obj->page_cpu_valid == NULL)
1842                 return;
1843
1844         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) {
1845                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
1846                         if (obj->page_cpu_valid[i] != 0)
1847                                 continue;
1848                         drm_clflush_pages(obj->pages + i, 1);
1849                 }
1850         }
1851
1852         kfree(obj->page_cpu_valid, DRM_I915_GEM);
1853         obj->page_cpu_valid = NULL;
1854 }
1855
1856 static int
1857 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
1858     uint64_t offset, uint64_t size)
1859 {
1860         uint32_t old_read_domains;
1861         int i, ret;
1862
1863         if (offset == 0 && size == obj->base.size)
1864                 return (i915_gem_object_set_to_cpu_domain(obj, 0));
1865
1866         ret = i915_gem_object_flush_gpu_write_domain(obj);
1867         if (ret != 0)
1868                 return (ret);
1869         ret = i915_gem_object_wait_rendering(obj);
1870         if (ret != 0)
1871                 return (ret);
1872
1873         i915_gem_object_flush_gtt_write_domain(obj);
1874
1875         if (obj->page_cpu_valid == NULL &&
1876             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
1877                 return (0);
1878
1879         if (obj->page_cpu_valid == NULL) {
1880                 obj->page_cpu_valid = kmalloc(obj->base.size / PAGE_SIZE,
1881                     DRM_I915_GEM, M_WAITOK | M_ZERO);
1882         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
1883                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
1884
1885         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
1886              i++) {
1887                 if (obj->page_cpu_valid[i])
1888                         continue;
1889                 drm_clflush_pages(obj->pages + i, 1);
1890                 obj->page_cpu_valid[i] = 1;
1891         }
1892
1893         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1894             ("In gpu write domain"));
1895
1896         old_read_domains = obj->base.read_domains;
1897         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
1898
1899         return (0);
1900 }
1901
1902 static uint32_t
1903 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1904 {
1905         uint32_t gtt_size;
1906
1907         if (INTEL_INFO(dev)->gen >= 4 ||
1908             tiling_mode == I915_TILING_NONE)
1909                 return (size);
1910
1911         /* Previous chips need a power-of-two fence region when tiling */
1912         if (INTEL_INFO(dev)->gen == 3)
1913                 gtt_size = 1024*1024;
1914         else
1915                 gtt_size = 512*1024;
1916
1917         while (gtt_size < size)
1918                 gtt_size <<= 1;
1919
1920         return (gtt_size);
1921 }
1922
1923 /**
1924  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1925  * @obj: object to check
1926  *
1927  * Return the required GTT alignment for an object, taking into account
1928  * potential fence register mapping.
1929  */
1930 static uint32_t
1931 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1932      int tiling_mode)
1933 {
1934
1935         /*
1936          * Minimum alignment is 4k (GTT page size), but might be greater
1937          * if a fence register is needed for the object.
1938          */
1939         if (INTEL_INFO(dev)->gen >= 4 ||
1940             tiling_mode == I915_TILING_NONE)
1941                 return (4096);
1942
1943         /*
1944          * Previous chips need to be aligned to the size of the smallest
1945          * fence register that can contain the object.
1946          */
1947         return (i915_gem_get_gtt_size(dev, size, tiling_mode));
1948 }
1949
1950 uint32_t
1951 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, uint32_t size,
1952     int tiling_mode)
1953 {
1954
1955         if (tiling_mode == I915_TILING_NONE)
1956                 return (4096);
1957
1958         /*
1959          * Minimum alignment is 4k (GTT page size) for sane hw.
1960          */
1961         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
1962                 return (4096);
1963
1964         /*
1965          * Previous hardware however needs to be aligned to a power-of-two
1966          * tile height. The simplest method for determining this is to reuse
1967          * the power-of-tile object size.
1968          */
1969         return (i915_gem_get_gtt_size(dev, size, tiling_mode));
1970 }
1971
1972 static int
1973 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
1974     unsigned alignment, bool map_and_fenceable)
1975 {
1976         struct drm_device *dev;
1977         struct drm_i915_private *dev_priv;
1978         struct drm_mm_node *free_space;
1979         uint32_t size, fence_size, fence_alignment, unfenced_alignment;
1980         bool mappable, fenceable;
1981         int ret;
1982
1983         dev = obj->base.dev;
1984         dev_priv = dev->dev_private;
1985
1986         if (obj->madv != I915_MADV_WILLNEED) {
1987                 DRM_ERROR("Attempting to bind a purgeable object\n");
1988                 return (-EINVAL);
1989         }
1990
1991         fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
1992             obj->tiling_mode);
1993         fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
1994             obj->tiling_mode);
1995         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
1996             obj->base.size, obj->tiling_mode);
1997         if (alignment == 0)
1998                 alignment = map_and_fenceable ? fence_alignment :
1999                     unfenced_alignment;
2000         if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
2001                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2002                 return (-EINVAL);
2003         }
2004
2005         size = map_and_fenceable ? fence_size : obj->base.size;
2006
2007         /* If the object is bigger than the entire aperture, reject it early
2008          * before evicting everything in a vain attempt to find space.
2009          */
2010         if (obj->base.size > (map_and_fenceable ?
2011             dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2012                 DRM_ERROR(
2013 "Attempting to bind an object larger than the aperture\n");
2014                 return (-E2BIG);
2015         }
2016
2017  search_free:
2018         if (map_and_fenceable)
2019                 free_space = drm_mm_search_free_in_range(
2020                     &dev_priv->mm.gtt_space, size, alignment, 0,
2021                     dev_priv->mm.gtt_mappable_end, 0);
2022         else
2023                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2024                     size, alignment, 0);
2025         if (free_space != NULL) {
2026                 if (map_and_fenceable)
2027                         obj->gtt_space = drm_mm_get_block_range_generic(
2028                             free_space, size, alignment, 0,
2029                             dev_priv->mm.gtt_mappable_end, 1);
2030                 else
2031                         obj->gtt_space = drm_mm_get_block_generic(free_space,
2032                             size, alignment, 1);
2033         }
2034         if (obj->gtt_space == NULL) {
2035                 ret = i915_gem_evict_something(dev, size, alignment,
2036                     map_and_fenceable);
2037                 if (ret != 0)
2038                         return (ret);
2039                 goto search_free;
2040         }
2041         ret = i915_gem_object_get_pages_gtt(obj, 0);
2042         if (ret != 0) {
2043                 drm_mm_put_block(obj->gtt_space);
2044                 obj->gtt_space = NULL;
2045                 /*
2046                  * i915_gem_object_get_pages_gtt() cannot return
2047                  * ENOMEM, since we use vm_page_grab(VM_ALLOC_RETRY)
2048                  * (which does not support operation without a flag
2049                  * anyway).
2050                  */
2051                 return (ret);
2052         }
2053
2054         ret = i915_gem_gtt_bind_object(obj);
2055         if (ret != 0) {
2056                 i915_gem_object_put_pages_gtt(obj);
2057                 drm_mm_put_block(obj->gtt_space);
2058                 obj->gtt_space = NULL;
2059                 if (i915_gem_evict_everything(dev, false))
2060                         return (ret);
2061                 goto search_free;
2062         }
2063
2064         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2065         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2066
2067         KASSERT((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0,
2068             ("Object in gpu read domain"));
2069         KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
2070             ("Object in gpu write domain"));
2071
2072         obj->gtt_offset = obj->gtt_space->start;
2073
2074         fenceable =
2075                 obj->gtt_space->size == fence_size &&
2076                 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2077
2078         mappable =
2079                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2080         obj->map_and_fenceable = mappable && fenceable;
2081
2082         return (0);
2083 }
2084
2085 static void
2086 i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2087 {
2088         u32 old_write_domain, old_read_domains;
2089
2090         /* Act a barrier for all accesses through the GTT */
2091         mb();
2092
2093         /* Force a pagefault for domain tracking on next user access */
2094         i915_gem_release_mmap(obj);
2095
2096         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2097                 return;
2098
2099         old_read_domains = obj->base.read_domains;
2100         old_write_domain = obj->base.write_domain;
2101
2102         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2103         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2104
2105 }
2106
2107 int
2108 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2109 {
2110         drm_i915_private_t *dev_priv;
2111         int ret;
2112
2113         dev_priv = obj->base.dev->dev_private;
2114         ret = 0;
2115         if (obj->gtt_space == NULL)
2116                 return (0);
2117         if (obj->pin_count != 0) {
2118                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2119                 return (-EINVAL);
2120         }
2121
2122         ret = i915_gem_object_finish_gpu(obj);
2123         if (ret == -ERESTART || ret == -EINTR)
2124                 return (ret);
2125
2126         i915_gem_object_finish_gtt(obj);
2127
2128         if (ret == 0)
2129                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2130         if (ret == -ERESTART || ret == -EINTR)
2131                 return (ret);
2132         if (ret != 0) {
2133                 i915_gem_clflush_object(obj);
2134                 obj->base.read_domains = obj->base.write_domain =
2135                     I915_GEM_DOMAIN_CPU;
2136         }
2137
2138         ret = i915_gem_object_put_fence(obj);
2139         if (ret == -ERESTART)
2140                 return (ret);
2141
2142         i915_gem_gtt_unbind_object(obj);
2143         if (obj->has_aliasing_ppgtt_mapping) {
2144                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2145                 obj->has_aliasing_ppgtt_mapping = 0;
2146         }
2147         i915_gem_object_put_pages_gtt(obj);
2148
2149         list_del_init(&obj->gtt_list);
2150         list_del_init(&obj->mm_list);
2151         obj->map_and_fenceable = true;
2152
2153         drm_mm_put_block(obj->gtt_space);
2154         obj->gtt_space = NULL;
2155         obj->gtt_offset = 0;
2156
2157         if (i915_gem_object_is_purgeable(obj))
2158                 i915_gem_object_truncate(obj);
2159
2160         return (ret);
2161 }
2162
2163 static int
2164 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
2165     int flags)
2166 {
2167         struct drm_device *dev;
2168         vm_object_t vm_obj;
2169         vm_page_t m;
2170         int page_count, i, j;
2171
2172         dev = obj->base.dev;
2173         KASSERT(obj->pages == NULL, ("Obj already has pages"));
2174         page_count = obj->base.size / PAGE_SIZE;
2175         obj->pages = kmalloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
2176             M_WAITOK);
2177         vm_obj = obj->base.vm_obj;
2178         VM_OBJECT_LOCK(vm_obj);
2179         for (i = 0; i < page_count; i++) {
2180                 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
2181                         goto failed;
2182         }
2183         VM_OBJECT_UNLOCK(vm_obj);
2184         if (i915_gem_object_needs_bit17_swizzle(obj))
2185                 i915_gem_object_do_bit_17_swizzle(obj);
2186         return (0);
2187
2188 failed:
2189         for (j = 0; j < i; j++) {
2190                 m = obj->pages[j];
2191                 vm_page_lock(m);
2192                 vm_page_unwire(m, 0);
2193                 vm_page_unlock(m);
2194                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2195         }
2196         VM_OBJECT_UNLOCK(vm_obj);
2197         kfree(obj->pages, DRM_I915_GEM);
2198         obj->pages = NULL;
2199         return (-EIO);
2200 }
2201
2202 #define GEM_PARANOID_CHECK_GTT 0
2203 #if GEM_PARANOID_CHECK_GTT
2204 static void
2205 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
2206     int page_count)
2207 {
2208         struct drm_i915_private *dev_priv;
2209         vm_paddr_t pa;
2210         unsigned long start, end;
2211         u_int i;
2212         int j;
2213
2214         dev_priv = dev->dev_private;
2215         start = OFF_TO_IDX(dev_priv->mm.gtt_start);
2216         end = OFF_TO_IDX(dev_priv->mm.gtt_end);
2217         for (i = start; i < end; i++) {
2218                 pa = intel_gtt_read_pte_paddr(i);
2219                 for (j = 0; j < page_count; j++) {
2220                         if (pa == VM_PAGE_TO_PHYS(ma[j])) {
2221                                 panic("Page %p in GTT pte index %d pte %x",
2222                                     ma[i], i, intel_gtt_read_pte(i));
2223                         }
2224                 }
2225         }
2226 }
2227 #endif
2228
2229 static void
2230 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2231 {
2232         vm_page_t m;
2233         int page_count, i;
2234
2235         KASSERT(obj->madv != I915_MADV_PURGED_INTERNAL, ("Purged object"));
2236
2237         if (obj->tiling_mode != I915_TILING_NONE)
2238                 i915_gem_object_save_bit_17_swizzle(obj);
2239         if (obj->madv == I915_MADV_DONTNEED)
2240                 obj->dirty = 0;
2241         page_count = obj->base.size / PAGE_SIZE;
2242         VM_OBJECT_LOCK(obj->base.vm_obj);
2243 #if GEM_PARANOID_CHECK_GTT
2244         i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
2245 #endif
2246         for (i = 0; i < page_count; i++) {
2247                 m = obj->pages[i];
2248                 if (obj->dirty)
2249                         vm_page_dirty(m);
2250                 if (obj->madv == I915_MADV_WILLNEED)
2251                         vm_page_reference(m);
2252                 vm_page_lock(m);
2253                 vm_page_unwire(obj->pages[i], 1);
2254                 vm_page_unlock(m);
2255                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2256         }
2257         VM_OBJECT_UNLOCK(obj->base.vm_obj);
2258         obj->dirty = 0;
2259         kfree(obj->pages, DRM_I915_GEM);
2260         obj->pages = NULL;
2261 }
2262
2263 void
2264 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2265 {
2266         vm_object_t devobj;
2267         vm_page_t m;
2268         int i, page_count;
2269
2270         if (!obj->fault_mappable)
2271                 return;
2272
2273         devobj = cdev_pager_lookup(obj);
2274         if (devobj != NULL) {
2275                 page_count = OFF_TO_IDX(obj->base.size);
2276
2277                 VM_OBJECT_LOCK(devobj);
2278 retry:
2279                 for (i = 0; i < page_count; i++) {
2280                         m = vm_page_lookup(devobj, i);
2281                         if (m == NULL)
2282                                 continue;
2283                         if (vm_page_sleep_if_busy(m, true, "915unm"))
2284                                 goto retry;
2285                         cdev_pager_free_page(devobj, m);
2286                 }
2287                 VM_OBJECT_UNLOCK(devobj);
2288                 vm_object_deallocate(devobj);
2289         }
2290
2291         obj->fault_mappable = false;
2292 }
2293
2294 int
2295 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2296 {
2297         int ret;
2298
2299         KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
2300             ("In GPU write domain"));
2301
2302         if (obj->active) {
2303                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno,
2304                     true);
2305                 if (ret != 0)
2306                         return (ret);
2307         }
2308         return (0);
2309 }
2310
2311 void
2312 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2313     struct intel_ring_buffer *ring, uint32_t seqno)
2314 {
2315         struct drm_device *dev = obj->base.dev;
2316         struct drm_i915_private *dev_priv = dev->dev_private;
2317         struct drm_i915_fence_reg *reg;
2318
2319         obj->ring = ring;
2320         KASSERT(ring != NULL, ("NULL ring"));
2321
2322         /* Add a reference if we're newly entering the active list. */
2323         if (!obj->active) {
2324                 drm_gem_object_reference(&obj->base);
2325                 obj->active = 1;
2326         }
2327
2328         /* Move from whatever list we were on to the tail of execution. */
2329         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
2330         list_move_tail(&obj->ring_list, &ring->active_list);
2331
2332         obj->last_rendering_seqno = seqno;
2333         if (obj->fenced_gpu_access) {
2334                 obj->last_fenced_seqno = seqno;
2335                 obj->last_fenced_ring = ring;
2336
2337                 /* Bump MRU to take account of the delayed flush */
2338                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2339                         reg = &dev_priv->fence_regs[obj->fence_reg];
2340                         list_move_tail(&reg->lru_list,
2341                                        &dev_priv->mm.fence_list);
2342                 }
2343         }
2344 }
2345
2346 static void
2347 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
2348 {
2349         list_del_init(&obj->ring_list);
2350         obj->last_rendering_seqno = 0;
2351         obj->last_fenced_seqno = 0;
2352 }
2353
2354 static void
2355 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
2356 {
2357         struct drm_device *dev = obj->base.dev;
2358         drm_i915_private_t *dev_priv = dev->dev_private;
2359
2360         KASSERT(obj->active, ("Object not active"));
2361         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
2362
2363         i915_gem_object_move_off_active(obj);
2364 }
2365
2366 static void
2367 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2368 {
2369         struct drm_device *dev = obj->base.dev;
2370         struct drm_i915_private *dev_priv = dev->dev_private;
2371
2372         if (obj->pin_count != 0)
2373                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
2374         else
2375                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2376
2377         KASSERT(list_empty(&obj->gpu_write_list), ("On gpu_write_list"));
2378         KASSERT(obj->active, ("Object not active"));
2379         obj->ring = NULL;
2380         obj->last_fenced_ring = NULL;
2381
2382         i915_gem_object_move_off_active(obj);
2383         obj->fenced_gpu_access = false;
2384
2385         obj->active = 0;
2386         obj->pending_gpu_write = false;
2387         drm_gem_object_unreference(&obj->base);
2388
2389 #if 1
2390         KIB_NOTYET();
2391 #else
2392         WARN_ON(i915_verify_lists(dev));
2393 #endif
2394 }
2395
2396 static void
2397 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2398 {
2399         vm_object_t vm_obj;
2400
2401         vm_obj = obj->base.vm_obj;
2402         VM_OBJECT_LOCK(vm_obj);
2403         vm_object_page_remove(vm_obj, 0, 0, false);
2404         VM_OBJECT_UNLOCK(vm_obj);
2405         obj->madv = I915_MADV_PURGED_INTERNAL;
2406 }
2407
2408 static inline int
2409 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
2410 {
2411
2412         return (obj->madv == I915_MADV_DONTNEED);
2413 }
2414
2415 static void
2416 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
2417     uint32_t flush_domains)
2418 {
2419         struct drm_i915_gem_object *obj, *next;
2420         uint32_t old_write_domain;
2421
2422         list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
2423             gpu_write_list) {
2424                 if (obj->base.write_domain & flush_domains) {
2425                         old_write_domain = obj->base.write_domain;
2426                         obj->base.write_domain = 0;
2427                         list_del_init(&obj->gpu_write_list);
2428                         i915_gem_object_move_to_active(obj, ring,
2429                             i915_gem_next_request_seqno(ring));
2430                 }
2431         }
2432 }
2433
2434 static int
2435 i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2436 {
2437         drm_i915_private_t *dev_priv;
2438
2439         dev_priv = obj->base.dev->dev_private;
2440         return (dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2441             obj->tiling_mode != I915_TILING_NONE);
2442 }
2443
2444 static vm_page_t
2445 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
2446 {
2447         vm_page_t m;
2448         int rv;
2449
2450         VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
2451         m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_RETRY);
2452         if (m->valid != VM_PAGE_BITS_ALL) {
2453                 if (vm_pager_has_page(object, pindex, NULL, NULL)) {
2454                         rv = vm_pager_get_pages(object, &m, 1, 0);
2455                         m = vm_page_lookup(object, pindex);
2456                         if (m == NULL)
2457                                 return (NULL);
2458                         if (rv != VM_PAGER_OK) {
2459                                 vm_page_lock(m);
2460                                 vm_page_free(m);
2461                                 vm_page_unlock(m);
2462                                 return (NULL);
2463                         }
2464                 } else {
2465                         pmap_zero_page(m);
2466                         m->valid = VM_PAGE_BITS_ALL;
2467                         m->dirty = 0;
2468                 }
2469         }
2470         vm_page_lock(m);
2471         vm_page_wire(m);
2472         vm_page_unlock(m);
2473         vm_page_wakeup(m);
2474         atomic_add_long(&i915_gem_wired_pages_cnt, 1);
2475         return (m);
2476 }
2477
2478 int
2479 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
2480     uint32_t flush_domains)
2481 {
2482         int ret;
2483
2484         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2485                 return 0;
2486
2487         ret = ring->flush(ring, invalidate_domains, flush_domains);
2488         if (ret)
2489                 return ret;
2490
2491         if (flush_domains & I915_GEM_GPU_DOMAINS)
2492                 i915_gem_process_flushing_list(ring, flush_domains);
2493         return 0;
2494 }
2495
2496 static int
2497 i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire)
2498 {
2499         int ret;
2500
2501         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2502                 return 0;
2503
2504         if (!list_empty(&ring->gpu_write_list)) {
2505                 ret = i915_gem_flush_ring(ring, I915_GEM_GPU_DOMAINS,
2506                     I915_GEM_GPU_DOMAINS);
2507                 if (ret != 0)
2508                         return ret;
2509         }
2510
2511         return (i915_wait_request(ring, i915_gem_next_request_seqno(ring),
2512             do_retire));
2513 }
2514
2515 int
2516 i915_gpu_idle(struct drm_device *dev, bool do_retire)
2517 {
2518         drm_i915_private_t *dev_priv = dev->dev_private;
2519         int ret, i;
2520
2521         /* Flush everything onto the inactive list. */
2522         for (i = 0; i < I915_NUM_RINGS; i++) {
2523                 ret = i915_ring_idle(&dev_priv->rings[i], do_retire);
2524                 if (ret)
2525                         return ret;
2526         }
2527
2528         return 0;
2529 }
2530
2531 int
2532 i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno, bool do_retire)
2533 {
2534         drm_i915_private_t *dev_priv;
2535         struct drm_i915_gem_request *request;
2536         uint32_t ier;
2537         int flags, ret;
2538         bool recovery_complete;
2539
2540         KASSERT(seqno != 0, ("Zero seqno"));
2541
2542         dev_priv = ring->dev->dev_private;
2543         ret = 0;
2544
2545         if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
2546                 /* Give the error handler a chance to run. */
2547                 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
2548                 recovery_complete = (&dev_priv->error_completion) > 0;
2549                 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
2550                 return (recovery_complete ? -EIO : -EAGAIN);
2551         }
2552
2553         if (seqno == ring->outstanding_lazy_request) {
2554                 request = kmalloc(sizeof(*request), DRM_I915_GEM,
2555                     M_WAITOK | M_ZERO);
2556                 if (request == NULL)
2557                         return (-ENOMEM);
2558
2559                 ret = i915_add_request(ring, NULL, request);
2560                 if (ret != 0) {
2561                         kfree(request, DRM_I915_GEM);
2562                         return (ret);
2563                 }
2564
2565                 seqno = request->seqno;
2566         }
2567
2568         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2569                 if (HAS_PCH_SPLIT(ring->dev))
2570                         ier = I915_READ(DEIER) | I915_READ(GTIER);
2571                 else
2572                         ier = I915_READ(IER);
2573                 if (!ier) {
2574                         DRM_ERROR("something (likely vbetool) disabled "
2575                                   "interrupts, re-enabling\n");
2576                         ring->dev->driver->irq_preinstall(ring->dev);
2577                         ring->dev->driver->irq_postinstall(ring->dev);
2578                 }
2579
2580                 ring->waiting_seqno = seqno;
2581                 lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
2582                 if (ring->irq_get(ring)) {
2583                         flags = dev_priv->mm.interruptible ? PCATCH : 0;
2584                         while (!i915_seqno_passed(ring->get_seqno(ring), seqno)
2585                             && !atomic_load_acq_int(&dev_priv->mm.wedged) &&
2586                             ret == 0) {
2587                                 ret = -lksleep(ring, &ring->irq_lock, flags,
2588                                     "915gwr", 0);
2589                         }
2590                         ring->irq_put(ring);
2591                         lockmgr(&ring->irq_lock, LK_RELEASE);
2592                 } else {
2593                         lockmgr(&ring->irq_lock, LK_RELEASE);
2594                         if (_intel_wait_for(ring->dev,
2595                             i915_seqno_passed(ring->get_seqno(ring), seqno) ||
2596                             atomic_load_acq_int(&dev_priv->mm.wedged), 3000,
2597                             0, "i915wrq") != 0)
2598                                 ret = -EBUSY;
2599                 }
2600                 ring->waiting_seqno = 0;
2601
2602         }
2603         if (atomic_load_acq_int(&dev_priv->mm.wedged))
2604                 ret = -EAGAIN;
2605
2606         /* Directly dispatch request retiring.  While we have the work queue
2607          * to handle this, the waiter on a request often wants an associated
2608          * buffer to have made it to the inactive list, and we would need
2609          * a separate wait queue to handle that.
2610          */
2611         if (ret == 0 && do_retire)
2612                 i915_gem_retire_requests_ring(ring);
2613
2614         return (ret);
2615 }
2616
2617 static u32
2618 i915_gem_get_seqno(struct drm_device *dev)
2619 {
2620         drm_i915_private_t *dev_priv = dev->dev_private;
2621         u32 seqno = dev_priv->next_seqno;
2622
2623         /* reserve 0 for non-seqno */
2624         if (++dev_priv->next_seqno == 0)
2625                 dev_priv->next_seqno = 1;
2626
2627         return seqno;
2628 }
2629
2630 u32
2631 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
2632 {
2633         if (ring->outstanding_lazy_request == 0)
2634                 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
2635
2636         return ring->outstanding_lazy_request;
2637 }
2638
2639 int
2640 i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file,
2641      struct drm_i915_gem_request *request)
2642 {
2643         drm_i915_private_t *dev_priv;
2644         struct drm_i915_file_private *file_priv;
2645         uint32_t seqno;
2646         u32 request_ring_position;
2647         int was_empty;
2648         int ret;
2649
2650         KASSERT(request != NULL, ("NULL request in add"));
2651         DRM_LOCK_ASSERT(ring->dev);
2652         dev_priv = ring->dev->dev_private;
2653
2654         seqno = i915_gem_next_request_seqno(ring);
2655         request_ring_position = intel_ring_get_tail(ring);
2656
2657         ret = ring->add_request(ring, &seqno);
2658         if (ret != 0)
2659             return ret;
2660
2661         request->seqno = seqno;
2662         request->ring = ring;
2663         request->tail = request_ring_position;
2664         request->emitted_jiffies = ticks;
2665         was_empty = list_empty(&ring->request_list);
2666         list_add_tail(&request->list, &ring->request_list);
2667
2668         if (file != NULL) {
2669                 file_priv = file->driver_priv;
2670
2671                 lockmgr(&file_priv->mm.lck, LK_EXCLUSIVE);
2672                 request->file_priv = file_priv;
2673                 list_add_tail(&request->client_list,
2674                     &file_priv->mm.request_list);
2675                 lockmgr(&file_priv->mm.lck, LK_RELEASE);
2676         }
2677
2678         ring->outstanding_lazy_request = 0;
2679
2680         if (!dev_priv->mm.suspended) {
2681                 if (i915_enable_hangcheck) {
2682                         callout_schedule(&dev_priv->hangcheck_timer,
2683                             DRM_I915_HANGCHECK_PERIOD);
2684                 }
2685                 if (was_empty)
2686                         taskqueue_enqueue_timeout(dev_priv->tq,
2687                             &dev_priv->mm.retire_task, hz);
2688         }
2689         return (0);
2690 }
2691
2692 static inline void
2693 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2694 {
2695         struct drm_i915_file_private *file_priv = request->file_priv;
2696
2697         if (!file_priv)
2698                 return;
2699
2700         DRM_LOCK_ASSERT(request->ring->dev);
2701
2702         lockmgr(&file_priv->mm.lck, LK_EXCLUSIVE);
2703         if (request->file_priv != NULL) {
2704                 list_del(&request->client_list);
2705                 request->file_priv = NULL;
2706         }
2707         lockmgr(&file_priv->mm.lck, LK_RELEASE);
2708 }
2709
2710 void
2711 i915_gem_release(struct drm_device *dev, struct drm_file *file)
2712 {
2713         struct drm_i915_file_private *file_priv;
2714         struct drm_i915_gem_request *request;
2715
2716         file_priv = file->driver_priv;
2717
2718         /* Clean up our request list when the client is going away, so that
2719          * later retire_requests won't dereference our soon-to-be-gone
2720          * file_priv.
2721          */
2722         lockmgr(&file_priv->mm.lck, LK_EXCLUSIVE);
2723         while (!list_empty(&file_priv->mm.request_list)) {
2724                 request = list_first_entry(&file_priv->mm.request_list,
2725                                            struct drm_i915_gem_request,
2726                                            client_list);
2727                 list_del(&request->client_list);
2728                 request->file_priv = NULL;
2729         }
2730         lockmgr(&file_priv->mm.lck, LK_RELEASE);
2731 }
2732
2733 static void
2734 i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2735     struct intel_ring_buffer *ring)
2736 {
2737
2738         if (ring->dev != NULL)
2739                 DRM_LOCK_ASSERT(ring->dev);
2740
2741         while (!list_empty(&ring->request_list)) {
2742                 struct drm_i915_gem_request *request;
2743
2744                 request = list_first_entry(&ring->request_list,
2745                     struct drm_i915_gem_request, list);
2746
2747                 list_del(&request->list);
2748                 i915_gem_request_remove_from_client(request);
2749                 kfree(request, DRM_I915_GEM);
2750         }
2751
2752         while (!list_empty(&ring->active_list)) {
2753                 struct drm_i915_gem_object *obj;
2754
2755                 obj = list_first_entry(&ring->active_list,
2756                     struct drm_i915_gem_object, ring_list);
2757
2758                 obj->base.write_domain = 0;
2759                 list_del_init(&obj->gpu_write_list);
2760                 i915_gem_object_move_to_inactive(obj);
2761         }
2762 }
2763
2764 static void
2765 i915_gem_reset_fences(struct drm_device *dev)
2766 {
2767         struct drm_i915_private *dev_priv = dev->dev_private;
2768         int i;
2769
2770         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2771                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2772                 struct drm_i915_gem_object *obj = reg->obj;
2773
2774                 if (!obj)
2775                         continue;
2776
2777                 if (obj->tiling_mode)
2778                         i915_gem_release_mmap(obj);
2779
2780                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
2781                 reg->obj->fenced_gpu_access = false;
2782                 reg->obj->last_fenced_seqno = 0;
2783                 reg->obj->last_fenced_ring = NULL;
2784                 i915_gem_clear_fence_reg(dev, reg);
2785         }
2786 }
2787
2788 void
2789 i915_gem_reset(struct drm_device *dev)
2790 {
2791         struct drm_i915_private *dev_priv = dev->dev_private;
2792         struct drm_i915_gem_object *obj;
2793         int i;
2794
2795         for (i = 0; i < I915_NUM_RINGS; i++)
2796                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->rings[i]);
2797
2798         /* Remove anything from the flushing lists. The GPU cache is likely
2799          * to be lost on reset along with the data, so simply move the
2800          * lost bo to the inactive list.
2801          */
2802         while (!list_empty(&dev_priv->mm.flushing_list)) {
2803                 obj = list_first_entry(&dev_priv->mm.flushing_list,
2804                                       struct drm_i915_gem_object,
2805                                       mm_list);
2806
2807                 obj->base.write_domain = 0;
2808                 list_del_init(&obj->gpu_write_list);
2809                 i915_gem_object_move_to_inactive(obj);
2810         }
2811
2812         /* Move everything out of the GPU domains to ensure we do any
2813          * necessary invalidation upon reuse.
2814          */
2815         list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
2816                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2817         }
2818
2819         /* The fence registers are invalidated so clear them out */
2820         i915_gem_reset_fences(dev);
2821 }
2822
2823 /**
2824  * This function clears the request list as sequence numbers are passed.
2825  */
2826 void
2827 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2828 {
2829         uint32_t seqno;
2830         int i;
2831
2832         if (list_empty(&ring->request_list))
2833                 return;
2834
2835         seqno = ring->get_seqno(ring);
2836         for (i = 0; i < DRM_ARRAY_SIZE(ring->sync_seqno); i++)
2837                 if (seqno >= ring->sync_seqno[i])
2838                         ring->sync_seqno[i] = 0;
2839
2840         while (!list_empty(&ring->request_list)) {
2841                 struct drm_i915_gem_request *request;
2842
2843                 request = list_first_entry(&ring->request_list,
2844                                            struct drm_i915_gem_request,
2845                                            list);
2846
2847                 if (!i915_seqno_passed(seqno, request->seqno))
2848                         break;
2849
2850                 ring->last_retired_head = request->tail;
2851
2852                 list_del(&request->list);
2853                 i915_gem_request_remove_from_client(request);
2854                 kfree(request, DRM_I915_GEM);
2855         }
2856
2857         /* Move any buffers on the active list that are no longer referenced
2858          * by the ringbuffer to the flushing/inactive lists as appropriate.
2859          */
2860         while (!list_empty(&ring->active_list)) {
2861                 struct drm_i915_gem_object *obj;
2862
2863                 obj = list_first_entry(&ring->active_list,
2864                                       struct drm_i915_gem_object,
2865                                       ring_list);
2866
2867                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
2868                         break;
2869
2870                 if (obj->base.write_domain != 0)
2871                         i915_gem_object_move_to_flushing(obj);
2872                 else
2873                         i915_gem_object_move_to_inactive(obj);
2874         }
2875
2876         if (ring->trace_irq_seqno &&
2877             i915_seqno_passed(seqno, ring->trace_irq_seqno)) {
2878                 lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
2879                 ring->irq_put(ring);
2880                 lockmgr(&ring->irq_lock, LK_RELEASE);
2881                 ring->trace_irq_seqno = 0;
2882         }
2883 }
2884
2885 void
2886 i915_gem_retire_requests(struct drm_device *dev)
2887 {
2888         drm_i915_private_t *dev_priv = dev->dev_private;
2889         struct drm_i915_gem_object *obj, *next;
2890         int i;
2891
2892         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
2893                 list_for_each_entry_safe(obj, next,
2894                     &dev_priv->mm.deferred_free_list, mm_list)
2895                         i915_gem_free_object_tail(obj);
2896         }
2897
2898         for (i = 0; i < I915_NUM_RINGS; i++)
2899                 i915_gem_retire_requests_ring(&dev_priv->rings[i]);
2900 }
2901
2902 static int
2903 sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2904     struct intel_ring_buffer *pipelined)
2905 {
2906         struct drm_device *dev = obj->base.dev;
2907         drm_i915_private_t *dev_priv = dev->dev_private;
2908         u32 size = obj->gtt_space->size;
2909         int regnum = obj->fence_reg;
2910         uint64_t val;
2911
2912         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2913                          0xfffff000) << 32;
2914         val |= obj->gtt_offset & 0xfffff000;
2915         val |= (uint64_t)((obj->stride / 128) - 1) <<
2916                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2917
2918         if (obj->tiling_mode == I915_TILING_Y)
2919                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2920         val |= I965_FENCE_REG_VALID;
2921
2922         if (pipelined) {
2923                 int ret = intel_ring_begin(pipelined, 6);
2924                 if (ret)
2925                         return ret;
2926
2927                 intel_ring_emit(pipelined, MI_NOOP);
2928                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2929                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2930                 intel_ring_emit(pipelined, (u32)val);
2931                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2932                 intel_ring_emit(pipelined, (u32)(val >> 32));
2933                 intel_ring_advance(pipelined);
2934         } else
2935                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2936
2937         return 0;
2938 }
2939
2940 static int
2941 i965_write_fence_reg(struct drm_i915_gem_object *obj,
2942     struct intel_ring_buffer *pipelined)
2943 {
2944         struct drm_device *dev = obj->base.dev;
2945         drm_i915_private_t *dev_priv = dev->dev_private;
2946         u32 size = obj->gtt_space->size;
2947         int regnum = obj->fence_reg;
2948         uint64_t val;
2949
2950         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2951                     0xfffff000) << 32;
2952         val |= obj->gtt_offset & 0xfffff000;
2953         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2954         if (obj->tiling_mode == I915_TILING_Y)
2955                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2956         val |= I965_FENCE_REG_VALID;
2957
2958         if (pipelined) {
2959                 int ret = intel_ring_begin(pipelined, 6);
2960                 if (ret)
2961                         return ret;
2962
2963                 intel_ring_emit(pipelined, MI_NOOP);
2964                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2965                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2966                 intel_ring_emit(pipelined, (u32)val);
2967                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2968                 intel_ring_emit(pipelined, (u32)(val >> 32));
2969                 intel_ring_advance(pipelined);
2970         } else
2971                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2972
2973         return 0;
2974 }
2975
2976 static int
2977 i915_write_fence_reg(struct drm_i915_gem_object *obj,
2978     struct intel_ring_buffer *pipelined)
2979 {
2980         struct drm_device *dev = obj->base.dev;
2981         drm_i915_private_t *dev_priv = dev->dev_private;
2982         u32 size = obj->gtt_space->size;
2983         u32 fence_reg, val, pitch_val;
2984         int tile_width;
2985
2986         if ((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2987             (size & -size) != size || (obj->gtt_offset & (size - 1))) {
2988                 kprintf(
2989 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2990                  obj->gtt_offset, obj->map_and_fenceable, size);
2991                 return -EINVAL;
2992         }
2993
2994         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2995                 tile_width = 128;
2996         else
2997                 tile_width = 512;
2998
2999         /* Note: pitch better be a power of two tile widths */
3000         pitch_val = obj->stride / tile_width;
3001         pitch_val = ffs(pitch_val) - 1;
3002
3003         val = obj->gtt_offset;
3004         if (obj->tiling_mode == I915_TILING_Y)
3005                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3006         val |= I915_FENCE_SIZE_BITS(size);
3007         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3008         val |= I830_FENCE_REG_VALID;
3009
3010         fence_reg = obj->fence_reg;
3011         if (fence_reg < 8)
3012                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3013         else
3014                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3015
3016         if (pipelined) {
3017                 int ret = intel_ring_begin(pipelined, 4);
3018                 if (ret)
3019                         return ret;
3020
3021                 intel_ring_emit(pipelined, MI_NOOP);
3022                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
3023                 intel_ring_emit(pipelined, fence_reg);
3024                 intel_ring_emit(pipelined, val);
3025                 intel_ring_advance(pipelined);
3026         } else
3027                 I915_WRITE(fence_reg, val);
3028
3029         return 0;
3030 }
3031
3032 static int
3033 i830_write_fence_reg(struct drm_i915_gem_object *obj,
3034     struct intel_ring_buffer *pipelined)
3035 {
3036         struct drm_device *dev = obj->base.dev;
3037         drm_i915_private_t *dev_priv = dev->dev_private;
3038         u32 size = obj->gtt_space->size;
3039         int regnum = obj->fence_reg;
3040         uint32_t val;
3041         uint32_t pitch_val;
3042
3043         if ((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
3044             (size & -size) != size || (obj->gtt_offset & (size - 1))) {
3045                 kprintf(
3046 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
3047                     obj->gtt_offset, size);
3048                 return -EINVAL;
3049         }
3050
3051         pitch_val = obj->stride / 128;
3052         pitch_val = ffs(pitch_val) - 1;
3053
3054         val = obj->gtt_offset;
3055         if (obj->tiling_mode == I915_TILING_Y)
3056                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3057         val |= I830_FENCE_SIZE_BITS(size);
3058         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3059         val |= I830_FENCE_REG_VALID;
3060
3061         if (pipelined) {
3062                 int ret = intel_ring_begin(pipelined, 4);
3063                 if (ret)
3064                         return ret;
3065
3066                 intel_ring_emit(pipelined, MI_NOOP);
3067                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
3068                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
3069                 intel_ring_emit(pipelined, val);
3070                 intel_ring_advance(pipelined);
3071         } else
3072                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
3073
3074         return 0;
3075 }
3076
3077 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
3078 {
3079         return i915_seqno_passed(ring->get_seqno(ring), seqno);
3080 }
3081
3082 static int
3083 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
3084     struct intel_ring_buffer *pipelined)
3085 {
3086         int ret;
3087
3088         if (obj->fenced_gpu_access) {
3089                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3090                         ret = i915_gem_flush_ring(obj->last_fenced_ring, 0,
3091                             obj->base.write_domain);
3092                         if (ret)
3093                                 return ret;
3094                 }
3095
3096                 obj->fenced_gpu_access = false;
3097         }
3098
3099         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
3100                 if (!ring_passed_seqno(obj->last_fenced_ring,
3101                                        obj->last_fenced_seqno)) {
3102                         ret = i915_wait_request(obj->last_fenced_ring,
3103                                                 obj->last_fenced_seqno,
3104                                                 true);
3105                         if (ret)
3106                                 return ret;
3107                 }
3108
3109                 obj->last_fenced_seqno = 0;
3110                 obj->last_fenced_ring = NULL;
3111         }
3112
3113         /* Ensure that all CPU reads are completed before installing a fence
3114          * and all writes before removing the fence.
3115          */
3116         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
3117                 mb();
3118
3119         return 0;
3120 }
3121
3122 int
3123 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3124 {
3125         int ret;
3126
3127         if (obj->tiling_mode)
3128                 i915_gem_release_mmap(obj);
3129
3130         ret = i915_gem_object_flush_fence(obj, NULL);
3131         if (ret)
3132                 return ret;
3133
3134         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3135                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3136
3137                 if (dev_priv->fence_regs[obj->fence_reg].pin_count != 0)
3138                         kprintf("%s: pin_count %d\n", __func__,
3139                             dev_priv->fence_regs[obj->fence_reg].pin_count);
3140                 i915_gem_clear_fence_reg(obj->base.dev,
3141                                          &dev_priv->fence_regs[obj->fence_reg]);
3142
3143                 obj->fence_reg = I915_FENCE_REG_NONE;
3144         }
3145
3146         return 0;
3147 }
3148
3149 static struct drm_i915_fence_reg *
3150 i915_find_fence_reg(struct drm_device *dev, struct intel_ring_buffer *pipelined)
3151 {
3152         struct drm_i915_private *dev_priv = dev->dev_private;
3153         struct drm_i915_fence_reg *reg, *first, *avail;
3154         int i;
3155
3156         /* First try to find a free reg */
3157         avail = NULL;
3158         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3159                 reg = &dev_priv->fence_regs[i];
3160                 if (!reg->obj)
3161                         return reg;
3162
3163                 if (!reg->pin_count)
3164                         avail = reg;
3165         }
3166
3167         if (avail == NULL)
3168                 return NULL;
3169
3170         /* None available, try to steal one or wait for a user to finish */
3171         avail = first = NULL;
3172         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3173                 if (reg->pin_count)
3174                         continue;
3175
3176                 if (first == NULL)
3177                         first = reg;
3178
3179                 if (!pipelined ||
3180                     !reg->obj->last_fenced_ring ||
3181                     reg->obj->last_fenced_ring == pipelined) {
3182                         avail = reg;
3183                         break;
3184                 }
3185         }
3186
3187         if (avail == NULL)
3188                 avail = first;
3189
3190         return avail;
3191 }
3192
3193 int
3194 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
3195     struct intel_ring_buffer *pipelined)
3196 {
3197         struct drm_device *dev = obj->base.dev;
3198         struct drm_i915_private *dev_priv = dev->dev_private;
3199         struct drm_i915_fence_reg *reg;
3200         int ret;
3201
3202         pipelined = NULL;
3203         ret = 0;
3204
3205         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3206                 reg = &dev_priv->fence_regs[obj->fence_reg];
3207                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
3208
3209                 if (obj->tiling_changed) {
3210                         ret = i915_gem_object_flush_fence(obj, pipelined);
3211                         if (ret)
3212                                 return ret;
3213
3214                         if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3215                                 pipelined = NULL;
3216
3217                         if (pipelined) {
3218                                 reg->setup_seqno =
3219                                         i915_gem_next_request_seqno(pipelined);
3220                                 obj->last_fenced_seqno = reg->setup_seqno;
3221                                 obj->last_fenced_ring = pipelined;
3222                         }
3223
3224                         goto update;
3225                 }
3226
3227                 if (!pipelined) {
3228                         if (reg->setup_seqno) {
3229                                 if (!ring_passed_seqno(obj->last_fenced_ring,
3230                                     reg->setup_seqno)) {
3231                                         ret = i915_wait_request(
3232                                             obj->last_fenced_ring,
3233                                             reg->setup_seqno,
3234                                             true);
3235                                         if (ret)
3236                                                 return ret;
3237                                 }
3238
3239                                 reg->setup_seqno = 0;
3240                         }
3241                 } else if (obj->last_fenced_ring &&
3242                            obj->last_fenced_ring != pipelined) {
3243                         ret = i915_gem_object_flush_fence(obj, pipelined);
3244                         if (ret)
3245                                 return ret;
3246                 }
3247
3248                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3249                         pipelined = NULL;
3250                 KASSERT(pipelined || reg->setup_seqno == 0, ("!pipelined"));
3251
3252                 if (obj->tiling_changed) {
3253                         if (pipelined) {
3254                                 reg->setup_seqno =
3255                                         i915_gem_next_request_seqno(pipelined);
3256                                 obj->last_fenced_seqno = reg->setup_seqno;
3257                                 obj->last_fenced_ring = pipelined;
3258                         }
3259                         goto update;
3260                 }
3261
3262                 return 0;
3263         }
3264
3265         reg = i915_find_fence_reg(dev, pipelined);
3266         if (reg == NULL)
3267                 return -EDEADLK;
3268
3269         ret = i915_gem_object_flush_fence(obj, pipelined);
3270         if (ret)
3271                 return ret;
3272
3273         if (reg->obj) {
3274                 struct drm_i915_gem_object *old = reg->obj;
3275
3276                 drm_gem_object_reference(&old->base);
3277
3278                 if (old->tiling_mode)
3279                         i915_gem_release_mmap(old);
3280
3281                 ret = i915_gem_object_flush_fence(old, pipelined);
3282                 if (ret) {
3283                         drm_gem_object_unreference(&old->base);
3284                         return ret;
3285                 }
3286
3287                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
3288                         pipelined = NULL;
3289
3290                 old->fence_reg = I915_FENCE_REG_NONE;
3291                 old->last_fenced_ring = pipelined;
3292                 old->last_fenced_seqno =
3293                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3294
3295                 drm_gem_object_unreference(&old->base);
3296         } else if (obj->last_fenced_seqno == 0)
3297                 pipelined = NULL;
3298
3299         reg->obj = obj;
3300         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
3301         obj->fence_reg = reg - dev_priv->fence_regs;
3302         obj->last_fenced_ring = pipelined;
3303
3304         reg->setup_seqno =
3305                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3306         obj->last_fenced_seqno = reg->setup_seqno;
3307
3308 update:
3309         obj->tiling_changed = false;
3310         switch (INTEL_INFO(dev)->gen) {
3311         case 7:
3312         case 6:
3313                 ret = sandybridge_write_fence_reg(obj, pipelined);
3314                 break;
3315         case 5:
3316         case 4:
3317                 ret = i965_write_fence_reg(obj, pipelined);
3318                 break;
3319         case 3:
3320                 ret = i915_write_fence_reg(obj, pipelined);
3321                 break;
3322         case 2:
3323                 ret = i830_write_fence_reg(obj, pipelined);
3324                 break;
3325         }
3326
3327         return ret;
3328 }
3329
3330 static void
3331 i915_gem_clear_fence_reg(struct drm_device *dev, struct drm_i915_fence_reg *reg)
3332 {
3333         drm_i915_private_t *dev_priv = dev->dev_private;
3334         uint32_t fence_reg = reg - dev_priv->fence_regs;
3335
3336         switch (INTEL_INFO(dev)->gen) {
3337         case 7:
3338         case 6:
3339                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
3340                 break;
3341         case 5:
3342         case 4:
3343                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
3344                 break;
3345         case 3:
3346                 if (fence_reg >= 8)
3347                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3348                 else
3349         case 2:
3350                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3351
3352                 I915_WRITE(fence_reg, 0);
3353                 break;
3354         }
3355
3356         list_del_init(&reg->lru_list);
3357         reg->obj = NULL;
3358         reg->setup_seqno = 0;
3359         reg->pin_count = 0;
3360 }
3361
3362 int
3363 i915_gem_init_object(struct drm_gem_object *obj)
3364 {
3365
3366         kprintf("i915_gem_init_object called\n");
3367         return (0);
3368 }
3369
3370 static bool
3371 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
3372 {
3373
3374         return (obj->gtt_space && !obj->active && obj->pin_count == 0);
3375 }
3376
3377 static void
3378 i915_gem_retire_task_handler(void *arg, int pending)
3379 {
3380         drm_i915_private_t *dev_priv;
3381         struct drm_device *dev;
3382         bool idle;
3383         int i;
3384
3385         dev_priv = arg;
3386         dev = dev_priv->dev;
3387
3388         /* Come back later if the device is busy... */
3389         if (!lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT)) {
3390                 taskqueue_enqueue_timeout(dev_priv->tq,
3391                     &dev_priv->mm.retire_task, hz);
3392                 return;
3393         }
3394
3395         i915_gem_retire_requests(dev);
3396
3397         /* Send a periodic flush down the ring so we don't hold onto GEM
3398          * objects indefinitely.
3399          */
3400         idle = true;
3401         for (i = 0; i < I915_NUM_RINGS; i++) {
3402                 struct intel_ring_buffer *ring = &dev_priv->rings[i];
3403
3404                 if (!list_empty(&ring->gpu_write_list)) {
3405                         struct drm_i915_gem_request *request;
3406                         int ret;
3407
3408                         ret = i915_gem_flush_ring(ring,
3409                                                   0, I915_GEM_GPU_DOMAINS);
3410                         request = kmalloc(sizeof(*request), DRM_I915_GEM,
3411                             M_WAITOK | M_ZERO);
3412                         if (ret || request == NULL ||
3413                             i915_add_request(ring, NULL, request))
3414                                 kfree(request, DRM_I915_GEM);
3415                 }
3416
3417                 idle &= list_empty(&ring->request_list);
3418         }
3419
3420         if (!dev_priv->mm.suspended && !idle)
3421                 taskqueue_enqueue_timeout(dev_priv->tq,
3422                     &dev_priv->mm.retire_task, hz);
3423
3424         DRM_UNLOCK(dev);
3425 }
3426
3427 void
3428 i915_gem_lastclose(struct drm_device *dev)
3429 {
3430         int ret;
3431
3432         if (drm_core_check_feature(dev, DRIVER_MODESET))
3433                 return;
3434
3435         ret = i915_gem_idle(dev);
3436         if (ret != 0)
3437                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3438 }
3439
3440 static int
3441 i915_gem_init_phys_object(struct drm_device *dev, int id, int size, int align)
3442 {
3443         drm_i915_private_t *dev_priv;
3444         struct drm_i915_gem_phys_object *phys_obj;
3445         int ret;
3446
3447         dev_priv = dev->dev_private;
3448         if (dev_priv->mm.phys_objs[id - 1] != NULL || size == 0)
3449                 return (0);
3450
3451         phys_obj = kmalloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
3452             M_WAITOK | M_ZERO);
3453
3454         phys_obj->id = id;
3455
3456         phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
3457         if (phys_obj->handle == NULL) {
3458                 ret = -ENOMEM;
3459                 goto free_obj;
3460         }
3461         pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3462             size / PAGE_SIZE, PAT_WRITE_COMBINING);
3463
3464         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3465
3466         return (0);
3467
3468 free_obj:
3469         kfree(phys_obj, DRM_I915_GEM);
3470         return (ret);
3471 }
3472
3473 static void
3474 i915_gem_free_phys_object(struct drm_device *dev, int id)
3475 {
3476         drm_i915_private_t *dev_priv;
3477         struct drm_i915_gem_phys_object *phys_obj;
3478
3479         dev_priv = dev->dev_private;
3480         if (dev_priv->mm.phys_objs[id - 1] == NULL)
3481                 return;
3482
3483         phys_obj = dev_priv->mm.phys_objs[id - 1];
3484         if (phys_obj->cur_obj != NULL)
3485                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3486
3487         drm_pci_free(dev, phys_obj->handle);
3488         kfree(phys_obj, DRM_I915_GEM);
3489         dev_priv->mm.phys_objs[id - 1] = NULL;
3490 }
3491
3492 void
3493 i915_gem_free_all_phys_object(struct drm_device *dev)
3494 {
3495         int i;
3496
3497         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3498                 i915_gem_free_phys_object(dev, i);
3499 }
3500
3501 void
3502 i915_gem_detach_phys_object(struct drm_device *dev,
3503     struct drm_i915_gem_object *obj)
3504 {
3505         vm_page_t m;
3506         struct sf_buf *sf;
3507         char *vaddr, *dst;
3508         int i, page_count;
3509
3510         if (obj->phys_obj == NULL)
3511                 return;
3512         vaddr = obj->phys_obj->handle->vaddr;
3513
3514         page_count = obj->base.size / PAGE_SIZE;
3515         VM_OBJECT_LOCK(obj->base.vm_obj);
3516         for (i = 0; i < page_count; i++) {
3517                 m = i915_gem_wire_page(obj->base.vm_obj, i);
3518                 if (m == NULL)
3519                         continue; /* XXX */
3520
3521                 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3522                 sf = sf_buf_alloc(m, 0);
3523                 if (sf != NULL) {
3524                         dst = (char *)sf_buf_kva(sf);
3525                         memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3526                         sf_buf_free(sf);
3527                 }
3528                 drm_clflush_pages(&m, 1);
3529
3530                 VM_OBJECT_LOCK(obj->base.vm_obj);
3531                 vm_page_reference(m);
3532                 vm_page_lock(m);
3533                 vm_page_dirty(m);
3534                 vm_page_unwire(m, 0);
3535                 vm_page_unlock(m);
3536                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3537         }
3538         VM_OBJECT_UNLOCK(obj->base.vm_obj);
3539         intel_gtt_chipset_flush();
3540
3541         obj->phys_obj->cur_obj = NULL;
3542         obj->phys_obj = NULL;
3543 }
3544
3545 int
3546 i915_gem_attach_phys_object(struct drm_device *dev,
3547     struct drm_i915_gem_object *obj, int id, int align)
3548 {
3549         drm_i915_private_t *dev_priv;
3550         vm_page_t m;
3551         struct sf_buf *sf;
3552         char *dst, *src;
3553         int i, page_count, ret;
3554
3555         if (id > I915_MAX_PHYS_OBJECT)
3556                 return (-EINVAL);
3557
3558         if (obj->phys_obj != NULL) {
3559                 if (obj->phys_obj->id == id)
3560                         return (0);
3561                 i915_gem_detach_phys_object(dev, obj);
3562         }
3563
3564         dev_priv = dev->dev_private;
3565         if (dev_priv->mm.phys_objs[id - 1] == NULL) {
3566                 ret = i915_gem_init_phys_object(dev, id, obj->base.size, align);
3567                 if (ret != 0) {
3568                         DRM_ERROR("failed to init phys object %d size: %zu\n",
3569                                   id, obj->base.size);
3570                         return (ret);
3571                 }
3572         }
3573
3574         /* bind to the object */
3575         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3576         obj->phys_obj->cur_obj = obj;
3577
3578         page_count = obj->base.size / PAGE_SIZE;
3579
3580         VM_OBJECT_LOCK(obj->base.vm_obj);
3581         ret = 0;
3582         for (i = 0; i < page_count; i++) {
3583                 m = i915_gem_wire_page(obj->base.vm_obj, i);
3584                 if (m == NULL) {
3585                         ret = -EIO;
3586                         break;
3587                 }
3588                 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3589                 sf = sf_buf_alloc(m, 0);
3590                 src = (char *)sf_buf_kva(sf);
3591                 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3592                 memcpy(dst, src, PAGE_SIZE);
3593                 sf_buf_free(sf);
3594
3595                 VM_OBJECT_LOCK(obj->base.vm_obj);
3596
3597                 vm_page_reference(m);
3598                 vm_page_lock(m);
3599                 vm_page_unwire(m, 0);
3600                 vm_page_unlock(m);
3601                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3602         }
3603         VM_OBJECT_UNLOCK(obj->base.vm_obj);
3604
3605         return (0);
3606 }
3607
3608 static int
3609 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_i915_gem_object *obj,
3610     uint64_t data_ptr, uint64_t offset, uint64_t size,
3611     struct drm_file *file_priv)
3612 {
3613         char *user_data, *vaddr;
3614         int ret;
3615
3616         vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3617         user_data = (char *)(uintptr_t)data_ptr;
3618
3619         if (copyin_nofault(user_data, vaddr, size) != 0) {
3620                 /* The physical object once assigned is fixed for the lifetime
3621                  * of the obj, so we can safely drop the lock and continue
3622                  * to access vaddr.
3623                  */
3624                 DRM_UNLOCK(dev);
3625                 ret = -copyin(user_data, vaddr, size);
3626                 DRM_LOCK(dev);
3627                 if (ret != 0)
3628                         return (ret);
3629         }
3630
3631         intel_gtt_chipset_flush();
3632         return (0);
3633 }
3634
3635 static int
3636 i915_gpu_is_active(struct drm_device *dev)
3637 {
3638         drm_i915_private_t *dev_priv;
3639
3640         dev_priv = dev->dev_private;
3641         return (!list_empty(&dev_priv->mm.flushing_list) ||
3642             !list_empty(&dev_priv->mm.active_list));
3643 }
3644
3645 static void
3646 i915_gem_lowmem(void *arg)
3647 {
3648         struct drm_device *dev;
3649         struct drm_i915_private *dev_priv;
3650         struct drm_i915_gem_object *obj, *next;
3651         int cnt, cnt_fail, cnt_total;
3652
3653         dev = arg;
3654         dev_priv = dev->dev_private;
3655
3656         if (!lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
3657                 return;
3658
3659 rescan:
3660         /* first scan for clean buffers */
3661         i915_gem_retire_requests(dev);
3662
3663         cnt_total = cnt_fail = cnt = 0;
3664
3665         list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3666             mm_list) {
3667                 if (i915_gem_object_is_purgeable(obj)) {
3668                         if (i915_gem_object_unbind(obj) != 0)
3669                                 cnt_total++;
3670                 } else
3671                         cnt_total++;
3672         }
3673
3674         /* second pass, evict/count anything still on the inactive list */
3675         list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3676             mm_list) {
3677                 if (i915_gem_object_unbind(obj) == 0)
3678                         cnt++;
3679                 else
3680                         cnt_fail++;
3681         }
3682
3683         if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
3684                 /*
3685                  * We are desperate for pages, so as a last resort, wait
3686                  * for the GPU to finish and discard whatever we can.
3687                  * This has a dramatic impact to reduce the number of
3688                  * OOM-killer events whilst running the GPU aggressively.
3689                  */
3690                 if (i915_gpu_idle(dev, true) == 0)
3691                         goto rescan;
3692         }
3693         DRM_UNLOCK(dev);
3694 }
3695
3696 void
3697 i915_gem_unload(struct drm_device *dev)
3698 {
3699         struct drm_i915_private *dev_priv;
3700
3701         dev_priv = dev->dev_private;
3702         EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);
3703 }