1 /*******************************************************************************
3 Copyright (c) 2001-2003, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 *******************************************************************************/
34 /*$FreeBSD: src/sys/dev/em/if_em_hw.c,v 1.1.2.8 2003/06/09 21:43:41 pdeuskar Exp $*/
35 /*$DragonFly: src/sys/dev/netif/em/if_em_hw.c,v 1.6 2004/05/11 14:00:20 joerg Exp $*/
37 * Shared functions for accessing and configuring the MAC
40 #include <dev/netif/em/if_em_hw.h>
42 static int32_t em_set_phy_type(struct em_hw *hw);
43 static void em_phy_init_script(struct em_hw *hw);
44 static int32_t em_setup_copper_link(struct em_hw *hw);
45 static int32_t em_setup_fiber_serdes_link(struct em_hw *hw);
46 static int32_t em_adjust_serdes_amplitude(struct em_hw *hw);
47 static int32_t em_phy_force_speed_duplex(struct em_hw *hw);
48 static int32_t em_config_mac_to_phy(struct em_hw *hw);
49 static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
50 static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
51 static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data,
53 static uint16_t em_shift_in_mdi_bits(struct em_hw *hw);
54 static int32_t em_phy_reset_dsp(struct em_hw *hw);
55 static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset,
56 uint16_t words, uint16_t *data);
57 static int32_t em_write_eeprom_microwire(struct em_hw *hw,
58 uint16_t offset, uint16_t words,
60 static int32_t em_spi_eeprom_ready(struct em_hw *hw);
61 static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd);
62 static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd);
63 static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data,
65 static int32_t em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
67 static int32_t em_read_phy_reg_ex(struct em_hw *hw,uint32_t reg_addr,
69 static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count);
70 static int32_t em_acquire_eeprom(struct em_hw *hw);
71 static void em_release_eeprom(struct em_hw *hw);
72 static void em_standby_eeprom(struct em_hw *hw);
73 static int32_t em_id_led_init(struct em_hw * hw);
74 static int32_t em_set_vco_speed(struct em_hw *hw);
76 /* IGP cable length table */
78 uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
79 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
80 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
81 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
82 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
83 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
84 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
85 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
86 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
89 /******************************************************************************
90 * Set the phy type member in the hw struct.
92 * hw - Struct containing variables accessed by shared code
93 *****************************************************************************/
95 em_set_phy_type(struct em_hw *hw)
97 DEBUGFUNC("em_set_phy_type");
100 case M88E1000_E_PHY_ID:
101 case M88E1000_I_PHY_ID:
102 case M88E1011_I_PHY_ID:
103 hw->phy_type = em_phy_m88;
105 case IGP01E1000_I_PHY_ID:
106 if(hw->mac_type == em_82541 ||
107 hw->mac_type == em_82541_rev_2 ||
108 hw->mac_type == em_82547 ||
109 hw->mac_type == em_82547_rev_2) {
110 hw->phy_type = em_phy_igp;
115 /* Should never have loaded on this device */
116 hw->phy_type = em_phy_undefined;
117 return -E1000_ERR_PHY_TYPE;
120 return E1000_SUCCESS;
123 /******************************************************************************
124 * IGP phy init script - initializes the GbE PHY
126 * hw - Struct containing variables accessed by shared code
127 *****************************************************************************/
129 em_phy_init_script(struct em_hw *hw)
131 DEBUGFUNC("em_phy_init_script");
133 if(hw->phy_init_script) {
136 em_write_phy_reg(hw,0x0000,0x0140);
140 if(hw->mac_type == em_82541 || hw->mac_type == em_82547) {
141 em_write_phy_reg(hw, 0x1F95, 0x0001);
143 em_write_phy_reg(hw, 0x1F71, 0xBD21);
145 em_write_phy_reg(hw, 0x1F79, 0x0018);
147 em_write_phy_reg(hw, 0x1F30, 0x1600);
149 em_write_phy_reg(hw, 0x1F31, 0x0014);
151 em_write_phy_reg(hw, 0x1F32, 0x161C);
153 em_write_phy_reg(hw, 0x1F94, 0x0003);
155 em_write_phy_reg(hw, 0x1F96, 0x003F);
157 em_write_phy_reg(hw, 0x2010, 0x0008);
159 em_write_phy_reg(hw, 0x1F73, 0x0099);
162 em_write_phy_reg(hw, 0x0000, 0x3300);
164 if(hw->mac_type == em_82547) {
165 uint16_t fused, fine, coarse;
167 /* Move to analog registers page */
168 em_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
170 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
171 em_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
173 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
174 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
176 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
177 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
178 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
179 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
180 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
182 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
183 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
184 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
186 em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
187 em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
188 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
194 /******************************************************************************
195 * Set the mac type member in the hw struct.
197 * hw - Struct containing variables accessed by shared code
198 *****************************************************************************/
200 em_set_mac_type(struct em_hw *hw)
202 DEBUGFUNC("em_set_mac_type");
204 switch (hw->device_id) {
205 case E1000_DEV_ID_82542:
206 switch (hw->revision_id) {
207 case E1000_82542_2_0_REV_ID:
208 hw->mac_type = em_82542_rev2_0;
210 case E1000_82542_2_1_REV_ID:
211 hw->mac_type = em_82542_rev2_1;
214 /* Invalid 82542 revision ID */
215 return -E1000_ERR_MAC_TYPE;
218 case E1000_DEV_ID_82543GC_FIBER:
219 case E1000_DEV_ID_82543GC_COPPER:
220 hw->mac_type = em_82543;
222 case E1000_DEV_ID_82544EI_COPPER:
223 case E1000_DEV_ID_82544EI_FIBER:
224 case E1000_DEV_ID_82544GC_COPPER:
225 case E1000_DEV_ID_82544GC_LOM:
226 hw->mac_type = em_82544;
228 case E1000_DEV_ID_82540EM:
229 case E1000_DEV_ID_82540EM_LOM:
230 case E1000_DEV_ID_82540EP:
231 case E1000_DEV_ID_82540EP_LOM:
232 case E1000_DEV_ID_82540EP_LP:
233 hw->mac_type = em_82540;
235 case E1000_DEV_ID_82545EM_COPPER:
236 case E1000_DEV_ID_82545EM_FIBER:
237 hw->mac_type = em_82545;
239 case E1000_DEV_ID_82545GM_COPPER:
240 case E1000_DEV_ID_82545GM_FIBER:
241 case E1000_DEV_ID_82545GM_SERDES:
242 hw->mac_type = em_82545_rev_3;
244 case E1000_DEV_ID_82546EB_COPPER:
245 case E1000_DEV_ID_82546EB_FIBER:
246 case E1000_DEV_ID_82546EB_QUAD_COPPER:
247 hw->mac_type = em_82546;
249 case E1000_DEV_ID_82546GB_COPPER:
250 case E1000_DEV_ID_82546GB_FIBER:
251 case E1000_DEV_ID_82546GB_SERDES:
252 hw->mac_type = em_82546_rev_3;
254 case E1000_DEV_ID_82541EI:
255 case E1000_DEV_ID_82541EI_MOBILE:
256 hw->mac_type = em_82541;
258 case E1000_DEV_ID_82541ER:
259 case E1000_DEV_ID_82541GI:
260 case E1000_DEV_ID_82541GI_MOBILE:
261 hw->mac_type = em_82541_rev_2;
263 case E1000_DEV_ID_82547EI:
264 hw->mac_type = em_82547;
266 case E1000_DEV_ID_82547GI:
267 hw->mac_type = em_82547_rev_2;
270 /* Should never have loaded on this device */
271 return -E1000_ERR_MAC_TYPE;
274 return E1000_SUCCESS;
277 /*****************************************************************************
278 * Set media type and TBI compatibility.
280 * hw - Struct containing variables accessed by shared code
281 * **************************************************************************/
283 em_set_media_type(struct em_hw *hw)
287 DEBUGFUNC("em_set_media_type");
289 if(hw->mac_type != em_82543) {
290 /* tbi_compatibility is only valid on 82543 */
291 hw->tbi_compatibility_en = FALSE;
294 switch (hw->device_id) {
295 case E1000_DEV_ID_82545GM_SERDES:
296 case E1000_DEV_ID_82546GB_SERDES:
297 hw->media_type = em_media_type_internal_serdes;
300 if(hw->mac_type >= em_82543) {
301 status = E1000_READ_REG(hw, STATUS);
302 if(status & E1000_STATUS_TBIMODE) {
303 hw->media_type = em_media_type_fiber;
304 /* tbi_compatibility not valid on fiber */
305 hw->tbi_compatibility_en = FALSE;
307 hw->media_type = em_media_type_copper;
310 /* This is an 82542 (fiber only) */
311 hw->media_type = em_media_type_fiber;
316 /******************************************************************************
317 * Reset the transmit and receive units; mask and clear all interrupts.
319 * hw - Struct containing variables accessed by shared code
320 *****************************************************************************/
322 em_reset_hw(struct em_hw *hw)
330 DEBUGFUNC("em_reset_hw");
332 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
333 if(hw->mac_type == em_82542_rev2_0) {
334 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
335 em_pci_clear_mwi(hw);
338 /* Clear interrupt mask to stop board from generating interrupts */
339 DEBUGOUT("Masking off all interrupts\n");
340 E1000_WRITE_REG(hw, IMC, 0xffffffff);
342 /* Disable the Transmit and Receive units. Then delay to allow
343 * any pending transactions to complete before we hit the MAC with
346 E1000_WRITE_REG(hw, RCTL, 0);
347 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
348 E1000_WRITE_FLUSH(hw);
350 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
351 hw->tbi_compatibility_on = FALSE;
353 /* Delay to allow any outstanding PCI transactions to complete before
354 * resetting the device
358 ctrl = E1000_READ_REG(hw, CTRL);
360 /* Must reset the PHY before resetting the MAC */
361 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
362 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
366 /* Issue a global reset to the MAC. This will reset the chip's
367 * transmit, receive, DMA, and link units. It will not effect
368 * the current PCI configuration. The global reset bit is self-
369 * clearing, and should clear within a microsecond.
371 DEBUGOUT("Issuing a global reset to MAC\n");
373 switch(hw->mac_type) {
380 /* These controllers can't ack the 64-bit write when issuing the
381 * reset, so use IO-mapping as a workaround to issue the reset */
382 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
386 /* Reset is performed on a shadow of the control register */
387 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
390 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
394 /* After MAC reset, force reload of EEPROM to restore power-on settings to
395 * device. Later controllers reload the EEPROM automatically, so just wait
396 * for reload to complete.
398 switch(hw->mac_type) {
399 case em_82542_rev2_0:
400 case em_82542_rev2_1:
403 /* Wait for reset to complete */
405 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
406 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
407 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
408 E1000_WRITE_FLUSH(hw);
409 /* Wait for EEPROM reload */
416 /* Wait for EEPROM reload */
420 /* Wait for EEPROM reload (it happens automatically) */
425 /* Disable HW ARPs on ASF enabled adapters */
426 if(hw->mac_type >= em_82540) {
427 manc = E1000_READ_REG(hw, MANC);
428 manc &= ~(E1000_MANC_ARP_EN);
429 E1000_WRITE_REG(hw, MANC, manc);
432 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
433 em_phy_init_script(hw);
435 /* Configure activity LED after PHY reset */
436 led_ctrl = E1000_READ_REG(hw, LEDCTL);
437 led_ctrl &= IGP_ACTIVITY_LED_MASK;
438 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
439 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
442 /* Clear interrupt mask to stop board from generating interrupts */
443 DEBUGOUT("Masking off all interrupts\n");
444 E1000_WRITE_REG(hw, IMC, 0xffffffff);
446 /* Clear any pending interrupt events. */
447 icr = E1000_READ_REG(hw, ICR);
449 /* If MWI was previously enabled, reenable it. */
450 if(hw->mac_type == em_82542_rev2_0) {
451 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
455 return E1000_SUCCESS;
458 /******************************************************************************
459 * Performs basic configuration of the adapter.
461 * hw - Struct containing variables accessed by shared code
463 * Assumes that the controller has previously been reset and is in a
464 * post-reset uninitialized state. Initializes the receive address registers,
465 * multicast table, and VLAN filter table. Calls routines to setup link
466 * configuration and flow control settings. Clears all on-chip counters. Leaves
467 * the transmit and receive units disabled and uninitialized.
468 *****************************************************************************/
470 em_init_hw(struct em_hw *hw)
475 uint16_t pcix_cmd_word;
476 uint16_t pcix_stat_hi_word;
480 DEBUGFUNC("em_init_hw");
482 /* Initialize Identification LED */
483 if((ret_val = em_id_led_init(hw))) {
484 DEBUGOUT("Error Initializing Identification LED\n");
488 /* Set the media type and TBI compatibility */
489 em_set_media_type(hw);
491 /* Disabling VLAN filtering. */
492 DEBUGOUT("Initializing the IEEE VLAN\n");
493 E1000_WRITE_REG(hw, VET, 0);
497 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
498 if(hw->mac_type == em_82542_rev2_0) {
499 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
500 em_pci_clear_mwi(hw);
501 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
502 E1000_WRITE_FLUSH(hw);
506 /* Setup the receive address. This involves initializing all of the Receive
507 * Address Registers (RARs 0 - 15).
509 em_init_rx_addrs(hw);
511 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
512 if(hw->mac_type == em_82542_rev2_0) {
513 E1000_WRITE_REG(hw, RCTL, 0);
514 E1000_WRITE_FLUSH(hw);
516 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
520 /* Zero out the Multicast HASH table */
521 DEBUGOUT("Zeroing the MTA\n");
522 for(i = 0; i < E1000_MC_TBL_SIZE; i++)
523 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
525 /* Set the PCI priority bit correctly in the CTRL register. This
526 * determines if the adapter gives priority to receives, or if it
527 * gives equal priority to transmits and receives.
529 if(hw->dma_fairness) {
530 ctrl = E1000_READ_REG(hw, CTRL);
531 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
534 switch(hw->mac_type) {
539 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
540 if(hw->bus_type == em_bus_type_pcix) {
541 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
542 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
544 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
545 PCIX_COMMAND_MMRBC_SHIFT;
546 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
547 PCIX_STATUS_HI_MMRBC_SHIFT;
548 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
549 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
550 if(cmd_mmrbc > stat_mmrbc) {
551 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
552 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
553 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
560 /* Call a subroutine to configure the link and setup flow control. */
561 ret_val = em_setup_link(hw);
563 /* Set the transmit descriptor write-back policy */
564 if(hw->mac_type > em_82544) {
565 ctrl = E1000_READ_REG(hw, TXDCTL);
566 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
567 E1000_WRITE_REG(hw, TXDCTL, ctrl);
570 /* Clear all of the statistics registers (clear on read). It is
571 * important that we do this after we have tried to establish link
572 * because the symbol error count will increment wildly if there
575 em_clear_hw_cntrs(hw);
580 /******************************************************************************
581 * Adjust SERDES output amplitude based on EEPROM setting.
583 * hw - Struct containing variables accessed by shared code.
584 *****************************************************************************/
586 em_adjust_serdes_amplitude(struct em_hw *hw)
588 uint16_t eeprom_data;
591 DEBUGFUNC("em_adjust_serdes_amplitude");
593 if(hw->media_type != em_media_type_internal_serdes)
594 return E1000_SUCCESS;
596 switch(hw->mac_type) {
601 return E1000_SUCCESS;
604 if ((ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
609 if(eeprom_data != EEPROM_RESERVED_WORD) {
610 /* Adjust SERDES output amplitude only. */
611 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
612 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
617 return E1000_SUCCESS;
620 /******************************************************************************
621 * Configures flow control and link settings.
623 * hw - Struct containing variables accessed by shared code
625 * Determines which flow control settings to use. Calls the apropriate media-
626 * specific link configuration function. Configures the flow control settings.
627 * Assuming the adapter has a valid link partner, a valid link should be
628 * established. Assumes the hardware has previously been reset and the
629 * transmitter and receiver are not enabled.
630 *****************************************************************************/
632 em_setup_link(struct em_hw *hw)
636 uint16_t eeprom_data;
638 DEBUGFUNC("em_setup_link");
640 /* Read and store word 0x0F of the EEPROM. This word contains bits
641 * that determine the hardware's default PAUSE (flow control) mode,
642 * a bit that determines whether the HW defaults to enabling or
643 * disabling auto-negotiation, and the direction of the
644 * SW defined pins. If there is no SW over-ride of the flow
645 * control setting, then the variable hw->fc will
646 * be initialized based on a value in the EEPROM.
648 if(em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
649 DEBUGOUT("EEPROM Read Error\n");
650 return -E1000_ERR_EEPROM;
653 if(hw->fc == em_fc_default) {
654 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
656 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
657 EEPROM_WORD0F_ASM_DIR)
658 hw->fc = em_fc_tx_pause;
663 /* We want to save off the original Flow Control configuration just
664 * in case we get disconnected and then reconnected into a different
665 * hub or switch with different Flow Control capabilities.
667 if(hw->mac_type == em_82542_rev2_0)
668 hw->fc &= (~em_fc_tx_pause);
670 if((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
671 hw->fc &= (~em_fc_rx_pause);
673 hw->original_fc = hw->fc;
675 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
677 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
678 * polarity value for the SW controlled pins, and setup the
679 * Extended Device Control reg with that info.
680 * This is needed because one of the SW controlled pins is used for
681 * signal detection. So this should be done before em_setup_pcs_link()
682 * or em_phy_setup() is called.
684 if(hw->mac_type == em_82543) {
685 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
687 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
690 /* Call the necessary subroutine to configure the link. */
691 ret_val = (hw->media_type == em_media_type_copper) ?
692 em_setup_copper_link(hw) :
693 em_setup_fiber_serdes_link(hw);
695 /* Initialize the flow control address, type, and PAUSE timer
696 * registers to their default values. This is done even if flow
697 * control is disabled, because it does not hurt anything to
698 * initialize these registers.
700 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
702 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
703 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
704 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
705 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
707 /* Set the flow control receive threshold registers. Normally,
708 * these registers will be set to a default threshold that may be
709 * adjusted later by the driver's runtime code. However, if the
710 * ability to transmit pause frames in not enabled, then these
711 * registers will be set to 0.
713 if(!(hw->fc & em_fc_tx_pause)) {
714 E1000_WRITE_REG(hw, FCRTL, 0);
715 E1000_WRITE_REG(hw, FCRTH, 0);
717 /* We need to set up the Receive Threshold high and low water marks
718 * as well as (optionally) enabling the transmission of XON frames.
720 if(hw->fc_send_xon) {
721 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
722 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
724 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
725 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
731 /******************************************************************************
732 * Sets up link for a fiber based or serdes based adapter
734 * hw - Struct containing variables accessed by shared code
736 * Manipulates Physical Coding Sublayer functions in order to configure
737 * link. Assumes the hardware has been previously reset and the transmitter
738 * and receiver are not enabled.
739 *****************************************************************************/
741 em_setup_fiber_serdes_link(struct em_hw *hw)
750 DEBUGFUNC("em_setup_fiber_serdes_link");
752 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
753 * set when the optics detect a signal. On older adapters, it will be
754 * cleared when there is a signal. This applies to fiber media only.
755 * If we're on serdes media, adjust the output amplitude to value set in
758 ctrl = E1000_READ_REG(hw, CTRL);
759 if(hw->media_type == em_media_type_fiber)
760 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
762 if((ret_val = em_adjust_serdes_amplitude(hw)))
765 /* Take the link out of reset */
766 ctrl &= ~(E1000_CTRL_LRST);
768 /* Adjust VCO speed to improve BER performance */
769 if((ret_val = em_set_vco_speed(hw)))
772 em_config_collision_dist(hw);
774 /* Check for a software override of the flow control settings, and setup
775 * the device accordingly. If auto-negotiation is enabled, then software
776 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
777 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
778 * auto-negotiation is disabled, then software will have to manually
779 * configure the two flow control enable bits in the CTRL register.
781 * The possible values of the "fc" parameter are:
782 * 0: Flow control is completely disabled
783 * 1: Rx flow control is enabled (we can receive pause frames, but
784 * not send pause frames).
785 * 2: Tx flow control is enabled (we can send pause frames but we do
786 * not support receiving pause frames).
787 * 3: Both Rx and TX flow control (symmetric) are enabled.
791 /* Flow control is completely disabled by a software over-ride. */
792 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
795 /* RX Flow control is enabled and TX Flow control is disabled by a
796 * software over-ride. Since there really isn't a way to advertise
797 * that we are capable of RX Pause ONLY, we will advertise that we
798 * support both symmetric and asymmetric RX PAUSE. Later, we will
799 * disable the adapter's ability to send PAUSE frames.
801 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
804 /* TX Flow control is enabled, and RX Flow control is disabled, by a
805 * software over-ride.
807 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
810 /* Flow control (both RX and TX) is enabled by a software over-ride. */
811 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
814 DEBUGOUT("Flow control param set incorrectly\n");
815 return -E1000_ERR_CONFIG;
819 /* Since auto-negotiation is enabled, take the link out of reset (the link
820 * will be in reset, because we previously reset the chip). This will
821 * restart auto-negotiation. If auto-neogtiation is successful then the
822 * link-up status bit will be set and the flow control enable bits (RFCE
823 * and TFCE) will be set according to their negotiated value.
825 DEBUGOUT("Auto-negotiation enabled\n");
827 E1000_WRITE_REG(hw, TXCW, txcw);
828 E1000_WRITE_REG(hw, CTRL, ctrl);
829 E1000_WRITE_FLUSH(hw);
834 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
835 * indication in the Device Status Register. Time-out if a link isn't
836 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
837 * less than 500 milliseconds even if the other end is doing it in SW).
838 * For internal serdes, we just assume a signal is present, then poll.
840 if(hw->media_type == em_media_type_internal_serdes ||
841 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
842 DEBUGOUT("Looking for Link\n");
843 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
845 status = E1000_READ_REG(hw, STATUS);
846 if(status & E1000_STATUS_LU) break;
848 if(i == (LINK_UP_TIMEOUT / 10)) {
849 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
850 hw->autoneg_failed = 1;
851 /* AutoNeg failed to achieve a link, so we'll call
852 * em_check_for_link. This routine will force the link up if
853 * we detect a signal. This will allow us to communicate with
854 * non-autonegotiating link partners.
856 if((ret_val = em_check_for_link(hw))) {
857 DEBUGOUT("Error while checking for link\n");
860 hw->autoneg_failed = 0;
862 hw->autoneg_failed = 0;
863 DEBUGOUT("Valid Link Found\n");
866 DEBUGOUT("No Signal Detected\n");
868 return E1000_SUCCESS;
871 /******************************************************************************
872 * Detects which PHY is present and the speed and duplex
874 * hw - Struct containing variables accessed by shared code
875 ******************************************************************************/
877 em_setup_copper_link(struct em_hw *hw)
885 DEBUGFUNC("em_setup_copper_link");
887 ctrl = E1000_READ_REG(hw, CTRL);
888 /* With 82543, we need to force speed and duplex on the MAC equal to what
889 * the PHY speed and duplex configuration is. In addition, we need to
890 * perform a hardware reset on the PHY to take it out of reset.
892 if(hw->mac_type > em_82543) {
893 ctrl |= E1000_CTRL_SLU;
894 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
895 E1000_WRITE_REG(hw, CTRL, ctrl);
897 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
898 E1000_WRITE_REG(hw, CTRL, ctrl);
902 /* Make sure we have a valid PHY */
903 if((ret_val = em_detect_gig_phy(hw))) {
904 DEBUGOUT("Error, did not detect valid phy.\n");
907 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
909 if(hw->mac_type <= em_82543 ||
910 hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
911 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
912 hw->phy_reset_disable = FALSE;
914 if(!hw->phy_reset_disable) {
915 if (hw->phy_type == em_phy_igp) {
917 if((ret_val = em_phy_reset(hw))) {
918 DEBUGOUT("Error Resetting the PHY\n");
922 /* Wait 10ms for MAC to configure PHY from eeprom settings */
925 /* Configure activity LED after PHY reset */
926 led_ctrl = E1000_READ_REG(hw, LEDCTL);
927 led_ctrl &= IGP_ACTIVITY_LED_MASK;
928 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
929 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
931 /* disable lplu d3 during driver init */
932 if((ret_val = em_set_d3_lplu_state(hw, FALSE))) {
933 DEBUGOUT("Error Disabling LPLU D3\n");
937 /* Configure mdi-mdix settings */
938 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
942 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
943 hw->dsp_config_state = em_dsp_config_disabled;
944 /* Force MDI for IGP B-0 PHY */
945 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
946 IGP01E1000_PSCR_FORCE_MDI_MDIX);
950 hw->dsp_config_state = em_dsp_config_enabled;
951 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
955 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
958 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
962 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
966 if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
970 /* set auto-master slave resolution settings */
972 em_ms_type phy_ms_setting = hw->master_slave;
974 if(hw->ffe_config_state == em_ffe_config_active)
975 hw->ffe_config_state = em_ffe_config_enabled;
977 if(hw->dsp_config_state == em_dsp_config_activated)
978 hw->dsp_config_state = em_dsp_config_enabled;
980 /* when autonegotiation advertisment is only 1000Mbps then we
981 * should disable SmartSpeed and enable Auto MasterSlave
982 * resolution as hardware default. */
983 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
984 /* Disable SmartSpeed */
985 if((ret_val = em_read_phy_reg(hw,
986 IGP01E1000_PHY_PORT_CONFIG,
989 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
990 if((ret_val = em_write_phy_reg(hw,
991 IGP01E1000_PHY_PORT_CONFIG,
994 /* Set auto Master/Slave resolution process */
995 if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
998 phy_data &= ~CR_1000T_MS_ENABLE;
999 if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
1004 if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
1008 /* load defaults for future use */
1009 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1010 ((phy_data & CR_1000T_MS_VALUE) ?
1011 em_ms_force_master :
1012 em_ms_force_slave) :
1015 switch (phy_ms_setting) {
1016 case em_ms_force_master:
1017 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1019 case em_ms_force_slave:
1020 phy_data |= CR_1000T_MS_ENABLE;
1021 phy_data &= ~(CR_1000T_MS_VALUE);
1024 phy_data &= ~CR_1000T_MS_ENABLE;
1028 if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
1033 /* Enable CRS on TX. This must be set for half-duplex operation. */
1034 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1038 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1041 * MDI/MDI-X = 0 (default)
1042 * 0 - Auto for all speeds
1045 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1047 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1051 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1054 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1057 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1061 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1066 * disable_polarity_correction = 0 (default)
1067 * Automatic Correction for Reversed Cable Polarity
1071 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1072 if(hw->disable_polarity_correction == 1)
1073 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1074 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1078 /* Force TX_CLK in the Extended PHY Specific Control Register
1081 if((ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1085 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1087 if (hw->phy_revision < M88E1011_I_REV_4) {
1088 /* Configure Master and Slave downshift values */
1089 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1090 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1091 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1092 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1093 if((ret_val = em_write_phy_reg(hw,
1094 M88E1000_EXT_PHY_SPEC_CTRL,
1099 /* SW Reset the PHY so all changes take effect */
1100 if((ret_val = em_phy_reset(hw))) {
1101 DEBUGOUT("Error Resetting the PHY\n");
1107 * autoneg = 1 (default)
1108 * PHY will advertise value(s) parsed from
1109 * autoneg_advertised and fc
1111 * PHY will be set to 10H, 10F, 100H, or 100F
1112 * depending on value parsed from forced_speed_duplex.
1115 /* Is autoneg enabled? This is enabled by default or by software
1116 * override. If so, call em_phy_setup_autoneg routine to parse the
1117 * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1118 * the user should have provided a speed/duplex override. If so, then
1119 * call em_phy_force_speed_duplex to parse and set this up.
1122 /* Perform some bounds checking on the hw->autoneg_advertised
1123 * parameter. If this variable is zero, then set it to the default.
1125 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1127 /* If autoneg_advertised is zero, we assume it was not defaulted
1128 * by the calling code so we set to advertise full capability.
1130 if(hw->autoneg_advertised == 0)
1131 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1133 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1134 if((ret_val = em_phy_setup_autoneg(hw))) {
1135 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1138 DEBUGOUT("Restarting Auto-Neg\n");
1140 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1141 * the Auto Neg Restart bit in the PHY control register.
1143 if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data)))
1146 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1147 if((ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data)))
1150 /* Does the user want to wait for Auto-Neg to complete here, or
1151 * check at a later time (for example, callback routine).
1153 if(hw->wait_autoneg_complete) {
1154 if((ret_val = em_wait_autoneg(hw))) {
1155 DEBUGOUT("Error while waiting for autoneg to complete\n");
1159 hw->get_link_status = TRUE;
1161 DEBUGOUT("Forcing speed and duplex\n");
1162 if((ret_val = em_phy_force_speed_duplex(hw))) {
1163 DEBUGOUT("Error Forcing Speed and Duplex\n");
1167 } /* !hw->phy_reset_disable */
1169 /* Check link status. Wait up to 100 microseconds for link to become
1172 for(i = 0; i < 10; i++) {
1173 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1175 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1178 if(phy_data & MII_SR_LINK_STATUS) {
1179 /* We have link, so we need to finish the config process:
1180 * 1) Set up the MAC to the current PHY speed/duplex
1181 * if we are on 82543. If we
1182 * are on newer silicon, we only need to configure
1183 * collision distance in the Transmit Control Register.
1184 * 2) Set up flow control on the MAC to that established with
1187 if(hw->mac_type >= em_82544) {
1188 em_config_collision_dist(hw);
1190 if((ret_val = em_config_mac_to_phy(hw))) {
1191 DEBUGOUT("Error configuring MAC to PHY settings\n");
1195 if((ret_val = em_config_fc_after_link_up(hw))) {
1196 DEBUGOUT("Error Configuring Flow Control\n");
1199 DEBUGOUT("Valid link established!!!\n");
1201 if(hw->phy_type == em_phy_igp) {
1202 if((ret_val = em_config_dsp_after_link_change(hw, TRUE))) {
1203 DEBUGOUT("Error Configuring DSP after link up\n");
1207 DEBUGOUT("Valid link established!!!\n");
1208 return E1000_SUCCESS;
1213 DEBUGOUT("Unable to establish link!!!\n");
1214 return E1000_SUCCESS;
1217 /******************************************************************************
1218 * Configures PHY autoneg and flow control advertisement settings
1220 * hw - Struct containing variables accessed by shared code
1221 ******************************************************************************/
1223 em_phy_setup_autoneg(struct em_hw *hw)
1226 uint16_t mii_autoneg_adv_reg;
1227 uint16_t mii_1000t_ctrl_reg;
1229 DEBUGFUNC("em_phy_setup_autoneg");
1231 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1232 if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
1233 &mii_autoneg_adv_reg)))
1236 /* Read the MII 1000Base-T Control Register (Address 9). */
1237 if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
1240 /* Need to parse both autoneg_advertised and fc and set up
1241 * the appropriate PHY registers. First we will parse for
1242 * autoneg_advertised software override. Since we can advertise
1243 * a plethora of combinations, we need to check each bit
1247 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1248 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1249 * the 1000Base-T Control Register (Address 9).
1251 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1252 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1254 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1256 /* Do we want to advertise 10 Mb Half Duplex? */
1257 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1258 DEBUGOUT("Advertise 10mb Half duplex\n");
1259 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1262 /* Do we want to advertise 10 Mb Full Duplex? */
1263 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1264 DEBUGOUT("Advertise 10mb Full duplex\n");
1265 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1268 /* Do we want to advertise 100 Mb Half Duplex? */
1269 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1270 DEBUGOUT("Advertise 100mb Half duplex\n");
1271 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1274 /* Do we want to advertise 100 Mb Full Duplex? */
1275 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1276 DEBUGOUT("Advertise 100mb Full duplex\n");
1277 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1280 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1281 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1282 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1285 /* Do we want to advertise 1000 Mb Full Duplex? */
1286 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1287 DEBUGOUT("Advertise 1000mb Full duplex\n");
1288 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1291 /* Check for a software override of the flow control settings, and
1292 * setup the PHY advertisement registers accordingly. If
1293 * auto-negotiation is enabled, then software will have to set the
1294 * "PAUSE" bits to the correct value in the Auto-Negotiation
1295 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1297 * The possible values of the "fc" parameter are:
1298 * 0: Flow control is completely disabled
1299 * 1: Rx flow control is enabled (we can receive pause frames
1300 * but not send pause frames).
1301 * 2: Tx flow control is enabled (we can send pause frames
1302 * but we do not support receiving pause frames).
1303 * 3: Both Rx and TX flow control (symmetric) are enabled.
1304 * other: No software override. The flow control configuration
1305 * in the EEPROM is used.
1308 case em_fc_none: /* 0 */
1309 /* Flow control (RX & TX) is completely disabled by a
1310 * software over-ride.
1312 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1314 case em_fc_rx_pause: /* 1 */
1315 /* RX Flow control is enabled, and TX Flow control is
1316 * disabled, by a software over-ride.
1318 /* Since there really isn't a way to advertise that we are
1319 * capable of RX Pause ONLY, we will advertise that we
1320 * support both symmetric and asymmetric RX PAUSE. Later
1321 * (in em_config_fc_after_link_up) we will disable the
1322 *hw's ability to send PAUSE frames.
1324 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1326 case em_fc_tx_pause: /* 2 */
1327 /* TX Flow control is enabled, and RX Flow control is
1328 * disabled, by a software over-ride.
1330 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1331 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1333 case em_fc_full: /* 3 */
1334 /* Flow control (both RX and TX) is enabled by a software
1337 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1340 DEBUGOUT("Flow control param set incorrectly\n");
1341 return -E1000_ERR_CONFIG;
1344 if((ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV,
1345 mii_autoneg_adv_reg)))
1348 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1350 if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
1353 return E1000_SUCCESS;
1356 /******************************************************************************
1357 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1359 * hw - Struct containing variables accessed by shared code
1360 ******************************************************************************/
1362 em_phy_force_speed_duplex(struct em_hw *hw)
1366 uint16_t mii_ctrl_reg;
1367 uint16_t mii_status_reg;
1371 DEBUGFUNC("em_phy_force_speed_duplex");
1373 /* Turn off Flow control if we are forcing speed and duplex. */
1374 hw->fc = em_fc_none;
1376 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1378 /* Read the Device Control Register. */
1379 ctrl = E1000_READ_REG(hw, CTRL);
1381 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1382 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1383 ctrl &= ~(DEVICE_SPEED_MASK);
1385 /* Clear the Auto Speed Detect Enable bit. */
1386 ctrl &= ~E1000_CTRL_ASDE;
1388 /* Read the MII Control Register. */
1389 if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg)))
1392 /* We need to disable autoneg in order to force link and duplex. */
1394 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1396 /* Are we forcing Full or Half Duplex? */
1397 if(hw->forced_speed_duplex == em_100_full ||
1398 hw->forced_speed_duplex == em_10_full) {
1399 /* We want to force full duplex so we SET the full duplex bits in the
1400 * Device and MII Control Registers.
1402 ctrl |= E1000_CTRL_FD;
1403 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1404 DEBUGOUT("Full Duplex\n");
1406 /* We want to force half duplex so we CLEAR the full duplex bits in
1407 * the Device and MII Control Registers.
1409 ctrl &= ~E1000_CTRL_FD;
1410 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1411 DEBUGOUT("Half Duplex\n");
1414 /* Are we forcing 100Mbps??? */
1415 if(hw->forced_speed_duplex == em_100_full ||
1416 hw->forced_speed_duplex == em_100_half) {
1417 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1418 ctrl |= E1000_CTRL_SPD_100;
1419 mii_ctrl_reg |= MII_CR_SPEED_100;
1420 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1421 DEBUGOUT("Forcing 100mb ");
1423 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1424 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1425 mii_ctrl_reg |= MII_CR_SPEED_10;
1426 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1427 DEBUGOUT("Forcing 10mb ");
1430 em_config_collision_dist(hw);
1432 /* Write the configured values back to the Device Control Reg. */
1433 E1000_WRITE_REG(hw, CTRL, ctrl);
1435 if (hw->phy_type == em_phy_m88) {
1436 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1440 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1441 * forced whenever speed are duplex are forced.
1443 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1444 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1448 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1450 /* Need to reset the PHY or these changes will be ignored */
1451 mii_ctrl_reg |= MII_CR_RESET;
1453 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1454 * forced whenever speed or duplex are forced.
1456 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1460 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1461 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1463 if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1468 /* Write back the modified PHY MII control register. */
1469 if((ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg)))
1474 /* The wait_autoneg_complete flag may be a little misleading here.
1475 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1476 * But we do want to delay for a period while forcing only so we
1477 * don't generate false No Link messages. So we will wait here
1478 * only if the user has set wait_autoneg_complete to 1, which is
1481 if(hw->wait_autoneg_complete) {
1482 /* We will wait for autoneg to complete. */
1483 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1486 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1487 for(i = PHY_FORCE_TIME; i > 0; i--) {
1488 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1491 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1494 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1497 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1500 if((i == 0) && (hw->phy_type == em_phy_m88)) {
1501 /* We didn't get link. Reset the DSP and wait again for link. */
1502 if((ret_val = em_phy_reset_dsp(hw))) {
1503 DEBUGOUT("Error Resetting PHY DSP\n");
1507 /* This loop will early-out if the link condition has been met. */
1508 for(i = PHY_FORCE_TIME; i > 0; i--) {
1509 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1511 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1514 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1517 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1522 if (hw->phy_type == em_phy_m88) {
1523 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1524 * Extended PHY Specific Control Register to 25MHz clock. This value
1525 * defaults back to a 2.5MHz clock when the PHY is reset.
1527 if((ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1531 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1532 if((ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1536 /* In addition, because of the s/w reset above, we need to enable CRS on
1537 * TX. This must be set for both full and half duplex operation.
1539 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1543 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1544 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1548 /* Polarity reversal workaround for forced 10F/10H links. */
1549 if(hw->mac_type <= em_82544 &&
1550 (hw->forced_speed_duplex == em_10_full ||
1551 hw->forced_speed_duplex == em_10_half)) {
1552 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
1555 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
1558 /* IEEE requirement is 150ms */
1560 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
1563 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
1568 return E1000_SUCCESS;
1571 /******************************************************************************
1572 * Sets the collision distance in the Transmit Control register
1574 * hw - Struct containing variables accessed by shared code
1576 * Link should have been established previously. Reads the speed and duplex
1577 * information from the Device Status register.
1578 ******************************************************************************/
1580 em_config_collision_dist(struct em_hw *hw)
1584 DEBUGFUNC("em_config_collision_dist");
1586 tctl = E1000_READ_REG(hw, TCTL);
1588 tctl &= ~E1000_TCTL_COLD;
1589 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1591 E1000_WRITE_REG(hw, TCTL, tctl);
1592 E1000_WRITE_FLUSH(hw);
1595 /******************************************************************************
1596 * Sets MAC speed and duplex settings to reflect the those in the PHY
1598 * hw - Struct containing variables accessed by shared code
1599 * mii_reg - data to write to the MII control register
1601 * The contents of the PHY register containing the needed information need to
1603 ******************************************************************************/
1605 em_config_mac_to_phy(struct em_hw *hw)
1611 DEBUGFUNC("em_config_mac_to_phy");
1613 /* Read the Device Control Register and set the bits to Force Speed
1616 ctrl = E1000_READ_REG(hw, CTRL);
1617 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1618 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1620 /* Set up duplex in the Device Control and Transmit Control
1621 * registers depending on negotiated values.
1623 if (hw->phy_type == em_phy_igp) {
1624 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1628 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1629 else ctrl &= ~E1000_CTRL_FD;
1631 em_config_collision_dist(hw);
1633 /* Set up speed in the Device Control register depending on
1634 * negotiated values.
1636 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1637 IGP01E1000_PSSR_SPEED_1000MBPS)
1638 ctrl |= E1000_CTRL_SPD_1000;
1639 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1640 IGP01E1000_PSSR_SPEED_100MBPS)
1641 ctrl |= E1000_CTRL_SPD_100;
1643 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1647 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1648 else ctrl &= ~E1000_CTRL_FD;
1650 em_config_collision_dist(hw);
1652 /* Set up speed in the Device Control register depending on
1653 * negotiated values.
1655 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1656 ctrl |= E1000_CTRL_SPD_1000;
1657 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1658 ctrl |= E1000_CTRL_SPD_100;
1660 /* Write the configured values back to the Device Control Reg. */
1661 E1000_WRITE_REG(hw, CTRL, ctrl);
1662 return E1000_SUCCESS;
1665 /******************************************************************************
1666 * Forces the MAC's flow control settings.
1668 * hw - Struct containing variables accessed by shared code
1670 * Sets the TFCE and RFCE bits in the device control register to reflect
1671 * the adapter settings. TFCE and RFCE need to be explicitly set by
1672 * software when a Copper PHY is used because autonegotiation is managed
1673 * by the PHY rather than the MAC. Software must also configure these
1674 * bits when link is forced on a fiber connection.
1675 *****************************************************************************/
1677 em_force_mac_fc(struct em_hw *hw)
1681 DEBUGFUNC("em_force_mac_fc");
1683 /* Get the current configuration of the Device Control Register */
1684 ctrl = E1000_READ_REG(hw, CTRL);
1686 /* Because we didn't get link via the internal auto-negotiation
1687 * mechanism (we either forced link or we got link via PHY
1688 * auto-neg), we have to manually enable/disable transmit an
1689 * receive flow control.
1691 * The "Case" statement below enables/disable flow control
1692 * according to the "hw->fc" parameter.
1694 * The possible values of the "fc" parameter are:
1695 * 0: Flow control is completely disabled
1696 * 1: Rx flow control is enabled (we can receive pause
1697 * frames but not send pause frames).
1698 * 2: Tx flow control is enabled (we can send pause frames
1699 * frames but we do not receive pause frames).
1700 * 3: Both Rx and TX flow control (symmetric) is enabled.
1701 * other: No other values should be possible at this point.
1706 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1708 case em_fc_rx_pause:
1709 ctrl &= (~E1000_CTRL_TFCE);
1710 ctrl |= E1000_CTRL_RFCE;
1712 case em_fc_tx_pause:
1713 ctrl &= (~E1000_CTRL_RFCE);
1714 ctrl |= E1000_CTRL_TFCE;
1717 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1720 DEBUGOUT("Flow control param set incorrectly\n");
1721 return -E1000_ERR_CONFIG;
1724 /* Disable TX Flow Control for 82542 (rev 2.0) */
1725 if(hw->mac_type == em_82542_rev2_0)
1726 ctrl &= (~E1000_CTRL_TFCE);
1728 E1000_WRITE_REG(hw, CTRL, ctrl);
1729 return E1000_SUCCESS;
1732 /******************************************************************************
1733 * Configures flow control settings after link is established
1735 * hw - Struct containing variables accessed by shared code
1737 * Should be called immediately after a valid link has been established.
1738 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1739 * and autonegotiation is enabled, the MAC flow control settings will be set
1740 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1741 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1742 *****************************************************************************/
1744 em_config_fc_after_link_up(struct em_hw *hw)
1747 uint16_t mii_status_reg;
1748 uint16_t mii_nway_adv_reg;
1749 uint16_t mii_nway_lp_ability_reg;
1753 DEBUGFUNC("em_config_fc_after_link_up");
1755 /* Check for the case where we have fiber media and auto-neg failed
1756 * so we had to force link. In this case, we need to force the
1757 * configuration of the MAC to match the "fc" parameter.
1759 if(((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
1760 ((hw->media_type == em_media_type_internal_serdes) && (hw->autoneg_failed)) ||
1761 ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
1762 if((ret_val = em_force_mac_fc(hw))) {
1763 DEBUGOUT("Error forcing flow control settings\n");
1768 /* Check for the case where we have copper media and auto-neg is
1769 * enabled. In this case, we need to check and see if Auto-Neg
1770 * has completed, and if so, how the PHY and link partner has
1771 * flow control configured.
1773 if((hw->media_type == em_media_type_copper) && hw->autoneg) {
1774 /* Read the MII Status Register and check to see if AutoNeg
1775 * has completed. We read this twice because this reg has
1776 * some "sticky" (latched) bits.
1778 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1780 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1783 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1784 /* The AutoNeg process has completed, so we now need to
1785 * read both the Auto Negotiation Advertisement Register
1786 * (Address 4) and the Auto_Negotiation Base Page Ability
1787 * Register (Address 5) to determine how flow control was
1790 if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
1791 &mii_nway_adv_reg)))
1793 if((ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
1794 &mii_nway_lp_ability_reg)))
1797 /* Two bits in the Auto Negotiation Advertisement Register
1798 * (Address 4) and two bits in the Auto Negotiation Base
1799 * Page Ability Register (Address 5) determine flow control
1800 * for both the PHY and the link partner. The following
1801 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1802 * 1999, describes these PAUSE resolution bits and how flow
1803 * control is determined based upon these settings.
1804 * NOTE: DC = Don't Care
1806 * LOCAL DEVICE | LINK PARTNER
1807 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1808 *-------|---------|-------|---------|--------------------
1809 * 0 | 0 | DC | DC | em_fc_none
1810 * 0 | 1 | 0 | DC | em_fc_none
1811 * 0 | 1 | 1 | 0 | em_fc_none
1812 * 0 | 1 | 1 | 1 | em_fc_tx_pause
1813 * 1 | 0 | 0 | DC | em_fc_none
1814 * 1 | DC | 1 | DC | em_fc_full
1815 * 1 | 1 | 0 | 0 | em_fc_none
1816 * 1 | 1 | 0 | 1 | em_fc_rx_pause
1819 /* Are both PAUSE bits set to 1? If so, this implies
1820 * Symmetric Flow Control is enabled at both ends. The
1821 * ASM_DIR bits are irrelevant per the spec.
1823 * For Symmetric Flow Control:
1825 * LOCAL DEVICE | LINK PARTNER
1826 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1827 *-------|---------|-------|---------|--------------------
1828 * 1 | DC | 1 | DC | em_fc_full
1831 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1832 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1833 /* Now we need to check if the user selected RX ONLY
1834 * of pause frames. In this case, we had to advertise
1835 * FULL flow control because we could not advertise RX
1836 * ONLY. Hence, we must now check to see if we need to
1837 * turn OFF the TRANSMISSION of PAUSE frames.
1839 if(hw->original_fc == em_fc_full) {
1840 hw->fc = em_fc_full;
1841 DEBUGOUT("Flow Control = FULL.\r\n");
1843 hw->fc = em_fc_rx_pause;
1844 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1847 /* For receiving PAUSE frames ONLY.
1849 * LOCAL DEVICE | LINK PARTNER
1850 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1851 *-------|---------|-------|---------|--------------------
1852 * 0 | 1 | 1 | 1 | em_fc_tx_pause
1855 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1856 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1857 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1858 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1859 hw->fc = em_fc_tx_pause;
1860 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1862 /* For transmitting PAUSE frames ONLY.
1864 * LOCAL DEVICE | LINK PARTNER
1865 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1866 *-------|---------|-------|---------|--------------------
1867 * 1 | 1 | 0 | 1 | em_fc_rx_pause
1870 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1871 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1872 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1873 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1874 hw->fc = em_fc_rx_pause;
1875 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1877 /* Per the IEEE spec, at this point flow control should be
1878 * disabled. However, we want to consider that we could
1879 * be connected to a legacy switch that doesn't advertise
1880 * desired flow control, but can be forced on the link
1881 * partner. So if we advertised no flow control, that is
1882 * what we will resolve to. If we advertised some kind of
1883 * receive capability (Rx Pause Only or Full Flow Control)
1884 * and the link partner advertised none, we will configure
1885 * ourselves to enable Rx Flow Control only. We can do
1886 * this safely for two reasons: If the link partner really
1887 * didn't want flow control enabled, and we enable Rx, no
1888 * harm done since we won't be receiving any PAUSE frames
1889 * anyway. If the intent on the link partner was to have
1890 * flow control enabled, then by us enabling RX only, we
1891 * can at least receive pause frames and process them.
1892 * This is a good idea because in most cases, since we are
1893 * predominantly a server NIC, more times than not we will
1894 * be asked to delay transmission of packets than asking
1895 * our link partner to pause transmission of frames.
1897 else if((hw->original_fc == em_fc_none ||
1898 hw->original_fc == em_fc_tx_pause) ||
1899 hw->fc_strict_ieee) {
1900 hw->fc = em_fc_none;
1901 DEBUGOUT("Flow Control = NONE.\r\n");
1903 hw->fc = em_fc_rx_pause;
1904 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1907 /* Now we need to do one last check... If we auto-
1908 * negotiated to HALF DUPLEX, flow control should not be
1909 * enabled per IEEE 802.3 spec.
1911 if((ret_val = em_get_speed_and_duplex(hw, &speed, &duplex))) {
1912 DEBUGOUT("Error getting link speed and duplex\n");
1916 if(duplex == HALF_DUPLEX)
1917 hw->fc = em_fc_none;
1919 /* Now we call a subroutine to actually force the MAC
1920 * controller to use the correct flow control settings.
1922 if((ret_val = em_force_mac_fc(hw))) {
1923 DEBUGOUT("Error forcing flow control settings\n");
1927 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
1930 return E1000_SUCCESS;
1933 /******************************************************************************
1934 * Checks to see if the link status of the hardware has changed.
1936 * hw - Struct containing variables accessed by shared code
1938 * Called by any function that needs to check the link status of the adapter.
1939 *****************************************************************************/
1941 em_check_for_link(struct em_hw *hw)
1947 uint32_t signal = 0;
1951 DEBUGFUNC("em_check_for_link");
1953 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
1954 * set when the optics detect a signal. On older adapters, it will be
1955 * cleared when there is a signal. This applies to fiber media only.
1957 if(hw->media_type == em_media_type_fiber)
1958 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
1960 ctrl = E1000_READ_REG(hw, CTRL);
1961 status = E1000_READ_REG(hw, STATUS);
1962 rxcw = E1000_READ_REG(hw, RXCW);
1964 /* If we have a copper PHY then we only want to go out to the PHY
1965 * registers to see if Auto-Neg has completed and/or if our link
1966 * status has changed. The get_link_status flag will be set if we
1967 * receive a Link Status Change interrupt or we have Rx Sequence
1970 if((hw->media_type == em_media_type_copper) && hw->get_link_status) {
1971 /* First we want to see if the MII Status Register reports
1972 * link. If so, then we want to get the current speed/duplex
1974 * Read the register twice since the link bit is sticky.
1976 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1978 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1981 if(phy_data & MII_SR_LINK_STATUS) {
1982 hw->get_link_status = FALSE;
1983 /* Check if there was DownShift, must be checked immediately after
1985 em_check_downshift(hw);
1988 /* No link detected */
1989 em_config_dsp_after_link_change(hw, FALSE);
1993 /* If we are forcing speed/duplex, then we simply return since
1994 * we have already determined whether we have link or not.
1996 if(!hw->autoneg) return -E1000_ERR_CONFIG;
1998 /* optimize the dsp settings for the igp phy */
1999 em_config_dsp_after_link_change(hw, TRUE);
2001 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2002 * have Si on board that is 82544 or newer, Auto
2003 * Speed Detection takes care of MAC speed/duplex
2004 * configuration. So we only need to configure Collision
2005 * Distance in the MAC. Otherwise, we need to force
2006 * speed/duplex on the MAC to the current PHY speed/duplex
2009 if(hw->mac_type >= em_82544)
2010 em_config_collision_dist(hw);
2012 if((ret_val = em_config_mac_to_phy(hw))) {
2013 DEBUGOUT("Error configuring MAC to PHY settings\n");
2018 /* Configure Flow Control now that Auto-Neg has completed. First, we
2019 * need to restore the desired flow control settings because we may
2020 * have had to re-autoneg with a different link partner.
2022 if((ret_val = em_config_fc_after_link_up(hw))) {
2023 DEBUGOUT("Error configuring flow control\n");
2027 /* At this point we know that we are on copper and we have
2028 * auto-negotiated link. These are conditions for checking the link
2029 * partner capability register. We use the link speed to determine if
2030 * TBI compatibility needs to be turned on or off. If the link is not
2031 * at gigabit speed, then TBI compatibility is not needed. If we are
2032 * at gigabit speed, we turn on TBI compatibility.
2034 if(hw->tbi_compatibility_en) {
2035 uint16_t speed, duplex;
2036 em_get_speed_and_duplex(hw, &speed, &duplex);
2037 if(speed != SPEED_1000) {
2038 /* If link speed is not set to gigabit speed, we do not need
2039 * to enable TBI compatibility.
2041 if(hw->tbi_compatibility_on) {
2042 /* If we previously were in the mode, turn it off. */
2043 rctl = E1000_READ_REG(hw, RCTL);
2044 rctl &= ~E1000_RCTL_SBP;
2045 E1000_WRITE_REG(hw, RCTL, rctl);
2046 hw->tbi_compatibility_on = FALSE;
2049 /* If TBI compatibility is was previously off, turn it on. For
2050 * compatibility with a TBI link partner, we will store bad
2051 * packets. Some frames have an additional byte on the end and
2052 * will look like CRC errors to to the hardware.
2054 if(!hw->tbi_compatibility_on) {
2055 hw->tbi_compatibility_on = TRUE;
2056 rctl = E1000_READ_REG(hw, RCTL);
2057 rctl |= E1000_RCTL_SBP;
2058 E1000_WRITE_REG(hw, RCTL, rctl);
2063 /* If we don't have link (auto-negotiation failed or link partner cannot
2064 * auto-negotiate), the cable is plugged in (we have signal), and our
2065 * link partner is not trying to auto-negotiate with us (we are receiving
2066 * idles or data), we need to force link up. We also need to give
2067 * auto-negotiation time to complete, in case the cable was just plugged
2068 * in. The autoneg_failed flag does this.
2070 else if((((hw->media_type == em_media_type_fiber) &&
2071 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2072 (hw->media_type == em_media_type_internal_serdes)) &&
2073 (!(status & E1000_STATUS_LU)) &&
2074 (!(rxcw & E1000_RXCW_C))) {
2075 if(hw->autoneg_failed == 0) {
2076 hw->autoneg_failed = 1;
2079 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2081 /* Disable auto-negotiation in the TXCW register */
2082 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2084 /* Force link-up and also force full-duplex. */
2085 ctrl = E1000_READ_REG(hw, CTRL);
2086 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2087 E1000_WRITE_REG(hw, CTRL, ctrl);
2089 /* Configure Flow Control after forcing link up. */
2090 if((ret_val = em_config_fc_after_link_up(hw))) {
2091 DEBUGOUT("Error configuring flow control\n");
2095 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2096 * auto-negotiation in the TXCW register and disable forced link in the
2097 * Device Control register in an attempt to auto-negotiate with our link
2100 else if(((hw->media_type == em_media_type_fiber) ||
2101 (hw->media_type == em_media_type_internal_serdes)) &&
2102 (ctrl & E1000_CTRL_SLU) &&
2103 (rxcw & E1000_RXCW_C)) {
2104 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2105 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2106 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2108 hw->serdes_link_down = FALSE;
2110 /* If we force link for non-auto-negotiation switch, check link status
2111 * based on MAC synchronization for internal serdes media type.
2113 else if((hw->media_type == em_media_type_internal_serdes) &&
2114 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2115 /* SYNCH bit and IV bit are sticky. */
2117 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2118 if(!(rxcw & E1000_RXCW_IV)) {
2119 hw->serdes_link_down = FALSE;
2120 DEBUGOUT("SERDES: Link is up.\n");
2123 hw->serdes_link_down = TRUE;
2124 DEBUGOUT("SERDES: Link is down.\n");
2127 if((hw->media_type == em_media_type_internal_serdes) &&
2128 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2129 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2131 return E1000_SUCCESS;
2134 /******************************************************************************
2135 * Detects the current speed and duplex settings of the hardware.
2137 * hw - Struct containing variables accessed by shared code
2138 * speed - Speed of the connection
2139 * duplex - Duplex setting of the connection
2140 *****************************************************************************/
2142 em_get_speed_and_duplex(struct em_hw *hw,
2150 DEBUGFUNC("em_get_speed_and_duplex");
2152 if(hw->mac_type >= em_82543) {
2153 status = E1000_READ_REG(hw, STATUS);
2154 if(status & E1000_STATUS_SPEED_1000) {
2155 *speed = SPEED_1000;
2156 DEBUGOUT("1000 Mbs, ");
2157 } else if(status & E1000_STATUS_SPEED_100) {
2159 DEBUGOUT("100 Mbs, ");
2162 DEBUGOUT("10 Mbs, ");
2165 if(status & E1000_STATUS_FD) {
2166 *duplex = FULL_DUPLEX;
2167 DEBUGOUT("Full Duplex\r\n");
2169 *duplex = HALF_DUPLEX;
2170 DEBUGOUT(" Half Duplex\r\n");
2173 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2174 *speed = SPEED_1000;
2175 *duplex = FULL_DUPLEX;
2178 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2179 * if it is operating at half duplex. Here we set the duplex settings to
2180 * match the duplex in the link partner's capabilities.
2182 if(hw->phy_type == em_phy_igp && hw->speed_downgraded) {
2183 if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data)))
2186 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2187 *duplex = HALF_DUPLEX;
2189 if((ret_val == em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data)))
2191 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2192 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2193 *duplex = HALF_DUPLEX;
2197 return E1000_SUCCESS;
2200 /******************************************************************************
2201 * Blocks until autoneg completes or times out (~4.5 seconds)
2203 * hw - Struct containing variables accessed by shared code
2204 ******************************************************************************/
2206 em_wait_autoneg(struct em_hw *hw)
2212 DEBUGFUNC("em_wait_autoneg");
2213 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2215 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2216 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2217 /* Read the MII Status Register and wait for Auto-Neg
2218 * Complete bit to be set.
2220 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2222 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2224 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2225 return E1000_SUCCESS;
2229 return E1000_SUCCESS;
2232 /******************************************************************************
2233 * Raises the Management Data Clock
2235 * hw - Struct containing variables accessed by shared code
2236 * ctrl - Device control register's current value
2237 ******************************************************************************/
2239 em_raise_mdi_clk(struct em_hw *hw,
2242 /* Raise the clock input to the Management Data Clock (by setting the MDC
2243 * bit), and then delay 10 microseconds.
2245 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2246 E1000_WRITE_FLUSH(hw);
2250 /******************************************************************************
2251 * Lowers the Management Data Clock
2253 * hw - Struct containing variables accessed by shared code
2254 * ctrl - Device control register's current value
2255 ******************************************************************************/
2257 em_lower_mdi_clk(struct em_hw *hw,
2260 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2261 * bit), and then delay 10 microseconds.
2263 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2264 E1000_WRITE_FLUSH(hw);
2268 /******************************************************************************
2269 * Shifts data bits out to the PHY
2271 * hw - Struct containing variables accessed by shared code
2272 * data - Data to send out to the PHY
2273 * count - Number of bits to shift out
2275 * Bits are shifted out in MSB to LSB order.
2276 ******************************************************************************/
2278 em_shift_out_mdi_bits(struct em_hw *hw,
2285 /* We need to shift "count" number of bits out to the PHY. So, the value
2286 * in the "data" parameter will be shifted out to the PHY one bit at a
2287 * time. In order to do this, "data" must be broken down into bits.
2290 mask <<= (count - 1);
2292 ctrl = E1000_READ_REG(hw, CTRL);
2294 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2295 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2298 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2299 * then raising and lowering the Management Data Clock. A "0" is
2300 * shifted out to the PHY by setting the MDIO bit to "0" and then
2301 * raising and lowering the clock.
2303 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2304 else ctrl &= ~E1000_CTRL_MDIO;
2306 E1000_WRITE_REG(hw, CTRL, ctrl);
2307 E1000_WRITE_FLUSH(hw);
2311 em_raise_mdi_clk(hw, &ctrl);
2312 em_lower_mdi_clk(hw, &ctrl);
2318 /******************************************************************************
2319 * Shifts data bits in from the PHY
2321 * hw - Struct containing variables accessed by shared code
2323 * Bits are shifted in in MSB to LSB order.
2324 ******************************************************************************/
2326 em_shift_in_mdi_bits(struct em_hw *hw)
2332 /* In order to read a register from the PHY, we need to shift in a total
2333 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2334 * to avoid contention on the MDIO pin when a read operation is performed.
2335 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2336 * by raising the input to the Management Data Clock (setting the MDC bit),
2337 * and then reading the value of the MDIO bit.
2339 ctrl = E1000_READ_REG(hw, CTRL);
2341 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2342 ctrl &= ~E1000_CTRL_MDIO_DIR;
2343 ctrl &= ~E1000_CTRL_MDIO;
2345 E1000_WRITE_REG(hw, CTRL, ctrl);
2346 E1000_WRITE_FLUSH(hw);
2348 /* Raise and Lower the clock before reading in the data. This accounts for
2349 * the turnaround bits. The first clock occurred when we clocked out the
2350 * last bit of the Register Address.
2352 em_raise_mdi_clk(hw, &ctrl);
2353 em_lower_mdi_clk(hw, &ctrl);
2355 for(data = 0, i = 0; i < 16; i++) {
2357 em_raise_mdi_clk(hw, &ctrl);
2358 ctrl = E1000_READ_REG(hw, CTRL);
2359 /* Check to see if we shifted in a "1". */
2360 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2361 em_lower_mdi_clk(hw, &ctrl);
2364 em_raise_mdi_clk(hw, &ctrl);
2365 em_lower_mdi_clk(hw, &ctrl);
2370 /*****************************************************************************
2371 * Reads the value from a PHY register, if the value is on a specific non zero
2372 * page, sets the page first.
2373 * hw - Struct containing variables accessed by shared code
2374 * reg_addr - address of the PHY register to read
2375 ******************************************************************************/
2377 em_read_phy_reg(struct em_hw *hw,
2383 DEBUGFUNC("em_read_phy_reg");
2385 if(hw->phy_type == em_phy_igp &&
2386 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2387 if((ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2388 (uint16_t)reg_addr)))
2392 ret_val = em_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2399 em_read_phy_reg_ex(struct em_hw *hw,
2405 const uint32_t phy_addr = 1;
2407 DEBUGFUNC("em_read_phy_reg_ex");
2409 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2410 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2411 return -E1000_ERR_PARAM;
2414 if(hw->mac_type > em_82543) {
2415 /* Set up Op-code, Phy Address, and register address in the MDI
2416 * Control register. The MAC will take care of interfacing with the
2417 * PHY to retrieve the desired data.
2419 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2420 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2421 (E1000_MDIC_OP_READ));
2423 E1000_WRITE_REG(hw, MDIC, mdic);
2425 /* Poll the ready bit to see if the MDI read completed */
2426 for(i = 0; i < 64; i++) {
2428 mdic = E1000_READ_REG(hw, MDIC);
2429 if(mdic & E1000_MDIC_READY) break;
2431 if(!(mdic & E1000_MDIC_READY)) {
2432 DEBUGOUT("MDI Read did not complete\n");
2433 return -E1000_ERR_PHY;
2435 if(mdic & E1000_MDIC_ERROR) {
2436 DEBUGOUT("MDI Error\n");
2437 return -E1000_ERR_PHY;
2439 *phy_data = (uint16_t) mdic;
2441 /* We must first send a preamble through the MDIO pin to signal the
2442 * beginning of an MII instruction. This is done by sending 32
2443 * consecutive "1" bits.
2445 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2447 /* Now combine the next few fields that are required for a read
2448 * operation. We use this method instead of calling the
2449 * em_shift_out_mdi_bits routine five different times. The format of
2450 * a MII read instruction consists of a shift out of 14 bits and is
2451 * defined as follows:
2452 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2453 * followed by a shift in of 18 bits. This first two bits shifted in
2454 * are TurnAround bits used to avoid contention on the MDIO pin when a
2455 * READ operation is performed. These two bits are thrown away
2456 * followed by a shift in of 16 bits which contains the desired data.
2458 mdic = ((reg_addr) | (phy_addr << 5) |
2459 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2461 em_shift_out_mdi_bits(hw, mdic, 14);
2463 /* Now that we've shifted out the read command to the MII, we need to
2464 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2467 *phy_data = em_shift_in_mdi_bits(hw);
2469 return E1000_SUCCESS;
2472 /******************************************************************************
2473 * Writes a value to a PHY register
2475 * hw - Struct containing variables accessed by shared code
2476 * reg_addr - address of the PHY register to write
2477 * data - data to write to the PHY
2478 ******************************************************************************/
2480 em_write_phy_reg(struct em_hw *hw,
2486 DEBUGFUNC("em_write_phy_reg");
2488 if(hw->phy_type == em_phy_igp &&
2489 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2490 if((ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2491 (uint16_t)reg_addr)))
2495 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2502 em_write_phy_reg_ex(struct em_hw *hw,
2508 const uint32_t phy_addr = 1;
2510 DEBUGFUNC("em_write_phy_reg_ex");
2512 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2513 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2514 return -E1000_ERR_PARAM;
2517 if(hw->mac_type > em_82543) {
2518 /* Set up Op-code, Phy Address, register address, and data intended
2519 * for the PHY register in the MDI Control register. The MAC will take
2520 * care of interfacing with the PHY to send the desired data.
2522 mdic = (((uint32_t) phy_data) |
2523 (reg_addr << E1000_MDIC_REG_SHIFT) |
2524 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2525 (E1000_MDIC_OP_WRITE));
2527 E1000_WRITE_REG(hw, MDIC, mdic);
2529 /* Poll the ready bit to see if the MDI read completed */
2530 for(i = 0; i < 640; i++) {
2532 mdic = E1000_READ_REG(hw, MDIC);
2533 if(mdic & E1000_MDIC_READY) break;
2535 if(!(mdic & E1000_MDIC_READY)) {
2536 DEBUGOUT("MDI Write did not complete\n");
2537 return -E1000_ERR_PHY;
2540 /* We'll need to use the SW defined pins to shift the write command
2541 * out to the PHY. We first send a preamble to the PHY to signal the
2542 * beginning of the MII instruction. This is done by sending 32
2543 * consecutive "1" bits.
2545 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2547 /* Now combine the remaining required fields that will indicate a
2548 * write operation. We use this method instead of calling the
2549 * em_shift_out_mdi_bits routine for each field in the command. The
2550 * format of a MII write instruction is as follows:
2551 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2553 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2554 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2556 mdic |= (uint32_t) phy_data;
2558 em_shift_out_mdi_bits(hw, mdic, 32);
2561 return E1000_SUCCESS;
2564 /******************************************************************************
2565 * Returns the PHY to the power-on reset state
2567 * hw - Struct containing variables accessed by shared code
2568 ******************************************************************************/
2570 em_phy_hw_reset(struct em_hw *hw)
2572 uint32_t ctrl, ctrl_ext;
2575 DEBUGFUNC("em_phy_hw_reset");
2577 DEBUGOUT("Resetting Phy...\n");
2579 if(hw->mac_type > em_82543) {
2580 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2581 * bit. Then, take it out of reset.
2583 ctrl = E1000_READ_REG(hw, CTRL);
2584 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2585 E1000_WRITE_FLUSH(hw);
2587 E1000_WRITE_REG(hw, CTRL, ctrl);
2588 E1000_WRITE_FLUSH(hw);
2590 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2591 * bit to put the PHY into reset. Then, take it out of reset.
2593 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2594 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2595 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2596 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2597 E1000_WRITE_FLUSH(hw);
2599 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2600 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2601 E1000_WRITE_FLUSH(hw);
2605 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
2606 /* Configure activity LED after PHY reset */
2607 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2608 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2609 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2610 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2614 /******************************************************************************
2617 * hw - Struct containing variables accessed by shared code
2619 * Sets bit 15 of the MII Control regiser
2620 ******************************************************************************/
2622 em_phy_reset(struct em_hw *hw)
2627 DEBUGFUNC("em_phy_reset");
2629 if(hw->mac_type != em_82541_rev_2) {
2630 if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data)))
2633 phy_data |= MII_CR_RESET;
2634 if((ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data)))
2638 } else em_phy_hw_reset(hw);
2640 if(hw->phy_type == em_phy_igp)
2641 em_phy_init_script(hw);
2643 return E1000_SUCCESS;
2646 /******************************************************************************
2647 * Probes the expected PHY address for known PHY IDs
2649 * hw - Struct containing variables accessed by shared code
2650 ******************************************************************************/
2652 em_detect_gig_phy(struct em_hw *hw)
2654 int32_t phy_init_status, ret_val;
2655 uint16_t phy_id_high, phy_id_low;
2656 boolean_t match = FALSE;
2658 DEBUGFUNC("em_detect_gig_phy");
2660 /* Read the PHY ID Registers to identify which PHY is onboard. */
2661 if((ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
2664 hw->phy_id = (uint32_t) (phy_id_high << 16);
2666 if((ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
2669 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2670 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2672 switch(hw->mac_type) {
2674 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2677 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2681 case em_82545_rev_3:
2683 case em_82546_rev_3:
2684 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2687 case em_82541_rev_2:
2689 case em_82547_rev_2:
2690 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2693 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2694 return -E1000_ERR_CONFIG;
2696 phy_init_status = em_set_phy_type(hw);
2698 if ((match) && (phy_init_status == E1000_SUCCESS)) {
2699 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2700 return E1000_SUCCESS;
2702 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2703 return -E1000_ERR_PHY;
2706 /******************************************************************************
2707 * Resets the PHY's DSP
2709 * hw - Struct containing variables accessed by shared code
2710 ******************************************************************************/
2712 em_phy_reset_dsp(struct em_hw *hw)
2715 DEBUGFUNC("em_phy_reset_dsp");
2718 if((ret_val = em_write_phy_reg(hw, 29, 0x001d))) break;
2719 if((ret_val = em_write_phy_reg(hw, 30, 0x00c1))) break;
2720 if((ret_val = em_write_phy_reg(hw, 30, 0x0000))) break;
2721 ret_val = E1000_SUCCESS;
2727 /******************************************************************************
2728 * Get PHY information from various PHY registers for igp PHY only.
2730 * hw - Struct containing variables accessed by shared code
2731 * phy_info - PHY information structure
2732 ******************************************************************************/
2734 em_phy_igp_get_info(struct em_hw *hw,
2735 struct em_phy_info *phy_info)
2738 uint16_t phy_data, polarity, min_length, max_length, average;
2740 DEBUGFUNC("em_phy_igp_get_info");
2742 /* The downshift status is checked only once, after link is established,
2743 * and it stored in the hw->speed_downgraded parameter. */
2744 phy_info->downshift = hw->speed_downgraded;
2746 /* IGP01E1000 does not need to support it. */
2747 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_normal;
2749 /* IGP01E1000 always correct polarity reversal */
2750 phy_info->polarity_correction = em_polarity_reversal_enabled;
2752 /* Check polarity status */
2753 if((ret_val = em_check_polarity(hw, &polarity)))
2756 phy_info->cable_polarity = polarity;
2758 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
2762 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
2763 IGP01E1000_PSSR_MDIX_SHIFT;
2765 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2766 IGP01E1000_PSSR_SPEED_1000MBPS) {
2767 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
2768 if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
2771 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2772 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2773 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2774 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2776 /* Get cable length */
2777 if((ret_val = em_get_cable_length(hw, &min_length, &max_length)))
2780 /* transalte to old method */
2781 average = (max_length + min_length) / 2;
2783 if(average <= em_igp_cable_length_50)
2784 phy_info->cable_length = em_cable_length_50;
2785 else if(average <= em_igp_cable_length_80)
2786 phy_info->cable_length = em_cable_length_50_80;
2787 else if(average <= em_igp_cable_length_110)
2788 phy_info->cable_length = em_cable_length_80_110;
2789 else if(average <= em_igp_cable_length_140)
2790 phy_info->cable_length = em_cable_length_110_140;
2792 phy_info->cable_length = em_cable_length_140;
2795 return E1000_SUCCESS;
2798 /******************************************************************************
2799 * Get PHY information from various PHY registers fot m88 PHY only.
2801 * hw - Struct containing variables accessed by shared code
2802 * phy_info - PHY information structure
2803 ******************************************************************************/
2805 em_phy_m88_get_info(struct em_hw *hw,
2806 struct em_phy_info *phy_info)
2809 uint16_t phy_data, polarity;
2811 DEBUGFUNC("em_phy_m88_get_info");
2813 /* The downshift status is checked only once, after link is established,
2814 * and it stored in the hw->speed_downgraded parameter. */
2815 phy_info->downshift = hw->speed_downgraded;
2817 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data)))
2820 phy_info->extended_10bt_distance =
2821 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
2822 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
2823 phy_info->polarity_correction =
2824 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
2825 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
2827 /* Check polarity status */
2828 if((ret_val = em_check_polarity(hw, &polarity)))
2831 phy_info->cable_polarity = polarity;
2833 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data)))
2836 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
2837 M88E1000_PSSR_MDIX_SHIFT;
2839 if(phy_data & M88E1000_PSSR_1000MBS) {
2840 /* Cable Length Estimation and Local/Remote Receiver Informatoion
2841 * are only valid at 1000 Mbps
2843 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2844 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2846 if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
2849 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2850 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2852 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2853 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2856 return E1000_SUCCESS;
2859 /******************************************************************************
2860 * Get PHY information from various PHY registers
2862 * hw - Struct containing variables accessed by shared code
2863 * phy_info - PHY information structure
2864 ******************************************************************************/
2866 em_phy_get_info(struct em_hw *hw,
2867 struct em_phy_info *phy_info)
2872 DEBUGFUNC("em_phy_get_info");
2874 phy_info->cable_length = em_cable_length_undefined;
2875 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_undefined;
2876 phy_info->cable_polarity = em_rev_polarity_undefined;
2877 phy_info->downshift = em_downshift_undefined;
2878 phy_info->polarity_correction = em_polarity_reversal_undefined;
2879 phy_info->mdix_mode = em_auto_x_mode_undefined;
2880 phy_info->local_rx = em_1000t_rx_status_undefined;
2881 phy_info->remote_rx = em_1000t_rx_status_undefined;
2883 if(hw->media_type != em_media_type_copper) {
2884 DEBUGOUT("PHY info is only valid for copper media\n");
2885 return -E1000_ERR_CONFIG;
2888 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2891 if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2894 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
2895 DEBUGOUT("PHY info is only valid if link is up\n");
2896 return -E1000_ERR_CONFIG;
2899 if(hw->phy_type == em_phy_igp)
2900 return em_phy_igp_get_info(hw, phy_info);
2902 return em_phy_m88_get_info(hw, phy_info);
2906 em_validate_mdi_setting(struct em_hw *hw)
2908 DEBUGFUNC("em_validate_mdi_settings");
2910 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
2911 DEBUGOUT("Invalid MDI setting detected\n");
2913 return -E1000_ERR_CONFIG;
2915 return E1000_SUCCESS;
2919 /******************************************************************************
2920 * Sets up eeprom variables in the hw struct. Must be called after mac_type
2923 * hw - Struct containing variables accessed by shared code
2924 *****************************************************************************/
2926 em_init_eeprom_params(struct em_hw *hw)
2928 struct em_eeprom_info *eeprom = &hw->eeprom;
2929 uint32_t eecd = E1000_READ_REG(hw, EECD);
2930 uint16_t eeprom_size;
2932 DEBUGFUNC("em_init_eeprom_params");
2934 switch (hw->mac_type) {
2935 case em_82542_rev2_0:
2936 case em_82542_rev2_1:
2939 eeprom->type = em_eeprom_microwire;
2940 eeprom->word_size = 64;
2941 eeprom->opcode_bits = 3;
2942 eeprom->address_bits = 6;
2943 eeprom->delay_usec = 50;
2947 case em_82545_rev_3:
2949 case em_82546_rev_3:
2950 eeprom->type = em_eeprom_microwire;
2951 eeprom->opcode_bits = 3;
2952 eeprom->delay_usec = 50;
2953 if(eecd & E1000_EECD_SIZE) {
2954 eeprom->word_size = 256;
2955 eeprom->address_bits = 8;
2957 eeprom->word_size = 64;
2958 eeprom->address_bits = 6;
2962 case em_82541_rev_2:
2964 case em_82547_rev_2:
2965 if (eecd & E1000_EECD_TYPE) {
2966 eeprom->type = em_eeprom_spi;
2967 eeprom->opcode_bits = 8;
2968 eeprom->delay_usec = 1;
2969 if (eecd & E1000_EECD_ADDR_BITS) {
2970 eeprom->page_size = 32;
2971 eeprom->address_bits = 16;
2973 eeprom->page_size = 8;
2974 eeprom->address_bits = 8;
2977 eeprom->type = em_eeprom_microwire;
2978 eeprom->opcode_bits = 3;
2979 eeprom->delay_usec = 50;
2980 if (eecd & E1000_EECD_ADDR_BITS) {
2981 eeprom->word_size = 256;
2982 eeprom->address_bits = 8;
2984 eeprom->word_size = 64;
2985 eeprom->address_bits = 6;
2990 eeprom->type = em_eeprom_spi;
2991 eeprom->opcode_bits = 8;
2992 eeprom->delay_usec = 1;
2993 if (eecd & E1000_EECD_ADDR_BITS) {
2994 eeprom->page_size = 32;
2995 eeprom->address_bits = 16;
2997 eeprom->page_size = 8;
2998 eeprom->address_bits = 8;
3003 if (eeprom->type == em_eeprom_spi) {
3004 eeprom->word_size = 64;
3005 if (em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3006 eeprom_size &= EEPROM_SIZE_MASK;
3008 switch (eeprom_size) {
3009 case EEPROM_SIZE_16KB:
3010 eeprom->word_size = 8192;
3012 case EEPROM_SIZE_8KB:
3013 eeprom->word_size = 4096;
3015 case EEPROM_SIZE_4KB:
3016 eeprom->word_size = 2048;
3018 case EEPROM_SIZE_2KB:
3019 eeprom->word_size = 1024;
3021 case EEPROM_SIZE_1KB:
3022 eeprom->word_size = 512;
3024 case EEPROM_SIZE_512B:
3025 eeprom->word_size = 256;
3027 case EEPROM_SIZE_128B:
3029 eeprom->word_size = 64;
3036 /******************************************************************************
3037 * Raises the EEPROM's clock input.
3039 * hw - Struct containing variables accessed by shared code
3040 * eecd - EECD's current value
3041 *****************************************************************************/
3043 em_raise_ee_clk(struct em_hw *hw,
3046 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3047 * wait <delay> microseconds.
3049 *eecd = *eecd | E1000_EECD_SK;
3050 E1000_WRITE_REG(hw, EECD, *eecd);
3051 E1000_WRITE_FLUSH(hw);
3052 usec_delay(hw->eeprom.delay_usec);
3055 /******************************************************************************
3056 * Lowers the EEPROM's clock input.
3058 * hw - Struct containing variables accessed by shared code
3059 * eecd - EECD's current value
3060 *****************************************************************************/
3062 em_lower_ee_clk(struct em_hw *hw,
3065 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3066 * wait 50 microseconds.
3068 *eecd = *eecd & ~E1000_EECD_SK;
3069 E1000_WRITE_REG(hw, EECD, *eecd);
3070 E1000_WRITE_FLUSH(hw);
3071 usec_delay(hw->eeprom.delay_usec);
3074 /******************************************************************************
3075 * Shift data bits out to the EEPROM.
3077 * hw - Struct containing variables accessed by shared code
3078 * data - data to send to the EEPROM
3079 * count - number of bits to shift out
3080 *****************************************************************************/
3082 em_shift_out_ee_bits(struct em_hw *hw,
3086 struct em_eeprom_info *eeprom = &hw->eeprom;
3090 /* We need to shift "count" bits out to the EEPROM. So, value in the
3091 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3092 * In order to do this, "data" must be broken down into bits.
3094 mask = 0x01 << (count - 1);
3095 eecd = E1000_READ_REG(hw, EECD);
3096 if (eeprom->type == em_eeprom_microwire) {
3097 eecd &= ~E1000_EECD_DO;
3098 } else if (eeprom->type == em_eeprom_spi) {
3099 eecd |= E1000_EECD_DO;
3102 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3103 * and then raising and then lowering the clock (the SK bit controls
3104 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3105 * by setting "DI" to "0" and then raising and then lowering the clock.
3107 eecd &= ~E1000_EECD_DI;
3110 eecd |= E1000_EECD_DI;
3112 E1000_WRITE_REG(hw, EECD, eecd);
3113 E1000_WRITE_FLUSH(hw);
3115 usec_delay(eeprom->delay_usec);
3117 em_raise_ee_clk(hw, &eecd);
3118 em_lower_ee_clk(hw, &eecd);
3124 /* We leave the "DI" bit set to "0" when we leave this routine. */
3125 eecd &= ~E1000_EECD_DI;
3126 E1000_WRITE_REG(hw, EECD, eecd);
3129 /******************************************************************************
3130 * Shift data bits in from the EEPROM
3132 * hw - Struct containing variables accessed by shared code
3133 *****************************************************************************/
3135 em_shift_in_ee_bits(struct em_hw *hw,
3142 /* In order to read a register from the EEPROM, we need to shift 'count'
3143 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3144 * input to the EEPROM (setting the SK bit), and then reading the value of
3145 * the "DO" bit. During this "shifting in" process the "DI" bit should
3149 eecd = E1000_READ_REG(hw, EECD);
3151 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3154 for(i = 0; i < count; i++) {
3156 em_raise_ee_clk(hw, &eecd);
3158 eecd = E1000_READ_REG(hw, EECD);
3160 eecd &= ~(E1000_EECD_DI);
3161 if(eecd & E1000_EECD_DO)
3164 em_lower_ee_clk(hw, &eecd);
3170 /******************************************************************************
3171 * Prepares EEPROM for access
3173 * hw - Struct containing variables accessed by shared code
3175 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3176 * function should be called before issuing a command to the EEPROM.
3177 *****************************************************************************/
3179 em_acquire_eeprom(struct em_hw *hw)
3181 struct em_eeprom_info *eeprom = &hw->eeprom;
3184 DEBUGFUNC("em_acquire_eeprom");
3186 eecd = E1000_READ_REG(hw, EECD);
3188 /* Request EEPROM Access */
3189 if(hw->mac_type > em_82544) {
3190 eecd |= E1000_EECD_REQ;
3191 E1000_WRITE_REG(hw, EECD, eecd);
3192 eecd = E1000_READ_REG(hw, EECD);
3193 while((!(eecd & E1000_EECD_GNT)) &&
3194 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3197 eecd = E1000_READ_REG(hw, EECD);
3199 if(!(eecd & E1000_EECD_GNT)) {
3200 eecd &= ~E1000_EECD_REQ;
3201 E1000_WRITE_REG(hw, EECD, eecd);
3202 DEBUGOUT("Could not acquire EEPROM grant\n");
3203 return -E1000_ERR_EEPROM;
3207 /* Setup EEPROM for Read/Write */
3209 if (eeprom->type == em_eeprom_microwire) {
3210 /* Clear SK and DI */
3211 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3212 E1000_WRITE_REG(hw, EECD, eecd);
3215 eecd |= E1000_EECD_CS;
3216 E1000_WRITE_REG(hw, EECD, eecd);
3217 } else if (eeprom->type == em_eeprom_spi) {
3218 /* Clear SK and CS */
3219 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3220 E1000_WRITE_REG(hw, EECD, eecd);
3224 return E1000_SUCCESS;
3227 /******************************************************************************
3228 * Returns EEPROM to a "standby" state
3230 * hw - Struct containing variables accessed by shared code
3231 *****************************************************************************/
3233 em_standby_eeprom(struct em_hw *hw)
3235 struct em_eeprom_info *eeprom = &hw->eeprom;
3238 eecd = E1000_READ_REG(hw, EECD);
3240 if(eeprom->type == em_eeprom_microwire) {
3241 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3242 E1000_WRITE_REG(hw, EECD, eecd);
3243 E1000_WRITE_FLUSH(hw);
3244 usec_delay(eeprom->delay_usec);
3247 eecd |= E1000_EECD_SK;
3248 E1000_WRITE_REG(hw, EECD, eecd);
3249 E1000_WRITE_FLUSH(hw);
3250 usec_delay(eeprom->delay_usec);
3253 eecd |= E1000_EECD_CS;
3254 E1000_WRITE_REG(hw, EECD, eecd);
3255 E1000_WRITE_FLUSH(hw);
3256 usec_delay(eeprom->delay_usec);
3259 eecd &= ~E1000_EECD_SK;
3260 E1000_WRITE_REG(hw, EECD, eecd);
3261 E1000_WRITE_FLUSH(hw);
3262 usec_delay(eeprom->delay_usec);
3263 } else if(eeprom->type == em_eeprom_spi) {
3264 /* Toggle CS to flush commands */
3265 eecd |= E1000_EECD_CS;
3266 E1000_WRITE_REG(hw, EECD, eecd);
3267 E1000_WRITE_FLUSH(hw);
3268 usec_delay(eeprom->delay_usec);
3269 eecd &= ~E1000_EECD_CS;
3270 E1000_WRITE_REG(hw, EECD, eecd);
3271 E1000_WRITE_FLUSH(hw);
3272 usec_delay(eeprom->delay_usec);
3276 /******************************************************************************
3277 * Terminates a command by inverting the EEPROM's chip select pin
3279 * hw - Struct containing variables accessed by shared code
3280 *****************************************************************************/
3282 em_release_eeprom(struct em_hw *hw)
3286 DEBUGFUNC("em_release_eeprom");
3288 eecd = E1000_READ_REG(hw, EECD);
3290 if (hw->eeprom.type == em_eeprom_spi) {
3291 eecd |= E1000_EECD_CS; /* Pull CS high */
3292 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3294 E1000_WRITE_REG(hw, EECD, eecd);
3296 usec_delay(hw->eeprom.delay_usec);
3297 } else if(hw->eeprom.type == em_eeprom_microwire) {
3298 /* cleanup eeprom */
3300 /* CS on Microwire is active-high */
3301 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3303 E1000_WRITE_REG(hw, EECD, eecd);
3305 /* Rising edge of clock */
3306 eecd |= E1000_EECD_SK;
3307 E1000_WRITE_REG(hw, EECD, eecd);
3308 E1000_WRITE_FLUSH(hw);
3309 usec_delay(hw->eeprom.delay_usec);
3311 /* Falling edge of clock */
3312 eecd &= ~E1000_EECD_SK;
3313 E1000_WRITE_REG(hw, EECD, eecd);
3314 E1000_WRITE_FLUSH(hw);
3315 usec_delay(hw->eeprom.delay_usec);
3318 /* Stop requesting EEPROM access */
3319 if(hw->mac_type > em_82544) {
3320 eecd &= ~E1000_EECD_REQ;
3321 E1000_WRITE_REG(hw, EECD, eecd);
3325 /******************************************************************************
3326 * Reads a 16 bit word from the EEPROM.
3328 * hw - Struct containing variables accessed by shared code
3329 *****************************************************************************/
3331 em_spi_eeprom_ready(struct em_hw *hw)
3333 uint16_t retry_count = 0;
3334 uint8_t spi_stat_reg;
3336 DEBUGFUNC("em_spi_eeprom_ready");
3338 /* Read "Status Register" repeatedly until the LSB is cleared. The
3339 * EEPROM will signal that the command has been completed by clearing
3340 * bit 0 of the internal status register. If it's not cleared within
3341 * 5 milliseconds, then error out.
3345 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3346 hw->eeprom.opcode_bits);
3347 spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8);
3348 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3354 } while(retry_count < EEPROM_MAX_RETRY_SPI);
3356 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3357 * only 0-5mSec on 5V devices)
3359 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3360 DEBUGOUT("SPI EEPROM Status error\n");
3361 return -E1000_ERR_EEPROM;
3364 return E1000_SUCCESS;
3367 /******************************************************************************
3368 * Reads a 16 bit word from the EEPROM.
3370 * hw - Struct containing variables accessed by shared code
3371 * offset - offset of word in the EEPROM to read
3372 * data - word read from the EEPROM
3373 * words - number of words to read
3374 *****************************************************************************/
3376 em_read_eeprom(struct em_hw *hw,
3381 struct em_eeprom_info *eeprom = &hw->eeprom;
3384 DEBUGFUNC("em_read_eeprom");
3386 /* A check for invalid values: offset too large, too many words, and not
3389 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3391 DEBUGOUT("\"words\" parameter out of bounds\n");
3392 return -E1000_ERR_EEPROM;
3395 /* Prepare the EEPROM for reading */
3396 if(em_acquire_eeprom(hw) != E1000_SUCCESS)
3397 return -E1000_ERR_EEPROM;
3399 if(eeprom->type == em_eeprom_spi) {
3401 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3403 if(em_spi_eeprom_ready(hw)) {
3404 em_release_eeprom(hw);
3405 return -E1000_ERR_EEPROM;
3408 em_standby_eeprom(hw);
3410 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3411 if((eeprom->address_bits == 8) && (offset >= 128))
3412 read_opcode |= EEPROM_A8_OPCODE_SPI;
3414 /* Send the READ command (opcode + addr) */
3415 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3416 em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3418 /* Read the data. The address of the eeprom internally increments with
3419 * each byte (spi) being read, saving on the overhead of eeprom setup
3420 * and tear-down. The address counter will roll over if reading beyond
3421 * the size of the eeprom, thus allowing the entire memory to be read
3422 * starting from any offset. */
3423 for (i = 0; i < words; i++) {
3424 word_in = em_shift_in_ee_bits(hw, 16);
3425 data[i] = (word_in >> 8) | (word_in << 8);
3427 } else if(eeprom->type == em_eeprom_microwire) {
3428 for (i = 0; i < words; i++) {
3429 /* Send the READ command (opcode + addr) */
3430 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3431 eeprom->opcode_bits);
3432 em_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3433 eeprom->address_bits);
3435 /* Read the data. For microwire, each word requires the overhead
3436 * of eeprom setup and tear-down. */
3437 data[i] = em_shift_in_ee_bits(hw, 16);
3438 em_standby_eeprom(hw);
3442 /* End this read operation */
3443 em_release_eeprom(hw);
3445 return E1000_SUCCESS;
3448 /******************************************************************************
3449 * Verifies that the EEPROM has a valid checksum
3451 * hw - Struct containing variables accessed by shared code
3453 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3454 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3456 *****************************************************************************/
3458 em_validate_eeprom_checksum(struct em_hw *hw)
3460 uint16_t checksum = 0;
3461 uint16_t i, eeprom_data;
3463 DEBUGFUNC("em_validate_eeprom_checksum");
3465 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3466 if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3467 DEBUGOUT("EEPROM Read Error\n");
3468 return -E1000_ERR_EEPROM;
3470 checksum += eeprom_data;
3473 if(checksum == (uint16_t) EEPROM_SUM)
3474 return E1000_SUCCESS;
3476 DEBUGOUT("EEPROM Checksum Invalid\n");
3477 return -E1000_ERR_EEPROM;
3481 /******************************************************************************
3482 * Calculates the EEPROM checksum and writes it to the EEPROM
3484 * hw - Struct containing variables accessed by shared code
3486 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3487 * Writes the difference to word offset 63 of the EEPROM.
3488 *****************************************************************************/
3490 em_update_eeprom_checksum(struct em_hw *hw)
3492 uint16_t checksum = 0;
3493 uint16_t i, eeprom_data;
3495 DEBUGFUNC("em_update_eeprom_checksum");
3497 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3498 if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3499 DEBUGOUT("EEPROM Read Error\n");
3500 return -E1000_ERR_EEPROM;
3502 checksum += eeprom_data;
3504 checksum = (uint16_t) EEPROM_SUM - checksum;
3505 if(em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3506 DEBUGOUT("EEPROM Write Error\n");
3507 return -E1000_ERR_EEPROM;
3509 return E1000_SUCCESS;
3512 /******************************************************************************
3513 * Parent function for writing words to the different EEPROM types.
3515 * hw - Struct containing variables accessed by shared code
3516 * offset - offset within the EEPROM to be written to
3517 * words - number of words to write
3518 * data - 16 bit word to be written to the EEPROM
3520 * If em_update_eeprom_checksum is not called after this function, the
3521 * EEPROM will most likely contain an invalid checksum.
3522 *****************************************************************************/
3524 em_write_eeprom(struct em_hw *hw,
3529 struct em_eeprom_info *eeprom = &hw->eeprom;
3532 DEBUGFUNC("em_write_eeprom");
3534 /* A check for invalid values: offset too large, too many words, and not
3537 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3539 DEBUGOUT("\"words\" parameter out of bounds\n");
3540 return -E1000_ERR_EEPROM;
3543 /* Prepare the EEPROM for writing */
3544 if (em_acquire_eeprom(hw) != E1000_SUCCESS)
3545 return -E1000_ERR_EEPROM;
3547 if(eeprom->type == em_eeprom_microwire) {
3548 status = em_write_eeprom_microwire(hw, offset, words, data);
3550 status = em_write_eeprom_spi(hw, offset, words, data);
3554 /* Done with writing */
3555 em_release_eeprom(hw);
3560 /******************************************************************************
3561 * Writes a 16 bit word to a given offset in an SPI EEPROM.
3563 * hw - Struct containing variables accessed by shared code
3564 * offset - offset within the EEPROM to be written to
3565 * words - number of words to write
3566 * data - pointer to array of 8 bit words to be written to the EEPROM
3568 *****************************************************************************/
3570 em_write_eeprom_spi(struct em_hw *hw,
3575 struct em_eeprom_info *eeprom = &hw->eeprom;
3578 DEBUGFUNC("em_write_eeprom_spi");
3580 while (widx < words) {
3581 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
3583 if(em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
3585 em_standby_eeprom(hw);
3587 /* Send the WRITE ENABLE command (8 bit opcode ) */
3588 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
3589 eeprom->opcode_bits);
3591 em_standby_eeprom(hw);
3593 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3594 if((eeprom->address_bits == 8) && (offset >= 128))
3595 write_opcode |= EEPROM_A8_OPCODE_SPI;
3597 /* Send the Write command (8-bit opcode + addr) */
3598 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
3600 em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
3601 eeprom->address_bits);
3605 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
3606 while (widx < words) {
3607 uint16_t word_out = data[widx];
3608 word_out = (word_out >> 8) | (word_out << 8);
3609 em_shift_out_ee_bits(hw, word_out, 16);
3612 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
3613 * operation, while the smaller eeproms are capable of an 8-byte
3614 * PAGE WRITE operation. Break the inner loop to pass new address
3616 if((((offset + widx)*2) % eeprom->page_size) == 0) {
3617 em_standby_eeprom(hw);
3623 return E1000_SUCCESS;
3626 /******************************************************************************
3627 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
3629 * hw - Struct containing variables accessed by shared code
3630 * offset - offset within the EEPROM to be written to
3631 * words - number of words to write
3632 * data - pointer to array of 16 bit words to be written to the EEPROM
3634 *****************************************************************************/
3636 em_write_eeprom_microwire(struct em_hw *hw,
3641 struct em_eeprom_info *eeprom = &hw->eeprom;
3643 uint16_t words_written = 0;
3646 DEBUGFUNC("em_write_eeprom_microwire");
3648 /* Send the write enable command to the EEPROM (3-bit opcode plus
3649 * 6/8-bit dummy address beginning with 11). It's less work to include
3650 * the 11 of the dummy address as part of the opcode than it is to shift
3651 * it over the correct number of bits for the address. This puts the
3652 * EEPROM into write/erase mode.
3654 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
3655 (uint16_t)(eeprom->opcode_bits + 2));
3657 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3659 /* Prepare the EEPROM */
3660 em_standby_eeprom(hw);
3662 while (words_written < words) {
3663 /* Send the Write command (3-bit opcode + addr) */
3664 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
3665 eeprom->opcode_bits);
3667 em_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
3668 eeprom->address_bits);
3671 em_shift_out_ee_bits(hw, data[words_written], 16);
3673 /* Toggle the CS line. This in effect tells the EEPROM to execute
3674 * the previous command.
3676 em_standby_eeprom(hw);
3678 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
3679 * signal that the command has been completed by raising the DO signal.
3680 * If DO does not go high in 10 milliseconds, then error out.
3682 for(i = 0; i < 200; i++) {
3683 eecd = E1000_READ_REG(hw, EECD);
3684 if(eecd & E1000_EECD_DO) break;
3688 DEBUGOUT("EEPROM Write did not complete\n");
3689 return -E1000_ERR_EEPROM;
3692 /* Recover from write */
3693 em_standby_eeprom(hw);
3698 /* Send the write disable command to the EEPROM (3-bit opcode plus
3699 * 6/8-bit dummy address beginning with 10). It's less work to include
3700 * the 10 of the dummy address as part of the opcode than it is to shift
3701 * it over the correct number of bits for the address. This takes the
3702 * EEPROM out of write/erase mode.
3704 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
3705 (uint16_t)(eeprom->opcode_bits + 2));
3707 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3709 return E1000_SUCCESS;
3712 /******************************************************************************
3713 * Reads the adapter's part number from the EEPROM
3715 * hw - Struct containing variables accessed by shared code
3716 * part_num - Adapter's part number
3717 *****************************************************************************/
3719 em_read_part_num(struct em_hw *hw,
3722 uint16_t offset = EEPROM_PBA_BYTE_1;
3723 uint16_t eeprom_data;
3725 DEBUGFUNC("em_read_part_num");
3727 /* Get word 0 from EEPROM */
3728 if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3729 DEBUGOUT("EEPROM Read Error\n");
3730 return -E1000_ERR_EEPROM;
3732 /* Save word 0 in upper half of part_num */
3733 *part_num = (uint32_t) (eeprom_data << 16);
3735 /* Get word 1 from EEPROM */
3736 if(em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
3737 DEBUGOUT("EEPROM Read Error\n");
3738 return -E1000_ERR_EEPROM;
3740 /* Save word 1 in lower half of part_num */
3741 *part_num |= eeprom_data;
3743 return E1000_SUCCESS;
3746 /******************************************************************************
3747 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
3748 * second function of dual function devices
3750 * hw - Struct containing variables accessed by shared code
3751 *****************************************************************************/
3753 em_read_mac_addr(struct em_hw * hw)
3756 uint16_t eeprom_data, i;
3758 DEBUGFUNC("em_read_mac_addr");
3760 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3762 if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3763 DEBUGOUT("EEPROM Read Error\n");
3764 return -E1000_ERR_EEPROM;
3766 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
3767 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
3769 if(((hw->mac_type == em_82546) || (hw->mac_type == em_82546_rev_3)) &&
3770 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
3771 hw->perm_mac_addr[5] ^= 0x01;
3773 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
3774 hw->mac_addr[i] = hw->perm_mac_addr[i];
3775 return E1000_SUCCESS;
3778 /******************************************************************************
3779 * Initializes receive address filters.
3781 * hw - Struct containing variables accessed by shared code
3783 * Places the MAC address in receive address register 0 and clears the rest
3784 * of the receive addresss registers. Clears the multicast table. Assumes
3785 * the receiver is in reset when the routine is called.
3786 *****************************************************************************/
3788 em_init_rx_addrs(struct em_hw *hw)
3792 DEBUGFUNC("em_init_rx_addrs");
3794 /* Setup the receive address. */
3795 DEBUGOUT("Programming MAC Address into RAR[0]\n");
3797 em_rar_set(hw, hw->mac_addr, 0);
3799 /* Zero out the other 15 receive addresses. */
3800 DEBUGOUT("Clearing RAR[1-15]\n");
3801 for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3802 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3803 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3807 /******************************************************************************
3808 * Updates the MAC's list of multicast addresses.
3810 * hw - Struct containing variables accessed by shared code
3811 * mc_addr_list - the list of new multicast addresses
3812 * mc_addr_count - number of addresses
3813 * pad - number of bytes between addresses in the list
3814 * rar_used_count - offset where to start adding mc addresses into the RAR's
3816 * The given list replaces any existing list. Clears the last 15 receive
3817 * address registers and the multicast table. Uses receive address registers
3818 * for the first 15 multicast addresses, and hashes the rest into the
3820 *****************************************************************************/
3822 em_mc_addr_list_update(struct em_hw *hw,
3823 uint8_t *mc_addr_list,
3824 uint32_t mc_addr_count,
3826 uint32_t rar_used_count)
3828 uint32_t hash_value;
3831 DEBUGFUNC("em_mc_addr_list_update");
3833 /* Set the new number of MC addresses that we are being requested to use. */
3834 hw->num_mc_addrs = mc_addr_count;
3836 /* Clear RAR[1-15] */
3837 DEBUGOUT(" Clearing RAR[1-15]\n");
3838 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
3839 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3840 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3844 DEBUGOUT(" Clearing MTA\n");
3845 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
3846 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3849 /* Add the new addresses */
3850 for(i = 0; i < mc_addr_count; i++) {
3851 DEBUGOUT(" Adding the multicast addresses:\n");
3852 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
3853 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
3854 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
3855 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
3856 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
3857 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
3858 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
3860 hash_value = em_hash_mc_addr(hw,
3862 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
3864 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
3866 /* Place this multicast address in the RAR if there is room, *
3867 * else put it in the MTA
3869 if(rar_used_count < E1000_RAR_ENTRIES) {
3871 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3875 em_mta_set(hw, hash_value);
3878 DEBUGOUT("MC Update Complete\n");
3881 /******************************************************************************
3882 * Hashes an address to determine its location in the multicast table
3884 * hw - Struct containing variables accessed by shared code
3885 * mc_addr - the multicast address to hash
3886 *****************************************************************************/
3888 em_hash_mc_addr(struct em_hw *hw,
3891 uint32_t hash_value = 0;
3893 /* The portion of the address that is used for the hash table is
3894 * determined by the mc_filter_type setting.
3896 switch (hw->mc_filter_type) {
3897 /* [0] [1] [2] [3] [4] [5]
3902 /* [47:36] i.e. 0x563 for above example address */
3903 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
3906 /* [46:35] i.e. 0xAC6 for above example address */
3907 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
3910 /* [45:34] i.e. 0x5D8 for above example address */
3911 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
3914 /* [43:32] i.e. 0x634 for above example address */
3915 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
3919 hash_value &= 0xFFF;
3923 /******************************************************************************
3924 * Sets the bit in the multicast table corresponding to the hash value.
3926 * hw - Struct containing variables accessed by shared code
3927 * hash_value - Multicast address hash value
3928 *****************************************************************************/
3930 em_mta_set(struct em_hw *hw,
3931 uint32_t hash_value)
3933 uint32_t hash_bit, hash_reg;
3937 /* The MTA is a register array of 128 32-bit registers.
3938 * It is treated like an array of 4096 bits. We want to set
3939 * bit BitArray[hash_value]. So we figure out what register
3940 * the bit is in, read it, OR in the new bit, then write
3941 * back the new value. The register is determined by the
3942 * upper 7 bits of the hash value and the bit within that
3943 * register are determined by the lower 5 bits of the value.
3945 hash_reg = (hash_value >> 5) & 0x7F;
3946 hash_bit = hash_value & 0x1F;
3948 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
3950 mta |= (1 << hash_bit);
3952 /* If we are on an 82544 and we are trying to write an odd offset
3953 * in the MTA, save off the previous entry before writing and
3954 * restore the old value after writing.
3956 if((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
3957 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
3958 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
3959 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
3961 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
3965 /******************************************************************************
3966 * Puts an ethernet address into a receive address register.
3968 * hw - Struct containing variables accessed by shared code
3969 * addr - Address to put into receive address register
3970 * index - Receive address register to write
3971 *****************************************************************************/
3973 em_rar_set(struct em_hw *hw,
3977 uint32_t rar_low, rar_high;
3979 /* HW expects these in little endian so we reverse the byte order
3980 * from network order (big endian) to little endian
3982 rar_low = ((uint32_t) addr[0] |
3983 ((uint32_t) addr[1] << 8) |
3984 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
3986 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
3988 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
3989 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
3992 /******************************************************************************
3993 * Writes a value to the specified offset in the VLAN filter table.
3995 * hw - Struct containing variables accessed by shared code
3996 * offset - Offset in VLAN filer table to write
3997 * value - Value to write into VLAN filter table
3998 *****************************************************************************/
4000 em_write_vfta(struct em_hw *hw,
4006 if((hw->mac_type == em_82544) && ((offset & 0x1) == 1)) {
4007 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4008 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4009 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4011 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4015 /******************************************************************************
4016 * Clears the VLAN filer table
4018 * hw - Struct containing variables accessed by shared code
4019 *****************************************************************************/
4021 em_clear_vfta(struct em_hw *hw)
4025 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
4026 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
4030 em_id_led_init(struct em_hw * hw)
4033 const uint32_t ledctl_mask = 0x000000FF;
4034 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4035 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4036 uint16_t eeprom_data, i, temp;
4037 const uint16_t led_mask = 0x0F;
4039 DEBUGFUNC("em_id_led_init");
4041 if(hw->mac_type < em_82540) {
4043 return E1000_SUCCESS;
4046 ledctl = E1000_READ_REG(hw, LEDCTL);
4047 hw->ledctl_default = ledctl;
4048 hw->ledctl_mode1 = hw->ledctl_default;
4049 hw->ledctl_mode2 = hw->ledctl_default;
4051 if(em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4052 DEBUGOUT("EEPROM Read Error\n");
4053 return -E1000_ERR_EEPROM;
4055 if((eeprom_data== ID_LED_RESERVED_0000) ||
4056 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
4057 for(i = 0; i < 4; i++) {
4058 temp = (eeprom_data >> (i << 2)) & led_mask;
4060 case ID_LED_ON1_DEF2:
4061 case ID_LED_ON1_ON2:
4062 case ID_LED_ON1_OFF2:
4063 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4064 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4066 case ID_LED_OFF1_DEF2:
4067 case ID_LED_OFF1_ON2:
4068 case ID_LED_OFF1_OFF2:
4069 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4070 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4077 case ID_LED_DEF1_ON2:
4078 case ID_LED_ON1_ON2:
4079 case ID_LED_OFF1_ON2:
4080 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4081 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4083 case ID_LED_DEF1_OFF2:
4084 case ID_LED_ON1_OFF2:
4085 case ID_LED_OFF1_OFF2:
4086 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4087 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4094 return E1000_SUCCESS;
4097 /******************************************************************************
4098 * Prepares SW controlable LED for use and saves the current state of the LED.
4100 * hw - Struct containing variables accessed by shared code
4101 *****************************************************************************/
4103 em_setup_led(struct em_hw *hw)
4106 int32_t ret_val = E1000_SUCCESS;
4108 DEBUGFUNC("em_setup_led");
4110 switch(hw->mac_type) {
4111 case em_82542_rev2_0:
4112 case em_82542_rev2_1:
4115 /* No setup necessary */
4119 case em_82541_rev_2:
4120 case em_82547_rev_2:
4121 /* Turn off PHY Smart Power Down (if enabled) */
4122 if((ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4123 &hw->phy_spd_default)))
4125 if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4126 (uint16_t)(hw->phy_spd_default &
4127 ~IGP01E1000_GMII_SPD))))
4131 if(hw->media_type == em_media_type_fiber) {
4132 ledctl = E1000_READ_REG(hw, LEDCTL);
4133 /* Save current LEDCTL settings */
4134 hw->ledctl_default = ledctl;
4136 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4137 E1000_LEDCTL_LED0_BLINK |
4138 E1000_LEDCTL_LED0_MODE_MASK);
4139 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4140 E1000_LEDCTL_LED0_MODE_SHIFT);
4141 E1000_WRITE_REG(hw, LEDCTL, ledctl);
4142 } else if(hw->media_type == em_media_type_copper)
4143 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4147 return E1000_SUCCESS;
4150 /******************************************************************************
4151 * Restores the saved state of the SW controlable LED.
4153 * hw - Struct containing variables accessed by shared code
4154 *****************************************************************************/
4156 em_cleanup_led(struct em_hw *hw)
4158 int32_t ret_val = E1000_SUCCESS;
4160 DEBUGFUNC("em_cleanup_led");
4162 switch(hw->mac_type) {
4163 case em_82542_rev2_0:
4164 case em_82542_rev2_1:
4167 /* No cleanup necessary */
4171 case em_82541_rev_2:
4172 case em_82547_rev_2:
4173 /* Turn on PHY Smart Power Down (if previously enabled) */
4174 if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4175 hw->phy_spd_default)))
4179 /* Restore LEDCTL settings */
4180 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
4184 return E1000_SUCCESS;
4187 /******************************************************************************
4188 * Turns on the software controllable LED
4190 * hw - Struct containing variables accessed by shared code
4191 *****************************************************************************/
4193 em_led_on(struct em_hw *hw)
4195 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4197 DEBUGFUNC("em_led_on");
4199 switch(hw->mac_type) {
4200 case em_82542_rev2_0:
4201 case em_82542_rev2_1:
4203 /* Set SW Defineable Pin 0 to turn on the LED */
4204 ctrl |= E1000_CTRL_SWDPIN0;
4205 ctrl |= E1000_CTRL_SWDPIO0;
4208 if(hw->media_type == em_media_type_fiber) {
4209 /* Set SW Defineable Pin 0 to turn on the LED */
4210 ctrl |= E1000_CTRL_SWDPIN0;
4211 ctrl |= E1000_CTRL_SWDPIO0;
4213 /* Clear SW Defineable Pin 0 to turn on the LED */
4214 ctrl &= ~E1000_CTRL_SWDPIN0;
4215 ctrl |= E1000_CTRL_SWDPIO0;
4219 if(hw->media_type == em_media_type_fiber) {
4220 /* Clear SW Defineable Pin 0 to turn on the LED */
4221 ctrl &= ~E1000_CTRL_SWDPIN0;
4222 ctrl |= E1000_CTRL_SWDPIO0;
4223 } else if(hw->media_type == em_media_type_copper) {
4224 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
4225 return E1000_SUCCESS;
4230 E1000_WRITE_REG(hw, CTRL, ctrl);
4232 return E1000_SUCCESS;
4235 /******************************************************************************
4236 * Turns off the software controllable LED
4238 * hw - Struct containing variables accessed by shared code
4239 *****************************************************************************/
4241 em_led_off(struct em_hw *hw)
4243 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4245 DEBUGFUNC("em_led_off");
4247 switch(hw->mac_type) {
4248 case em_82542_rev2_0:
4249 case em_82542_rev2_1:
4251 /* Clear SW Defineable Pin 0 to turn off the LED */
4252 ctrl &= ~E1000_CTRL_SWDPIN0;
4253 ctrl |= E1000_CTRL_SWDPIO0;
4256 if(hw->media_type == em_media_type_fiber) {
4257 /* Clear SW Defineable Pin 0 to turn off the LED */
4258 ctrl &= ~E1000_CTRL_SWDPIN0;
4259 ctrl |= E1000_CTRL_SWDPIO0;
4261 /* Set SW Defineable Pin 0 to turn off the LED */
4262 ctrl |= E1000_CTRL_SWDPIN0;
4263 ctrl |= E1000_CTRL_SWDPIO0;
4267 if(hw->media_type == em_media_type_fiber) {
4268 /* Set SW Defineable Pin 0 to turn off the LED */
4269 ctrl |= E1000_CTRL_SWDPIN0;
4270 ctrl |= E1000_CTRL_SWDPIO0;
4271 } else if(hw->media_type == em_media_type_copper) {
4272 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4273 return E1000_SUCCESS;
4278 E1000_WRITE_REG(hw, CTRL, ctrl);
4280 return E1000_SUCCESS;
4283 /******************************************************************************
4284 * Clears all hardware statistics counters.
4286 * hw - Struct containing variables accessed by shared code
4287 *****************************************************************************/
4289 em_clear_hw_cntrs(struct em_hw *hw)
4291 volatile uint32_t temp;
4293 temp = E1000_READ_REG(hw, CRCERRS);
4294 temp = E1000_READ_REG(hw, SYMERRS);
4295 temp = E1000_READ_REG(hw, MPC);
4296 temp = E1000_READ_REG(hw, SCC);
4297 temp = E1000_READ_REG(hw, ECOL);
4298 temp = E1000_READ_REG(hw, MCC);
4299 temp = E1000_READ_REG(hw, LATECOL);
4300 temp = E1000_READ_REG(hw, COLC);
4301 temp = E1000_READ_REG(hw, DC);
4302 temp = E1000_READ_REG(hw, SEC);
4303 temp = E1000_READ_REG(hw, RLEC);
4304 temp = E1000_READ_REG(hw, XONRXC);
4305 temp = E1000_READ_REG(hw, XONTXC);
4306 temp = E1000_READ_REG(hw, XOFFRXC);
4307 temp = E1000_READ_REG(hw, XOFFTXC);
4308 temp = E1000_READ_REG(hw, FCRUC);
4309 temp = E1000_READ_REG(hw, PRC64);
4310 temp = E1000_READ_REG(hw, PRC127);
4311 temp = E1000_READ_REG(hw, PRC255);
4312 temp = E1000_READ_REG(hw, PRC511);
4313 temp = E1000_READ_REG(hw, PRC1023);
4314 temp = E1000_READ_REG(hw, PRC1522);
4315 temp = E1000_READ_REG(hw, GPRC);
4316 temp = E1000_READ_REG(hw, BPRC);
4317 temp = E1000_READ_REG(hw, MPRC);
4318 temp = E1000_READ_REG(hw, GPTC);
4319 temp = E1000_READ_REG(hw, GORCL);
4320 temp = E1000_READ_REG(hw, GORCH);
4321 temp = E1000_READ_REG(hw, GOTCL);
4322 temp = E1000_READ_REG(hw, GOTCH);
4323 temp = E1000_READ_REG(hw, RNBC);
4324 temp = E1000_READ_REG(hw, RUC);
4325 temp = E1000_READ_REG(hw, RFC);
4326 temp = E1000_READ_REG(hw, ROC);
4327 temp = E1000_READ_REG(hw, RJC);
4328 temp = E1000_READ_REG(hw, TORL);
4329 temp = E1000_READ_REG(hw, TORH);
4330 temp = E1000_READ_REG(hw, TOTL);
4331 temp = E1000_READ_REG(hw, TOTH);
4332 temp = E1000_READ_REG(hw, TPR);
4333 temp = E1000_READ_REG(hw, TPT);
4334 temp = E1000_READ_REG(hw, PTC64);
4335 temp = E1000_READ_REG(hw, PTC127);
4336 temp = E1000_READ_REG(hw, PTC255);
4337 temp = E1000_READ_REG(hw, PTC511);
4338 temp = E1000_READ_REG(hw, PTC1023);
4339 temp = E1000_READ_REG(hw, PTC1522);
4340 temp = E1000_READ_REG(hw, MPTC);
4341 temp = E1000_READ_REG(hw, BPTC);
4343 if(hw->mac_type < em_82543) return;
4345 temp = E1000_READ_REG(hw, ALGNERRC);
4346 temp = E1000_READ_REG(hw, RXERRC);
4347 temp = E1000_READ_REG(hw, TNCRS);
4348 temp = E1000_READ_REG(hw, CEXTERR);
4349 temp = E1000_READ_REG(hw, TSCTC);
4350 temp = E1000_READ_REG(hw, TSCTFC);
4352 if(hw->mac_type <= em_82544) return;
4354 temp = E1000_READ_REG(hw, MGTPRC);
4355 temp = E1000_READ_REG(hw, MGTPDC);
4356 temp = E1000_READ_REG(hw, MGTPTC);
4359 /******************************************************************************
4360 * Resets Adaptive IFS to its default state.
4362 * hw - Struct containing variables accessed by shared code
4364 * Call this after em_init_hw. You may override the IFS defaults by setting
4365 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
4366 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4367 * before calling this function.
4368 *****************************************************************************/
4370 em_reset_adaptive(struct em_hw *hw)
4372 DEBUGFUNC("em_reset_adaptive");
4374 if(hw->adaptive_ifs) {
4375 if(!hw->ifs_params_forced) {
4376 hw->current_ifs_val = 0;
4377 hw->ifs_min_val = IFS_MIN;
4378 hw->ifs_max_val = IFS_MAX;
4379 hw->ifs_step_size = IFS_STEP;
4380 hw->ifs_ratio = IFS_RATIO;
4382 hw->in_ifs_mode = FALSE;
4383 E1000_WRITE_REG(hw, AIT, 0);
4385 DEBUGOUT("Not in Adaptive IFS mode!\n");
4389 /******************************************************************************
4390 * Called during the callback/watchdog routine to update IFS value based on
4391 * the ratio of transmits to collisions.
4393 * hw - Struct containing variables accessed by shared code
4394 * tx_packets - Number of transmits since last callback
4395 * total_collisions - Number of collisions since last callback
4396 *****************************************************************************/
4398 em_update_adaptive(struct em_hw *hw)
4400 DEBUGFUNC("em_update_adaptive");
4402 if(hw->adaptive_ifs) {
4403 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
4404 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
4405 hw->in_ifs_mode = TRUE;
4406 if(hw->current_ifs_val < hw->ifs_max_val) {
4407 if(hw->current_ifs_val == 0)
4408 hw->current_ifs_val = hw->ifs_min_val;
4410 hw->current_ifs_val += hw->ifs_step_size;
4411 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
4415 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4416 hw->current_ifs_val = 0;
4417 hw->in_ifs_mode = FALSE;
4418 E1000_WRITE_REG(hw, AIT, 0);
4422 DEBUGOUT("Not in Adaptive IFS mode!\n");
4426 /******************************************************************************
4427 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4429 * hw - Struct containing variables accessed by shared code
4430 * frame_len - The length of the frame in question
4431 * mac_addr - The Ethernet destination address of the frame in question
4432 *****************************************************************************/
4434 em_tbi_adjust_stats(struct em_hw *hw,
4435 struct em_hw_stats *stats,
4441 /* First adjust the frame length. */
4443 /* We need to adjust the statistics counters, since the hardware
4444 * counters overcount this packet as a CRC error and undercount
4445 * the packet as a good packet
4447 /* This packet should not be counted as a CRC error. */
4449 /* This packet does count as a Good Packet Received. */
4452 /* Adjust the Good Octets received counters */
4453 carry_bit = 0x80000000 & stats->gorcl;
4454 stats->gorcl += frame_len;
4455 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4456 * Received Count) was one before the addition,
4457 * AND it is zero after, then we lost the carry out,
4458 * need to add one to Gorch (Good Octets Received Count High).
4459 * This could be simplified if all environments supported
4462 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
4464 /* Is this a broadcast or multicast? Check broadcast first,
4465 * since the test for a multicast frame will test positive on
4466 * a broadcast frame.
4468 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
4469 /* Broadcast packet */
4471 else if(*mac_addr & 0x01)
4472 /* Multicast packet */
4475 if(frame_len == hw->max_frame_size) {
4476 /* In this case, the hardware has overcounted the number of
4483 /* Adjust the bin counters when the extra byte put the frame in the
4484 * wrong bin. Remember that the frame_len was adjusted above.
4486 if(frame_len == 64) {
4489 } else if(frame_len == 127) {
4492 } else if(frame_len == 255) {
4495 } else if(frame_len == 511) {
4498 } else if(frame_len == 1023) {
4501 } else if(frame_len == 1522) {
4506 /******************************************************************************
4507 * Gets the current PCI bus type, speed, and width of the hardware
4509 * hw - Struct containing variables accessed by shared code
4510 *****************************************************************************/
4512 em_get_bus_info(struct em_hw *hw)
4516 if(hw->mac_type < em_82543) {
4517 hw->bus_type = em_bus_type_unknown;
4518 hw->bus_speed = em_bus_speed_unknown;
4519 hw->bus_width = em_bus_width_unknown;
4523 status = E1000_READ_REG(hw, STATUS);
4524 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4525 em_bus_type_pcix : em_bus_type_pci;
4527 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4528 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ?
4529 em_bus_speed_66 : em_bus_speed_120;
4530 } else if(hw->bus_type == em_bus_type_pci) {
4531 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4532 em_bus_speed_66 : em_bus_speed_33;
4534 switch (status & E1000_STATUS_PCIX_SPEED) {
4535 case E1000_STATUS_PCIX_SPEED_66:
4536 hw->bus_speed = em_bus_speed_66;
4538 case E1000_STATUS_PCIX_SPEED_100:
4539 hw->bus_speed = em_bus_speed_100;
4541 case E1000_STATUS_PCIX_SPEED_133:
4542 hw->bus_speed = em_bus_speed_133;
4545 hw->bus_speed = em_bus_speed_reserved;
4549 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4550 em_bus_width_64 : em_bus_width_32;
4553 /******************************************************************************
4554 * Estimates the cable length.
4556 * hw - Struct containing variables accessed by shared code
4557 * min_length - The estimated minimum length
4558 * max_length - The estimated maximum length
4560 * returns: - E1000_ERR_XXX
4563 * This function always returns a ranged length (minimum & maximum).
4564 * So for M88 phy's, this function interprets the one value returned from the
4565 * register to the minimum and maximum range.
4566 * For IGP phy's, the function calculates the range by the AGC registers.
4567 *****************************************************************************/
4569 em_get_cable_length(struct em_hw *hw,
4570 uint16_t *min_length,
4571 uint16_t *max_length)
4574 uint16_t agc_value = 0;
4575 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4576 uint16_t i, phy_data;
4578 DEBUGFUNC("em_get_cable_length");
4580 *min_length = *max_length = 0;
4582 /* Use old method for Phy older than IGP */
4583 if(hw->phy_type == em_phy_m88) {
4584 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4588 /* Convert the enum value to ranged values */
4589 switch((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4590 M88E1000_PSSR_CABLE_LENGTH_SHIFT) {
4591 case em_cable_length_50:
4593 *max_length = em_igp_cable_length_50;
4595 case em_cable_length_50_80:
4596 *min_length = em_igp_cable_length_50;
4597 *max_length = em_igp_cable_length_80;
4599 case em_cable_length_80_110:
4600 *min_length = em_igp_cable_length_80;
4601 *max_length = em_igp_cable_length_110;
4603 case em_cable_length_110_140:
4604 *min_length = em_igp_cable_length_110;
4605 *max_length = em_igp_cable_length_140;
4607 case em_cable_length_140:
4608 *min_length = em_igp_cable_length_140;
4609 *max_length = em_igp_cable_length_170;
4612 return -E1000_ERR_PHY;
4615 } else if(hw->phy_type == em_phy_igp) { /* For IGP PHY */
4616 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4617 {IGP01E1000_PHY_AGC_A,
4618 IGP01E1000_PHY_AGC_B,
4619 IGP01E1000_PHY_AGC_C,
4620 IGP01E1000_PHY_AGC_D};
4621 /* Read the AGC registers for all channels */
4622 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4624 if((ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data)))
4627 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4629 /* Array bound check. */
4630 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4632 return -E1000_ERR_PHY;
4634 agc_value += cur_agc;
4636 /* Update minimal AGC value. */
4637 if(min_agc > cur_agc)
4641 /* Remove the minimal AGC result for length < 50m */
4642 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * em_igp_cable_length_50) {
4643 agc_value -= min_agc;
4645 /* Get the average length of the remaining 3 channels */
4646 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4648 /* Get the average length of all the 4 channels. */
4649 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4652 /* Set the range of the calculated length. */
4653 *min_length = ((em_igp_cable_length_table[agc_value] -
4654 IGP01E1000_AGC_RANGE) > 0) ?
4655 (em_igp_cable_length_table[agc_value] -
4656 IGP01E1000_AGC_RANGE) : 0;
4657 *max_length = em_igp_cable_length_table[agc_value] +
4658 IGP01E1000_AGC_RANGE;
4661 return E1000_SUCCESS;
4664 /******************************************************************************
4665 * Check the cable polarity
4667 * hw - Struct containing variables accessed by shared code
4668 * polarity - output parameter : 0 - Polarity is not reversed
4669 * 1 - Polarity is reversed.
4671 * returns: - E1000_ERR_XXX
4674 * For phy's older then IGP, this function simply reads the polarity bit in the
4675 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
4676 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
4677 * return 0. If the link speed is 1000 Mbps the polarity status is in the
4678 * IGP01E1000_PHY_PCS_INIT_REG.
4679 *****************************************************************************/
4681 em_check_polarity(struct em_hw *hw,
4687 DEBUGFUNC("em_check_polarity");
4689 if(hw->phy_type == em_phy_m88) {
4690 /* return the Polarity bit in the Status register. */
4691 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4694 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
4695 M88E1000_PSSR_REV_POLARITY_SHIFT;
4696 } else if(hw->phy_type == em_phy_igp) {
4697 /* Read the Status register to check the speed */
4698 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
4702 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
4703 * find the polarity status */
4704 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4705 IGP01E1000_PSSR_SPEED_1000MBPS) {
4707 /* Read the GIG initialization PCS register (0x00B4) */
4708 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
4712 /* Check the polarity bits */
4713 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
4715 /* For 10 Mbps, read the polarity bit in the status register. (for
4716 * 100 Mbps this bit is always 0) */
4717 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
4720 return E1000_SUCCESS;
4723 /******************************************************************************
4724 * Check if Downshift occured
4726 * hw - Struct containing variables accessed by shared code
4727 * downshift - output parameter : 0 - No Downshift ocured.
4728 * 1 - Downshift ocured.
4730 * returns: - E1000_ERR_XXX
4733 * For phy's older then IGP, this function reads the Downshift bit in the Phy
4734 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
4735 * Link Health register. In IGP this bit is latched high, so the driver must
4736 * read it immediately after link is established.
4737 *****************************************************************************/
4739 em_check_downshift(struct em_hw *hw)
4744 DEBUGFUNC("em_check_downshift");
4746 if(hw->phy_type == em_phy_igp) {
4747 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
4751 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
4753 else if(hw->phy_type == em_phy_m88) {
4754 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4758 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
4759 M88E1000_PSSR_DOWNSHIFT_SHIFT;
4761 return E1000_SUCCESS;
4764 /*****************************************************************************
4766 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
4767 * gigabit link is achieved to improve link quality.
4769 * hw: Struct containing variables accessed by shared code
4771 * returns: - E1000_ERR_PHY if fail to read/write the PHY
4772 * E1000_SUCCESS at any other case.
4774 ****************************************************************************/
4777 em_config_dsp_after_link_change(struct em_hw *hw,
4781 uint16_t phy_data, speed, duplex, i;
4782 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4783 {IGP01E1000_PHY_AGC_PARAM_A,
4784 IGP01E1000_PHY_AGC_PARAM_B,
4785 IGP01E1000_PHY_AGC_PARAM_C,
4786 IGP01E1000_PHY_AGC_PARAM_D};
4787 uint16_t min_length, max_length;
4789 DEBUGFUNC("em_config_dsp_after_link_change");
4791 if(hw->phy_type != em_phy_igp)
4792 return E1000_SUCCESS;
4795 if((ret_val = em_get_speed_and_duplex(hw, &speed, &duplex))) {
4796 DEBUGOUT("Error getting link speed and duplex\n");
4800 if(speed == SPEED_1000) {
4802 em_get_cable_length(hw, &min_length, &max_length);
4804 if((hw->dsp_config_state == em_dsp_config_enabled) &&
4805 min_length >= em_igp_cable_length_50) {
4807 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4808 if((ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
4812 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
4814 if((ret_val = em_write_phy_reg(hw, dsp_reg_array[i],
4818 hw->dsp_config_state = em_dsp_config_activated;
4821 if((hw->ffe_config_state == em_ffe_config_enabled) &&
4822 (min_length < em_igp_cable_length_50)) {
4824 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
4825 uint32_t idle_errs = 0;
4827 /* clear previous idle error counts */
4828 if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
4832 for(i = 0; i < ffe_idle_err_timeout; i++) {
4834 if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
4838 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
4839 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
4840 hw->ffe_config_state = em_ffe_config_active;
4842 if((ret_val = em_write_phy_reg(hw,
4843 IGP01E1000_PHY_DSP_FFE,
4844 IGP01E1000_PHY_DSP_FFE_CM_CP)))
4850 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
4855 if(hw->dsp_config_state == em_dsp_config_activated) {
4856 if((ret_val = em_write_phy_reg(hw, 0x0000,
4857 IGP01E1000_IEEE_FORCE_GIGA)))
4859 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4860 if((ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
4864 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
4865 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
4867 if((ret_val = em_write_phy_reg(hw,dsp_reg_array[i],
4872 if((ret_val = em_write_phy_reg(hw, 0x0000,
4873 IGP01E1000_IEEE_RESTART_AUTONEG)))
4876 hw->dsp_config_state = em_dsp_config_enabled;
4879 if(hw->ffe_config_state == em_ffe_config_active) {
4880 if((ret_val = em_write_phy_reg(hw, 0x0000,
4881 IGP01E1000_IEEE_FORCE_GIGA)))
4883 if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
4884 IGP01E1000_PHY_DSP_FFE_DEFAULT)))
4887 if((ret_val = em_write_phy_reg(hw, 0x0000,
4888 IGP01E1000_IEEE_RESTART_AUTONEG)))
4890 hw->ffe_config_state = em_ffe_config_enabled;
4893 return E1000_SUCCESS;
4896 /*****************************************************************************
4898 * This function sets the lplu state according to the active flag. When
4899 * activating lplu this function also disables smart speed and vise versa.
4900 * lplu will not be activated unless the device autonegotiation advertisment
4901 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
4902 * hw: Struct containing variables accessed by shared code
4903 * active - true to enable lplu false to disable lplu.
4905 * returns: - E1000_ERR_PHY if fail to read/write the PHY
4906 * E1000_SUCCESS at any other case.
4908 ****************************************************************************/
4911 em_set_d3_lplu_state(struct em_hw *hw,
4916 DEBUGFUNC("em_set_d3_lplu_state");
4918 if(!((hw->mac_type == em_82541_rev_2) ||
4919 (hw->mac_type == em_82547_rev_2)))
4920 return E1000_SUCCESS;
4922 /* During driver activity LPLU should not be used or it will attain link
4923 * from the lowest speeds starting from 10Mbps. The capability is used for
4924 * Dx transitions and states */
4925 if((ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data)))
4929 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
4930 if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
4933 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
4934 * Dx states where the power conservation is most important. During
4935 * driver activity we should enable SmartSpeed, so performance is
4937 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
4941 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
4942 if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
4946 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
4947 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
4948 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
4950 phy_data |= IGP01E1000_GMII_FLEX_SPD;
4951 if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
4954 /* When LPLU is enabled we should disable SmartSpeed */
4955 if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
4959 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
4960 if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
4965 return E1000_SUCCESS;
4968 /******************************************************************************
4969 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
4971 * hw - Struct containing variables accessed by shared code
4972 *****************************************************************************/
4974 em_set_vco_speed(struct em_hw *hw)
4977 uint16_t default_page = 0;
4980 DEBUGFUNC("em_set_vco_speed");
4982 switch(hw->mac_type) {
4983 case em_82545_rev_3:
4984 case em_82546_rev_3:
4987 return E1000_SUCCESS;
4990 /* Set PHY register 30, page 5, bit 8 to 0 */
4992 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
4996 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005)))
4999 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
5002 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5003 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
5006 /* Set PHY register 30, page 4, bit 11 to 1 */
5008 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004)))
5011 if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
5014 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5015 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
5018 if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5022 return E1000_SUCCESS;