2 * Copyright (c) 1993 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * $FreeBSD: src/sys/i386/include/cpufunc.h,v 1.96.2.3 2002/04/28 22:50:54 dwmalone Exp $
37 * Functions to provide access to special i386 instructions.
40 #ifndef _CPU_CPUFUNC_H_
41 #define _CPU_CPUFUNC_H_
44 #include <sys/types.h>
47 #include <sys/cdefs.h>
51 #define readb(va) (*(volatile u_int8_t *) (va))
52 #define readw(va) (*(volatile u_int16_t *) (va))
53 #define readl(va) (*(volatile u_int32_t *) (va))
55 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
56 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
57 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
62 #include <machine/lock.h> /* XXX */
65 #ifdef SWTCH_OPTIM_STATS
66 extern int tlb_flush_count; /* XXX */
72 __asm __volatile("int $3");
78 __asm __volatile("pause");
82 * Find the first 1 in mask, starting with bit 0 and return the
83 * bit number. If mask is 0 the result is undefined.
90 __asm __volatile("bsfl %0,%0" : "=r" (result) : "0" (mask));
99 __asm __volatile("bsfl %0,%0" : "=r" (result) : "0" (mask));
104 * Find the last 1 in mask, starting with bit 31 and return the
105 * bit number. If mask is 0 the result is undefined.
107 static __inline u_int
112 __asm __volatile("bsrl %0,%0" : "=r" (result) : "0" (mask));
117 * Test and set the specified bit (1 << bit) in the integer. The
118 * previous value of the bit is returned (0 or 1).
121 btsl(u_int *mask, int bit)
125 __asm __volatile("btsl %2,%1; movl $0,%0; adcl $0,%0" :
126 "=r"(result), "=m"(*mask) : "r" (bit));
131 * Test and clear the specified bit (1 << bit) in the integer. The
132 * previous value of the bit is returned (0 or 1).
135 btrl(u_int *mask, int bit)
139 __asm __volatile("btrl %2,%1; movl $0,%0; adcl $0,%0" :
140 "=r"(result), "=m"(*mask) : "r" (bit));
145 do_cpuid(u_int ax, u_int *p)
147 __asm __volatile("cpuid"
148 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
153 cpuid_count(u_int ax, u_int cx, u_int *p)
155 __asm __volatile("cpuid"
156 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
157 : "0" (ax), "c" (cx));
160 #ifndef _CPU_DISABLE_INTR_DEFINED
163 cpu_disable_intr(void)
165 __asm __volatile("cli" : : : "memory");
170 #ifndef _CPU_ENABLE_INTR_DEFINED
173 cpu_enable_intr(void)
175 __asm __volatile("sti");
181 * Cpu and compiler memory ordering fence. mfence ensures strong read and
184 * A serializing or fence instruction is required here. A locked bus
185 * cycle on data for which we already own cache mastership is the most
193 __asm __volatile("mfence" : : : "memory");
195 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
198 __asm __volatile("" : : : "memory");
203 * cpu_lfence() ensures strong read ordering for reads issued prior
204 * to the instruction verses reads issued afterwords.
206 * A serializing or fence instruction is required here. A locked bus
207 * cycle on data for which we already own cache mastership is the most
215 __asm __volatile("lfence" : : : "memory");
217 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
220 __asm __volatile("" : : : "memory");
225 * cpu_sfence() ensures strong write ordering for writes issued prior
226 * to the instruction verses writes issued afterwords. Writes are
227 * ordered on intel cpus so we do not actually have to do anything.
234 * Don't use 'sfence' here, as it will create a lot of
235 * unnecessary stalls.
237 __asm __volatile("" : : : "memory");
241 * cpu_ccfence() prevents the compiler from reordering instructions, in
242 * particular stores, relative to the current cpu. Use cpu_sfence() if
243 * you need to guarentee ordering by both the compiler and by the cpu.
245 * This also prevents the compiler from caching memory loads into local
246 * variables across the routine.
251 __asm __volatile("" : : : "memory");
255 * This is a horrible, horrible hack that might have to be put at the
256 * end of certain procedures (on a case by case basis), just before it
257 * returns to avoid what we believe to be an unreported AMD cpu bug.
258 * Found to occur on both a Phenom II X4 820 (two of them), as well
259 * as a 48-core built around an Opteron 6168 (Id = 0x100f91 Stepping = 1).
260 * The problem does not appear to occur w/Intel cpus.
262 * The bug is likely related to either a write combining issue or the
263 * Return Address Stack (RAS) hardware cache.
265 * In particular, we had to do this for GCC's fill_sons_in_loop() routine
266 * which due to its deep recursion and stack flow appears to be able to
267 * tickle the amd cpu bug (w/ gcc-4.4.7). Adding a single 'nop' to the
268 * end of the routine just before it returns works around the bug.
270 * The bug appears to be extremely sensitive to %rip and %rsp values, to
271 * the point where even just inserting an instruction in an unrelated
272 * procedure (shifting the entire code base being run) effects the outcome.
273 * DragonFly is probably able to more readily reproduce the bug due to
274 * the stackgap randomization code. We would expect OpenBSD (where we got
275 * the stackgap randomization code from) to also be able to reproduce the
276 * issue. To date we have only reproduced the issue in DragonFly.
278 #define __AMDCPUBUG_DFLY01_AVAILABLE__
281 cpu_amdcpubug_dfly01(void)
283 __asm __volatile("nop" : : : "memory");
288 #define HAVE_INLINE_FFS
294 * Note that gcc-2's builtin ffs would be used if we didn't declare
295 * this inline or turn off the builtin. The builtin is faster but
296 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
299 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
302 #define HAVE_INLINE_FLS
307 return (mask == 0 ? mask : (int) bsrl((u_int)mask) + 1);
313 * The following complications are to get around gcc not having a
314 * constraint letter for the range 0..255. We still put "d" in the
315 * constraint because "i" isn't a valid constraint when the port
316 * isn't constant. This only matters for -O0 because otherwise
317 * the non-working version gets optimized away.
319 * Use an expression-statement instead of a conditional expression
320 * because gcc-2.6.0 would promote the operands of the conditional
321 * and produce poor code for "if ((inb(var) & const1) == const2)".
323 * The unnecessary test `(port) < 0x10000' is to generate a warning if
324 * the `port' has type u_short or smaller. Such types are pessimal.
325 * This actually only works for signed types. The range check is
326 * careful to avoid generating warnings.
328 #define inb(port) __extension__ ({ \
330 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
331 && (port) < 0x10000) \
332 _data = inbc(port); \
334 _data = inbv(port); \
337 #define outb(port, data) ( \
338 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
339 && (port) < 0x10000 \
340 ? outbc(port, data) : outbv(port, data))
342 static __inline u_char
347 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
352 outbc(u_int port, u_char data)
354 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
357 static __inline u_char
362 * We use %%dx and not %1 here because i/o is done at %dx and not at
363 * %edx, while gcc generates inferior code (movw instead of movl)
364 * if we tell it to load (u_short) port.
366 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
370 static __inline u_int
375 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
380 insb(u_int port, void *addr, size_t cnt)
382 __asm __volatile("cld; rep; insb"
383 : "=D" (addr), "=c" (cnt)
384 : "0" (addr), "1" (cnt), "d" (port)
389 insw(u_int port, void *addr, size_t cnt)
391 __asm __volatile("cld; rep; insw"
392 : "=D" (addr), "=c" (cnt)
393 : "0" (addr), "1" (cnt), "d" (port)
398 insl(u_int port, void *addr, size_t cnt)
400 __asm __volatile("cld; rep; insl"
401 : "=D" (addr), "=c" (cnt)
402 : "0" (addr), "1" (cnt), "d" (port)
409 __asm __volatile("invd");
415 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
416 * will cause the invl*() functions to be equivalent to the cpu_invl*()
420 void smp_invltlb(void);
421 void smp_invltlb_intr(void);
423 #define smp_invltlb()
426 #ifndef _CPU_INVLPG_DEFINED
429 * Invalidate a patricular VA on this cpu only
432 cpu_invlpg(void *addr)
434 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
439 #ifndef _CPU_INVLTLB_DEFINED
442 * Invalidate the TLB on this cpu only
449 * This should be implemented as load_cr3(rcr3()) when load_cr3()
452 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
454 #if defined(SWTCH_OPTIM_STATS)
464 __asm __volatile("rep; nop");
469 static __inline u_short
474 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
478 static __inline u_int
479 loadandclear(volatile u_int *addr)
483 __asm __volatile("xorl %0,%0; xchgl %1,%0"
484 : "=&r" (result) : "m" (*addr));
489 outbv(u_int port, u_char data)
493 * Use an unnecessary assignment to help gcc's register allocator.
494 * This make a large difference for gcc-1.40 and a tiny difference
495 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
496 * best results. gcc-2.6.0 can't handle this.
499 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
503 outl(u_int port, u_int data)
506 * outl() and outw() aren't used much so we haven't looked at
507 * possible micro-optimizations such as the unnecessary
508 * assignment for them.
510 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
514 outsb(u_int port, const void *addr, size_t cnt)
516 __asm __volatile("cld; rep; outsb"
517 : "=S" (addr), "=c" (cnt)
518 : "0" (addr), "1" (cnt), "d" (port));
522 outsw(u_int port, const void *addr, size_t cnt)
524 __asm __volatile("cld; rep; outsw"
525 : "=S" (addr), "=c" (cnt)
526 : "0" (addr), "1" (cnt), "d" (port));
530 outsl(u_int port, const void *addr, size_t cnt)
532 __asm __volatile("cld; rep; outsl"
533 : "=S" (addr), "=c" (cnt)
534 : "0" (addr), "1" (cnt), "d" (port));
538 outw(u_int port, u_short data)
540 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
543 static __inline u_int
548 __asm __volatile("movl %%cr2,%0" : "=r" (data));
552 static __inline u_int
557 __asm __volatile("pushfl; popl %0" : "=r" (ef));
561 static __inline u_int64_t
566 __asm __volatile("rdmsr" : "=A" (rv) : "c" (msr));
570 static __inline u_int64_t
575 __asm __volatile("rdpmc" : "=A" (rv) : "c" (pmc));
579 #define _RDTSC_SUPPORTED_
581 static __inline u_int64_t
586 __asm __volatile("rdtsc" : "=A" (rv));
593 __asm __volatile("wbinvd");
597 write_eflags(u_int ef)
599 __asm __volatile("pushl %0; popfl" : : "r" (ef));
603 wrmsr(u_int msr, u_int64_t newval)
605 __asm __volatile("wrmsr" : : "A" (newval), "c" (msr));
608 static __inline u_short
612 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
616 static __inline u_short
620 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
627 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
633 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
636 static __inline u_int
640 __asm __volatile("movl %%dr0,%0" : "=r" (data));
647 __asm __volatile("movl %0,%%dr0" : : "r" (sel));
650 static __inline u_int
654 __asm __volatile("movl %%dr1,%0" : "=r" (data));
661 __asm __volatile("movl %0,%%dr1" : : "r" (sel));
664 static __inline u_int
668 __asm __volatile("movl %%dr2,%0" : "=r" (data));
675 __asm __volatile("movl %0,%%dr2" : : "r" (sel));
678 static __inline u_int
682 __asm __volatile("movl %%dr3,%0" : "=r" (data));
689 __asm __volatile("movl %0,%%dr3" : : "r" (sel));
692 static __inline u_int
696 __asm __volatile("movl %%dr4,%0" : "=r" (data));
703 __asm __volatile("movl %0,%%dr4" : : "r" (sel));
706 static __inline u_int
710 __asm __volatile("movl %%dr5,%0" : "=r" (data));
717 __asm __volatile("movl %0,%%dr5" : : "r" (sel));
720 static __inline u_int
724 __asm __volatile("movl %%dr6,%0" : "=r" (data));
731 __asm __volatile("movl %0,%%dr6" : : "r" (sel));
734 static __inline u_int
738 __asm __volatile("movl %%dr7,%0" : "=r" (data));
745 __asm __volatile("movl %0,%%dr7" : : "r" (sel));
748 #else /* !__GNUC__ */
750 int breakpoint (void);
751 void cpu_pause (void);
752 u_int bsfl (u_int mask);
753 u_int bsrl (u_int mask);
754 void cpu_disable_intr (void);
755 void do_cpuid (u_int ax, u_int *p);
756 void cpu_enable_intr (void);
757 u_char inb (u_int port);
758 u_int inl (u_int port);
759 void insb (u_int port, void *addr, size_t cnt);
760 void insl (u_int port, void *addr, size_t cnt);
761 void insw (u_int port, void *addr, size_t cnt);
763 u_short inw (u_int port);
764 u_int loadandclear (u_int *addr);
765 void outb (u_int port, u_char data);
766 void outl (u_int port, u_int data);
767 void outsb (u_int port, void *addr, size_t cnt);
768 void outsl (u_int port, void *addr, size_t cnt);
769 void outsw (u_int port, void *addr, size_t cnt);
770 void outw (u_int port, u_short data);
772 u_int64_t rdmsr (u_int msr);
773 u_int64_t rdpmc (u_int pmc);
774 u_int64_t rdtsc (void);
775 u_int read_eflags (void);
777 void write_eflags (u_int ef);
778 void wrmsr (u_int msr, u_int64_t newval);
781 void load_fs (u_short sel);
782 void load_gs (u_short sel);
784 #endif /* __GNUC__ */
786 void load_cr0 (u_int cr0);
787 void load_cr3 (u_int cr3);
788 void load_cr4 (u_int cr4);
789 void ltr (u_short sel);
793 int rdmsr_safe (u_int msr, uint64_t *val);
794 void reset_dbregs (void);
797 #endif /* !_CPU_CPUFUNC_H_ */