sys/dev/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_irq.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <sys/sfbuf.h>
  31
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 static void i915_capture_error_state(struct drm_device *dev);
  38 static u32 ring_last_seqno(struct intel_ring_buffer *ring);
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 /* For display hotplug interrupt */
  68 static void
  69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  70 {
  71         if ((dev_priv->irq_mask & mask) != 0) {
  72                 dev_priv->irq_mask &= ~mask;
  73                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  74                 POSTING_READ(DEIMR);
  75         }
  76 }
  77
  78 static inline void
  79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  80 {
  81         if ((dev_priv->irq_mask & mask) != mask) {
  82                 dev_priv->irq_mask |= mask;
  83                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  84                 POSTING_READ(DEIMR);
  85         }
  86 }
  87
  88 void
  89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  90 {
  91         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  92                 u32 reg = PIPESTAT(pipe);
  93
  94                 dev_priv->pipestat[pipe] |= mask;
  95                 /* Enable the interrupt, clear any pending status */
  96                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  97                 POSTING_READ(reg);
  98         }
  99 }
 100
 101 void
 102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 103 {
 104         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 105                 u32 reg = PIPESTAT(pipe);
 106
 107                 dev_priv->pipestat[pipe] &= ~mask;
 108                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 109                 POSTING_READ(reg);
 110         }
 111 }
 112
 113 /**
 114  * intel_enable_asle - enable ASLE interrupt for OpRegion
 115  */
 116 void intel_enable_asle(struct drm_device *dev)
 117 {
 118         drm_i915_private_t *dev_priv = dev->dev_private;
 119
 120         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 121
 122         if (HAS_PCH_SPLIT(dev))
 123                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 124         else {
 125                 i915_enable_pipestat(dev_priv, 1,
 126                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 127                 if (INTEL_INFO(dev)->gen >= 4)
 128                         i915_enable_pipestat(dev_priv, 0,
 129                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 130         }
 131
 132         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 133 }
 134
 135 /**
 136  * i915_pipe_enabled - check if a pipe is enabled
 137  * @dev: DRM device
 138  * @pipe: pipe to check
 139  *
 140  * Reading certain registers when the pipe is disabled can hang the chip.
 141  * Use this routine to make sure the PLL is running and the pipe is active
 142  * before reading such registers if unsure.
 143  */
 144 static int
 145 i915_pipe_enabled(struct drm_device *dev, int pipe)
 146 {
 147         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 148         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 149 }
 150
 151 /* Called from drm generic code, passed a 'crtc', which
 152  * we use as a pipe index
 153  */
 154 static u32
 155 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 156 {
 157         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 158         unsigned long high_frame;
 159         unsigned long low_frame;
 160         u32 high1, high2, low;
 161
 162         if (!i915_pipe_enabled(dev, pipe)) {
 163                 DRM_DEBUG("trying to get vblank count for disabled "
 164                                 "pipe %c\n", pipe_name(pipe));
 165                 return 0;
 166         }
 167
 168         high_frame = PIPEFRAME(pipe);
 169         low_frame = PIPEFRAMEPIXEL(pipe);
 170
 171         /*
 172          * High & low register fields aren't synchronized, so make sure
 173          * we get a low value that's stable across two reads of the high
 174          * register.
 175          */
 176         do {
 177                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 178                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 179                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 180         } while (high1 != high2);
 181
 182         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 183         low >>= PIPE_FRAME_LOW_SHIFT;
 184         return (high1 << 8) | low;
 185 }
 186
 187 static u32
 188 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 189 {
 190         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 191         int reg = PIPE_FRMCOUNT_GM45(pipe);
 192
 193         if (!i915_pipe_enabled(dev, pipe)) {
 194                 DRM_DEBUG("i915: trying to get vblank count for disabled "
 195                                  "pipe %c\n", pipe_name(pipe));
 196                 return 0;
 197         }
 198
 199         return I915_READ(reg);
 200 }
 201
 202 static int
 203 i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 204     int *vpos, int *hpos)
 205 {
 206         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 207         u32 vbl = 0, position = 0;
 208         int vbl_start, vbl_end, htotal, vtotal;
 209         bool in_vbl = true;
 210         int ret = 0;
 211
 212         if (!i915_pipe_enabled(dev, pipe)) {
 213                 DRM_DEBUG("i915: trying to get scanoutpos for disabled "
 214                                  "pipe %c\n", pipe_name(pipe));
 215                 return 0;
 216         }
 217
 218         /* Get vtotal. */
 219         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 220
 221         if (INTEL_INFO(dev)->gen >= 4) {
 222                 /* No obvious pixelcount register. Only query vertical
 223                  * scanout position from Display scan line register.
 224                  */
 225                 position = I915_READ(PIPEDSL(pipe));
 226
 227                 /* Decode into vertical scanout position. Don't have
 228                  * horizontal scanout position.
 229                  */
 230                 *vpos = position & 0x1fff;
 231                 *hpos = 0;
 232         } else {
 233                 /* Have access to pixelcount since start of frame.
 234                  * We can split this into vertical and horizontal
 235                  * scanout position.
 236                  */
 237                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 238
 239                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 240                 *vpos = position / htotal;
 241                 *hpos = position - (*vpos * htotal);
 242         }
 243
 244         /* Query vblank area. */
 245         vbl = I915_READ(VBLANK(pipe));
 246
 247         /* Test position against vblank region. */
 248         vbl_start = vbl & 0x1fff;
 249         vbl_end = (vbl >> 16) & 0x1fff;
 250
 251         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 252                 in_vbl = false;
 253
 254         /* Inside "upper part" of vblank area? Apply corrective offset: */
 255         if (in_vbl && (*vpos >= vbl_start))
 256                 *vpos = *vpos - vtotal;
 257
 258         /* Readouts valid? */
 259         if (vbl > 0)
 260                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 261
 262         /* In vblank? */
 263         if (in_vbl)
 264                 ret |= DRM_SCANOUTPOS_INVBL;
 265
 266         return ret;
 267 }
 268
 269 static int
 270 i915_get_vblank_timestamp(struct drm_device *dev, int pipe, int *max_error,
 271     struct timeval *vblank_time, unsigned flags)
 272 {
 273         struct drm_i915_private *dev_priv = dev->dev_private;
 274         struct drm_crtc *crtc;
 275
 276         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 277                 DRM_ERROR("Invalid crtc %d\n", pipe);
 278                 return -EINVAL;
 279         }
 280
 281         /* Get drm_crtc to timestamp: */
 282         crtc = intel_get_crtc_for_pipe(dev, pipe);
 283         if (crtc == NULL) {
 284                 DRM_ERROR("Invalid crtc %d\n", pipe);
 285                 return -EINVAL;
 286         }
 287
 288         if (!crtc->enabled) {
 289 #if 0
 290                 DRM_DEBUG("crtc %d is disabled\n", pipe);
 291 #endif
 292                 return -EBUSY;
 293         }
 294
 295         /* Helper routine in DRM core does all the work: */
 296         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 297                                                      vblank_time, flags,
 298                                                      crtc);
 299 }
 300
 301 /*
 302  * Handle hotplug events outside the interrupt handler proper.
 303  */
 304 static void
 305 i915_hotplug_work_func(void *context, int pending)
 306 {
 307         drm_i915_private_t *dev_priv = context;
 308         struct drm_device *dev = dev_priv->dev;
 309         struct drm_mode_config *mode_config;
 310         struct intel_encoder *encoder;
 311
 312         DRM_DEBUG("running encoder hotplug functions\n");
 313         dev_priv = context;
 314         dev = dev_priv->dev;
 315
 316         mode_config = &dev->mode_config;
 317
 318         lockmgr(&mode_config->mutex, LK_EXCLUSIVE);
 319         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 320
 321         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 322                 if (encoder->hot_plug)
 323                         encoder->hot_plug(encoder);
 324
 325         lockmgr(&mode_config->mutex, LK_RELEASE);
 326
 327         /* Just fire off a uevent and let userspace tell us what to do */
 328 #if 0
 329         drm_helper_hpd_irq_event(dev);
 330 #endif
 331 }
 332
 333 static void i915_handle_rps_change(struct drm_device *dev)
 334 {
 335         drm_i915_private_t *dev_priv = dev->dev_private;
 336         u32 busy_up, busy_down, max_avg, min_avg;
 337         u8 new_delay = dev_priv->cur_delay;
 338
 339         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 340         busy_up = I915_READ(RCPREVBSYTUPAVG);
 341         busy_down = I915_READ(RCPREVBSYTDNAVG);
 342         max_avg = I915_READ(RCBMAXAVG);
 343         min_avg = I915_READ(RCBMINAVG);
 344
 345         /* Handle RCS change request from hw */
 346         if (busy_up > max_avg) {
 347                 if (dev_priv->cur_delay != dev_priv->max_delay)
 348                         new_delay = dev_priv->cur_delay - 1;
 349                 if (new_delay < dev_priv->max_delay)
 350                         new_delay = dev_priv->max_delay;
 351         } else if (busy_down < min_avg) {
 352                 if (dev_priv->cur_delay != dev_priv->min_delay)
 353                         new_delay = dev_priv->cur_delay + 1;
 354                 if (new_delay > dev_priv->min_delay)
 355                         new_delay = dev_priv->min_delay;
 356         }
 357
 358         if (ironlake_set_drps(dev, new_delay))
 359                 dev_priv->cur_delay = new_delay;
 360
 361         return;
 362 }
 363
 364 static void notify_ring(struct drm_device *dev,
 365                         struct intel_ring_buffer *ring)
 366 {
 367         struct drm_i915_private *dev_priv = dev->dev_private;
 368         u32 seqno;
 369
 370         if (ring->obj == NULL)
 371                 return;
 372
 373         seqno = ring->get_seqno(ring);
 374
 375         lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
 376         ring->irq_seqno = seqno;
 377         wakeup(ring);
 378         lockmgr(&ring->irq_lock, LK_RELEASE);
 379
 380         if (i915_enable_hangcheck) {
 381                 dev_priv->hangcheck_count = 0;
 382                 callout_reset(&dev_priv->hangcheck_timer,
 383                     DRM_I915_HANGCHECK_PERIOD, i915_hangcheck_elapsed, dev);
 384         }
 385 }
 386
 387 static void
 388 gen6_pm_rps_work_func(void *arg, int pending)
 389 {
 390         struct drm_device *dev;
 391         drm_i915_private_t *dev_priv;
 392         u8 new_delay;
 393         u32 pm_iir, pm_imr;
 394
 395         dev_priv = (drm_i915_private_t *)arg;
 396         dev = dev_priv->dev;
 397         new_delay = dev_priv->cur_delay;
 398
 399         lockmgr(&dev_priv->rps_lock, LK_EXCLUSIVE);
 400         pm_iir = dev_priv->pm_iir;
 401         dev_priv->pm_iir = 0;
 402         pm_imr = I915_READ(GEN6_PMIMR);
 403         I915_WRITE(GEN6_PMIMR, 0);
 404         lockmgr(&dev_priv->rps_lock, LK_RELEASE);
 405
 406         if (!pm_iir)
 407                 return;
 408
 409         DRM_LOCK(dev);
 410         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 411                 if (dev_priv->cur_delay != dev_priv->max_delay)
 412                         new_delay = dev_priv->cur_delay + 1;
 413                 if (new_delay > dev_priv->max_delay)
 414                         new_delay = dev_priv->max_delay;
 415         } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
 416                 gen6_gt_force_wake_get(dev_priv);
 417                 if (dev_priv->cur_delay != dev_priv->min_delay)
 418                         new_delay = dev_priv->cur_delay - 1;
 419                 if (new_delay < dev_priv->min_delay) {
 420                         new_delay = dev_priv->min_delay;
 421                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 422                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
 423                                    ((new_delay << 16) & 0x3f0000));
 424                 } else {
 425                         /* Make sure we continue to get down interrupts
 426                          * until we hit the minimum frequency */
 427                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 428                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
 429                 }
 430                 gen6_gt_force_wake_put(dev_priv);
 431         }
 432
 433         gen6_set_rps(dev, new_delay);
 434         dev_priv->cur_delay = new_delay;
 435
 436         /*
 437          * rps_lock not held here because clearing is non-destructive. There is
 438          * an *extremely* unlikely race with gen6_rps_enable() that is prevented
 439          * by holding struct_mutex for the duration of the write.
 440          */
 441         DRM_UNLOCK(dev);
 442 }
 443
 444 static void pch_irq_handler(struct drm_device *dev)
 445 {
 446         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 447         u32 pch_iir;
 448         int pipe;
 449
 450         pch_iir = I915_READ(SDEIIR);
 451
 452         if (pch_iir & SDE_AUDIO_POWER_MASK)
 453                 DRM_DEBUG("i915: PCH audio power change on port %d\n",
 454                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 455                                  SDE_AUDIO_POWER_SHIFT);
 456
 457         if (pch_iir & SDE_GMBUS)
 458                 DRM_DEBUG("i915: PCH GMBUS interrupt\n");
 459
 460         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 461                 DRM_DEBUG("i915: PCH HDCP audio interrupt\n");
 462
 463         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 464                 DRM_DEBUG("i915: PCH transcoder audio interrupt\n");
 465
 466         if (pch_iir & SDE_POISON)
 467                 DRM_ERROR("i915: PCH poison interrupt\n");
 468
 469         if (pch_iir & SDE_FDI_MASK)
 470                 for_each_pipe(pipe)
 471                         DRM_DEBUG("  pipe %c FDI IIR: 0x%08x\n",
 472                                          pipe_name(pipe),
 473                                          I915_READ(FDI_RX_IIR(pipe)));
 474
 475         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 476                 DRM_DEBUG("i915: PCH transcoder CRC done interrupt\n");
 477
 478         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 479                 DRM_DEBUG("i915: PCH transcoder CRC error interrupt\n");
 480
 481         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 482                 DRM_DEBUG("i915: PCH transcoder B underrun interrupt\n");
 483         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 484                 DRM_DEBUG("PCH transcoder A underrun interrupt\n");
 485 }
 486
 487 static void
 488 ivybridge_irq_handler(void *arg)
 489 {
 490         struct drm_device *dev = (struct drm_device *) arg;
 491         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 492         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 493 #if 0
 494         struct drm_i915_master_private *master_priv;
 495 #endif
 496
 497         atomic_inc(&dev_priv->irq_received);
 498
 499         /* disable master interrupt before clearing iir  */
 500         de_ier = I915_READ(DEIER);
 501         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 502         POSTING_READ(DEIER);
 503
 504         de_iir = I915_READ(DEIIR);
 505         gt_iir = I915_READ(GTIIR);
 506         pch_iir = I915_READ(SDEIIR);
 507         pm_iir = I915_READ(GEN6_PMIIR);
 508
 509         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
 510                 goto done;
 511
 512 #if 0
 513         if (dev->primary->master) {
 514                 master_priv = dev->primary->master->driver_priv;
 515                 if (master_priv->sarea_priv)
 516                         master_priv->sarea_priv->last_dispatch =
 517                                 READ_BREADCRUMB(dev_priv);
 518         }
 519 #else
 520         if (dev_priv->sarea_priv)
 521                 dev_priv->sarea_priv->last_dispatch =
 522                     READ_BREADCRUMB(dev_priv);
 523 #endif
 524
 525         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 526                 notify_ring(dev, &dev_priv->rings[RCS]);
 527         if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
 528                 notify_ring(dev, &dev_priv->rings[VCS]);
 529         if (gt_iir & GT_GEN6_BLT_USER_INTERRUPT)
 530                 notify_ring(dev, &dev_priv->rings[BCS]);
 531
 532         if (de_iir & DE_GSE_IVB) {
 533 #if 1
 534                 KIB_NOTYET();
 535 #else
 536                 intel_opregion_gse_intr(dev);
 537 #endif
 538         }
 539
 540         if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
 541                 intel_prepare_page_flip(dev, 0);
 542                 intel_finish_page_flip_plane(dev, 0);
 543         }
 544
 545         if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
 546                 intel_prepare_page_flip(dev, 1);
 547                 intel_finish_page_flip_plane(dev, 1);
 548         }
 549
 550         if (de_iir & DE_PIPEA_VBLANK_IVB)
 551                 drm_handle_vblank(dev, 0);
 552
 553         if (de_iir & DE_PIPEB_VBLANK_IVB)
 554                 drm_handle_vblank(dev, 1);
 555
 556         /* check event from PCH */
 557         if (de_iir & DE_PCH_EVENT_IVB) {
 558                 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 559                         taskqueue_enqueue(dev_priv->tq, &dev_priv->hotplug_task);
 560                 pch_irq_handler(dev);
 561         }
 562
 563         if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 564                 lockmgr(&dev_priv->rps_lock, LK_EXCLUSIVE);
 565                 if ((dev_priv->pm_iir & pm_iir) != 0)
 566                         kprintf("Missed a PM interrupt\n");
 567                 dev_priv->pm_iir |= pm_iir;
 568                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 569                 POSTING_READ(GEN6_PMIMR);
 570                 lockmgr(&dev_priv->rps_lock, LK_RELEASE);
 571                 taskqueue_enqueue(dev_priv->tq, &dev_priv->rps_task);
 572         }
 573
 574         /* should clear PCH hotplug event before clear CPU irq */
 575         I915_WRITE(SDEIIR, pch_iir);
 576         I915_WRITE(GTIIR, gt_iir);
 577         I915_WRITE(DEIIR, de_iir);
 578         I915_WRITE(GEN6_PMIIR, pm_iir);
 579
 580 done:
 581         I915_WRITE(DEIER, de_ier);
 582         POSTING_READ(DEIER);
 583 }
 584
 585 static void
 586 ironlake_irq_handler(void *arg)
 587 {
 588         struct drm_device *dev = arg;
 589         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 590         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 591         u32 hotplug_mask;
 592 #if 0
 593         struct drm_i915_master_private *master_priv;
 594 #endif
 595         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 596
 597         atomic_inc(&dev_priv->irq_received);
 598
 599         if (IS_GEN6(dev))
 600                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 601
 602         /* disable master interrupt before clearing iir  */
 603         de_ier = I915_READ(DEIER);
 604         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 605         POSTING_READ(DEIER);
 606
 607         de_iir = I915_READ(DEIIR);
 608         gt_iir = I915_READ(GTIIR);
 609         pch_iir = I915_READ(SDEIIR);
 610         pm_iir = I915_READ(GEN6_PMIIR);
 611
 612         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 613             (!IS_GEN6(dev) || pm_iir == 0))
 614                 goto done;
 615
 616         if (HAS_PCH_CPT(dev))
 617                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 618         else
 619                 hotplug_mask = SDE_HOTPLUG_MASK;
 620
 621 #if 0
 622         if (dev->primary->master) {
 623                 master_priv = dev->primary->master->driver_priv;
 624                 if (master_priv->sarea_priv)
 625                         master_priv->sarea_priv->last_dispatch =
 626                                 READ_BREADCRUMB(dev_priv);
 627         }
 628 #else
 629                 if (dev_priv->sarea_priv)
 630                         dev_priv->sarea_priv->last_dispatch =
 631                             READ_BREADCRUMB(dev_priv);
 632 #endif
 633
 634         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 635                 notify_ring(dev, &dev_priv->rings[RCS]);
 636         if (gt_iir & bsd_usr_interrupt)
 637                 notify_ring(dev, &dev_priv->rings[VCS]);
 638         if (gt_iir & GT_GEN6_BLT_USER_INTERRUPT)
 639                 notify_ring(dev, &dev_priv->rings[BCS]);
 640
 641         if (de_iir & DE_GSE) {
 642 #if 1
 643                 KIB_NOTYET();
 644 #else
 645                 intel_opregion_gse_intr(dev);
 646 #endif
 647         }
 648
 649         if (de_iir & DE_PLANEA_FLIP_DONE) {
 650                 intel_prepare_page_flip(dev, 0);
 651                 intel_finish_page_flip_plane(dev, 0);
 652         }
 653
 654         if (de_iir & DE_PLANEB_FLIP_DONE) {
 655                 intel_prepare_page_flip(dev, 1);
 656                 intel_finish_page_flip_plane(dev, 1);
 657         }
 658
 659         if (de_iir & DE_PIPEA_VBLANK)
 660                 drm_handle_vblank(dev, 0);
 661
 662         if (de_iir & DE_PIPEB_VBLANK)
 663                 drm_handle_vblank(dev, 1);
 664
 665         /* check event from PCH */
 666         if (de_iir & DE_PCH_EVENT) {
 667                 if (pch_iir & hotplug_mask)
 668                         taskqueue_enqueue(dev_priv->tq,
 669                             &dev_priv->hotplug_task);
 670                 pch_irq_handler(dev);
 671         }
 672
 673         if (de_iir & DE_PCU_EVENT) {
 674                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 675                 i915_handle_rps_change(dev);
 676         }
 677
 678         if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 679                 lockmgr(&dev_priv->rps_lock, LK_EXCLUSIVE);
 680                 if ((dev_priv->pm_iir & pm_iir) != 0)
 681                         kprintf("Missed a PM interrupt\n");
 682                 dev_priv->pm_iir |= pm_iir;
 683                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 684                 POSTING_READ(GEN6_PMIMR);
 685                 lockmgr(&dev_priv->rps_lock, LK_RELEASE);
 686                 taskqueue_enqueue(dev_priv->tq, &dev_priv->rps_task);
 687         }
 688
 689         /* should clear PCH hotplug event before clear CPU irq */
 690         I915_WRITE(SDEIIR, pch_iir);
 691         I915_WRITE(GTIIR, gt_iir);
 692         I915_WRITE(DEIIR, de_iir);
 693         I915_WRITE(GEN6_PMIIR, pm_iir);
 694
 695 done:
 696         I915_WRITE(DEIER, de_ier);
 697         POSTING_READ(DEIER);
 698 }
 699
 700 /**
 701  * i915_error_work_func - do process context error handling work
 702  * @work: work struct
 703  *
 704  * Fire an error uevent so userspace can see that a hang or error
 705  * was detected.
 706  */
 707 static void
 708 i915_error_work_func(void *context, int pending)
 709 {
 710         drm_i915_private_t *dev_priv = context;
 711         struct drm_device *dev = dev_priv->dev;
 712
 713         /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); */
 714
 715         if (atomic_load_acq_int(&dev_priv->mm.wedged)) {
 716                 DRM_DEBUG("i915: resetting chip\n");
 717                 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); */
 718                 if (!i915_reset(dev, GRDOM_RENDER)) {
 719                         atomic_store_rel_int(&dev_priv->mm.wedged, 0);
 720                         /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); */
 721                 }
 722                 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
 723                 dev_priv->error_completion++;
 724                 wakeup(&dev_priv->error_completion);
 725                 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 726         }
 727 }
 728
 729 static void i915_report_and_clear_eir(struct drm_device *dev)
 730 {
 731         struct drm_i915_private *dev_priv = dev->dev_private;
 732         u32 eir = I915_READ(EIR);
 733         int pipe;
 734
 735         if (!eir)
 736                 return;
 737
 738         kprintf("i915: render error detected, EIR: 0x%08x\n", eir);
 739
 740         if (IS_G4X(dev)) {
 741                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 742                         u32 ipeir = I915_READ(IPEIR_I965);
 743
 744                         kprintf("  IPEIR: 0x%08x\n",
 745                                I915_READ(IPEIR_I965));
 746                         kprintf("  IPEHR: 0x%08x\n",
 747                                I915_READ(IPEHR_I965));
 748                         kprintf("  INSTDONE: 0x%08x\n",
 749                                I915_READ(INSTDONE_I965));
 750                         kprintf("  INSTPS: 0x%08x\n",
 751                                I915_READ(INSTPS));
 752                         kprintf("  INSTDONE1: 0x%08x\n",
 753                                I915_READ(INSTDONE1));
 754                         kprintf("  ACTHD: 0x%08x\n",
 755                                I915_READ(ACTHD_I965));
 756                         I915_WRITE(IPEIR_I965, ipeir);
 757                         POSTING_READ(IPEIR_I965);
 758                 }
 759                 if (eir & GM45_ERROR_PAGE_TABLE) {
 760                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 761                         kprintf("page table error\n");
 762                         kprintf("  PGTBL_ER: 0x%08x\n",
 763                                pgtbl_err);
 764                         I915_WRITE(PGTBL_ER, pgtbl_err);
 765                         POSTING_READ(PGTBL_ER);
 766                 }
 767         }
 768
 769         if (!IS_GEN2(dev)) {
 770                 if (eir & I915_ERROR_PAGE_TABLE) {
 771                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 772                         kprintf("page table error\n");
 773                         kprintf("  PGTBL_ER: 0x%08x\n",
 774                                pgtbl_err);
 775                         I915_WRITE(PGTBL_ER, pgtbl_err);
 776                         POSTING_READ(PGTBL_ER);
 777                 }
 778         }
 779
 780         if (eir & I915_ERROR_MEMORY_REFRESH) {
 781                 kprintf("memory refresh error:\n");
 782                 for_each_pipe(pipe)
 783                         kprintf("pipe %c stat: 0x%08x\n",
 784                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
 785                 /* pipestat has already been acked */
 786         }
 787         if (eir & I915_ERROR_INSTRUCTION) {
 788                 kprintf("instruction error\n");
 789                 kprintf("  INSTPM: 0x%08x\n",
 790                        I915_READ(INSTPM));
 791                 if (INTEL_INFO(dev)->gen < 4) {
 792                         u32 ipeir = I915_READ(IPEIR);
 793
 794                         kprintf("  IPEIR: 0x%08x\n",
 795                                I915_READ(IPEIR));
 796                         kprintf("  IPEHR: 0x%08x\n",
 797                                I915_READ(IPEHR));
 798                         kprintf("  INSTDONE: 0x%08x\n",
 799                                I915_READ(INSTDONE));
 800                         kprintf("  ACTHD: 0x%08x\n",
 801                                I915_READ(ACTHD));
 802                         I915_WRITE(IPEIR, ipeir);
 803                         POSTING_READ(IPEIR);
 804                 } else {
 805                         u32 ipeir = I915_READ(IPEIR_I965);
 806
 807                         kprintf("  IPEIR: 0x%08x\n",
 808                                I915_READ(IPEIR_I965));
 809                         kprintf("  IPEHR: 0x%08x\n",
 810                                I915_READ(IPEHR_I965));
 811                         kprintf("  INSTDONE: 0x%08x\n",
 812                                I915_READ(INSTDONE_I965));
 813                         kprintf("  INSTPS: 0x%08x\n",
 814                                I915_READ(INSTPS));
 815                         kprintf("  INSTDONE1: 0x%08x\n",
 816                                I915_READ(INSTDONE1));
 817                         kprintf("  ACTHD: 0x%08x\n",
 818                                I915_READ(ACTHD_I965));
 819                         I915_WRITE(IPEIR_I965, ipeir);
 820                         POSTING_READ(IPEIR_I965);
 821                 }
 822         }
 823
 824         I915_WRITE(EIR, eir);
 825         POSTING_READ(EIR);
 826         eir = I915_READ(EIR);
 827         if (eir) {
 828                 /*
 829                  * some errors might have become stuck,
 830                  * mask them.
 831                  */
 832                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 833                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 834                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 835         }
 836 }
 837
 838 /**
 839  * i915_handle_error - handle an error interrupt
 840  * @dev: drm device
 841  *
 842  * Do some basic checking of regsiter state at error interrupt time and
 843  * dump it to the syslog.  Also call i915_capture_error_state() to make
 844  * sure we get a record and make it available in debugfs.  Fire a uevent
 845  * so userspace knows something bad happened (should trigger collection
 846  * of a ring dump etc.).
 847  */
 848 void i915_handle_error(struct drm_device *dev, bool wedged)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851
 852         i915_capture_error_state(dev);
 853         i915_report_and_clear_eir(dev);
 854
 855         if (wedged) {
 856                 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
 857                 dev_priv->error_completion = 0;
 858                 dev_priv->mm.wedged = 1;
 859                 /* unlock acts as rel barrier for store to wedged */
 860                 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 861
 862                 /*
 863                  * Wakeup waiting processes so they don't hang
 864                  */
 865                 lockmgr(&dev_priv->rings[RCS].irq_lock, LK_EXCLUSIVE);
 866                 wakeup(&dev_priv->rings[RCS]);
 867                 lockmgr(&dev_priv->rings[RCS].irq_lock, LK_RELEASE);
 868                 if (HAS_BSD(dev)) {
 869                         lockmgr(&dev_priv->rings[VCS].irq_lock, LK_EXCLUSIVE);
 870                         wakeup(&dev_priv->rings[VCS]);
 871                         lockmgr(&dev_priv->rings[VCS].irq_lock, LK_RELEASE);
 872                 }
 873                 if (HAS_BLT(dev)) {
 874                         lockmgr(&dev_priv->rings[BCS].irq_lock, LK_EXCLUSIVE);
 875                         wakeup(&dev_priv->rings[BCS]);
 876                         lockmgr(&dev_priv->rings[BCS].irq_lock, LK_RELEASE);
 877                 }
 878         }
 879
 880         taskqueue_enqueue(dev_priv->tq, &dev_priv->error_task);
 881 }
 882
 883 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 884 {
 885         drm_i915_private_t *dev_priv = dev->dev_private;
 886         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 888         struct drm_i915_gem_object *obj;
 889         struct intel_unpin_work *work;
 890         bool stall_detected;
 891
 892         /* Ignore early vblank irqs */
 893         if (intel_crtc == NULL)
 894                 return;
 895
 896         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
 897         work = intel_crtc->unpin_work;
 898
 899         if (work == NULL || work->pending || !work->enable_stall_check) {
 900                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
 901                 lockmgr(&dev->event_lock, LK_RELEASE);
 902                 return;
 903         }
 904
 905         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 906         obj = work->pending_flip_obj;
 907         if (INTEL_INFO(dev)->gen >= 4) {
 908                 int dspsurf = DSPSURF(intel_crtc->plane);
 909                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
 910         } else {
 911                 int dspaddr = DSPADDR(intel_crtc->plane);
 912                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
 913                                                         crtc->y * crtc->fb->pitches[0] +
 914                                                         crtc->x * crtc->fb->bits_per_pixel/8);
 915         }
 916
 917         lockmgr(&dev->event_lock, LK_RELEASE);
 918
 919         if (stall_detected) {
 920                 DRM_DEBUG("Pageflip stall detected\n");
 921                 intel_prepare_page_flip(dev, intel_crtc->plane);
 922         }
 923 }
 924
 925 static void
 926 i915_driver_irq_handler(void *arg)
 927 {
 928         struct drm_device *dev = (struct drm_device *)arg;
 929         drm_i915_private_t *dev_priv = (drm_i915_private_t *)dev->dev_private;
 930 #if 0
 931         struct drm_i915_master_private *master_priv;
 932 #endif
 933         u32 iir, new_iir;
 934         u32 pipe_stats[I915_MAX_PIPES];
 935         u32 vblank_status;
 936         int vblank = 0;
 937         int irq_received;
 938         int pipe;
 939         bool blc_event = false;
 940
 941         atomic_inc(&dev_priv->irq_received);
 942
 943         iir = I915_READ(IIR);
 944
 945         if (INTEL_INFO(dev)->gen >= 4)
 946                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
 947         else
 948                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
 949
 950         for (;;) {
 951                 irq_received = iir != 0;
 952
 953                 /* Can't rely on pipestat interrupt bit in iir as it might
 954                  * have been cleared after the pipestat interrupt was received.
 955                  * It doesn't set the bit in iir again, but it still produces
 956                  * interrupts (for non-MSI).
 957                  */
 958                 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 959                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 960                         i915_handle_error(dev, false);
 961
 962                 for_each_pipe(pipe) {
 963                         int reg = PIPESTAT(pipe);
 964                         pipe_stats[pipe] = I915_READ(reg);
 965
 966                         /*
 967                          * Clear the PIPE*STAT regs before the IIR
 968                          */
 969                         if (pipe_stats[pipe] & 0x8000ffff) {
 970                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 971                                         DRM_DEBUG("pipe %c underrun\n",
 972                                                          pipe_name(pipe));
 973                                 I915_WRITE(reg, pipe_stats[pipe]);
 974                                 irq_received = 1;
 975                         }
 976                 }
 977                 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 978
 979                 if (!irq_received)
 980                         break;
 981
 982                 /* Consume port.  Then clear IIR or we'll miss events */
 983                 if ((I915_HAS_HOTPLUG(dev)) &&
 984                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 985                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 986
 987                         DRM_DEBUG("i915: hotplug event received, stat 0x%08x\n",
 988                                   hotplug_status);
 989                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 990                                 taskqueue_enqueue(dev_priv->tq,
 991                                     &dev_priv->hotplug_task);
 992
 993                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 994                         I915_READ(PORT_HOTPLUG_STAT);
 995                 }
 996
 997                 I915_WRITE(IIR, iir);
 998                 new_iir = I915_READ(IIR); /* Flush posted writes */
 999
1000 #if 0
1001                 if (dev->primary->master) {
1002                         master_priv = dev->primary->master->driver_priv;
1003                         if (master_priv->sarea_priv)
1004                                 master_priv->sarea_priv->last_dispatch =
1005                                         READ_BREADCRUMB(dev_priv);
1006                 }
1007 #else
1008                 if (dev_priv->sarea_priv)
1009                         dev_priv->sarea_priv->last_dispatch =
1010                             READ_BREADCRUMB(dev_priv);
1011 #endif
1012
1013                 if (iir & I915_USER_INTERRUPT)
1014                         notify_ring(dev, &dev_priv->rings[RCS]);
1015                 if (iir & I915_BSD_USER_INTERRUPT)
1016                         notify_ring(dev, &dev_priv->rings[VCS]);
1017
1018                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1019                         intel_prepare_page_flip(dev, 0);
1020                         if (dev_priv->flip_pending_is_done)
1021                                 intel_finish_page_flip_plane(dev, 0);
1022                 }
1023
1024                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1025                         intel_prepare_page_flip(dev, 1);
1026                         if (dev_priv->flip_pending_is_done)
1027                                 intel_finish_page_flip_plane(dev, 1);
1028                 }
1029
1030                 for_each_pipe(pipe) {
1031                         if (pipe_stats[pipe] & vblank_status &&
1032                             drm_handle_vblank(dev, pipe)) {
1033                                 vblank++;
1034                                 if (!dev_priv->flip_pending_is_done) {
1035                                         i915_pageflip_stall_check(dev, pipe);
1036                                         intel_finish_page_flip(dev, pipe);
1037                                 }
1038                         }
1039
1040                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1041                                 blc_event = true;
1042                 }
1043
1044
1045                 if (blc_event || (iir & I915_ASLE_INTERRUPT)) {
1046 #if 1
1047                         KIB_NOTYET();
1048 #else
1049                         intel_opregion_asle_intr(dev);
1050 #endif
1051                 }
1052
1053                 /* With MSI, interrupts are only generated when iir
1054                  * transitions from zero to nonzero.  If another bit got
1055                  * set while we were handling the existing iir bits, then
1056                  * we would never get another interrupt.
1057                  *
1058                  * This is fine on non-MSI as well, as if we hit this path
1059                  * we avoid exiting the interrupt handler only to generate
1060                  * another one.
1061                  *
1062                  * Note that for MSI this could cause a stray interrupt report
1063                  * if an interrupt landed in the time between writing IIR and
1064                  * the posting read.  This should be rare enough to never
1065                  * trigger the 99% of 100,000 interrupts test for disabling
1066                  * stray interrupts.
1067                  */
1068                 iir = new_iir;
1069         }
1070 }
1071
1072 static int i915_emit_irq(struct drm_device * dev)
1073 {
1074         drm_i915_private_t *dev_priv = dev->dev_private;
1075 #if 0
1076         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1077 #endif
1078
1079         i915_kernel_lost_context(dev);
1080
1081         DRM_DEBUG("i915: emit_irq\n");
1082
1083         dev_priv->counter++;
1084         if (dev_priv->counter > 0x7FFFFFFFUL)
1085                 dev_priv->counter = 1;
1086 #if 0
1087         if (master_priv->sarea_priv)
1088                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1089 #else
1090         if (dev_priv->sarea_priv)
1091                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
1092 #endif
1093
1094         if (BEGIN_LP_RING(4) == 0) {
1095                 OUT_RING(MI_STORE_DWORD_INDEX);
1096                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1097                 OUT_RING(dev_priv->counter);
1098                 OUT_RING(MI_USER_INTERRUPT);
1099                 ADVANCE_LP_RING();
1100         }
1101
1102         return dev_priv->counter;
1103 }
1104
1105 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1106 {
1107         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1108 #if 0
1109         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1110 #endif
1111         int ret;
1112         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1113
1114         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
1115                   READ_BREADCRUMB(dev_priv));
1116
1117 #if 0
1118         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1119                 if (master_priv->sarea_priv)
1120                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1121                 return 0;
1122         }
1123
1124         if (master_priv->sarea_priv)
1125                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1126 #else
1127         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1128                 if (dev_priv->sarea_priv) {
1129                         dev_priv->sarea_priv->last_dispatch =
1130                                 READ_BREADCRUMB(dev_priv);
1131                 }
1132                 return 0;
1133         }
1134
1135         if (dev_priv->sarea_priv)
1136                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1137 #endif
1138
1139         ret = 0;
1140         lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
1141         if (ring->irq_get(ring)) {
1142                 DRM_UNLOCK(dev);
1143                 while (ret == 0 && READ_BREADCRUMB(dev_priv) < irq_nr) {
1144                         ret = -lksleep(ring, &ring->irq_lock, PCATCH,
1145                             "915wtq", 3 * hz);
1146                 }
1147                 ring->irq_put(ring);
1148                 lockmgr(&ring->irq_lock, LK_RELEASE);
1149                 DRM_LOCK(dev);
1150         } else {
1151                 lockmgr(&ring->irq_lock, LK_RELEASE);
1152                 if (_intel_wait_for(dev, READ_BREADCRUMB(dev_priv) >= irq_nr,
1153                      3000, 1, "915wir"))
1154                         ret = -EBUSY;
1155         }
1156
1157         if (ret == -EBUSY) {
1158                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1159                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1160         }
1161
1162         return ret;
1163 }
1164
1165 /* Needs the lock as it touches the ring.
1166  */
1167 int i915_irq_emit(struct drm_device *dev, void *data,
1168                          struct drm_file *file_priv)
1169 {
1170         drm_i915_private_t *dev_priv = dev->dev_private;
1171         drm_i915_irq_emit_t *emit = data;
1172         int result;
1173
1174         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1175                 DRM_ERROR("called with no initialization\n");
1176                 return -EINVAL;
1177         }
1178
1179         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1180
1181         DRM_LOCK(dev);
1182         result = i915_emit_irq(dev);
1183         DRM_UNLOCK(dev);
1184
1185         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1186                 DRM_ERROR("copy_to_user\n");
1187                 return -EFAULT;
1188         }
1189
1190         return 0;
1191 }
1192
1193 /* Doesn't need the hardware lock.
1194  */
1195 int i915_irq_wait(struct drm_device *dev, void *data,
1196                          struct drm_file *file_priv)
1197 {
1198         drm_i915_private_t *dev_priv = dev->dev_private;
1199         drm_i915_irq_wait_t *irqwait = data;
1200
1201         if (!dev_priv) {
1202                 DRM_ERROR("called with no initialization\n");
1203                 return -EINVAL;
1204         }
1205
1206         return i915_wait_irq(dev, irqwait->irq_seq);
1207 }
1208
1209 /* Called from drm generic code, passed 'crtc' which
1210  * we use as a pipe index
1211  */
1212 static int
1213 i915_enable_vblank(struct drm_device *dev, int pipe)
1214 {
1215         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1216
1217         if (!i915_pipe_enabled(dev, pipe))
1218                 return -EINVAL;
1219
1220         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1221         if (INTEL_INFO(dev)->gen >= 4)
1222                 i915_enable_pipestat(dev_priv, pipe,
1223                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1224         else
1225                 i915_enable_pipestat(dev_priv, pipe,
1226                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1227
1228         /* maintain vblank delivery even in deep C-states */
1229         if (dev_priv->info->gen == 3)
1230                 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1231         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1232
1233         return 0;
1234 }
1235
1236 static int
1237 ironlake_enable_vblank(struct drm_device *dev, int pipe)
1238 {
1239         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1240
1241         if (!i915_pipe_enabled(dev, pipe))
1242                 return -EINVAL;
1243
1244         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1245         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1246             DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1247         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1248
1249         return 0;
1250 }
1251
1252 static int
1253 ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1254 {
1255         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1256
1257         if (!i915_pipe_enabled(dev, pipe))
1258                 return -EINVAL;
1259
1260         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1261         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1262                                     DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1263         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1264
1265         return 0;
1266 }
1267
1268
1269 /* Called from drm generic code, passed 'crtc' which
1270  * we use as a pipe index
1271  */
1272 static void
1273 i915_disable_vblank(struct drm_device *dev, int pipe)
1274 {
1275         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1276
1277         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1278         if (dev_priv->info->gen == 3)
1279                 I915_WRITE(INSTPM,
1280                            INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1281
1282         i915_disable_pipestat(dev_priv, pipe,
1283             PIPE_VBLANK_INTERRUPT_ENABLE |
1284             PIPE_START_VBLANK_INTERRUPT_ENABLE);
1285         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1286 }
1287
1288 static void
1289 ironlake_disable_vblank(struct drm_device *dev, int pipe)
1290 {
1291         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1292
1293         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1294         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1295             DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1296         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1297 }
1298
1299 static void
1300 ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1301 {
1302         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1303
1304         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1305         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1306                                      DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1307         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1308 }
1309
1310 /* Set the vblank monitor pipe
1311  */
1312 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1313                          struct drm_file *file_priv)
1314 {
1315         drm_i915_private_t *dev_priv = dev->dev_private;
1316
1317         if (!dev_priv) {
1318                 DRM_ERROR("called with no initialization\n");
1319                 return -EINVAL;
1320         }
1321
1322         return 0;
1323 }
1324
1325 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1326                          struct drm_file *file_priv)
1327 {
1328         drm_i915_private_t *dev_priv = dev->dev_private;
1329         drm_i915_vblank_pipe_t *pipe = data;
1330
1331         if (!dev_priv) {
1332                 DRM_ERROR("called with no initialization\n");
1333                 return -EINVAL;
1334         }
1335
1336         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1337
1338         return 0;
1339 }
1340
1341 /**
1342  * Schedule buffer swap at given vertical blank.
1343  */
1344 int i915_vblank_swap(struct drm_device *dev, void *data,
1345                      struct drm_file *file_priv)
1346 {
1347         /* The delayed swap mechanism was fundamentally racy, and has been
1348          * removed.  The model was that the client requested a delayed flip/swap
1349          * from the kernel, then waited for vblank before continuing to perform
1350          * rendering.  The problem was that the kernel might wake the client
1351          * up before it dispatched the vblank swap (since the lock has to be
1352          * held while touching the ringbuffer), in which case the client would
1353          * clear and start the next frame before the swap occurred, and
1354          * flicker would occur in addition to likely missing the vblank.
1355          *
1356          * In the absence of this ioctl, userland falls back to a correct path
1357          * of waiting for a vblank, then dispatching the swap on its own.
1358          * Context switching to userland and back is plenty fast enough for
1359          * meeting the requirements of vblank swapping.
1360          */
1361         return -EINVAL;
1362 }
1363
1364 static u32
1365 ring_last_seqno(struct intel_ring_buffer *ring)
1366 {
1367
1368         if (list_empty(&ring->request_list))
1369                 return (0);
1370         else
1371                 return (list_entry(ring->request_list.prev,
1372                     struct drm_i915_gem_request, list)->seqno);
1373 }
1374
1375 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1376 {
1377         if (list_empty(&ring->request_list) ||
1378             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1379                 /* Issue a wake-up to catch stuck h/w. */
1380                 if (ring->waiting_seqno) {
1381                         DRM_ERROR(
1382 "Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1383                                   ring->name,
1384                                   ring->waiting_seqno,
1385                                   ring->get_seqno(ring));
1386                         wakeup(ring);
1387                         *err = true;
1388                 }
1389                 return true;
1390         }
1391         return false;
1392 }
1393
1394 static bool kick_ring(struct intel_ring_buffer *ring)
1395 {
1396         struct drm_device *dev = ring->dev;
1397         struct drm_i915_private *dev_priv = dev->dev_private;
1398         u32 tmp = I915_READ_CTL(ring);
1399         if (tmp & RING_WAIT) {
1400                 DRM_ERROR("Kicking stuck wait on %s\n",
1401                           ring->name);
1402                 I915_WRITE_CTL(ring, tmp);
1403                 return true;
1404         }
1405         return false;
1406 }
1407
1408 /**
1409  * This is called when the chip hasn't reported back with completed
1410  * batchbuffers in a long time. The first time this is called we simply record
1411  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1412  * again, we assume the chip is wedged and try to fix it.
1413  */
1414 void
1415 i915_hangcheck_elapsed(void *context)
1416 {
1417         struct drm_device *dev = (struct drm_device *)context;
1418         drm_i915_private_t *dev_priv = dev->dev_private;
1419         uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
1420         bool err = false;
1421
1422         if (!i915_enable_hangcheck)
1423                 return;
1424
1425         /* If all work is done then ACTHD clearly hasn't advanced. */
1426         if (i915_hangcheck_ring_idle(&dev_priv->rings[RCS], &err) &&
1427             i915_hangcheck_ring_idle(&dev_priv->rings[VCS], &err) &&
1428             i915_hangcheck_ring_idle(&dev_priv->rings[BCS], &err)) {
1429                 dev_priv->hangcheck_count = 0;
1430                 if (err)
1431                         goto repeat;
1432                 return;
1433         }
1434
1435         if (INTEL_INFO(dev)->gen < 4) {
1436                 instdone = I915_READ(INSTDONE);
1437                 instdone1 = 0;
1438         } else {
1439                 instdone = I915_READ(INSTDONE_I965);
1440                 instdone1 = I915_READ(INSTDONE1);
1441         }
1442         acthd = intel_ring_get_active_head(&dev_priv->rings[RCS]);
1443         acthd_bsd = HAS_BSD(dev) ?
1444                 intel_ring_get_active_head(&dev_priv->rings[VCS]) : 0;
1445         acthd_blt = HAS_BLT(dev) ?
1446                 intel_ring_get_active_head(&dev_priv->rings[BCS]) : 0;
1447
1448         if (dev_priv->last_acthd == acthd &&
1449             dev_priv->last_acthd_bsd == acthd_bsd &&
1450             dev_priv->last_acthd_blt == acthd_blt &&
1451             dev_priv->last_instdone == instdone &&
1452             dev_priv->last_instdone1 == instdone1) {
1453                 if (dev_priv->hangcheck_count++ > 1) {
1454                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1455                         i915_handle_error(dev, true);
1456
1457                         if (!IS_GEN2(dev)) {
1458                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1459                                  * If so we can simply poke the RB_WAIT bit
1460                                  * and break the hang. This should work on
1461                                  * all but the second generation chipsets.
1462                                  */
1463                                 if (kick_ring(&dev_priv->rings[RCS]))
1464                                         goto repeat;
1465
1466                                 if (HAS_BSD(dev) &&
1467                                     kick_ring(&dev_priv->rings[VCS]))
1468                                         goto repeat;
1469
1470                                 if (HAS_BLT(dev) &&
1471                                     kick_ring(&dev_priv->rings[BCS]))
1472                                         goto repeat;
1473                         }
1474
1475                         return;
1476                 }
1477         } else {
1478                 dev_priv->hangcheck_count = 0;
1479
1480                 dev_priv->last_acthd = acthd;
1481                 dev_priv->last_acthd_bsd = acthd_bsd;
1482                 dev_priv->last_acthd_blt = acthd_blt;
1483                 dev_priv->last_instdone = instdone;
1484                 dev_priv->last_instdone1 = instdone1;
1485         }
1486
1487 repeat:
1488         /* Reset timer case chip hangs without another request being added */
1489         callout_reset(&dev_priv->hangcheck_timer, DRM_I915_HANGCHECK_PERIOD,
1490             i915_hangcheck_elapsed, dev);
1491 }
1492
1493 /* drm_dma.h hooks
1494 */
1495 static void
1496 ironlake_irq_preinstall(struct drm_device *dev)
1497 {
1498         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1499
1500         atomic_set(&dev_priv->irq_received, 0);
1501
1502         TASK_INIT(&dev_priv->hotplug_task, 0, i915_hotplug_work_func,
1503             dev->dev_private);
1504         TASK_INIT(&dev_priv->error_task, 0, i915_error_work_func,
1505             dev->dev_private);
1506         TASK_INIT(&dev_priv->rps_task, 0, gen6_pm_rps_work_func,
1507             dev->dev_private);
1508
1509         I915_WRITE(HWSTAM, 0xeffe);
1510
1511         /* XXX hotplug from PCH */
1512
1513         I915_WRITE(DEIMR, 0xffffffff);
1514         I915_WRITE(DEIER, 0x0);
1515         POSTING_READ(DEIER);
1516
1517         /* and GT */
1518         I915_WRITE(GTIMR, 0xffffffff);
1519         I915_WRITE(GTIER, 0x0);
1520         POSTING_READ(GTIER);
1521
1522         /* south display irq */
1523         I915_WRITE(SDEIMR, 0xffffffff);
1524         I915_WRITE(SDEIER, 0x0);
1525         POSTING_READ(SDEIER);
1526 }
1527
1528 /*
1529  * Enable digital hotplug on the PCH, and configure the DP short pulse
1530  * duration to 2ms (which is the minimum in the Display Port spec)
1531  *
1532  * This register is the same on all known PCH chips.
1533  */
1534
1535 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1536 {
1537         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1538         u32     hotplug;
1539
1540         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1541         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1542         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1543         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1544         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1545         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1546 }
1547
1548 static int ironlake_irq_postinstall(struct drm_device *dev)
1549 {
1550         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1551         /* enable kind of interrupts always enabled */
1552         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1553                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1554         u32 render_irqs;
1555         u32 hotplug_mask;
1556
1557         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1558         dev_priv->irq_mask = ~display_mask;
1559
1560         /* should always can generate irq */
1561         I915_WRITE(DEIIR, I915_READ(DEIIR));
1562         I915_WRITE(DEIMR, dev_priv->irq_mask);
1563         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1564         POSTING_READ(DEIER);
1565
1566         dev_priv->gt_irq_mask = ~0;
1567
1568         I915_WRITE(GTIIR, I915_READ(GTIIR));
1569         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1570
1571         if (IS_GEN6(dev))
1572                 render_irqs =
1573                         GT_USER_INTERRUPT |
1574                         GT_GEN6_BSD_USER_INTERRUPT |
1575                         GT_GEN6_BLT_USER_INTERRUPT;
1576         else
1577                 render_irqs =
1578                         GT_USER_INTERRUPT |
1579                         GT_PIPE_NOTIFY |
1580                         GT_BSD_USER_INTERRUPT;
1581         I915_WRITE(GTIER, render_irqs);
1582         POSTING_READ(GTIER);
1583
1584         if (HAS_PCH_CPT(dev)) {
1585                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1586                                 SDE_PORTB_HOTPLUG_CPT |
1587                                 SDE_PORTC_HOTPLUG_CPT |
1588                                 SDE_PORTD_HOTPLUG_CPT);
1589         } else {
1590                 hotplug_mask = (SDE_CRT_HOTPLUG |
1591                                 SDE_PORTB_HOTPLUG |
1592                                 SDE_PORTC_HOTPLUG |
1593                                 SDE_PORTD_HOTPLUG |
1594                                 SDE_AUX_MASK);
1595         }
1596
1597         dev_priv->pch_irq_mask = ~hotplug_mask;
1598
1599         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1600         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1601         I915_WRITE(SDEIER, hotplug_mask);
1602         POSTING_READ(SDEIER);
1603
1604         ironlake_enable_pch_hotplug(dev);
1605
1606         if (IS_IRONLAKE_M(dev)) {
1607                 /* Clear & enable PCU event interrupts */
1608                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1609                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1610                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1611         }
1612
1613         return 0;
1614 }
1615
1616 static int
1617 ivybridge_irq_postinstall(struct drm_device *dev)
1618 {
1619         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1620         /* enable kind of interrupts always enabled */
1621         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1622                 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1623                 DE_PLANEB_FLIP_DONE_IVB;
1624         u32 render_irqs;
1625         u32 hotplug_mask;
1626
1627         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1628         dev_priv->irq_mask = ~display_mask;
1629
1630         /* should always can generate irq */
1631         I915_WRITE(DEIIR, I915_READ(DEIIR));
1632         I915_WRITE(DEIMR, dev_priv->irq_mask);
1633         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1634                    DE_PIPEB_VBLANK_IVB);
1635         POSTING_READ(DEIER);
1636
1637         dev_priv->gt_irq_mask = ~0;
1638
1639         I915_WRITE(GTIIR, I915_READ(GTIIR));
1640         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1641
1642         render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
1643                 GT_GEN6_BLT_USER_INTERRUPT;
1644         I915_WRITE(GTIER, render_irqs);
1645         POSTING_READ(GTIER);
1646
1647         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1648                         SDE_PORTB_HOTPLUG_CPT |
1649                         SDE_PORTC_HOTPLUG_CPT |
1650                         SDE_PORTD_HOTPLUG_CPT);
1651         dev_priv->pch_irq_mask = ~hotplug_mask;
1652
1653         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1654         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1655         I915_WRITE(SDEIER, hotplug_mask);
1656         POSTING_READ(SDEIER);
1657
1658         ironlake_enable_pch_hotplug(dev);
1659
1660         return 0;
1661 }
1662
1663 static void
1664 i915_driver_irq_preinstall(struct drm_device * dev)
1665 {
1666         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1667         int pipe;
1668
1669         atomic_set(&dev_priv->irq_received, 0);
1670
1671         TASK_INIT(&dev_priv->hotplug_task, 0, i915_hotplug_work_func,
1672             dev->dev_private);
1673         TASK_INIT(&dev_priv->error_task, 0, i915_error_work_func,
1674             dev->dev_private);
1675         TASK_INIT(&dev_priv->rps_task, 0, gen6_pm_rps_work_func,
1676             dev->dev_private);
1677
1678         if (I915_HAS_HOTPLUG(dev)) {
1679                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1680                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1681         }
1682
1683         I915_WRITE(HWSTAM, 0xeffe);
1684         for_each_pipe(pipe)
1685                 I915_WRITE(PIPESTAT(pipe), 0);
1686         I915_WRITE(IMR, 0xffffffff);
1687         I915_WRITE(IER, 0x0);
1688         POSTING_READ(IER);
1689 }
1690
1691 /*
1692  * Must be called after intel_modeset_init or hotplug interrupts won't be
1693  * enabled correctly.
1694  */
1695 static int
1696 i915_driver_irq_postinstall(struct drm_device *dev)
1697 {
1698         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1699         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1700         u32 error_mask;
1701
1702         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1703
1704         /* Unmask the interrupts that we always want on. */
1705         dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1706
1707         dev_priv->pipestat[0] = 0;
1708         dev_priv->pipestat[1] = 0;
1709
1710         if (I915_HAS_HOTPLUG(dev)) {
1711                 /* Enable in IER... */
1712                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1713                 /* and unmask in IMR */
1714                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1715         }
1716
1717         /*
1718          * Enable some error detection, note the instruction error mask
1719          * bit is reserved, so we leave it masked.
1720          */
1721         if (IS_G4X(dev)) {
1722                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1723                                GM45_ERROR_MEM_PRIV |
1724                                GM45_ERROR_CP_PRIV |
1725                                I915_ERROR_MEMORY_REFRESH);
1726         } else {
1727                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1728                                I915_ERROR_MEMORY_REFRESH);
1729         }
1730         I915_WRITE(EMR, error_mask);
1731
1732         I915_WRITE(IMR, dev_priv->irq_mask);
1733         I915_WRITE(IER, enable_mask);
1734         POSTING_READ(IER);
1735
1736         if (I915_HAS_HOTPLUG(dev)) {
1737                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1738
1739                 /* Note HDMI and DP share bits */
1740                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1741                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1742                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1743                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1744                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1745                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1746                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
1747                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1748                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
1749                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1750                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1751                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1752
1753                         /* Programming the CRT detection parameters tends
1754                            to generate a spurious hotplug event about three
1755                            seconds later.  So just do it once.
1756                         */
1757                         if (IS_G4X(dev))
1758                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1759                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1760                 }
1761
1762                 /* Ignore TV since it's buggy */
1763
1764                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1765         }
1766
1767 #if 1
1768         KIB_NOTYET();
1769 #else
1770         intel_opregion_enable_asle(dev);
1771 #endif
1772
1773         return 0;
1774 }
1775
1776 static void
1777 ironlake_irq_uninstall(struct drm_device *dev)
1778 {
1779         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1780
1781         if (dev_priv == NULL)
1782                 return;
1783
1784         dev_priv->vblank_pipe = 0;
1785
1786         I915_WRITE(HWSTAM, 0xffffffff);
1787
1788         I915_WRITE(DEIMR, 0xffffffff);
1789         I915_WRITE(DEIER, 0x0);
1790         I915_WRITE(DEIIR, I915_READ(DEIIR));
1791
1792         I915_WRITE(GTIMR, 0xffffffff);
1793         I915_WRITE(GTIER, 0x0);
1794         I915_WRITE(GTIIR, I915_READ(GTIIR));
1795
1796         I915_WRITE(SDEIMR, 0xffffffff);
1797         I915_WRITE(SDEIER, 0x0);
1798         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1799
1800         taskqueue_drain(dev_priv->tq, &dev_priv->hotplug_task);
1801         taskqueue_drain(dev_priv->tq, &dev_priv->error_task);
1802         taskqueue_drain(dev_priv->tq, &dev_priv->rps_task);
1803 }
1804
1805 static void i915_driver_irq_uninstall(struct drm_device * dev)
1806 {
1807         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1808         int pipe;
1809
1810         if (!dev_priv)
1811                 return;
1812
1813         dev_priv->vblank_pipe = 0;
1814
1815         if (I915_HAS_HOTPLUG(dev)) {
1816                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1817                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1818         }
1819
1820         I915_WRITE(HWSTAM, 0xffffffff);
1821         for_each_pipe(pipe)
1822                 I915_WRITE(PIPESTAT(pipe), 0);
1823         I915_WRITE(IMR, 0xffffffff);
1824         I915_WRITE(IER, 0x0);
1825
1826         for_each_pipe(pipe)
1827                 I915_WRITE(PIPESTAT(pipe),
1828                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
1829         I915_WRITE(IIR, I915_READ(IIR));
1830
1831         taskqueue_drain(dev_priv->tq, &dev_priv->hotplug_task);
1832         taskqueue_drain(dev_priv->tq, &dev_priv->error_task);
1833         taskqueue_drain(dev_priv->tq, &dev_priv->rps_task);
1834 }
1835
1836 void
1837 intel_irq_init(struct drm_device *dev)
1838 {
1839
1840         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1841         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1842         if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
1843                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1844                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1845         }
1846
1847         if (drm_core_check_feature(dev, DRIVER_MODESET))
1848                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
1849         else
1850                 dev->driver->get_vblank_timestamp = NULL;
1851         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
1852
1853         if (IS_IVYBRIDGE(dev)) {
1854                 /* Share pre & uninstall handlers with ILK/SNB */
1855                 dev->driver->irq_handler = ivybridge_irq_handler;
1856                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
1857                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
1858                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
1859                 dev->driver->enable_vblank = ivybridge_enable_vblank;
1860                 dev->driver->disable_vblank = ivybridge_disable_vblank;
1861         } else if (HAS_PCH_SPLIT(dev)) {
1862                 dev->driver->irq_handler = ironlake_irq_handler;
1863                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
1864                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
1865                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
1866                 dev->driver->enable_vblank = ironlake_enable_vblank;
1867                 dev->driver->disable_vblank = ironlake_disable_vblank;
1868         } else {
1869                 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
1870                 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
1871                 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
1872                 dev->driver->irq_handler = i915_driver_irq_handler;
1873                 dev->driver->enable_vblank = i915_enable_vblank;
1874                 dev->driver->disable_vblank = i915_disable_vblank;
1875         }
1876 }
1877
1878 static struct drm_i915_error_object *
1879 i915_error_object_create(struct drm_i915_private *dev_priv,
1880     struct drm_i915_gem_object *src)
1881 {
1882         struct drm_i915_error_object *dst;
1883         struct sf_buf *sf;
1884         void *d, *s;
1885         int page, page_count;
1886         u32 reloc_offset;
1887
1888         if (src == NULL || src->pages == NULL)
1889                 return NULL;
1890
1891         page_count = src->base.size / PAGE_SIZE;
1892
1893         dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), DRM_I915_GEM,
1894             M_NOWAIT);
1895         if (dst == NULL)
1896                 return (NULL);
1897
1898         reloc_offset = src->gtt_offset;
1899         for (page = 0; page < page_count; page++) {
1900                 d = kmalloc(PAGE_SIZE, DRM_I915_GEM, M_NOWAIT);
1901                 if (d == NULL)
1902                         goto unwind;
1903
1904                 if (reloc_offset < dev_priv->mm.gtt_mappable_end) {
1905                         /* Simply ignore tiling or any overlapping fence.
1906                          * It's part of the error state, and this hopefully
1907                          * captures what the GPU read.
1908                          */
1909                         s = pmap_mapdev_attr(src->base.dev->agp->base +
1910                             reloc_offset, PAGE_SIZE, PAT_WRITE_COMBINING);
1911                         memcpy(d, s, PAGE_SIZE);
1912                         pmap_unmapdev((vm_offset_t)s, PAGE_SIZE);
1913                 } else {
1914                         drm_clflush_pages(&src->pages[page], 1);
1915
1916                         sf = sf_buf_alloc(src->pages[page]);
1917                         if (sf != NULL) {
1918                                 s = (void *)(uintptr_t)sf_buf_kva(sf);
1919                                 memcpy(d, s, PAGE_SIZE);
1920                                 sf_buf_free(sf);
1921                         } else {
1922                                 bzero(d, PAGE_SIZE);
1923                                 strcpy(d, "XXXKIB");
1924                         }
1925
1926                         drm_clflush_pages(&src->pages[page], 1);
1927                 }
1928
1929                 dst->pages[page] = d;
1930
1931                 reloc_offset += PAGE_SIZE;
1932         }
1933         dst->page_count = page_count;
1934         dst->gtt_offset = src->gtt_offset;
1935
1936         return (dst);
1937
1938 unwind:
1939         while (page--)
1940                 drm_free(dst->pages[page], DRM_I915_GEM);
1941         drm_free(dst, DRM_I915_GEM);
1942         return (NULL);
1943 }
1944
1945 static void
1946 i915_error_object_free(struct drm_i915_error_object *obj)
1947 {
1948         int page;
1949
1950         if (obj == NULL)
1951                 return;
1952
1953         for (page = 0; page < obj->page_count; page++)
1954                 drm_free(obj->pages[page], DRM_I915_GEM);
1955
1956         drm_free(obj, DRM_I915_GEM);
1957 }
1958
1959 static void
1960 i915_error_state_free(struct drm_device *dev,
1961                       struct drm_i915_error_state *error)
1962 {
1963         int i;
1964
1965         for (i = 0; i < DRM_ARRAY_SIZE(error->ring); i++) {
1966                 i915_error_object_free(error->ring[i].batchbuffer);
1967                 i915_error_object_free(error->ring[i].ringbuffer);
1968                 drm_free(error->ring[i].requests, DRM_I915_GEM);
1969         }
1970
1971         drm_free(error->active_bo, DRM_I915_GEM);
1972         drm_free(error->overlay, DRM_I915_GEM);
1973         drm_free(error, DRM_I915_GEM);
1974 }
1975
1976 static u32
1977 capture_bo_list(struct drm_i915_error_buffer *err, int count,
1978     struct list_head *head)
1979 {
1980         struct drm_i915_gem_object *obj;
1981         int i = 0;
1982
1983         list_for_each_entry(obj, head, mm_list) {
1984                 err->size = obj->base.size;
1985                 err->name = obj->base.name;
1986                 err->seqno = obj->last_rendering_seqno;
1987                 err->gtt_offset = obj->gtt_offset;
1988                 err->read_domains = obj->base.read_domains;
1989                 err->write_domain = obj->base.write_domain;
1990                 err->fence_reg = obj->fence_reg;
1991                 err->pinned = 0;
1992                 if (obj->pin_count > 0)
1993                         err->pinned = 1;
1994                 if (obj->user_pin_count > 0)
1995                         err->pinned = -1;
1996                 err->tiling = obj->tiling_mode;
1997                 err->dirty = obj->dirty;
1998                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1999                 err->ring = obj->ring ? obj->ring->id : -1;
2000                 err->cache_level = obj->cache_level;
2001
2002                 if (++i == count)
2003                         break;
2004
2005                 err++;
2006         }
2007
2008         return (i);
2009 }
2010
2011 static void
2012 i915_gem_record_fences(struct drm_device *dev,
2013     struct drm_i915_error_state *error)
2014 {
2015         struct drm_i915_private *dev_priv = dev->dev_private;
2016         int i;
2017
2018         /* Fences */
2019         switch (INTEL_INFO(dev)->gen) {
2020         case 7:
2021         case 6:
2022                 for (i = 0; i < 16; i++)
2023                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
2024                 break;
2025         case 5:
2026         case 4:
2027                 for (i = 0; i < 16; i++)
2028                         error->fence[i] = I915_READ64(FENCE_REG_965_0 +
2029                             (i * 8));
2030                 break;
2031         case 3:
2032                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2033                         for (i = 0; i < 8; i++)
2034                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
2035                                     (i * 4));
2036         case 2:
2037                 for (i = 0; i < 8; i++)
2038                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
2039                 break;
2040
2041         }
2042 }
2043
2044 static struct drm_i915_error_object *
2045 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
2046                              struct intel_ring_buffer *ring)
2047 {
2048         struct drm_i915_gem_object *obj;
2049         u32 seqno;
2050
2051         if (!ring->get_seqno)
2052                 return (NULL);
2053
2054         seqno = ring->get_seqno(ring);
2055         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
2056                 if (obj->ring != ring)
2057                         continue;
2058
2059                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
2060                         continue;
2061
2062                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
2063                         continue;
2064
2065                 /* We need to copy these to an anonymous buffer as the simplest
2066                  * method to avoid being overwritten by userspace.
2067                  */
2068                 return (i915_error_object_create(dev_priv, obj));
2069         }
2070
2071         return NULL;
2072 }
2073
2074 static void
2075 i915_record_ring_state(struct drm_device *dev,
2076     struct drm_i915_error_state *error,
2077     struct intel_ring_buffer *ring)
2078 {
2079         struct drm_i915_private *dev_priv = dev->dev_private;
2080
2081         if (INTEL_INFO(dev)->gen >= 6) {
2082                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
2083                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
2084                 error->semaphore_mboxes[ring->id][0]
2085                         = I915_READ(RING_SYNC_0(ring->mmio_base));
2086                 error->semaphore_mboxes[ring->id][1]
2087                         = I915_READ(RING_SYNC_1(ring->mmio_base));
2088         }
2089
2090         if (INTEL_INFO(dev)->gen >= 4) {
2091                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
2092                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
2093                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
2094                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
2095                 if (ring->id == RCS) {
2096                         error->instdone1 = I915_READ(INSTDONE1);
2097                         error->bbaddr = I915_READ64(BB_ADDR);
2098                 }
2099         } else {
2100                 error->ipeir[ring->id] = I915_READ(IPEIR);
2101                 error->ipehr[ring->id] = I915_READ(IPEHR);
2102                 error->instdone[ring->id] = I915_READ(INSTDONE);
2103         }
2104
2105         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
2106         error->seqno[ring->id] = ring->get_seqno(ring);
2107         error->acthd[ring->id] = intel_ring_get_active_head(ring);
2108         error->head[ring->id] = I915_READ_HEAD(ring);
2109         error->tail[ring->id] = I915_READ_TAIL(ring);
2110
2111         error->cpu_ring_head[ring->id] = ring->head;
2112         error->cpu_ring_tail[ring->id] = ring->tail;
2113 }
2114
2115 static void
2116 i915_gem_record_rings(struct drm_device *dev,
2117     struct drm_i915_error_state *error)
2118 {
2119         struct drm_i915_private *dev_priv = dev->dev_private;
2120         struct drm_i915_gem_request *request;
2121         int i, count;
2122
2123         for (i = 0; i < I915_NUM_RINGS; i++) {
2124                 struct intel_ring_buffer *ring = &dev_priv->rings[i];
2125
2126                 if (ring->obj == NULL)
2127                         continue;
2128
2129                 i915_record_ring_state(dev, error, ring);
2130
2131                 error->ring[i].batchbuffer =
2132                         i915_error_first_batchbuffer(dev_priv, ring);
2133
2134                 error->ring[i].ringbuffer =
2135                         i915_error_object_create(dev_priv, ring->obj);
2136
2137                 count = 0;
2138                 list_for_each_entry(request, &ring->request_list, list)
2139                         count++;
2140
2141                 error->ring[i].num_requests = count;
2142                 error->ring[i].requests = kmalloc(count *
2143                     sizeof(struct drm_i915_error_request), DRM_I915_GEM,
2144                     M_WAITOK);
2145                 if (error->ring[i].requests == NULL) {
2146                         error->ring[i].num_requests = 0;
2147                         continue;
2148                 }
2149
2150                 count = 0;
2151                 list_for_each_entry(request, &ring->request_list, list) {
2152                         struct drm_i915_error_request *erq;
2153
2154                         erq = &error->ring[i].requests[count++];
2155                         erq->seqno = request->seqno;
2156                         erq->jiffies = request->emitted_jiffies;
2157                         erq->tail = request->tail;
2158                 }
2159         }
2160 }
2161
2162 static void
2163 i915_capture_error_state(struct drm_device *dev)
2164 {
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct drm_i915_gem_object *obj;
2167         struct drm_i915_error_state *error;
2168         int i, pipe;
2169
2170         lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE);
2171         error = dev_priv->first_error;
2172         lockmgr(&dev_priv->error_lock, LK_RELEASE);
2173         if (error != NULL)
2174                 return;
2175
2176         /* Account for pipe specific data like PIPE*STAT */
2177         error = kmalloc(sizeof(*error), DRM_I915_GEM, M_NOWAIT | M_ZERO);
2178         if (error == NULL) {
2179                 DRM_DEBUG("out of memory, not capturing error state\n");
2180                 return;
2181         }
2182
2183         DRM_INFO("capturing error event; look for more information in "
2184             "sysctl hw.dri.%d.info.i915_error_state\n", dev->sysctl_node_idx);
2185
2186         error->eir = I915_READ(EIR);
2187         error->pgtbl_er = I915_READ(PGTBL_ER);
2188         for_each_pipe(pipe)
2189                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
2190
2191         if (INTEL_INFO(dev)->gen >= 6) {
2192                 error->error = I915_READ(ERROR_GEN6);
2193                 error->done_reg = I915_READ(DONE_REG);
2194         }
2195
2196         i915_gem_record_fences(dev, error);
2197         i915_gem_record_rings(dev, error);
2198
2199         /* Record buffers on the active and pinned lists. */
2200         error->active_bo = NULL;
2201         error->pinned_bo = NULL;
2202
2203         i = 0;
2204         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
2205                 i++;
2206         error->active_bo_count = i;
2207         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
2208                 i++;
2209         error->pinned_bo_count = i - error->active_bo_count;
2210
2211         error->active_bo = NULL;
2212         error->pinned_bo = NULL;
2213         if (i) {
2214                 error->active_bo = kmalloc(sizeof(*error->active_bo) * i,
2215                     DRM_I915_GEM, M_NOWAIT);
2216                 if (error->active_bo)
2217                         error->pinned_bo = error->active_bo +
2218                             error->active_bo_count;
2219         }
2220
2221         if (error->active_bo)
2222                 error->active_bo_count = capture_bo_list(error->active_bo,
2223                     error->active_bo_count, &dev_priv->mm.active_list);
2224
2225         if (error->pinned_bo)
2226                 error->pinned_bo_count = capture_bo_list(error->pinned_bo,
2227                     error->pinned_bo_count, &dev_priv->mm.pinned_list);
2228
2229         microtime(&error->time);
2230
2231         error->overlay = intel_overlay_capture_error_state(dev);
2232         error->display = intel_display_capture_error_state(dev);
2233
2234         lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE);
2235         if (dev_priv->first_error == NULL) {
2236                 dev_priv->first_error = error;
2237                 error = NULL;
2238         }
2239         lockmgr(&dev_priv->error_lock, LK_RELEASE);
2240
2241         if (error != NULL)
2242                 i915_error_state_free(dev, error);
2243 }
2244
2245 void
2246 i915_destroy_error_state(struct drm_device *dev)
2247 {
2248         struct drm_i915_private *dev_priv = dev->dev_private;
2249         struct drm_i915_error_state *error;
2250
2251         lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE);
2252         error = dev_priv->first_error;
2253         dev_priv->first_error = NULL;
2254         lockmgr(&dev_priv->error_lock, LK_RELEASE);
2255
2256         if (error != NULL)
2257                 i915_error_state_free(dev, error);
2258 }