2 * $FreeBSD: src/sys/boot/alpha/libalpha/pal.S,v 1.2.2.1 2001/08/03 07:14:52 obrien Exp $
3 * From: $NetBSD: pal.s,v 1.12 1998/02/27 03:44:53 thorpej Exp $
7 * Copyright (c) 1994, 1995 Carnegie-Mellon University.
10 * Author: Chris G. Demetriou
12 * Permission to use, copy, modify and distribute this software and
13 * its documentation is hereby granted, provided that both the copyright
14 * notice and this permission notice appear in all copies of the
15 * software, derivative works or modified versions, and any portions
16 * thereof, and that both notices appear in supporting documentation.
18 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
19 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
20 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
22 * Carnegie Mellon requests users of this software to return to
24 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
25 * School of Computer Science
26 * Carnegie Mellon University
27 * Pittsburgh PA 15213-3890
29 * any improvements or extensions that they make and grant Carnegie the
30 * rights to redistribute these changes.
34 * The various OSF PALcode routines.
36 * The following code is originally derived from pages: (I) 6-5 - (I) 6-7
37 * and (III) 2-1 - (III) 2-25 of "Alpha Architecture Reference Manual" by
40 * Updates taken from pages: (II-B) 2-1 - (II-B) 2-33 of "Alpha AXP
41 * Architecture Reference Manual, Second Edition" by Richard L. Sites
42 * and Richard T. Witek.
45 #include <machine/asm.h>
47 /*inc2: .stabs __FILE__,132,0,0,inc2; .loc 1 __LINE__*/
48 inc2: .stabs __FILE__,132,0,0,inc2
50 * alpha_rpcc: read process cycle counter (XXX INSTRUCTION, NOT PALcode OP)
59 * alpha_mb: memory barrier (XXX INSTRUCTION, NOT PALcode OP)
68 * alpha_wmb: write memory barrier (XXX INSTRUCTION, NOT PALcode OP)
78 * alpha_amask: read architecture features (XXX INSTRUCTION, NOT PALcode OP)
81 * a0 bitmask of features to test
84 * v0 bitmask - bit is _cleared_ if feature is supported
93 * alpha_implver: read implementation version (XXX INSTRUCTION, NOT PALcode OP)
96 * v0 implementation version - see <machine/alpha_cpu.h>
103 .long 0x47e03d80 /* XXX gas(1) does the Wrong Thing */
109 * alpha_pal_imb: I-Stream memory barrier. [UNPRIVILEGED]
110 * (Makes instruction stream coherent with data stream.)
113 LEAF(alpha_pal_imb,0)
119 * alpha_pal_cflush: Cache flush [PRIVILEGED]
121 * Flush the entire physical page specified by the PFN specified in
122 * a0 from any data caches associated with the current processor.
125 * a0 page frame number of page to flush
128 LEAF(alpha_pal_cflush,1)
131 END(alpha_pal_cflush)
134 * alpha_pal_draina: Drain aborts. [PRIVILEGED]
137 LEAF(alpha_pal_draina,0)
140 END(alpha_pal_draina)
143 * alpha_pal_halt: Halt the processor. [PRIVILEGED]
146 LEAF(alpha_pal_halt,0)
148 br zero,alpha_pal_halt /* Just in case */
153 * alpha_pal_rdmces: Read MCES processor register. [PRIVILEGED]
156 * v0 current MCES value
159 LEAF(alpha_pal_rdmces,1)
160 call_pal PAL_OSF1_rdmces
162 END(alpha_pal_rdmces)
165 * alpha_pal_rdps: Read processor status. [PRIVILEGED]
168 * v0 current PS value
171 LEAF(alpha_pal_rdps,0)
172 call_pal PAL_OSF1_rdps
177 * alpha_pal_rdusp: Read user stack pointer. [PRIVILEGED]
180 * v0 current user stack pointer
183 LEAF(alpha_pal_rdusp,0)
184 call_pal PAL_OSF1_rdusp
189 * alpha_pal_rdval: Read system value. [PRIVILEGED]
191 * Returns the sysvalue in v0, allowing access to a 64-bit
192 * per-processor value for use by the operating system.
198 LEAF(alpha_pal_rdval,0)
199 call_pal PAL_OSF1_rdval
204 * alpha_pal_swpipl: Swap Interrupt priority level. [PRIVILEGED]
205 * _alpha_pal_swpipl: Same, from profiling code. [PRIVILEGED]
214 LEAF(alpha_pal_swpipl,1)
215 call_pal PAL_OSF1_swpipl
217 END(alpha_pal_swpipl)
219 LEAF_NOPROFILE(_alpha_pal_swpipl,1)
220 call_pal PAL_OSF1_swpipl
222 END(_alpha_pal_swpipl)
225 * alpha_pal_tbi: Translation buffer invalidate. [PRIVILEGED]
228 * a0 operation selector
229 * a1 address to operate on (if necessary)
232 LEAF(alpha_pal_tbi,2)
233 call_pal PAL_OSF1_tbi
238 * alpha_pal_whami: Who am I? [PRIVILEGED]
241 * v0 processor number
244 LEAF(alpha_pal_whami,0)
245 call_pal PAL_OSF1_whami
250 * alpha_pal_wrent: Write system entry address. [PRIVILEGED]
257 LEAF(alpha_pal_wrent,2)
258 call_pal PAL_OSF1_wrent
263 * alpha_pal_wrfen: Write floating-point enable. [PRIVILEGED]
266 * a0 new enable value (val & 0x1 -> enable).
269 LEAF(alpha_pal_wrfen,1)
270 call_pal PAL_OSF1_wrfen
275 * alpha_pal_wripir: Write interprocessor interrupt request. [PRIVILEGED]
277 * Generate an interprocessor interrupt on the processor specified by
278 * processor number in a0.
281 * a0 processor to interrupt
284 LEAF(alpha_pal_wripir,1)
287 END(alpha_pal_wripir)
290 * alpha_pal_wrusp: Write user stack pointer. [PRIVILEGED]
293 * a0 new user stack pointer
296 LEAF(alpha_pal_wrusp,1)
297 call_pal PAL_OSF1_wrusp
302 * alpha_pal_wrvptptr: Write virtual page table pointer. [PRIVILEGED]
305 * a0 new virtual page table pointer
308 LEAF(alpha_pal_wrvptptr,1)
309 call_pal PAL_OSF1_wrvptptr
311 END(alpha_pal_wrvptptr)
314 * alpha_pal_wrmces: Write MCES processor register. [PRIVILEGED]
317 * a0 value to write to MCES
320 LEAF(alpha_pal_wrmces,1)
321 call_pal PAL_OSF1_wrmces
323 END(alpha_pal_wrmces)
326 * alpha_pal_wrval: Write system value. [PRIVILEGED]
328 * Write the value passed in a0 to this processor's sysvalue.
331 * a0 value to write to sysvalue
333 LEAF(alpha_pal_wrval,1)
334 call_pal PAL_OSF1_wrval
339 * alpha_pal_swpctx: Swap context. [PRIVILEGED]
341 * Switch to a new process context.
344 * a0 physical address of hardware PCB describing context
347 * v0 physical address of hardware PCB describing previous context
349 LEAF(alpha_pal_swpctx,1)
350 call_pal PAL_OSF1_swpctx
352 END(alpha_pal_swpctx)