2 * Copyright (c) 1994 Charles Hannum.
3 * Copyright (c) 1994 Jarle Greipsland.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Jarle Greipsland
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
23 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
29 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/dev/aic/aic6360reg.h,v 1.1 1999/10/21 08:56:52 luoqi Exp $
35 #define SCSISEQ 0x00 /* SCSI sequence control */
36 #define SXFRCTL0 0x01 /* SCSI transfer control 0 */
37 #define SXFRCTL1 0x02 /* SCSI transfer control 1 */
38 #define SCSISIGI 0x03 /* SCSI signal in */
39 #define SCSISIGO 0x03 /* SCSI signal out */
40 #define SCSIRATE 0x04 /* SCSI rate control */
41 #define SCSIID 0x05 /* SCSI ID */
42 #define SELID 0x05 /* Selection/Reselection ID */
43 #define SCSIDAT 0x06 /* SCSI Latched Data */
44 #define SCSIBUS 0x07 /* SCSI Data Bus*/
45 #define STCNT0 0x08 /* SCSI transfer count */
48 #define CLRSINT0 0x0b /* Clear SCSI interrupts 0 */
49 #define SSTAT0 0x0b /* SCSI interrupt status 0 */
50 #define CLRSINT1 0x0c /* Clear SCSI interrupts 1 */
51 #define SSTAT1 0x0c /* SCSI status 1 */
52 #define SSTAT2 0x0d /* SCSI status 2 */
53 #define SCSITEST 0x0e /* SCSI test control */
54 #define SSTAT3 0x0e /* SCSI status 3 */
55 #define CLRSERR 0x0f /* Clear SCSI errors */
56 #define SSTAT4 0x0f /* SCSI status 4 */
57 #define SIMODE0 0x10 /* SCSI interrupt mode 0 */
58 #define SIMODE1 0x11 /* SCSI interrupt mode 1 */
59 #define DMACNTRL0 0x12 /* DMA control 0 */
60 #define DMACNTRL1 0x13 /* DMA control 1 */
61 #define DMASTAT 0x14 /* DMA status */
62 #define FIFOSTAT 0x15 /* FIFO status */
63 #define DMADATA 0x16 /* DMA data */
64 #define DMADATAL 0x16 /* DMA data low byte */
65 #define DMADATAH 0x17 /* DMA data high byte */
66 #define BRSTCNTRL 0x18 /* Burst Control */
67 #define DMADATALONG 0x18
68 #define PORTA 0x1a /* Port A */
69 #define PORTB 0x1b /* Port B */
70 #define REV 0x1c /* Revision (001 for 6360) */
71 #define STACK 0x1d /* Stack */
72 #define TEST 0x1e /* Test register */
73 #define ID 0x1f /* ID register */
75 #define IDSTRING "(C)1991ADAPTECAIC6360 "
77 /* What all the bits do */
84 #define ENAUTOATNO 0x08
85 #define ENAUTOATNI 0x04
86 #define ENAUTOATNP 0x02
98 #define BITBUCKET 0x80
101 #define STIMESEL1 0x10
102 #define STIMESEL0 0x08
103 #define STIMO_256ms 0x00
104 #define STIMO_128ms 0x08
105 #define STIMO_64ms 0x10
106 #define STIMO_32ms 0x18
107 #define ENSTIMER 0x04
108 #define BYTEALIGN 0x02
120 /* Important! The 3 most significant bits of this register, in initiator mode,
121 * represents the "expected" SCSI bus phase and can be used to trigger phase
122 * mismatch and phase change interrupts. But more important: If there is a
123 * phase mismatch the chip will not transfer any data! This is actually a nice
124 * feature as it gives us a bit more control over what is happening when we are
125 * bursting data (in) through the FIFOs and the phase suddenly changes from
126 * DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the
127 * proper phase to be set in this register instead of dumping the bits into the
140 /* Information transfer phases */
141 #define PH_DATAOUT (0)
142 #define PH_DATAIN (IOI)
144 #define PH_STAT (CDI|IOI)
145 #define PH_MSGOUT (MSGI|CDI)
146 #define PH_MSGIN (MSGI|CDI|IOI)
147 #define PH_MASK (MSGI|CDI|IOI)
162 #define OID_S 4 /* shift value */
166 #define SCSI_ID_MASK 0x7
168 /* SCSI selection/reselection ID (both target *and* initiator) */
178 /* CLRSINT0 Clears what? (interrupt and/or status bit) */
179 #define SETSDONE 0x80
180 #define CLRSELDO 0x40 /* I */
181 #define CLRSELDI 0x20 /* I+ */
182 #define CLRSELINGO 0x10 /* I */
183 #define CLRSWRAP 0x08 /* I+S */
184 #define CLRSDONE 0x04 /* I+S */
185 #define CLRSPIORDY 0x02 /* I */
186 #define CLRDMADONE 0x01 /* I */
188 /* SSTAT0 Howto clear */
190 #define SELDO 0x40 /* Selfclearing */
191 #define SELDI 0x20 /* Selfclearing when CLRSELDI is set */
192 #define SELINGO 0x10 /* Selfclearing */
193 #define SWRAP 0x08 /* CLRSWAP */
194 #define SDONE 0x04 /* Not used in initiator mode */
195 #define SPIORDY 0x02 /* Selfclearing (op on SCSIDAT) */
196 #define DMADONE 0x01 /* Selfclearing (all FIFOs empty & T/C */
198 /* CLRSINT1 Clears what? */
199 #define CLRSELTIMO 0x80 /* I+S */
201 #define CLRSCSIRSTI 0x20 /* I+S */
202 #define CLRBUSFREE 0x08 /* I+S */
203 #define CLRSCSIPERR 0x04 /* I+S */
204 #define CLRPHASECHG 0x02 /* I+S */
205 #define CLRREQINIT 0x01 /* I+S */
207 /* SSTAT1 How to clear? When set?*/
208 #define SELTO 0x80 /* C select out timeout */
209 #define ATNTARG 0x40 /* Not used in initiator mode */
210 #define SCSIRSTI 0x20 /* C RST asserted */
211 #define PHASEMIS 0x10 /* Selfclearing */
212 #define BUSFREE 0x08 /* C bus free condition */
213 #define SCSIPERR 0x04 /* C parity error on inbound data */
214 #define PHASECHG 0x02 /* C phase in SCSISIGI doesn't match */
215 #define REQINIT 0x01 /* C or ACK asserting edge of REQ */
231 #define SCSICNT3 0x80
232 #define SCSICNT2 0x40
233 #define SCSICNT1 0x20
234 #define SCSICNT0 0x10
241 #define CLRSYNCERR 0x04
242 #define CLRFWERR 0x02
243 #define CLRFRERR 0x01
253 #define ENSELINGO 0x10
256 #define ENSPIORDY 0x02
257 #define ENDMADONE 0x01
260 #define ENSELTIMO 0x80
261 #define ENATNTARG 0x40
262 #define ENSCSIRST 0x20
263 #define ENPHASEMIS 0x10
264 #define ENBUSFREE 0x08
265 #define ENSCSIPERR 0x04
266 #define ENPHASECHG 0x02
267 #define ENREQINIT 0x01
273 #define DWORDPIO 0x10
292 #define DFIFOFULL 0x10
293 #define DFIFOEMP 0x08
295 #define DWORDRDY 0x02
317 #define PORTA_ID(a) ((a) & 7)
318 #define PORTA_IRQ(a) ((((a) >> 3) & 3) + 9)
319 #define PORTA_DRQ(a) ((((a) >> 5) & 3) ? (((a) >> 5) & 3) + 4 : 0)
320 #define PORTA_PARITY(a) ((a) & 0x80)
323 #define PORTB_DISC(b) ((b) & 4)
324 #define PORTB_SYNC(b) ((b) & 8)
325 #define PORTB_BOOT(b) ((b) & 0x40)
326 #define PORTB_DMA(b) ((b) & 0x80)
328 /* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */
329 #define EISA_BRST_TIM ((15<<4) + 1) /* 15us on, 1us off */