4 * Tekram DC395U/UW/F ,DC315/U
5 * PCI SCSI Bus Master Host Adapter Device Driver
6 * (SCSI chip set used Tekram ASIC TRM-S1040)
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * $FreeBSD: src/sys/dev/trm/trm.h,v 1.1.2.2 2002/12/19 20:34:46 cognet Exp $
38 #define TRM_TRANS_CUR 0x01 /* Modify current neogtiation status */
39 #define TRM_TRANS_ACTIVE 0x03 /* Assume this is the active target */
40 #define TRM_TRANS_GOAL 0x04 /* Modify negotiation goal */
41 #define TRM_TRANS_USER 0x08 /* Modify user negotiation settings */
43 struct trm_transinfo {
49 struct trm_target_info {
50 u_int8_t disc_tag; /* bits define..... */
51 #define TRM_CUR_DISCENB 0x01 /* current setting disconnect enable */
52 #define TRM_CUR_TAGENB 0x02 /* current setting tag command Q enable */
53 #define TRM_USR_DISCENB 0x04 /* user adapter device setting disconnect enable */
54 #define TRM_USR_TAGENB 0x08 /* user adapter device setting tag command Q enable*/
55 struct trm_transinfo current; /* info of current */
56 struct trm_transinfo goal; /* info of after negotiating */
57 struct trm_transinfo user; /* info of user adapter device setting */
66 * Describes a single contiguous DMA transaction. Values
67 * are suitable for programming into DMA registers.
69 *typedef struct bus_dma_segment
71 * bus_addr_t ds_addr; // DMA address
72 * bus_size_t ds_len; // length of transfer
76 /*;----------------------Segment Entry------------------------------------*/
77 typedef struct _SGentry {
82 *-----------------------------------------------------------------------
83 * feature of chip set MAX value
84 *-----------------------------------------------------------------------
87 #define MAX_ADAPTER_NUM 4
88 #define MAX_DEVICES 16
89 #define MAX_SG_LISTENTRY 32
90 #define MAX_TARGETS 16
91 #define MAX_TAGS_CMD_QUEUE 32 /* MAX_CMD_QUEUE 20*/
92 #define MAX_CMD_PER_LUN 32
93 #define MAX_SRB_CNT MAX_CMD_PER_LUN*4
94 #define MAX_START_JOB MAX_CMD_PER_LUN*4
95 #define TRM_NSEG (btoc(MAXPHYS) + 1)
96 #define TRM_MAXTRANSFER_SIZE 0xFFFFFF /* restricted by 24 bit counter */
99 #define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40MHz) */
103 * Union of all CCB types for kernel space allocation. This union should
104 * never be used for manipulating CCBs - its only use is for the allocation
105 * and deallocation of raw CCB space and is the return type of xpt_ccb_alloc
106 * and the argument to xpt_ccb_free.
109 * struct ccb_hdr ccb_h; // For convenience
110 * struct ccb_scsiio csio;
111 * struct ccb_getdev cgd;
112 * struct ccb_getdevlist cgdl;
113 * struct ccb_pathinq cpi;
114 * struct ccb_relsim crs;
115 * struct ccb_setasync csa;
116 * struct ccb_setdev csd;
117 * struct ccb_dev_match cdm;
118 * struct ccb_trans_settings cts;
119 * struct ccb_calc_geometry ccg;
120 * struct ccb_abort cab;
121 * struct ccb_resetbus crb;
122 * struct ccb_resetdev crd;
123 * struct ccb_termio tio;
124 * struct ccb_accept_tio atio;
125 * struct ccb_scsiio ctio;
126 * struct ccb_en_lun cel;
127 * struct ccb_immed_notify cin;
128 * struct ccb_notify_ack cna;
129 * struct ccb_eng_inq cei;
130 * struct ccb_eng_exec cee;
131 * struct ccb_rescan crcn;
132 * struct ccb_debug cdbg;
137 *-----------------------------------------------------------------------
139 *-----------------------------------------------------------------------
142 u_int8_t CmdBlock[12];
146 struct _SRB *pNextSRB;
147 struct _DCB *pSRBDCB;
148 SGentry SegmentX[MAX_SG_LISTENTRY];
155 PSEG SRBSGListPointer; /* scatter gather list */
156 u_long SRBTotalXferLength;
157 u_long SRBSGPhyAddr; /* a segment starting address */
163 u_int8_t MsgInBuf[6];
164 u_int8_t MsgOutBuf[6];
166 u_int8_t AdaptStatus;
167 u_int8_t TargetStatus;
173 /* b0-AutoReqSense,b6-Read,b7-write */
174 /* b4-settimeout,b5-Residual valid */
178 u_int8_t Reserved[3]; /*;for dword alignment */
180 typedef struct _SRB TRM_SRB, *PSRB;
183 *-----------------------------------------------------------------------
184 * Device Control Block
185 *-----------------------------------------------------------------------
189 struct _DCB *pNextDCB;
190 struct _ACB *pDCBACB;
203 u_int16_t GoingSRBCnt;
204 u_int16_t WaitSRBCnt;
206 u_int8_t TargetID; /*; SCSI Target ID (SCSI Only) */
207 u_int8_t TargetLUN; /*; SCSI Log. Unit (SCSI Only) */
211 u_int8_t SyncMode; /* mode ? (1 sync):(0 async) */
212 u_int8_t MaxNegoPeriod; /* for nego. */
213 u_int8_t SyncPeriod; /* for reg. */
214 u_int8_t SyncOffset; /* for reg. and nego.(low nibble) */
216 struct trm_target_info tinfo; /* 10 bytes */
218 u_int16_t MaxCommand;
222 u_int8_t IdentifyMsg;
223 u_int8_t Reserved[3]; /*for dword alignment */
225 typedef struct _DCB TRM_DCB, *PDCB;
228 *-----------------------------------------------------------------------
229 * Adapter Control Block
230 *-----------------------------------------------------------------------
235 bus_space_handle_t bsh;
236 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
237 struct _ACB *pNextACB;
239 struct resource *iores, *irq;
244 struct cam_sim *psim;
245 struct cam_path *ppath;
247 TRM_SRB SRB_array[MAX_SRB_CNT]; /* */
265 u_int16_t IOPortBase;
266 u_int16_t AdapterUnit; /*; nth Adapter this driver */
268 u_int8_t msgin123[4];
270 u_int8_t scan_devices[16][8];
272 u_int8_t AdaptSCSIID; /*; Adapter SCSI Target ID */
273 u_int8_t AdaptSCSILUN; /*; Adapter SCSI LUN */
279 u_int8_t Reserved[2]; /* for dword alignment */
281 typedef struct _ACB TRM_ACB, *PACB;
283 * ----SRB State machine definition
285 #define SRB_FREE 0x0000
286 #define SRB_WAIT 0x0001
287 #define SRB_READY 0x0002
288 #define SRB_MSGOUT 0x0004 /*arbitration+msg_out 1st byte*/
289 #define SRB_MSGIN 0x0008
290 #define SRB_EXTEND_MSGIN 0x0010
291 #define SRB_COMMAND 0x0020
292 #define SRB_START_ 0x0040 /*arbitration+msg_out+command_out*/
293 #define SRB_DISCONNECT 0x0080
294 #define SRB_DATA_XFER 0x0100
295 #define SRB_XFERPAD 0x0200
296 #define SRB_STATUS 0x0400
297 #define SRB_COMPLETED 0x0800
298 #define SRB_ABORT_SENT 0x1000
299 #define SRB_DO_SYNC_NEGO 0x2000
300 #define SRB_DO_WIDE_NEGO 0x4000
301 #define SRB_UNEXPECT_RESEL 0x8000
307 #define HCC_WIDE_CARD 0x20
308 #define HCC_SCSI_RESET 0x10
309 #define HCC_PARITY 0x08
310 #define HCC_AUTOTERM 0x04
311 #define HCC_LOW8TERM 0x02
312 #define HCC_UP8TERM 0x01
316 #define RESET_DEV 0x00000001
317 #define RESET_DETECT 0x00000002
318 #define RESET_DONE 0x00000004
323 #define ABORT_DEV_ 0x00000001
328 #define SRB_OK 0x00000001
329 #define ABORTION 0x00000002
330 #define OVER_RUN 0x00000004
331 #define UNDER_RUN 0x00000008
332 #define PARITY_ERROR 0x00000010
333 #define SRB_ERROR 0x00000020
338 #define DATAOUT 0x00000080
339 #define DATAIN 0x00000040
340 #define RESIDUAL_VALID 0x00000020
341 #define ENABLE_TIMER 0x00000010
342 #define RESET_DEV0 0x00000004
343 #define ABORT_DEV 0x00000002
344 #define AUTO_REQSENSE 0x00000001
349 #define H_STATUS_GOOD 0x00
350 #define H_SEL_TIMEOUT 0x11
351 #define H_OVER_UNDER_RUN 0x12
352 #define H_UNEXP_BUS_FREE 0x13
353 #define H_TARGET_PHASE_F 0x14
354 #define H_INVALID_CCB_OP 0x16
355 #define H_LINK_CCB_BAD 0x17
356 #define H_BAD_TARGET_DIR 0x18
357 #define H_DUPLICATE_CCB 0x19
358 #define H_BAD_CCB_OR_SG 0x1A
359 #define H_ABORT 0x0FF
362 * ---SCSI Status byte codes
364 #define SCSI_STAT_GOOD 0x00 /*; Good status */
365 #define SCSI_STAT_CHECKCOND 0x02 /*; SCSI Check Condition */
366 #define SCSI_STAT_CONDMET 0x04 /*; Condition Met */
367 #define SCSI_STAT_BUSY 0x08 /*; Target busy status */
368 #define SCSI_STAT_INTER 0x10 /*; Intermediate status */
369 #define SCSI_STAT_INTERCONDMET 0x14 /*; Intermediate condition met */
370 #define SCSI_STAT_RESCONFLICT 0x18 /*; Reservation conflict */
371 #define SCSI_STAT_CMDTERM 0x22 /*; Command Terminated */
372 #define SCSI_STAT_QUEUEFULL 0x28 /*; Queue Full */
373 #define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */
374 #define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */
375 #define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */
380 #define SYNC_WIDE_TAG_ATNT_DISABLE 0x00000000
381 #define SYNC_NEGO_ENABLE 0x00000001
382 #define SYNC_NEGO_DONE 0x00000002
383 #define WIDE_NEGO_ENABLE 0x00000004
384 #define WIDE_NEGO_DONE 0x00000008
385 #define EN_TAG_QUEUING 0x00000010
386 #define EN_ATN_STOP 0x00000020
388 #define SYNC_NEGO_OFFSET 15
392 #define SCSI_DATA_OUT_ 0
393 #define SCSI_DATA_IN_ 1
394 #define SCSI_COMMAND 2
395 #define SCSI_STATUS_ 3
398 #define SCSI_MSG_OUT 6
399 #define SCSI_MSG_IN 7
402 * ----SCSI MSG u_int8_t
404 #define MSG_COMPLETE 0x00
405 #define MSG_EXTENDED 0x01
406 #define MSG_SAVE_PTR 0x02
407 #define MSG_RESTORE_PTR 0x03
408 #define MSG_DISCONNECT 0x04
409 #define MSG_INITIATOR_ERROR 0x05
410 #define MSG_ABORT 0x06
411 #define MSG_REJECT_ 0x07
413 #define MSG_PARITY_ERROR 0x09
414 #define MSG_LINK_CMD_COMPL 0x0A
415 #define MSG_LINK_CMD_COMPL_FLG 0x0B
416 #define MSG_BUS_RESET 0x0C
417 #define MSG_ABORT_TAG 0x0D
418 #define MSG_SIMPLE_QTAG 0x20
419 #define MSG_HEAD_QTAG 0x21
420 #define MSG_ORDER_QTAG 0x22
421 #define MSG_IGNOREWIDE 0x23
422 #define MSG_IDENTIFY 0x80
423 #define MSG_HOST_ID 0xC0
424 /* bus wide length */
425 #define MSG_EXT_WDTR_BUS_8_BIT 0x00
426 #define MSG_EXT_WDTR_BUS_16_BIT 0x01
427 #define MSG_EXT_WDTR_BUS_32_BIT 0x02
429 * ----SCSI STATUS u_int8_t
431 #define STATUS_GOOD 0x00
432 #define CHECK_CONDITION_ 0x02
433 #define STATUS_BUSY 0x08
434 #define STATUS_INTERMEDIATE 0x10
435 #define RESERVE_CONFLICT 0x18
440 #define STATUS_MASK_ 0xFF
441 #define MSG_MASK 0xFF00
442 #define RETURN_MASK 0xFF0000
445 * Inquiry Data format
448 typedef struct _SCSIInqData { /* INQ */
450 u_int8_t DevType; /* Periph Qualifier & Periph Dev Type */
451 u_int8_t RMB_TypeMod; /* rem media bit & Dev Type Modifier */
452 u_int8_t Vers; /* ISO, ECMA, & ANSI versions */
453 u_int8_t RDF; /* AEN, TRMIOP, & response data format*/
454 u_int8_t AddLen; /* length of additional data */
455 u_int8_t Res1; /* reserved */
456 u_int8_t Res2; /* reserved */
457 u_int8_t Flags; /* RelADr,Wbus32,Wbus16,Sync,etc. */
458 u_int8_t VendorID[8]; /* Vendor Identification */
459 u_int8_t ProductID[16]; /* Product Identification */
460 u_int8_t ProductRev[4]; /* Product Revision */
461 } SCSI_INQDATA, *PSCSI_INQDATA;
465 * Inquiry byte 0 masks
467 #define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */
468 #define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */
470 * Inquiry byte 1 mask
472 #define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */
474 * Peripheral Device Type definitions
476 #define SCSI_DASD 0x00 /* Direct-access Device */
477 #define SCSI_SEQACESS 0x01 /* Sequential-access device */
478 #define SCSI_PRINTER 0x02 /* Printer device */
479 #define SCSI_PROCESSOR 0x03 /* Processor device */
480 #define SCSI_WRITEONCE 0x04 /* Write-once device */
481 #define SCSI_CDROM 0x05 /* CD-ROM device */
482 #define SCSI_SCANNER 0x06 /* Scanner device */
483 #define SCSI_OPTICAL 0x07 /* Optical memory device */
484 #define SCSI_MEDCHGR 0x08 /* Medium changer device */
485 #define SCSI_COMM 0x09 /* Communications device */
486 #define SCSI_NODEV 0x1F /* Unknown or no device type */
488 * Inquiry flag definitions (Inq data byte 7)
490 #define SCSI_INQ_RELADR 0x80 /* device supports relative addressing*/
491 #define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */
492 #define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */
493 #define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */
494 #define SCSI_INQ_LINKED 0x08 /* device supports linked commands */
495 #define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */
496 #define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */
498 *==========================================================
500 *==========================================================
502 typedef struct _EEprom {
509 #define EE_ADAPT_SCSI_ID 64
512 #define EE_TAG_CMD_NUM 67
515 * EE_MODE1 bits definition
517 #define PARITY_CHK_ 0x00000001
518 #define SYNC_NEGO_ 0x00000002
519 #define EN_DISCONNECT_ 0x00000004
520 #define SEND_START_ 0x00000008
521 #define TAG_QUEUING_ 0x00000010
524 * EE_MODE2 bits definition
526 #define MORE2_DRV 0x00000001
527 #define GREATER_1G 0x00000002
528 #define RST_SCSI_BUS 0x00000004
529 #define ACTIVE_NEGATION 0x00000008
530 #define NO_SEEK 0x00000010
531 #define LUN_CHECK 0x00000020
533 #define ENABLE_CE 0x01
534 #define DISABLE_CE 0x00
535 #define EEPROM_READ 0x80
538 * The PCI configuration register offset for TRM_S1040
539 * Registers bit Definition
541 #define TRMREG_ID 0x00 /* Vendor and Device ID */
542 #define TRMREG_COMMAND 0x04 /* PCI command register */
543 #define TRMREG_IOBASE 0x10 /* I/O Space base address */
544 #define TRMREG_ROMBASE 0x30 /* Expansion ROM Base Address */
545 #define TRMREG_INTLINE 0x3C /* Interrupt line */
549 * The SCSI register offset for TRM_S1040
552 #define TRMREG_SCSI_STATUS 0x80 /* SCSI Status (R) */
554 #define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */
555 #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */
556 #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero*/
557 #define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */
558 #define COMMANDABORT 0x0040 /* SCSI command abort */
559 #define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */
560 #define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */
561 #define PARITYERROR 0x0008 /* SCSI parity error */
563 #define PHASEMASK 0x0007 /* Phase MSG/CD/IO */
564 #define PH_DATA_OUT 0x00 /* Data out phase */
565 #define PH_DATA_IN 0x01 /* Data in phase */
566 #define PH_COMMAND 0x02 /* Command phase */
567 #define PH_STATUS 0x03 /* Status phase */
568 #define PH_BUS_FREE 0x05 /* Invalid phase used as bus free */
569 #define PH_MSG_OUT 0x06 /* Message out phase */
570 #define PH_MSG_IN 0x07 /* Message in phase */
572 #define TRMREG_SCSI_CONTROL 0x80 /* SCSI Control (W) */
574 #define DO_CLRATN 0x0400 /* Clear ATN */
575 #define DO_SETATN 0x0200 /* Set ATN */
576 #define DO_CMDABORT 0x0100 /* Abort SCSI command */
577 #define DO_RSTMODULE 0x0010 /* Reset SCSI chip */
578 #define DO_RSTSCSI 0x0008 /* Reset SCSI bus */
579 #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */
580 #define DO_DATALATCH 0x0002 /* Enable SCSI bus data latch */
581 #define DO_HWRESELECT 0x0001 /* Enable hardware reselection */
582 #define TRMREG_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */
583 #define TRMREG_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */
584 #define TRMREG_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */
586 #define INT_SCAM 0x80 /* SCAM selection interrupt */
587 #define INT_SELECT 0x40 /* Selection interrupt */
588 #define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */
589 #define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */
590 #define INT_RESELECTED 0x08 /* Reselected interrupt */
591 #define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt*/
592 #define INT_BUSSERVICE 0x02 /* Bus service interrupt */
593 #define INT_CMDDONE 0x01 /* SCSI command done interrupt */
594 #define TRMREG_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */
596 * Bit Name Definition
597 * 07-05 0 RSVD Reversed. Always 0.
598 * 04 0 OFFSET4 Reversed for LVDS. Always 0.
599 * 03-00 0 OFFSET[03:00] Offset number from 0 to 15
601 #define TRMREG_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W)*/
603 #define LVDS_SYNC 0x20 /* Enable LVDS synchronous */
604 #define WIDE_SYNC 0x10 /* Enable WIDE synchronous */
605 #define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */
607 * SYNCM 7 6 5 4 3 2 1 0
608 * Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0
609 * Default 0 0 0 0 0 0 0 0
612 * Bit Name Definition
613 * 07-06 0 RSVD Reversed. Always read 0
614 * 05 0 LVDS Reversed. Always read 0
615 * 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI transfer.
616 * 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode.
618 * @@ When this bit is set,
619 * the synchronous period bits 2:0
620 * in the Synchronous Mode register
621 * are used to transfer data
622 * at the Fast-20 rate.
623 * @@ When this bit is reset,
624 * the synchronous period bits 2:0
625 * in the Synchronous Mode Register
626 * are used to transfer data
627 * at the Fast-40 rate.
629 * 02-00 0 PERIOD[2:0]/SXPD[02:00] Synchronous SCSI Transfer Rate.
630 * These 3 bits specify
631 * the Synchronous SCSI Transfer Rate
632 * for Fast-20 and Fast-10.
633 * These bits are also reset
634 * by a SCSI Bus reset.
636 * For Fast-10 bit ALTPD = 0 and LVDS = 0
637 * and 0x00000004,0x00000002,0x00000001 is defined as follows :
639 * 000 100ns, 10.0 Mbytes/s
640 * 001 150ns, 6.6 Mbytes/s
641 * 010 200ns, 5.0 Mbytes/s
642 * 011 250ns, 4.0 Mbytes/s
643 * 100 300ns, 3.3 Mbytes/s
644 * 101 350ns, 2.8 Mbytes/s
645 * 110 400ns, 2.5 Mbytes/s
646 * 111 450ns, 2.2 Mbytes/s
648 * For Fast-20 bit ALTPD = 1 and LVDS = 0
649 * and 0x00000004,0x00000002,0x00000001 is defined as follows :
651 * 000 50ns, 20.0 Mbytes/s
652 * 001 75ns, 13.3 Mbytes/s
653 * 010 100ns, 10.0 Mbytes/s
654 * 011 125ns, 8.0 Mbytes/s
655 * 100 150ns, 6.6 Mbytes/s
656 * 101 175ns, 5.7 Mbytes/s
657 * 110 200ns, 5.0 Mbytes/s
658 * 111 250ns, 4.0 Mbytes/s
660 * For Fast-40 bit ALTPD = 0 and LVDS = 1
661 * and 0x00000004,0x00000002,0x00000001 is defined as follows :
663 * 000 25ns, 40.0 Mbytes/s
664 * 001 50ns, 20.0 Mbytes/s
665 * 010 75ns, 13.3 Mbytes/s
666 * 011 100ns, 10.0 Mbytes/s
667 * 100 125ns, 8.0 Mbytes/s
668 * 101 150ns, 6.6 Mbytes/s
669 * 110 175ns, 5.7 Mbytes/s
670 * 111 200ns, 5.0 Mbytes/s
674 ***************************************
676 #define TRMREG_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */
678 ***************************************
680 #define TRMREG_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */
682 ***************************************
684 #define TRMREG_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */
686 ***************************************
688 #define TRMREG_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W)*/
690 ***************************************
692 #define TRMREG_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */
694 #define EN_SCAM 0x80 /* Enable SCAM selection interrupt*/
695 #define EN_SELECT 0x40 /* Enable selection interrupt */
696 #define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt*/
697 #define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt*/
698 #define EN_RESELECTED 0x08 /* Enable reselected interrupt */
699 #define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt*/
700 #define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */
701 #define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt*/
703 ***************************************
705 #define TRMREG_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */
707 #define PHASELATCH 0x40 /* Enable phase latch */
708 #define INITIATOR 0x20 /* Enable initiator mode */
709 #define PARITYCHECK 0x10 /* Enable parity check */
710 #define BLOCKRST 0x01 /* Disable SCSI reset1 */
712 ***************************************
714 #define TRMREG_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */
716 #define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */
717 #define FILTER_DISABLE 0x08 /* Disable SCSI data filter */
718 #define ACTIVE_NEG 0x02 /* Enable active negation */
720 ***************************************
722 #define TRMREG_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */
724 ***************************************
726 #define TRMREG_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */
728 #define SCMD_COMP 0x12 /* Command complete */
729 #define SCMD_SEL_ATN 0x60 /* Selection with ATN */
730 #define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */
731 #define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */
732 #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */
733 #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */
734 #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */
735 #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */
736 #define SCMD_MSGACCEPT 0xD8 /* Message accept */
738 * Code Command Description
740 * 02 Enable reselection with FIFO
741 * 40 Select without ATN with FIFO
742 * 60 Select with ATN with FIFO
743 * 64 Select with ATN3 with FIFO
744 * A0 Select with ATN and stop with FIFO
745 * C0 Transfer information out with FIFO
746 * C1 Transfer information out with DMA
747 * C2 Transfer information in with FIFO
748 * C3 Transfer information in with DMA
749 * 12 Initiator command complete with FIFO
750 * 50 Initiator transfer information out sequence without ATN with FIFO
751 * 70 Initiator transfer information out sequence with ATN with FIFO
752 * 74 Initiator transfer information out sequence with ATN3 with FIFO
753 * 52 Initiator transfer information in sequence without ATN with FIFO
754 * 72 Initiator transfer information in sequence with ATN with FIFO
755 * 76 Initiator transfer information in sequence with ATN3 with FIFO
756 * 90 Initiator transfer information out command complete with FIFO
757 * 92 Initiator transfer information in command complete with FIFO
758 * D2 Enable selection
760 * 48 Disconnect command with FIFO
761 * 88 Terminate command with FIFO
762 * C8 Target command complete with FIFO
763 * 18 SCAM Arbitration/ Selection
764 * 5A Enable reselection
765 * 98 Select without ATN with FIFO
766 * B8 Select with ATN with FIFO
767 * D8 Message Accepted
771 ***************************************
773 #define TRMREG_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */
775 ***************************************
777 #define TRMREG_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */
779 ***************************************
781 #define TRMREG_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */
783 #define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */
784 #define TCR0_SYNC_NEGO_DONE 0x4000 /* Synchronous nego done*/
785 #define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS synchronous*/
786 #define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE synchronous*/
787 #define TCR0_ENABLE_ALT 0x0800 /* Enable alternate synchronous */
788 #define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */
790 #define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */
791 #define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */
792 #define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */
793 #define TCR0_OFFSET_MASK 0x001F /* Offset number */
795 ***************************************
797 #define TRMREG_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */
799 #define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */
800 #define NON_TAG_BUSY 0x0080 /* Non tag command active */
801 #define ACTTAG_MASK 0x007F /* Active tags */
804 * The DMA register offset for TRM_S1040
807 #define TRMREG_DMA_COMMAND 0xA0 /* DMA Command (R/W) */
809 #define XFERDATAIN 0x0103 /* Transfer data in */
810 #define XFERDATAOUT 0x0102 /* Transfer data out */
812 ***************************************
814 #define TRMREG_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */
816 ***************************************
818 #define TRMREG_DMA_CONTROL 0xA1 /* DMA Control (W) */
820 #define STOPDMAXFER 0x08 /* Stop DMA transfer */
821 #define ABORTXFER 0x04 /* Abort DMA transfer */
822 #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */
823 #define STARTDMAXFER 0x01 /* Start DMA transfer */
825 ***************************************
827 #define TRMREG_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */
829 #define XFERPENDING 0x80 /* Transfer pending */
830 #define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */
831 #define SCSICOMP 0x01 /* SCSI complete interrupt */
833 ***************************************
835 #define TRMREG_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W)*/
837 #define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */
839 ***************************************
841 #define TRMREG_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */
843 #define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature */
845 ***************************************
847 #define TRMREG_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W)*/
849 ***************************************
851 #define TRMREG_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */
853 ***************************************
855 #define TRMREG_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */
857 ***************************************
859 #define TRMREG_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */
863 * The general register offset for TRM_S1040
866 #define TRMREG_GEN_CONTROL 0xD4 /* Global Control */
868 #define EN_EEPROM 0x10 /* Enable EEPROM programming */
869 #define AUTOTERM 0x04 /* Enable Auto SCSI terminator */
870 #define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */
871 #define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */
873 ***************************************
875 #define TRMREG_GEN_STATUS 0xD5 /* Global Status */
877 #define GTIMEOUT 0x80 /* Global timer reach 0 */
878 #define CON5068 0x10 /* External 50/68 pin connected */
879 #define CON68 0x08 /* Internal 68 pin connected */
880 #define CON50 0x04 /* Internal 50 pin connected */
881 #define WIDESCSI 0x02 /* Wide SCSI card */
883 ***************************************
885 #define TRMREG_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */
887 #define NVR_BITOUT 0x08 /* Serial data out */
888 #define NVR_BITIN 0x04 /* Serial data in */
889 #define NVR_CLOCK 0x02 /* Serial clock */
890 #define NVR_SELECT 0x01 /* Serial select */
892 ***************************************
894 #define TRMREG_GEN_EDATA 0xD7 /* Parallel EEPROM data port */
896 ***************************************
898 #define TRMREG_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */
900 ***************************************
902 #define TRMREG_GEN_TIMER 0xDB /* Global timer */
905 * The SEEPROM structure for TRM_S1040
907 typedef struct NVRAM_TARGET_STRUCT
909 u_int8_t NvmTarCfg0; /* Target configuration byte 0 */
910 u_int8_t NvmTarPeriod; /* Target period */
911 u_int8_t NvmTarCfg2; /* Target configuration byte 2 */
912 u_int8_t NvmTarCfg3; /* Target configuration byte 3 */
914 /* NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode */
915 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */
916 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tag queuing */
917 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP*/
918 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */
919 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */
920 #define NTC_DO_PARITY_CHK 0x01 /* (it sould define at NAC )
921 Parity check enable */
928 typedef struct NVRAM_STRUC {
929 u_int8_t NvramSubVendorID[2]; /*0,1 Sub Vendor ID */
930 u_int8_t NvramSubSysID[2]; /*2,3 Sub System ID*/
931 u_int8_t NvramSubClass; /*4 Sub Class */
932 u_int8_t NvramVendorID[2]; /*5,6 Vendor ID */
933 u_int8_t NvramDeviceID[2]; /*7,8 Device ID */
934 u_int8_t NvramReserved; /*9 Reserved */
935 NVRAMTARGETTYPE NvramTarget[MAX_TARGETS];/* *10,11,12,13
940 u_int8_t NvramScsiId; /*74 Host Adapter SCSI ID */
941 u_int8_t NvramChannelCfg; /*75 Channel configuration */
942 u_int8_t NvramDelayTime; /*76 Power on delay time */
943 u_int8_t NvramMaxTag; /*77 Maximum tags */
944 u_int8_t NvramReserved0; /*78 */
945 u_int8_t NvramBootTarget; /*79 */
946 u_int8_t NvramBootLun; /*80 */
947 u_int8_t NvramReserved1; /*81 */
948 u_int16_t Reserved[22]; /*82,..125 */
949 u_int16_t NvramCheckSum; /*126,127*/
950 } NVRAMTYPE,*PNVRAMTYPE;
951 /* Nvram Initiater bits definition */
952 #define MORE2_DRV 0x00000001
953 #define GREATER_1G 0x00000002
954 #define RST_SCSI_BUS 0x00000004
955 #define ACTIVE_NEGATION 0x00000008
956 #define NO_SEEK 0x00000010
957 #define LUN_CHECK 0x00000020
959 /* Nvram Adapter Cfg bits definition */
960 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device*/
961 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */
962 #define NAC_GREATER_1G 0x02 /* > 1G support enable */
963 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives*/
965 *#define NAC_DO_PARITY_CHK 0x08 // Parity check enable