sys/dev/drm/radeon/radeon_state.c

   1 /* radeon_state.c -- State support for Radeon -*- linux-c -*-
   2  *
   3  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *    Gareth Hughes <gareth@valinux.com>
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *
  29  * $FreeBSD: src/sys/dev/drm/radeon_state.c,v 1.6.2.1 2003/04/26 07:05:30 anholt Exp $
  30  */
  31
  32 #include "dev/drm/radeon.h"
  33 #include "dev/drm/drmP.h"
  34 #include "dev/drm/drm.h"
  35 #include "dev/drm/drm_sarea.h"
  36 #include "dev/drm/radeon_drm.h"
  37 #include "dev/drm/radeon_drv.h"
  38
  39
  40 /* ================================================================
  41  * CP hardware state programming functions
  42  */
  43
  44 static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
  45                                           drm_clip_rect_t *box )
  46 {
  47         RING_LOCALS;
  48
  49         DRM_DEBUG( "   box:  x1=%d y1=%d  x2=%d y2=%d\n",
  50                    box->x1, box->y1, box->x2, box->y2 );
  51
  52         BEGIN_RING( 4 );
  53         OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
  54         OUT_RING( (box->y1 << 16) | box->x1 );
  55         OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
  56         OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );
  57         ADVANCE_RING();
  58 }
  59
  60 /* Emit 1.1 state
  61  */
  62 static void radeon_emit_state( drm_radeon_private_t *dev_priv,
  63                                drm_radeon_context_regs_t *ctx,
  64                                drm_radeon_texture_regs_t *tex,
  65                                unsigned int dirty )
  66 {
  67         RING_LOCALS;
  68         DRM_DEBUG( "dirty=0x%08x\n", dirty );
  69
  70         if ( dirty & RADEON_UPLOAD_CONTEXT ) {
  71                 BEGIN_RING( 14 );
  72                 OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) );
  73                 OUT_RING( ctx->pp_misc );
  74                 OUT_RING( ctx->pp_fog_color );
  75                 OUT_RING( ctx->re_solid_color );
  76                 OUT_RING( ctx->rb3d_blendcntl );
  77                 OUT_RING( ctx->rb3d_depthoffset );
  78                 OUT_RING( ctx->rb3d_depthpitch );
  79                 OUT_RING( ctx->rb3d_zstencilcntl );
  80                 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) );
  81                 OUT_RING( ctx->pp_cntl );
  82                 OUT_RING( ctx->rb3d_cntl );
  83                 OUT_RING( ctx->rb3d_coloroffset );
  84                 OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) );
  85                 OUT_RING( ctx->rb3d_colorpitch );
  86                 ADVANCE_RING();
  87         }
  88
  89         if ( dirty & RADEON_UPLOAD_VERTFMT ) {
  90                 BEGIN_RING( 2 );
  91                 OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) );
  92                 OUT_RING( ctx->se_coord_fmt );
  93                 ADVANCE_RING();
  94         }
  95
  96         if ( dirty & RADEON_UPLOAD_LINE ) {
  97                 BEGIN_RING( 5 );
  98                 OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) );
  99                 OUT_RING( ctx->re_line_pattern );
 100                 OUT_RING( ctx->re_line_state );
 101                 OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) );
 102                 OUT_RING( ctx->se_line_width );
 103                 ADVANCE_RING();
 104         }
 105
 106         if ( dirty & RADEON_UPLOAD_BUMPMAP ) {
 107                 BEGIN_RING( 5 );
 108                 OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) );
 109                 OUT_RING( ctx->pp_lum_matrix );
 110                 OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) );
 111                 OUT_RING( ctx->pp_rot_matrix_0 );
 112                 OUT_RING( ctx->pp_rot_matrix_1 );
 113                 ADVANCE_RING();
 114         }
 115
 116         if ( dirty & RADEON_UPLOAD_MASKS ) {
 117                 BEGIN_RING( 4 );
 118                 OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) );
 119                 OUT_RING( ctx->rb3d_stencilrefmask );
 120                 OUT_RING( ctx->rb3d_ropcntl );
 121                 OUT_RING( ctx->rb3d_planemask );
 122                 ADVANCE_RING();
 123         }
 124
 125         if ( dirty & RADEON_UPLOAD_VIEWPORT ) {
 126                 BEGIN_RING( 7 );
 127                 OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) );
 128                 OUT_RING( ctx->se_vport_xscale );
 129                 OUT_RING( ctx->se_vport_xoffset );
 130                 OUT_RING( ctx->se_vport_yscale );
 131                 OUT_RING( ctx->se_vport_yoffset );
 132                 OUT_RING( ctx->se_vport_zscale );
 133                 OUT_RING( ctx->se_vport_zoffset );
 134                 ADVANCE_RING();
 135         }
 136
 137         if ( dirty & RADEON_UPLOAD_SETUP ) {
 138                 BEGIN_RING( 4 );
 139                 OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
 140                 OUT_RING( ctx->se_cntl );
 141                 OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) );
 142                 OUT_RING( ctx->se_cntl_status );
 143                 ADVANCE_RING();
 144         }
 145
 146         if ( dirty & RADEON_UPLOAD_MISC ) {
 147                 BEGIN_RING( 2 );
 148                 OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) );
 149                 OUT_RING( ctx->re_misc );
 150                 ADVANCE_RING();
 151         }
 152
 153         if ( dirty & RADEON_UPLOAD_TEX0 ) {
 154                 BEGIN_RING( 9 );
 155                 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) );
 156                 OUT_RING( tex[0].pp_txfilter );
 157                 OUT_RING( tex[0].pp_txformat );
 158                 OUT_RING( tex[0].pp_txoffset );
 159                 OUT_RING( tex[0].pp_txcblend );
 160                 OUT_RING( tex[0].pp_txablend );
 161                 OUT_RING( tex[0].pp_tfactor );
 162                 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
 163                 OUT_RING( tex[0].pp_border_color );
 164                 ADVANCE_RING();
 165         }
 166
 167         if ( dirty & RADEON_UPLOAD_TEX1 ) {
 168                 BEGIN_RING( 9 );
 169                 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) );
 170                 OUT_RING( tex[1].pp_txfilter );
 171                 OUT_RING( tex[1].pp_txformat );
 172                 OUT_RING( tex[1].pp_txoffset );
 173                 OUT_RING( tex[1].pp_txcblend );
 174                 OUT_RING( tex[1].pp_txablend );
 175                 OUT_RING( tex[1].pp_tfactor );
 176                 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
 177                 OUT_RING( tex[1].pp_border_color );
 178                 ADVANCE_RING();
 179         }
 180
 181         if ( dirty & RADEON_UPLOAD_TEX2 ) {
 182                 BEGIN_RING( 9 );
 183                 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) );
 184                 OUT_RING( tex[2].pp_txfilter );
 185                 OUT_RING( tex[2].pp_txformat );
 186                 OUT_RING( tex[2].pp_txoffset );
 187                 OUT_RING( tex[2].pp_txcblend );
 188                 OUT_RING( tex[2].pp_txablend );
 189                 OUT_RING( tex[2].pp_tfactor );
 190                 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
 191                 OUT_RING( tex[2].pp_border_color );
 192                 ADVANCE_RING();
 193         }
 194 }
 195
 196 /* Emit 1.2 state
 197  */
 198 static void radeon_emit_state2( drm_radeon_private_t *dev_priv,
 199                                 drm_radeon_state_t *state )
 200 {
 201         RING_LOCALS;
 202
 203         if (state->dirty & RADEON_UPLOAD_ZBIAS) {
 204                 BEGIN_RING( 3 );
 205                 OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) );
 206                 OUT_RING( state->context2.se_zbias_factor );
 207                 OUT_RING( state->context2.se_zbias_constant );
 208                 ADVANCE_RING();
 209         }
 210
 211         radeon_emit_state( dev_priv, &state->context,
 212                            state->tex, state->dirty );
 213 }
 214
 215 /* New (1.3) state mechanism.  3 commands (packet, scalar, vector) in
 216  * 1.3 cmdbuffers allow all previous state to be updated as well as
 217  * the tcl scalar and vector areas.
 218  */
 219 static struct {
 220         int start;
 221         int len;
 222         const char *name;
 223 } packet[RADEON_MAX_STATE_PACKETS] = {
 224         { RADEON_PP_MISC,7,"RADEON_PP_MISC" },
 225         { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
 226         { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
 227         { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
 228         { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
 229         { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
 230         { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
 231         { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
 232         { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
 233         { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
 234         { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
 235         { RADEON_RE_MISC,1,"RADEON_RE_MISC" },
 236         { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
 237         { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
 238         { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
 239         { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
 240         { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
 241         { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
 242         { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
 243         { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
 244         { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
 245         { R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" },
 246         { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" },
 247         { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" },
 248         { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" },
 249         { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" },
 250         { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" },
 251         { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" },
 252         { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" },
 253         { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
 254         { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" },
 255         { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" },
 256         { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" },
 257         { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" },
 258         { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
 259         { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
 260         { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" },
 261         { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" },
 262         { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" },
 263         { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" },
 264         { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" },
 265         { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" },
 266         { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" },
 267         { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" },
 268         { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" },
 269         { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" },
 270         { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" },
 271         { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" },
 272         { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" },
 273         { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
 274         { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" },
 275         { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" },
 276         { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" },
 277         { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" },
 278         { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" },
 279         { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" },
 280         { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" },
 281         { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" },
 282         { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" },
 283         { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" },
 284         { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
 285         { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
 286         { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
 287         { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" },
 288         { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
 289         { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" },
 290         { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
 291         { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" },
 292         { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
 293         { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" },
 294         { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
 295         { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
 296         { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
 297 };
 298
 299
 300
 301 /* ================================================================
 302  * Performance monitoring functions
 303  */
 304
 305 static void radeon_clear_box( drm_radeon_private_t *dev_priv,
 306                               int x, int y, int w, int h,
 307                               int r, int g, int b )
 308 {
 309         u32 color;
 310         RING_LOCALS;
 311
 312         x += dev_priv->sarea_priv->boxes[0].x1;
 313         y += dev_priv->sarea_priv->boxes[0].y1;
 314
 315         switch ( dev_priv->color_fmt ) {
 316         case RADEON_COLOR_FORMAT_RGB565:
 317                 color = (((r & 0xf8) << 8) |
 318                          ((g & 0xfc) << 3) |
 319                          ((b & 0xf8) >> 3));
 320                 break;
 321         case RADEON_COLOR_FORMAT_ARGB8888:
 322         default:
 323                 color = (((0xff) << 24) | (r << 16) | (g <<  8) | b);
 324                 break;
 325         }
 326
 327         BEGIN_RING( 4 );
 328         RADEON_WAIT_UNTIL_3D_IDLE();
 329         OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
 330         OUT_RING( 0xffffffff );
 331         ADVANCE_RING();
 332
 333         BEGIN_RING( 6 );
 334
 335         OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 336         OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 337                   RADEON_GMC_BRUSH_SOLID_COLOR |
 338                   (dev_priv->color_fmt << 8) |
 339                   RADEON_GMC_SRC_DATATYPE_COLOR |
 340                   RADEON_ROP3_P |
 341                   RADEON_GMC_CLR_CMP_CNTL_DIS );
 342
 343         if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
 344                 OUT_RING( dev_priv->front_pitch_offset );
 345         } else {
 346                 OUT_RING( dev_priv->back_pitch_offset );
 347         }
 348
 349         OUT_RING( color );
 350
 351         OUT_RING( (x << 16) | y );
 352         OUT_RING( (w << 16) | h );
 353
 354         ADVANCE_RING();
 355 }
 356
 357 static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
 358 {
 359         /* Collapse various things into a wait flag -- trying to
 360          * guess if userspase slept -- better just to have them tell us.
 361          */
 362         if (dev_priv->stats.last_frame_reads > 1 ||
 363             dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
 364                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 365         }
 366
 367         if (dev_priv->stats.freelist_loops) {
 368                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 369         }
 370
 371         /* Purple box for page flipping
 372          */
 373         if ( dev_priv->stats.boxes & RADEON_BOX_FLIP )
 374                 radeon_clear_box( dev_priv, 4, 4, 8, 8, 255, 0, 255 );
 375
 376         /* Red box if we have to wait for idle at any point
 377          */
 378         if ( dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE )
 379                 radeon_clear_box( dev_priv, 16, 4, 8, 8, 255, 0, 0 );
 380
 381         /* Blue box: lost context?
 382          */
 383
 384         /* Yellow box for texture swaps
 385          */
 386         if ( dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD )
 387                 radeon_clear_box( dev_priv, 40, 4, 8, 8, 255, 255, 0 );
 388
 389         /* Green box if hardware never idles (as far as we can tell)
 390          */
 391         if ( !(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE) )
 392                 radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
 393
 394
 395         /* Draw bars indicating number of buffers allocated
 396          * (not a great measure, easily confused)
 397          */
 398         if (dev_priv->stats.requested_bufs) {
 399                 if (dev_priv->stats.requested_bufs > 100)
 400                         dev_priv->stats.requested_bufs = 100;
 401
 402                 radeon_clear_box( dev_priv, 4, 16,
 403                                   dev_priv->stats.requested_bufs, 4,
 404                                   196, 128, 128 );
 405         }
 406
 407         memset( &dev_priv->stats, 0, sizeof(dev_priv->stats) );
 408
 409 }
 410 /* ================================================================
 411  * CP command dispatch functions
 412  */
 413
 414 static void radeon_cp_dispatch_clear( drm_device_t *dev,
 415                                       drm_radeon_clear_t *clear,
 416                                       drm_radeon_clear_rect_t *depth_boxes )
 417 {
 418         drm_radeon_private_t *dev_priv = dev->dev_private;
 419         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 420         drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
 421         int nbox = sarea_priv->nbox;
 422         drm_clip_rect_t *pbox = sarea_priv->boxes;
 423         unsigned int flags = clear->flags;
 424         u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0;
 425         int i;
 426         RING_LOCALS;
 427         DRM_DEBUG( "flags = 0x%x\n", flags );
 428
 429         dev_priv->stats.clears++;
 430
 431         if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
 432                 unsigned int tmp = flags;
 433
 434                 flags &= ~(RADEON_FRONT | RADEON_BACK);
 435                 if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK;
 436                 if ( tmp & RADEON_BACK )  flags |= RADEON_FRONT;
 437         }
 438
 439         if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
 440
 441                 BEGIN_RING( 4 );
 442
 443                 /* Ensure the 3D stream is idle before doing a
 444                  * 2D fill to clear the front or back buffer.
 445                  */
 446                 RADEON_WAIT_UNTIL_3D_IDLE();
 447
 448                 OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
 449                 OUT_RING( clear->color_mask );
 450
 451                 ADVANCE_RING();
 452
 453                 /* Make sure we restore the 3D state next time.
 454                  */
 455                 dev_priv->sarea_priv->ctx_owner = 0;
 456
 457                 for ( i = 0 ; i < nbox ; i++ ) {
 458                         int x = pbox[i].x1;
 459                         int y = pbox[i].y1;
 460                         int w = pbox[i].x2 - x;
 461                         int h = pbox[i].y2 - y;
 462
 463                         DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
 464                                    x, y, w, h, flags );
 465
 466                         if ( flags & RADEON_FRONT ) {
 467                                 BEGIN_RING( 6 );
 468
 469                                 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 470                                 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 471                                           RADEON_GMC_BRUSH_SOLID_COLOR |
 472                                           (dev_priv->color_fmt << 8) |
 473                                           RADEON_GMC_SRC_DATATYPE_COLOR |
 474                                           RADEON_ROP3_P |
 475                                           RADEON_GMC_CLR_CMP_CNTL_DIS );
 476
 477                                 OUT_RING( dev_priv->front_pitch_offset );
 478                                 OUT_RING( clear->clear_color );
 479
 480                                 OUT_RING( (x << 16) | y );
 481                                 OUT_RING( (w << 16) | h );
 482
 483                                 ADVANCE_RING();
 484                         }
 485
 486                         if ( flags & RADEON_BACK ) {
 487                                 BEGIN_RING( 6 );
 488
 489                                 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 490                                 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 491                                           RADEON_GMC_BRUSH_SOLID_COLOR |
 492                                           (dev_priv->color_fmt << 8) |
 493                                           RADEON_GMC_SRC_DATATYPE_COLOR |
 494                                           RADEON_ROP3_P |
 495                                           RADEON_GMC_CLR_CMP_CNTL_DIS );
 496
 497                                 OUT_RING( dev_priv->back_pitch_offset );
 498                                 OUT_RING( clear->clear_color );
 499
 500                                 OUT_RING( (x << 16) | y );
 501                                 OUT_RING( (w << 16) | h );
 502
 503                                 ADVANCE_RING();
 504                         }
 505                 }
 506         }
 507
 508         /* We have to clear the depth and/or stencil buffers by
 509          * rendering a quad into just those buffers.  Thus, we have to
 510          * make sure the 3D engine is configured correctly.
 511          */
 512         if ( dev_priv->is_r200 &&
 513              (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
 514
 515                 int tempPP_CNTL;
 516                 int tempRE_CNTL;
 517                 int tempRB3D_CNTL;
 518                 int tempRB3D_ZSTENCILCNTL;
 519                 int tempRB3D_STENCILREFMASK;
 520                 int tempRB3D_PLANEMASK;
 521                 int tempSE_CNTL;
 522                 int tempSE_VTE_CNTL;
 523                 int tempSE_VTX_FMT_0;
 524                 int tempSE_VTX_FMT_1;
 525                 int tempSE_VAP_CNTL;
 526                 int tempRE_AUX_SCISSOR_CNTL;
 527
 528                 tempPP_CNTL = 0;
 529                 tempRE_CNTL = 0;
 530
 531                 tempRB3D_CNTL = depth_clear->rb3d_cntl;
 532                 tempRB3D_CNTL &= ~(1<<15); /* unset radeon magic flag */
 533
 534                 tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
 535                 tempRB3D_STENCILREFMASK = 0x0;
 536
 537                 tempSE_CNTL = depth_clear->se_cntl;
 538
 539
 540
 541                 /* Disable TCL */
 542
 543                 tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK |  */
 544                                    (0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
 545
 546                 tempRB3D_PLANEMASK = 0x0;
 547
 548                 tempRE_AUX_SCISSOR_CNTL = 0x0;
 549
 550                 tempSE_VTE_CNTL =
 551                         SE_VTE_CNTL__VTX_XY_FMT_MASK |
 552                         SE_VTE_CNTL__VTX_Z_FMT_MASK;
 553
 554                 /* Vertex format (X, Y, Z, W)*/
 555                 tempSE_VTX_FMT_0 =
 556                         SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
 557                         SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
 558                 tempSE_VTX_FMT_1 = 0x0;
 559
 560
 561                 /*
 562                  * Depth buffer specific enables
 563                  */
 564                 if (flags & RADEON_DEPTH) {
 565                         /* Enable depth buffer */
 566                         tempRB3D_CNTL |= RADEON_Z_ENABLE;
 567                 } else {
 568                         /* Disable depth buffer */
 569                         tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
 570                 }
 571
 572                 /*
 573                  * Stencil buffer specific enables
 574                  */
 575                 if ( flags & RADEON_STENCIL ) {
 576                         tempRB3D_CNTL |=  RADEON_STENCIL_ENABLE;
 577                         tempRB3D_STENCILREFMASK = clear->depth_mask;
 578                 } else {
 579                         tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
 580                         tempRB3D_STENCILREFMASK = 0x00000000;
 581                 }
 582
 583                 BEGIN_RING( 26 );
 584                 RADEON_WAIT_UNTIL_2D_IDLE();
 585
 586                 OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL );
 587                 OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL );
 588                 OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL );
 589                 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
 590                               tempRB3D_ZSTENCILCNTL );
 591                 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
 592                               tempRB3D_STENCILREFMASK );
 593                 OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK );
 594                 OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL );
 595                 OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL );
 596                 OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 );
 597                 OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 );
 598                 OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL );
 599                 OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL,
 600                               tempRE_AUX_SCISSOR_CNTL );
 601                 ADVANCE_RING();
 602
 603                 /* Make sure we restore the 3D state next time.
 604                  */
 605                 dev_priv->sarea_priv->ctx_owner = 0;
 606
 607                 for ( i = 0 ; i < nbox ; i++ ) {
 608
 609                         /* Funny that this should be required --
 610                          *  sets top-left?
 611                          */
 612                         radeon_emit_clip_rect( dev_priv,
 613                                                &sarea_priv->boxes[i] );
 614
 615                         BEGIN_RING( 14 );
 616                         OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) );
 617                         OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
 618                                    RADEON_PRIM_WALK_RING |
 619                                    (3 << RADEON_NUM_VERTICES_SHIFT)) );
 620                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 621                         OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
 622                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 623                         OUT_RING( 0x3f800000 );
 624                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 625                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 626                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 627                         OUT_RING( 0x3f800000 );
 628                         OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
 629                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 630                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 631                         OUT_RING( 0x3f800000 );
 632                         ADVANCE_RING();
 633                 }
 634         }
 635         else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
 636
 637                 rb3d_cntl = depth_clear->rb3d_cntl;
 638
 639                 if ( flags & RADEON_DEPTH ) {
 640                         rb3d_cntl |=  RADEON_Z_ENABLE;
 641                 } else {
 642                         rb3d_cntl &= ~RADEON_Z_ENABLE;
 643                 }
 644
 645                 if ( flags & RADEON_STENCIL ) {
 646                         rb3d_cntl |=  RADEON_STENCIL_ENABLE;
 647                         rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
 648                 } else {
 649                         rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
 650                         rb3d_stencilrefmask = 0x00000000;
 651                 }
 652
 653                 BEGIN_RING( 13 );
 654                 RADEON_WAIT_UNTIL_2D_IDLE();
 655
 656                 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
 657                 OUT_RING( 0x00000000 );
 658                 OUT_RING( rb3d_cntl );
 659
 660                 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
 661                               depth_clear->rb3d_zstencilcntl );
 662                 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
 663                               rb3d_stencilrefmask );
 664                 OUT_RING_REG( RADEON_RB3D_PLANEMASK,
 665                               0x00000000 );
 666                 OUT_RING_REG( RADEON_SE_CNTL,
 667                               depth_clear->se_cntl );
 668                 ADVANCE_RING();
 669
 670                 /* Make sure we restore the 3D state next time.
 671                  */
 672                 dev_priv->sarea_priv->ctx_owner = 0;
 673
 674                 for ( i = 0 ; i < nbox ; i++ ) {
 675
 676                         /* Funny that this should be required --
 677                          *  sets top-left?
 678                          */
 679                         radeon_emit_clip_rect( dev_priv,
 680                                                &sarea_priv->boxes[i] );
 681
 682                         BEGIN_RING( 15 );
 683
 684                         OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) );
 685                         OUT_RING( RADEON_VTX_Z_PRESENT |
 686                                   RADEON_VTX_PKCOLOR_PRESENT);
 687                         OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
 688                                    RADEON_PRIM_WALK_RING |
 689                                    RADEON_MAOS_ENABLE |
 690                                    RADEON_VTX_FMT_RADEON_MODE |
 691                                    (3 << RADEON_NUM_VERTICES_SHIFT)) );
 692
 693
 694                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 695                         OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
 696                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 697                         OUT_RING( 0x0 );
 698
 699                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 700                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 701                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 702                         OUT_RING( 0x0 );
 703
 704                         OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
 705                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 706                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 707                         OUT_RING( 0x0 );
 708
 709                         ADVANCE_RING();
 710                 }
 711         }
 712
 713         /* Increment the clear counter.  The client-side 3D driver must
 714          * wait on this value before performing the clear ioctl.  We
 715          * need this because the card's so damned fast...
 716          */
 717         dev_priv->sarea_priv->last_clear++;
 718
 719         BEGIN_RING( 4 );
 720
 721         RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear );
 722         RADEON_WAIT_UNTIL_IDLE();
 723
 724         ADVANCE_RING();
 725 }
 726
 727 static void radeon_cp_dispatch_swap( drm_device_t *dev )
 728 {
 729         drm_radeon_private_t *dev_priv = dev->dev_private;
 730         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 731         int nbox = sarea_priv->nbox;
 732         drm_clip_rect_t *pbox = sarea_priv->boxes;
 733         int i;
 734         RING_LOCALS;
 735         DRM_DEBUG( "\n" );
 736
 737         /* Do some trivial performance monitoring...
 738          */
 739         if (dev_priv->do_boxes)
 740                 radeon_cp_performance_boxes( dev_priv );
 741
 742
 743         /* Wait for the 3D stream to idle before dispatching the bitblt.
 744          * This will prevent data corruption between the two streams.
 745          */
 746         BEGIN_RING( 2 );
 747
 748         RADEON_WAIT_UNTIL_3D_IDLE();
 749
 750         ADVANCE_RING();
 751
 752         for ( i = 0 ; i < nbox ; i++ ) {
 753                 int x = pbox[i].x1;
 754                 int y = pbox[i].y1;
 755                 int w = pbox[i].x2 - x;
 756                 int h = pbox[i].y2 - y;
 757
 758                 DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
 759                            x, y, w, h );
 760
 761                 BEGIN_RING( 7 );
 762
 763                 OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) );
 764                 OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 765                           RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 766                           RADEON_GMC_BRUSH_NONE |
 767                           (dev_priv->color_fmt << 8) |
 768                           RADEON_GMC_SRC_DATATYPE_COLOR |
 769                           RADEON_ROP3_S |
 770                           RADEON_DP_SRC_SOURCE_MEMORY |
 771                           RADEON_GMC_CLR_CMP_CNTL_DIS |
 772                           RADEON_GMC_WR_MSK_DIS );
 773
 774                 /* Make this work even if front & back are flipped:
 775                  */
 776                 if (dev_priv->current_page == 0) {
 777                         OUT_RING( dev_priv->back_pitch_offset );
 778                         OUT_RING( dev_priv->front_pitch_offset );
 779                 }
 780                 else {
 781                         OUT_RING( dev_priv->front_pitch_offset );
 782                         OUT_RING( dev_priv->back_pitch_offset );
 783                 }
 784
 785                 OUT_RING( (x << 16) | y );
 786                 OUT_RING( (x << 16) | y );
 787                 OUT_RING( (w << 16) | h );
 788
 789                 ADVANCE_RING();
 790         }
 791
 792         /* Increment the frame counter.  The client-side 3D driver must
 793          * throttle the framerate by waiting for this value before
 794          * performing the swapbuffer ioctl.
 795          */
 796         dev_priv->sarea_priv->last_frame++;
 797
 798         BEGIN_RING( 4 );
 799
 800         RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
 801         RADEON_WAIT_UNTIL_2D_IDLE();
 802
 803         ADVANCE_RING();
 804 }
 805
 806 static void radeon_cp_dispatch_flip( drm_device_t *dev )
 807 {
 808         drm_radeon_private_t *dev_priv = dev->dev_private;
 809         drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle;
 810         int offset = (dev_priv->current_page == 1)
 811                    ? dev_priv->front_offset : dev_priv->back_offset;
 812         RING_LOCALS;
 813         DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n",
 814                 __FUNCTION__,
 815                 dev_priv->current_page,
 816                 dev_priv->sarea_priv->pfCurrentPage);
 817
 818         /* Do some trivial performance monitoring...
 819          */
 820         if (dev_priv->do_boxes) {
 821                 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
 822                 radeon_cp_performance_boxes( dev_priv );
 823         }
 824
 825         /* Update the frame offsets for both CRTCs
 826          */
 827         BEGIN_RING( 6 );
 828
 829         RADEON_WAIT_UNTIL_3D_IDLE();
 830         OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch
 831                                               + sarea->frame.x
 832                                               * ( dev_priv->color_fmt - 2 ) ) & ~7 )
 833                                           + offset );
 834         OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
 835                                            + offset );
 836
 837         ADVANCE_RING();
 838
 839         /* Increment the frame counter.  The client-side 3D driver must
 840          * throttle the framerate by waiting for this value before
 841          * performing the swapbuffer ioctl.
 842          */
 843         dev_priv->sarea_priv->last_frame++;
 844         dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
 845                                               1 - dev_priv->current_page;
 846
 847         BEGIN_RING( 2 );
 848
 849         RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
 850
 851         ADVANCE_RING();
 852 }
 853
 854 static int bad_prim_vertex_nr( int primitive, int nr )
 855 {
 856         switch (primitive & RADEON_PRIM_TYPE_MASK) {
 857         case RADEON_PRIM_TYPE_NONE:
 858         case RADEON_PRIM_TYPE_POINT:
 859                 return nr < 1;
 860         case RADEON_PRIM_TYPE_LINE:
 861                 return (nr & 1) || nr == 0;
 862         case RADEON_PRIM_TYPE_LINE_STRIP:
 863                 return nr < 2;
 864         case RADEON_PRIM_TYPE_TRI_LIST:
 865         case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
 866         case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
 867         case RADEON_PRIM_TYPE_RECT_LIST:
 868                 return nr % 3 || nr == 0;
 869         case RADEON_PRIM_TYPE_TRI_FAN:
 870         case RADEON_PRIM_TYPE_TRI_STRIP:
 871                 return nr < 3;
 872         default:
 873                 return 1;
 874         }
 875 }
 876
 877
 878
 879 typedef struct {
 880         unsigned int start;
 881         unsigned int finish;
 882         unsigned int prim;
 883         unsigned int numverts;
 884         unsigned int offset;
 885         unsigned int vc_format;
 886 } drm_radeon_tcl_prim_t;
 887
 888 static void radeon_cp_dispatch_vertex( drm_device_t *dev,
 889                                        drm_buf_t *buf,
 890                                        drm_radeon_tcl_prim_t *prim,
 891                                        drm_clip_rect_t *boxes,
 892                                        int nbox )
 893
 894 {
 895         drm_radeon_private_t *dev_priv = dev->dev_private;
 896         drm_clip_rect_t box;
 897         int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
 898         int numverts = (int)prim->numverts;
 899         int i = 0;
 900         RING_LOCALS;
 901
 902         DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
 903                   prim->prim,
 904                   prim->vc_format,
 905                   prim->start,
 906                   prim->finish,
 907                   prim->numverts);
 908
 909         if (bad_prim_vertex_nr( prim->prim, prim->numverts )) {
 910                 DRM_ERROR( "bad prim %x numverts %d\n",
 911                            prim->prim, prim->numverts );
 912                 return;
 913         }
 914
 915         do {
 916                 /* Emit the next cliprect */
 917                 if ( i < nbox ) {
 918                         if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
 919                                 return;
 920
 921                         radeon_emit_clip_rect( dev_priv, &box );
 922                 }
 923
 924                 /* Emit the vertex buffer rendering commands */
 925                 BEGIN_RING( 5 );
 926
 927                 OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) );
 928                 OUT_RING( offset );
 929                 OUT_RING( numverts );
 930                 OUT_RING( prim->vc_format );
 931                 OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST |
 932                           RADEON_COLOR_ORDER_RGBA |
 933                           RADEON_VTX_FMT_RADEON_MODE |
 934                           (numverts << RADEON_NUM_VERTICES_SHIFT) );
 935
 936                 ADVANCE_RING();
 937
 938                 i++;
 939         } while ( i < nbox );
 940 }
 941
 942
 943
 944 static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
 945 {
 946         drm_radeon_private_t *dev_priv = dev->dev_private;
 947         drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
 948         RING_LOCALS;
 949
 950         buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
 951
 952         /* Emit the vertex buffer age */
 953         BEGIN_RING( 2 );
 954         RADEON_DISPATCH_AGE( buf_priv->age );
 955         ADVANCE_RING();
 956
 957         buf->pending = 1;
 958         buf->used = 0;
 959 }
 960
 961 static void radeon_cp_dispatch_indirect( drm_device_t *dev,
 962                                          drm_buf_t *buf,
 963                                          int start, int end )
 964 {
 965         drm_radeon_private_t *dev_priv = dev->dev_private;
 966         RING_LOCALS;
 967         DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
 968                    buf->idx, start, end );
 969
 970         if ( start != end ) {
 971                 int offset = (dev_priv->agp_buffers_offset
 972                               + buf->offset + start);
 973                 int dwords = (end - start + 3) / sizeof(u32);
 974
 975                 /* Indirect buffer data must be an even number of
 976                  * dwords, so if we've been given an odd number we must
 977                  * pad the data with a Type-2 CP packet.
 978                  */
 979                 if ( dwords & 1 ) {
 980                         u32 *data = (u32 *)
 981                                 ((char *)dev_priv->buffers->handle
 982                                  + buf->offset + start);
 983                         data[dwords++] = RADEON_CP_PACKET2;
 984                 }
 985
 986                 /* Fire off the indirect buffer */
 987                 BEGIN_RING( 3 );
 988
 989                 OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) );
 990                 OUT_RING( offset );
 991                 OUT_RING( dwords );
 992
 993                 ADVANCE_RING();
 994         }
 995 }
 996
 997
 998 static void radeon_cp_dispatch_indices( drm_device_t *dev,
 999                                         drm_buf_t *elt_buf,
1000                                         drm_radeon_tcl_prim_t *prim,
1001                                         drm_clip_rect_t *boxes,
1002                                         int nbox )
1003 {
1004         drm_radeon_private_t *dev_priv = dev->dev_private;
1005         drm_clip_rect_t box;
1006         int offset = dev_priv->agp_buffers_offset + prim->offset;
1007         u32 *data;
1008         int dwords;
1009         int i = 0;
1010         int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
1011         int count = (prim->finish - start) / sizeof(u16);
1012
1013         DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
1014                   prim->prim,
1015                   prim->vc_format,
1016                   prim->start,
1017                   prim->finish,
1018                   prim->offset,
1019                   prim->numverts);
1020
1021         if (bad_prim_vertex_nr( prim->prim, count )) {
1022                 DRM_ERROR( "bad prim %x count %d\n",
1023                            prim->prim, count );
1024                 return;
1025         }
1026
1027
1028         if ( start >= prim->finish ||
1029              (prim->start & 0x7) ) {
1030                 DRM_ERROR( "buffer prim %d\n", prim->prim );
1031                 return;
1032         }
1033
1034         dwords = (prim->finish - prim->start + 3) / sizeof(u32);
1035
1036         data = (u32 *)((char *)dev_priv->buffers->handle +
1037                        elt_buf->offset + prim->start);
1038
1039         data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 );
1040         data[1] = offset;
1041         data[2] = prim->numverts;
1042         data[3] = prim->vc_format;
1043         data[4] = (prim->prim |
1044                    RADEON_PRIM_WALK_IND |
1045                    RADEON_COLOR_ORDER_RGBA |
1046                    RADEON_VTX_FMT_RADEON_MODE |
1047                    (count << RADEON_NUM_VERTICES_SHIFT) );
1048
1049         do {
1050                 if ( i < nbox ) {
1051                         if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
1052                                 return;
1053
1054                         radeon_emit_clip_rect( dev_priv, &box );
1055                 }
1056
1057                 radeon_cp_dispatch_indirect( dev, elt_buf,
1058                                              prim->start,
1059                                              prim->finish );
1060
1061                 i++;
1062         } while ( i < nbox );
1063
1064 }
1065
1066 #define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32))
1067
1068 static int radeon_cp_dispatch_texture( DRMFILE filp,
1069                                        drm_device_t *dev,
1070                                        drm_radeon_texture_t *tex,
1071                                        drm_radeon_tex_image_t *image )
1072 {
1073         drm_radeon_private_t *dev_priv = dev->dev_private;
1074         drm_buf_t *buf;
1075         u32 format;
1076         u32 *buffer;
1077         const u8 *data;
1078         int size, dwords, tex_width, blit_width;
1079         u32 height;
1080         int i;
1081         RING_LOCALS;
1082
1083         dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
1084
1085         /* Flush the pixel cache.  This ensures no pixel data gets mixed
1086          * up with the texture data from the host data blit, otherwise
1087          * part of the texture image may be corrupted.
1088          */
1089         BEGIN_RING( 4 );
1090         RADEON_FLUSH_CACHE();
1091         RADEON_WAIT_UNTIL_IDLE();
1092         ADVANCE_RING();
1093
1094 #ifdef __BIG_ENDIAN
1095         /* The Mesa texture functions provide the data in little endian as the
1096          * chip wants it, but we need to compensate for the fact that the CP
1097          * ring gets byte-swapped
1098          */
1099         BEGIN_RING( 2 );
1100         OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT );
1101         ADVANCE_RING();
1102 #endif
1103
1104
1105         /* The compiler won't optimize away a division by a variable,
1106          * even if the only legal values are powers of two.  Thus, we'll
1107          * use a shift instead.
1108          */
1109         switch ( tex->format ) {
1110         case RADEON_TXFORMAT_ARGB8888:
1111         case RADEON_TXFORMAT_RGBA8888:
1112                 format = RADEON_COLOR_FORMAT_ARGB8888;
1113                 tex_width = tex->width * 4;
1114                 blit_width = image->width * 4;
1115                 break;
1116         case RADEON_TXFORMAT_AI88:
1117         case RADEON_TXFORMAT_ARGB1555:
1118         case RADEON_TXFORMAT_RGB565:
1119         case RADEON_TXFORMAT_ARGB4444:
1120         case RADEON_TXFORMAT_VYUY422:
1121         case RADEON_TXFORMAT_YVYU422:
1122                 format = RADEON_COLOR_FORMAT_RGB565;
1123                 tex_width = tex->width * 2;
1124                 blit_width = image->width * 2;
1125                 break;
1126         case RADEON_TXFORMAT_I8:
1127         case RADEON_TXFORMAT_RGB332:
1128                 format = RADEON_COLOR_FORMAT_CI8;
1129                 tex_width = tex->width * 1;
1130                 blit_width = image->width * 1;
1131                 break;
1132         default:
1133                 DRM_ERROR( "invalid texture format %d\n", tex->format );
1134                 return DRM_ERR(EINVAL);
1135         }
1136
1137         DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width );
1138
1139         do {
1140                 DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
1141                            tex->offset >> 10, tex->pitch, tex->format,
1142                            image->x, image->y, image->width, image->height );
1143
1144                 /* Make a copy of some parameters in case we have to
1145                  * update them for a multi-pass texture blit.
1146                  */
1147                 height = image->height;
1148                 data = (const u8 *)image->data;
1149
1150                 size = height * blit_width;
1151
1152                 if ( size > RADEON_MAX_TEXTURE_SIZE ) {
1153                         height = RADEON_MAX_TEXTURE_SIZE / blit_width;
1154                         size = height * blit_width;
1155                 } else if ( size < 4 && size > 0 ) {
1156                         size = 4;
1157                 } else if ( size == 0 ) {
1158                         return 0;
1159                 }
1160
1161                 buf = radeon_freelist_get( dev );
1162                 if ( 0 && !buf ) {
1163                         radeon_do_cp_idle( dev_priv );
1164                         buf = radeon_freelist_get( dev );
1165                 }
1166                 if ( !buf ) {
1167                         DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n");
1168                         DRM_COPY_TO_USER( tex->image, image, sizeof(*image) );
1169                         return DRM_ERR(EAGAIN);
1170                 }
1171
1172
1173                 /* Dispatch the indirect buffer.
1174                  */
1175                 buffer = (u32*)((char*)dev_priv->buffers->handle + buf->offset);
1176                 dwords = size / 4;
1177                 buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
1178                 buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1179                              RADEON_GMC_BRUSH_NONE |
1180                              (format << 8) |
1181                              RADEON_GMC_SRC_DATATYPE_COLOR |
1182                              RADEON_ROP3_S |
1183                              RADEON_DP_SRC_SOURCE_HOST_DATA |
1184                              RADEON_GMC_CLR_CMP_CNTL_DIS |
1185                              RADEON_GMC_WR_MSK_DIS);
1186
1187                 buffer[2] = (tex->pitch << 22) | (tex->offset >> 10);
1188                 buffer[3] = 0xffffffff;
1189                 buffer[4] = 0xffffffff;
1190                 buffer[5] = (image->y << 16) | image->x;
1191                 buffer[6] = (height << 16) | image->width;
1192                 buffer[7] = dwords;
1193                 buffer += 8;
1194
1195                 if ( tex_width >= 32 ) {
1196                         /* Texture image width is larger than the minimum, so we
1197                          * can upload it directly.
1198                          */
1199                         if ( DRM_COPY_FROM_USER( buffer, data,
1200                                                  dwords * sizeof(u32) ) ) {
1201                                 DRM_ERROR( "EFAULT on data, %d dwords\n",
1202                                            dwords );
1203                                 return DRM_ERR(EFAULT);
1204                         }
1205                 } else {
1206                         /* Texture image width is less than the minimum, so we
1207                          * need to pad out each image scanline to the minimum
1208                          * width.
1209                          */
1210                         for ( i = 0 ; i < tex->height ; i++ ) {
1211                                 if ( DRM_COPY_FROM_USER( buffer, data,
1212                                                          tex_width ) ) {
1213                                         DRM_ERROR( "EFAULT on pad, %d bytes\n",
1214                                                    tex_width );
1215                                         return DRM_ERR(EFAULT);
1216                                 }
1217                                 buffer += 8;
1218                                 data += tex_width;
1219                         }
1220                 }
1221
1222                 buf->filp = filp;
1223                 buf->used = (dwords + 8) * sizeof(u32);
1224                 radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
1225                 radeon_cp_discard_buffer( dev, buf );
1226
1227                 /* Update the input parameters for next time */
1228                 image->y += height;
1229                 image->height -= height;
1230                 (const u8 *)image->data += size;
1231         } while (image->height > 0);
1232
1233         /* Flush the pixel cache after the blit completes.  This ensures
1234          * the texture data is written out to memory before rendering
1235          * continues.
1236          */
1237         BEGIN_RING( 4 );
1238         RADEON_FLUSH_CACHE();
1239         RADEON_WAIT_UNTIL_2D_IDLE();
1240         ADVANCE_RING();
1241         return 0;
1242 }
1243
1244
1245 static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
1246 {
1247         drm_radeon_private_t *dev_priv = dev->dev_private;
1248         int i;
1249         RING_LOCALS;
1250         DRM_DEBUG( "\n" );
1251
1252         BEGIN_RING( 35 );
1253
1254         OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) );
1255         OUT_RING( 0x00000000 );
1256
1257         OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) );
1258         for ( i = 0 ; i < 32 ; i++ ) {
1259                 OUT_RING( stipple[i] );
1260         }
1261
1262         ADVANCE_RING();
1263 }
1264
1265
1266 /* ================================================================
1267  * IOCTL functions
1268  */
1269
1270 int radeon_cp_clear( DRM_IOCTL_ARGS )
1271 {
1272         DRM_DEVICE;
1273         drm_radeon_private_t *dev_priv = dev->dev_private;
1274         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1275         drm_radeon_clear_t clear;
1276         drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
1277         DRM_DEBUG( "\n" );
1278
1279         LOCK_TEST_WITH_RETURN( dev, filp );
1280
1281         DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t *)data,
1282                              sizeof(clear) );
1283
1284         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1285
1286         if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
1287                 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
1288
1289         if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes,
1290                              sarea_priv->nbox * sizeof(depth_boxes[0]) ) )
1291                 return DRM_ERR(EFAULT);
1292
1293         radeon_cp_dispatch_clear( dev, &clear, depth_boxes );
1294
1295         COMMIT_RING();
1296         return 0;
1297 }
1298
1299
1300 /* Not sure why this isn't set all the time:
1301  */
1302 static int radeon_do_init_pageflip( drm_device_t *dev )
1303 {
1304         drm_radeon_private_t *dev_priv = dev->dev_private;
1305         RING_LOCALS;
1306
1307         DRM_DEBUG( "\n" );
1308
1309         BEGIN_RING( 6 );
1310         RADEON_WAIT_UNTIL_3D_IDLE();
1311         OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) );
1312         OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
1313         OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) );
1314         OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
1315         ADVANCE_RING();
1316
1317         dev_priv->page_flipping = 1;
1318         dev_priv->current_page = 0;
1319         dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
1320
1321         return 0;
1322 }
1323
1324 /* Called whenever a client dies, from DRM(release).
1325  * NOTE:  Lock isn't necessarily held when this is called!
1326  */
1327 int radeon_do_cleanup_pageflip( drm_device_t *dev )
1328 {
1329         drm_radeon_private_t *dev_priv = dev->dev_private;
1330         DRM_DEBUG( "\n" );
1331
1332         if (dev_priv->current_page != 0)
1333                 radeon_cp_dispatch_flip( dev );
1334
1335         dev_priv->page_flipping = 0;
1336         return 0;
1337 }
1338
1339 /* Swapping and flipping are different operations, need different ioctls.
1340  * They can & should be intermixed to support multiple 3d windows.
1341  */
1342 int radeon_cp_flip( DRM_IOCTL_ARGS )
1343 {
1344         DRM_DEVICE;
1345         drm_radeon_private_t *dev_priv = dev->dev_private;
1346         DRM_DEBUG( "\n" );
1347
1348         LOCK_TEST_WITH_RETURN( dev, filp );
1349
1350         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1351
1352         if (!dev_priv->page_flipping)
1353                 radeon_do_init_pageflip( dev );
1354
1355         radeon_cp_dispatch_flip( dev );
1356
1357         COMMIT_RING();
1358         return 0;
1359 }
1360
1361 int radeon_cp_swap( DRM_IOCTL_ARGS )
1362 {
1363         DRM_DEVICE;
1364         drm_radeon_private_t *dev_priv = dev->dev_private;
1365         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1366         DRM_DEBUG( "\n" );
1367
1368         LOCK_TEST_WITH_RETURN( dev, filp );
1369
1370         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1371
1372         if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
1373                 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
1374
1375         radeon_cp_dispatch_swap( dev );
1376         dev_priv->sarea_priv->ctx_owner = 0;
1377
1378         COMMIT_RING();
1379         return 0;
1380 }
1381
1382 int radeon_cp_vertex( DRM_IOCTL_ARGS )
1383 {
1384         DRM_DEVICE;
1385         drm_radeon_private_t *dev_priv = dev->dev_private;
1386         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1387         drm_device_dma_t *dma = dev->dma;
1388         drm_buf_t *buf;
1389         drm_radeon_vertex_t vertex;
1390         drm_radeon_tcl_prim_t prim;
1391
1392         LOCK_TEST_WITH_RETURN( dev, filp );
1393
1394         if ( !dev_priv ) {
1395                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1396                 return DRM_ERR(EINVAL);
1397         }
1398
1399         DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t *)data,
1400                              sizeof(vertex) );
1401
1402         DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n",
1403                    DRM_CURRENTPID,
1404                    vertex.idx, vertex.count, vertex.discard );
1405
1406         if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
1407                 DRM_ERROR( "buffer index %d (of %d max)\n",
1408                            vertex.idx, dma->buf_count - 1 );
1409                 return DRM_ERR(EINVAL);
1410         }
1411         if ( vertex.prim < 0 ||
1412              vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
1413                 DRM_ERROR( "buffer prim %d\n", vertex.prim );
1414                 return DRM_ERR(EINVAL);
1415         }
1416
1417         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1418         VB_AGE_TEST_WITH_RETURN( dev_priv );
1419
1420         buf = dma->buflist[vertex.idx];
1421
1422         if ( buf->filp != filp ) {
1423                 DRM_ERROR( "process %d using buffer owned by %p\n",
1424                            DRM_CURRENTPID, buf->filp );
1425                 return DRM_ERR(EINVAL);
1426         }
1427         if ( buf->pending ) {
1428                 DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
1429                 return DRM_ERR(EINVAL);
1430         }
1431
1432         /* Build up a prim_t record:
1433          */
1434         if (vertex.count) {
1435                 buf->used = vertex.count; /* not used? */
1436
1437                 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
1438                         radeon_emit_state( dev_priv,
1439                                            &sarea_priv->context_state,
1440                                            sarea_priv->tex_state,
1441                                            sarea_priv->dirty );
1442
1443                         sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
1444                                                RADEON_UPLOAD_TEX1IMAGES |
1445                                                RADEON_UPLOAD_TEX2IMAGES |
1446                                                RADEON_REQUIRE_QUIESCENCE);
1447                 }
1448
1449                 prim.start = 0;
1450                 prim.finish = vertex.count; /* unused */
1451                 prim.prim = vertex.prim;
1452                 prim.numverts = vertex.count;
1453                 prim.vc_format = dev_priv->sarea_priv->vc_format;
1454
1455                 radeon_cp_dispatch_vertex( dev, buf, &prim,
1456                                            dev_priv->sarea_priv->boxes,
1457                                            dev_priv->sarea_priv->nbox );
1458         }
1459
1460         if (vertex.discard) {
1461                 radeon_cp_discard_buffer( dev, buf );
1462         }
1463
1464         COMMIT_RING();
1465         return 0;
1466 }
1467
1468 int radeon_cp_indices( DRM_IOCTL_ARGS )
1469 {
1470         DRM_DEVICE;
1471         drm_radeon_private_t *dev_priv = dev->dev_private;
1472         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1473         drm_device_dma_t *dma = dev->dma;
1474         drm_buf_t *buf;
1475         drm_radeon_indices_t elts;
1476         drm_radeon_tcl_prim_t prim;
1477         int count;
1478
1479         LOCK_TEST_WITH_RETURN( dev, filp );
1480
1481         if ( !dev_priv ) {
1482                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1483                 return DRM_ERR(EINVAL);
1484         }
1485
1486         DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t *)data,
1487                              sizeof(elts) );
1488
1489         DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n",
1490                    DRM_CURRENTPID,
1491                    elts.idx, elts.start, elts.end, elts.discard );
1492
1493         if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
1494                 DRM_ERROR( "buffer index %d (of %d max)\n",
1495                            elts.idx, dma->buf_count - 1 );
1496                 return DRM_ERR(EINVAL);
1497         }
1498         if ( elts.prim < 0 ||
1499              elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
1500                 DRM_ERROR( "buffer prim %d\n", elts.prim );
1501                 return DRM_ERR(EINVAL);
1502         }
1503
1504         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1505         VB_AGE_TEST_WITH_RETURN( dev_priv );
1506
1507         buf = dma->buflist[elts.idx];
1508
1509         if ( buf->filp != filp ) {
1510                 DRM_ERROR( "process %d using buffer owned by %p\n",
1511                            DRM_CURRENTPID, buf->filp );
1512                 return DRM_ERR(EINVAL);
1513         }
1514         if ( buf->pending ) {
1515                 DRM_ERROR( "sending pending buffer %d\n", elts.idx );
1516                 return DRM_ERR(EINVAL);
1517         }
1518
1519         count = (elts.end - elts.start) / sizeof(u16);
1520         elts.start -= RADEON_INDEX_PRIM_OFFSET;
1521
1522         if ( elts.start & 0x7 ) {
1523                 DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
1524                 return DRM_ERR(EINVAL);
1525         }
1526         if ( elts.start < buf->used ) {
1527                 DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
1528                 return DRM_ERR(EINVAL);
1529         }
1530
1531         buf->used = elts.end;
1532
1533         if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
1534                 radeon_emit_state( dev_priv,
1535                                    &sarea_priv->context_state,
1536                                    sarea_priv->tex_state,
1537                                    sarea_priv->dirty );
1538
1539                 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
1540                                        RADEON_UPLOAD_TEX1IMAGES |
1541                                        RADEON_UPLOAD_TEX2IMAGES |
1542                                        RADEON_REQUIRE_QUIESCENCE);
1543         }
1544
1545
1546         /* Build up a prim_t record:
1547          */
1548         prim.start = elts.start;
1549         prim.finish = elts.end;
1550         prim.prim = elts.prim;
1551         prim.offset = 0;        /* offset from start of dma buffers */
1552         prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
1553         prim.vc_format = dev_priv->sarea_priv->vc_format;
1554
1555         radeon_cp_dispatch_indices( dev, buf, &prim,
1556                                    dev_priv->sarea_priv->boxes,
1557                                    dev_priv->sarea_priv->nbox );
1558         if (elts.discard) {
1559                 radeon_cp_discard_buffer( dev, buf );
1560         }
1561
1562         COMMIT_RING();
1563         return 0;
1564 }
1565
1566 int radeon_cp_texture( DRM_IOCTL_ARGS )
1567 {
1568         DRM_DEVICE;
1569         drm_radeon_private_t *dev_priv = dev->dev_private;
1570         drm_radeon_texture_t tex;
1571         drm_radeon_tex_image_t image;
1572         int ret;
1573
1574         LOCK_TEST_WITH_RETURN( dev, filp );
1575
1576         DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t *)data, sizeof(tex) );
1577
1578         if ( tex.image == NULL ) {
1579                 DRM_ERROR( "null texture image!\n" );
1580                 return DRM_ERR(EINVAL);
1581         }
1582
1583         if ( DRM_COPY_FROM_USER( &image,
1584                              (drm_radeon_tex_image_t *)tex.image,
1585                              sizeof(image) ) )
1586                 return DRM_ERR(EFAULT);
1587
1588         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1589         VB_AGE_TEST_WITH_RETURN( dev_priv );
1590
1591         ret = radeon_cp_dispatch_texture( filp, dev, &tex, &image );
1592
1593         COMMIT_RING();
1594         return ret;
1595 }
1596
1597 int radeon_cp_stipple( DRM_IOCTL_ARGS )
1598 {
1599         DRM_DEVICE;
1600         drm_radeon_private_t *dev_priv = dev->dev_private;
1601         drm_radeon_stipple_t stipple;
1602         u32 mask[32];
1603
1604         LOCK_TEST_WITH_RETURN( dev, filp );
1605
1606         DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t *)data,
1607                              sizeof(stipple) );
1608
1609         if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) )
1610                 return DRM_ERR(EFAULT);
1611
1612         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1613
1614         radeon_cp_dispatch_stipple( dev, mask );
1615
1616         COMMIT_RING();
1617         return 0;
1618 }
1619
1620 int radeon_cp_indirect( DRM_IOCTL_ARGS )
1621 {
1622         DRM_DEVICE;
1623         drm_radeon_private_t *dev_priv = dev->dev_private;
1624         drm_device_dma_t *dma = dev->dma;
1625         drm_buf_t *buf;
1626         drm_radeon_indirect_t indirect;
1627         RING_LOCALS;
1628
1629         LOCK_TEST_WITH_RETURN( dev, filp );
1630
1631         if ( !dev_priv ) {
1632                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1633                 return DRM_ERR(EINVAL);
1634         }
1635
1636         DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t *)data,
1637                              sizeof(indirect) );
1638
1639         DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
1640                    indirect.idx, indirect.start,
1641                    indirect.end, indirect.discard );
1642
1643         if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
1644                 DRM_ERROR( "buffer index %d (of %d max)\n",
1645                            indirect.idx, dma->buf_count - 1 );
1646                 return DRM_ERR(EINVAL);
1647         }
1648
1649         buf = dma->buflist[indirect.idx];
1650
1651         if ( buf->filp != filp ) {
1652                 DRM_ERROR( "process %d using buffer owned by %p\n",
1653                            DRM_CURRENTPID, buf->filp );
1654                 return DRM_ERR(EINVAL);
1655         }
1656         if ( buf->pending ) {
1657                 DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
1658                 return DRM_ERR(EINVAL);
1659         }
1660
1661         if ( indirect.start < buf->used ) {
1662                 DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
1663                            indirect.start, buf->used );
1664                 return DRM_ERR(EINVAL);
1665         }
1666
1667         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1668         VB_AGE_TEST_WITH_RETURN( dev_priv );
1669
1670         buf->used = indirect.end;
1671
1672         /* Wait for the 3D stream to idle before the indirect buffer
1673          * containing 2D acceleration commands is processed.
1674          */
1675         BEGIN_RING( 2 );
1676
1677         RADEON_WAIT_UNTIL_3D_IDLE();
1678
1679         ADVANCE_RING();
1680
1681         /* Dispatch the indirect buffer full of commands from the
1682          * X server.  This is insecure and is thus only available to
1683          * privileged clients.
1684          */
1685         radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end );
1686         if (indirect.discard) {
1687                 radeon_cp_discard_buffer( dev, buf );
1688         }
1689
1690
1691         COMMIT_RING();
1692         return 0;
1693 }
1694
1695 int radeon_cp_vertex2( DRM_IOCTL_ARGS )
1696 {
1697         DRM_DEVICE;
1698         drm_radeon_private_t *dev_priv = dev->dev_private;
1699         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1700         drm_device_dma_t *dma = dev->dma;
1701         drm_buf_t *buf;
1702         drm_radeon_vertex2_t vertex;
1703         int i;
1704         unsigned char laststate;
1705
1706         LOCK_TEST_WITH_RETURN( dev, filp );
1707
1708         if ( !dev_priv ) {
1709                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1710                 return DRM_ERR(EINVAL);
1711         }
1712
1713         DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t *)data,
1714                              sizeof(vertex) );
1715
1716         DRM_DEBUG( "pid=%d index=%d discard=%d\n",
1717                    DRM_CURRENTPID,
1718                    vertex.idx, vertex.discard );
1719
1720         if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
1721                 DRM_ERROR( "buffer index %d (of %d max)\n",
1722                            vertex.idx, dma->buf_count - 1 );
1723                 return DRM_ERR(EINVAL);
1724         }
1725
1726         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1727         VB_AGE_TEST_WITH_RETURN( dev_priv );
1728
1729         buf = dma->buflist[vertex.idx];
1730
1731         if ( buf->filp != filp ) {
1732                 DRM_ERROR( "process %d using buffer owned by %p\n",
1733                            DRM_CURRENTPID, buf->filp );
1734                 return DRM_ERR(EINVAL);
1735         }
1736
1737         if ( buf->pending ) {
1738                 DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
1739                 return DRM_ERR(EINVAL);
1740         }
1741
1742         if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
1743                 return DRM_ERR(EINVAL);
1744
1745         for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) {
1746                 drm_radeon_prim_t prim;
1747                 drm_radeon_tcl_prim_t tclprim;
1748
1749                 if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) )
1750                         return DRM_ERR(EFAULT);
1751
1752                 if ( prim.stateidx != laststate ) {
1753                         drm_radeon_state_t state;
1754
1755                         if ( DRM_COPY_FROM_USER( &state,
1756                                              &vertex.state[prim.stateidx],
1757                                              sizeof(state) ) )
1758                                 return DRM_ERR(EFAULT);
1759
1760                         radeon_emit_state2( dev_priv, &state );
1761
1762                         laststate = prim.stateidx;
1763                 }
1764
1765                 tclprim.start = prim.start;
1766                 tclprim.finish = prim.finish;
1767                 tclprim.prim = prim.prim;
1768                 tclprim.vc_format = prim.vc_format;
1769
1770                 if ( prim.prim & RADEON_PRIM_WALK_IND ) {
1771                         tclprim.offset = prim.numverts * 64;
1772                         tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
1773
1774                         radeon_cp_dispatch_indices( dev, buf, &tclprim,
1775                                                     sarea_priv->boxes,
1776                                                     sarea_priv->nbox);
1777                 } else {
1778                         tclprim.numverts = prim.numverts;
1779                         tclprim.offset = 0; /* not used */
1780
1781                         radeon_cp_dispatch_vertex( dev, buf, &tclprim,
1782                                                    sarea_priv->boxes,
1783                                                    sarea_priv->nbox);
1784                 }
1785
1786                 if (sarea_priv->nbox == 1)
1787                         sarea_priv->nbox = 0;
1788         }
1789
1790         if ( vertex.discard ) {
1791                 radeon_cp_discard_buffer( dev, buf );
1792         }
1793
1794         COMMIT_RING();
1795         return 0;
1796 }
1797
1798
1799 static int radeon_emit_packets(
1800         drm_radeon_private_t *dev_priv,
1801         drm_radeon_cmd_header_t header,
1802         drm_radeon_cmd_buffer_t *cmdbuf )
1803 {
1804         int id = (int)header.packet.packet_id;
1805         int sz, reg;
1806         int *data = (int *)cmdbuf->buf;
1807         RING_LOCALS;
1808
1809         if (id >= RADEON_MAX_STATE_PACKETS)
1810                 return DRM_ERR(EINVAL);
1811
1812         sz = packet[id].len;
1813         reg = packet[id].start;
1814
1815         if (sz * sizeof(int) > cmdbuf->bufsz)
1816                 return DRM_ERR(EINVAL);
1817
1818         BEGIN_RING(sz+1);
1819         OUT_RING( CP_PACKET0( reg, (sz-1) ) );
1820         OUT_RING_USER_TABLE( data, sz );
1821         ADVANCE_RING();
1822
1823         cmdbuf->buf += sz * sizeof(int);
1824         cmdbuf->bufsz -= sz * sizeof(int);
1825         return 0;
1826 }
1827
1828 static __inline__ int radeon_emit_scalars(
1829         drm_radeon_private_t *dev_priv,
1830         drm_radeon_cmd_header_t header,
1831         drm_radeon_cmd_buffer_t *cmdbuf )
1832 {
1833         int sz = header.scalars.count;
1834         int *data = (int *)cmdbuf->buf;
1835         int start = header.scalars.offset;
1836         int stride = header.scalars.stride;
1837         RING_LOCALS;
1838
1839         BEGIN_RING( 3+sz );
1840         OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
1841         OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
1842         OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
1843         OUT_RING_USER_TABLE( data, sz );
1844         ADVANCE_RING();
1845         cmdbuf->buf += sz * sizeof(int);
1846         cmdbuf->bufsz -= sz * sizeof(int);
1847         return 0;
1848 }
1849
1850 /* God this is ugly
1851  */
1852 static __inline__ int radeon_emit_scalars2(
1853         drm_radeon_private_t *dev_priv,
1854         drm_radeon_cmd_header_t header,
1855         drm_radeon_cmd_buffer_t *cmdbuf )
1856 {
1857         int sz = header.scalars.count;
1858         int *data = (int *)cmdbuf->buf;
1859         int start = ((unsigned int)header.scalars.offset) + 0x100;
1860         int stride = header.scalars.stride;
1861         RING_LOCALS;
1862
1863         BEGIN_RING( 3+sz );
1864         OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
1865         OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
1866         OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
1867         OUT_RING_USER_TABLE( data, sz );
1868         ADVANCE_RING();
1869         cmdbuf->buf += sz * sizeof(int);
1870         cmdbuf->bufsz -= sz * sizeof(int);
1871         return 0;
1872 }
1873
1874 static __inline__ int radeon_emit_vectors(
1875         drm_radeon_private_t *dev_priv,
1876         drm_radeon_cmd_header_t header,
1877         drm_radeon_cmd_buffer_t *cmdbuf )
1878 {
1879         int sz = header.vectors.count;
1880         int *data = (int *)cmdbuf->buf;
1881         int start = header.vectors.offset;
1882         int stride = header.vectors.stride;
1883         RING_LOCALS;
1884
1885         BEGIN_RING( 3+sz );
1886         OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) );
1887         OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
1888         OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) );
1889         OUT_RING_USER_TABLE( data, sz );
1890         ADVANCE_RING();
1891
1892         cmdbuf->buf += sz * sizeof(int);
1893         cmdbuf->bufsz -= sz * sizeof(int);
1894         return 0;
1895 }
1896
1897
1898 static int radeon_emit_packet3( drm_device_t *dev,
1899                                 drm_radeon_cmd_buffer_t *cmdbuf )
1900 {
1901         drm_radeon_private_t *dev_priv = dev->dev_private;
1902         int cmdsz, tmp;
1903         int *cmd = (int *)cmdbuf->buf;
1904         RING_LOCALS;
1905
1906
1907         DRM_DEBUG("\n");
1908
1909         if (DRM_GET_USER_UNCHECKED( tmp, &cmd[0]))
1910                 return DRM_ERR(EFAULT);
1911
1912         cmdsz = 2 + ((tmp & RADEON_CP_PACKET_COUNT_MASK) >> 16);
1913
1914         if ((tmp & 0xc0000000) != RADEON_CP_PACKET3 ||
1915             cmdsz * 4 > cmdbuf->bufsz)
1916                 return DRM_ERR(EINVAL);
1917
1918         BEGIN_RING( cmdsz );
1919         OUT_RING_USER_TABLE( cmd, cmdsz );
1920         ADVANCE_RING();
1921
1922         cmdbuf->buf += cmdsz * 4;
1923         cmdbuf->bufsz -= cmdsz * 4;
1924         return 0;
1925 }
1926
1927
1928 static int radeon_emit_packet3_cliprect( drm_device_t *dev,
1929                                          drm_radeon_cmd_buffer_t *cmdbuf,
1930                                          int orig_nbox )
1931 {
1932         drm_radeon_private_t *dev_priv = dev->dev_private;
1933         drm_clip_rect_t box;
1934         int cmdsz, tmp;
1935         int *cmd = (int *)cmdbuf->buf;
1936         drm_clip_rect_t *boxes = cmdbuf->boxes;
1937         int i = 0;
1938         RING_LOCALS;
1939
1940         DRM_DEBUG("\n");
1941
1942         if (DRM_GET_USER_UNCHECKED( tmp, &cmd[0]))
1943                 return DRM_ERR(EFAULT);
1944
1945         cmdsz = 2 + ((tmp & RADEON_CP_PACKET_COUNT_MASK) >> 16);
1946
1947         if ((tmp & 0xc0000000) != RADEON_CP_PACKET3 ||
1948             cmdsz * 4 > cmdbuf->bufsz)
1949                 return DRM_ERR(EINVAL);
1950
1951         if (!orig_nbox)
1952                 goto out;
1953
1954         do {
1955                 if ( i < cmdbuf->nbox ) {
1956                         if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
1957                                 return DRM_ERR(EFAULT);
1958                         /* FIXME The second and subsequent times round
1959                          * this loop, send a WAIT_UNTIL_3D_IDLE before
1960                          * calling emit_clip_rect(). This fixes a
1961                          * lockup on fast machines when sending
1962                          * several cliprects with a cmdbuf, as when
1963                          * waving a 2D window over a 3D
1964                          * window. Something in the commands from user
1965                          * space seems to hang the card when they're
1966                          * sent several times in a row. That would be
1967                          * the correct place to fix it but this works
1968                          * around it until I can figure that out - Tim
1969                          * Smith */
1970                         if ( i ) {
1971                                 BEGIN_RING( 2 );
1972                                 RADEON_WAIT_UNTIL_3D_IDLE();
1973                                 ADVANCE_RING();
1974                         }
1975                         radeon_emit_clip_rect( dev_priv, &box );
1976                 }
1977
1978                 BEGIN_RING( cmdsz );
1979                 OUT_RING_USER_TABLE( cmd, cmdsz );
1980                 ADVANCE_RING();
1981
1982         } while ( ++i < cmdbuf->nbox );
1983         if (cmdbuf->nbox == 1)
1984                 cmdbuf->nbox = 0;
1985
1986  out:
1987         cmdbuf->buf += cmdsz * 4;
1988         cmdbuf->bufsz -= cmdsz * 4;
1989         return 0;
1990 }
1991
1992
1993 static int radeon_emit_wait( drm_device_t *dev, int flags )
1994 {
1995         drm_radeon_private_t *dev_priv = dev->dev_private;
1996         RING_LOCALS;
1997
1998         DRM_DEBUG("%s: %x\n", __FUNCTION__, flags);
1999         switch (flags) {
2000         case RADEON_WAIT_2D:
2001                 BEGIN_RING( 2 );
2002                 RADEON_WAIT_UNTIL_2D_IDLE();
2003                 ADVANCE_RING();
2004                 break;
2005         case RADEON_WAIT_3D:
2006                 BEGIN_RING( 2 );
2007                 RADEON_WAIT_UNTIL_3D_IDLE();
2008                 ADVANCE_RING();
2009                 break;
2010         case RADEON_WAIT_2D|RADEON_WAIT_3D:
2011                 BEGIN_RING( 2 );
2012                 RADEON_WAIT_UNTIL_IDLE();
2013                 ADVANCE_RING();
2014                 break;
2015         default:
2016                 return DRM_ERR(EINVAL);
2017         }
2018
2019         return 0;
2020 }
2021
2022 int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2023 {
2024         DRM_DEVICE;
2025         drm_radeon_private_t *dev_priv = dev->dev_private;
2026         drm_device_dma_t *dma = dev->dma;
2027         drm_buf_t *buf = 0;
2028         int idx;
2029         drm_radeon_cmd_buffer_t cmdbuf;
2030         drm_radeon_cmd_header_t header;
2031         int orig_nbox;
2032
2033         LOCK_TEST_WITH_RETURN( dev, filp );
2034
2035         if ( !dev_priv ) {
2036                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
2037                 return DRM_ERR(EINVAL);
2038         }
2039
2040         DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t *)data,
2041                              sizeof(cmdbuf) );
2042
2043         RING_SPACE_TEST_WITH_RETURN( dev_priv );
2044         VB_AGE_TEST_WITH_RETURN( dev_priv );
2045
2046
2047         if (DRM_VERIFYAREA_READ( cmdbuf.buf, cmdbuf.bufsz ))
2048                 return DRM_ERR(EFAULT);
2049
2050         if (cmdbuf.nbox &&
2051             DRM_VERIFYAREA_READ(cmdbuf.boxes,
2052                          cmdbuf.nbox * sizeof(drm_clip_rect_t)))
2053                 return DRM_ERR(EFAULT);
2054
2055         orig_nbox = cmdbuf.nbox;
2056
2057         while ( cmdbuf.bufsz >= sizeof(header) ) {
2058
2059                 if (DRM_GET_USER_UNCHECKED( header.i, (int *)cmdbuf.buf )) {
2060                         DRM_ERROR("__get_user %p\n", cmdbuf.buf);
2061                         return DRM_ERR(EFAULT);
2062                 }
2063
2064                 cmdbuf.buf += sizeof(header);
2065                 cmdbuf.bufsz -= sizeof(header);
2066
2067                 switch (header.header.cmd_type) {
2068                 case RADEON_CMD_PACKET:
2069                         DRM_DEBUG("RADEON_CMD_PACKET\n");
2070                         if (radeon_emit_packets( dev_priv, header, &cmdbuf )) {
2071                                 DRM_ERROR("radeon_emit_packets failed\n");
2072                                 return DRM_ERR(EINVAL);
2073                         }
2074                         break;
2075
2076                 case RADEON_CMD_SCALARS:
2077                         DRM_DEBUG("RADEON_CMD_SCALARS\n");
2078                         if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) {
2079                                 DRM_ERROR("radeon_emit_scalars failed\n");
2080                                 return DRM_ERR(EINVAL);
2081                         }
2082                         break;
2083
2084                 case RADEON_CMD_VECTORS:
2085                         DRM_DEBUG("RADEON_CMD_VECTORS\n");
2086                         if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) {
2087                                 DRM_ERROR("radeon_emit_vectors failed\n");
2088                                 return DRM_ERR(EINVAL);
2089                         }
2090                         break;
2091
2092                 case RADEON_CMD_DMA_DISCARD:
2093                         DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
2094                         idx = header.dma.buf_idx;
2095                         if ( idx < 0 || idx >= dma->buf_count ) {
2096                                 DRM_ERROR( "buffer index %d (of %d max)\n",
2097                                            idx, dma->buf_count - 1 );
2098                                 return DRM_ERR(EINVAL);
2099                         }
2100
2101                         buf = dma->buflist[idx];
2102                         if ( buf->filp != filp || buf->pending ) {
2103                                 DRM_ERROR( "bad buffer %p %p %d\n",
2104                                            buf->filp, filp, buf->pending);
2105                                 return DRM_ERR(EINVAL);
2106                         }
2107
2108                         radeon_cp_discard_buffer( dev, buf );
2109                         break;
2110
2111                 case RADEON_CMD_PACKET3:
2112                         DRM_DEBUG("RADEON_CMD_PACKET3\n");
2113                         if (radeon_emit_packet3( dev, &cmdbuf )) {
2114                                 DRM_ERROR("radeon_emit_packet3 failed\n");
2115                                 return DRM_ERR(EINVAL);
2116                         }
2117                         break;
2118
2119                 case RADEON_CMD_PACKET3_CLIP:
2120                         DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
2121                         if (radeon_emit_packet3_cliprect( dev, &cmdbuf, orig_nbox )) {
2122                                 DRM_ERROR("radeon_emit_packet3_clip failed\n");
2123                                 return DRM_ERR(EINVAL);
2124                         }
2125                         break;
2126
2127                 case RADEON_CMD_SCALARS2:
2128                         DRM_DEBUG("RADEON_CMD_SCALARS2\n");
2129                         if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) {
2130                                 DRM_ERROR("radeon_emit_scalars2 failed\n");
2131                                 return DRM_ERR(EINVAL);
2132                         }
2133                         break;
2134
2135                 case RADEON_CMD_WAIT:
2136                         DRM_DEBUG("RADEON_CMD_WAIT\n");
2137                         if (radeon_emit_wait( dev, header.wait.flags )) {
2138                                 DRM_ERROR("radeon_emit_wait failed\n");
2139                                 return DRM_ERR(EINVAL);
2140                         }
2141                         break;
2142                 default:
2143                         DRM_ERROR("bad cmd_type %d at %p\n",
2144                                   header.header.cmd_type,
2145                                   cmdbuf.buf - sizeof(header));
2146                         return DRM_ERR(EINVAL);
2147                 }
2148         }
2149
2150
2151         DRM_DEBUG("DONE\n");
2152         COMMIT_RING();
2153         return 0;
2154 }
2155
2156
2157
2158 int radeon_cp_getparam( DRM_IOCTL_ARGS )
2159 {
2160         DRM_DEVICE;
2161         drm_radeon_private_t *dev_priv = dev->dev_private;
2162         drm_radeon_getparam_t param;
2163         int value;
2164
2165         if ( !dev_priv ) {
2166                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
2167                 return DRM_ERR(EINVAL);
2168         }
2169
2170         DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t *)data,
2171                              sizeof(param) );
2172
2173         DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
2174
2175         switch( param.param ) {
2176         case RADEON_PARAM_AGP_BUFFER_OFFSET:
2177                 value = dev_priv->agp_buffers_offset;
2178                 break;
2179         case RADEON_PARAM_LAST_FRAME:
2180                 dev_priv->stats.last_frame_reads++;
2181                 value = GET_SCRATCH( 0 );
2182                 break;
2183         case RADEON_PARAM_LAST_DISPATCH:
2184                 value = GET_SCRATCH( 1 );
2185                 break;
2186         case RADEON_PARAM_LAST_CLEAR:
2187                 dev_priv->stats.last_clear_reads++;
2188                 value = GET_SCRATCH( 2 );
2189                 break;
2190         case RADEON_PARAM_IRQ_NR:
2191                 value = dev->irq;
2192                 break;
2193         case RADEON_PARAM_AGP_BASE:
2194                 value = dev_priv->agp_vm_start;
2195                 break;
2196         case RADEON_PARAM_REGISTER_HANDLE:
2197                 value = dev_priv->mmio_offset;
2198                 break;
2199         case RADEON_PARAM_STATUS_HANDLE:
2200                 value = dev_priv->ring_rptr_offset;
2201                 break;
2202         case RADEON_PARAM_SAREA_HANDLE:
2203                 /* The lock is the first dword in the sarea. */
2204                 value = (int)dev->lock.hw_lock;
2205                 break;
2206         case RADEON_PARAM_AGP_TEX_HANDLE:
2207                 value = dev_priv->agp_textures_offset;
2208                 break;
2209         default:
2210                 return DRM_ERR(EINVAL);
2211         }
2212
2213         if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
2214                 DRM_ERROR( "copy_to_user\n" );
2215                 return DRM_ERR(EFAULT);
2216         }
2217
2218         return 0;
2219 }