sys/dev/misc/pcic/i82365reg.h

   1 /*      $NetBSD: i82365reg.h,v 1.3 1998/12/20 17:53:28 nathanw Exp $    */
   2 /* $FreeBSD: src/sys/dev/pcic/i82365reg.h,v 1.3.2.4 2001/07/09 07:19:58 imp Exp $ */
   3
   4 /*
   5  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Marc Horowitz.
  18  * 4. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /*
  34  * All information is from the intel 82365sl PC Card Interface Controller
  35  * (PCIC) data sheet, marked "preliminary".  Order number 290423-002, January
  36  * 1993.
  37  */
  38
  39 #define PCIC_IOSIZE             2
  40
  41 #define PCIC_REG_INDEX          0
  42 #define PCIC_REG_DATA           1
  43
  44 /*
  45  * I/o ports
  46  */
  47 #define PCIC_INDEX0             0x3e0
  48
  49 /*
  50  * The PCIC allows two chips to share the same address.  In order not to run
  51  * afoul of the netbsd device model, this driver will treat those chips as
  52  * the same device.
  53  */
  54
  55 #define PCIC_CHIP0_BASE         0x00
  56 #define PCIC_CHIP1_BASE         0x80
  57
  58 /* Each PCIC chip can drive two sockets */
  59
  60 #define PCIC_SOCKETA_INDEX      0x00
  61 #define PCIC_SOCKETB_INDEX      0x40
  62
  63 /* general setup registers */
  64
  65 #define PCIC_IDENT                              0x00    /* RO */
  66 #define PCIC_IDENT_IFTYPE_MASK                  0xC0
  67 #define PCIC_IDENT_IFTYPE_IO_ONLY               0x00
  68 #define PCIC_IDENT_IFTYPE_MEM_ONLY              0x40
  69 #define PCIC_IDENT_IFTYPE_MEM_AND_IO            0x80
  70 #define PCIC_IDENT_IFTYPE_RESERVED              0xC0
  71 #define PCIC_IDENT_ZERO                         0x30
  72 #define PCIC_IDENT_REV_MASK                     0x0F
  73 #define PCIC_IDENT_REV_I82365SLR0               0x02
  74 #define PCIC_IDENT_REV_I82365SLR1               0x03
  75
  76 #define PCIC_IF_STATUS                          0x01    /* RO */
  77 #define PCIC_IF_STATUS_GPI                      0x80 /* General Purpose Input */
  78 #define PCIC_IF_STATUS_POWERACTIVE              0x40
  79 #define PCIC_IF_STATUS_READY                    0x20 /* really READY/!BUSY */
  80 #define PCIC_IF_STATUS_MEM_WP                   0x10
  81 #define PCIC_IF_STATUS_CARDDETECT_MASK          0x0C
  82 #define PCIC_IF_STATUS_CARDDETECT_PRESENT       0x0C
  83 #define PCIC_IF_STATUS_BATTERY_MASK             0x03
  84 #define PCIC_IF_STATUS_BATTERY_DEAD1            0x00
  85 #define PCIC_IF_STATUS_BATTERY_DEAD2            0x01
  86 #define PCIC_IF_STATUS_BATTERY_WARNING          0x02
  87 #define PCIC_IF_STATUS_BATTERY_GOOD             0x03
  88
  89 #define PCIC_PWRCTL                             0x02    /* RW */
  90 #define PCIC_PWRCTL_OE                          0x80    /* output enable */
  91 #define PCIC_PWRCTL_DISABLE_RESETDRV            0x40
  92 #define PCIC_PWRCTL_AUTOSWITCH_ENABLE           0x20
  93 #define PCIC_PWRCTL_PWR_ENABLE                  0x10
  94 #define PCIC_PWRCTL_VPP2_MASK                   0x0C
  95 /* XXX these are a little unclear from the data sheet */
  96 #define PCIC_PWRCTL_VPP2_RESERVED               0x0C
  97 #define PCIC_PWRCTL_VPP2_EN1                    0x08
  98 #define PCIC_PWRCTL_VPP2_EN0                    0x04
  99 #define PCIC_PWRCTL_VPP2_ENX                    0x00
 100 #define PCIC_PWRCTL_VPP1_MASK                   0x03
 101 /* XXX these are a little unclear from the data sheet */
 102 #define PCIC_PWRCTL_VPP1_RESERVED               0x03
 103 #define PCIC_PWRCTL_VPP1_EN1                    0x02
 104 #define PCIC_PWRCTL_VPP1_EN0                    0x01
 105 #define PCIC_PWRCTL_VPP1_ENX                    0x00
 106
 107 #define PCIC_CSC                                0x04    /* RW */
 108 #define PCIC_CSC_ZERO                           0xE0
 109 #define PCIC_CSC_GPI                            0x10
 110 #define PCIC_CSC_CD                             0x08 /* Card Detect Change */
 111 #define PCIC_CSC_READY                          0x04
 112 #define PCIC_CSC_BATTWARN                       0x02
 113 #define PCIC_CSC_BATTDEAD                       0x01    /* for memory cards */
 114 #define PCIC_CSC_RI                             0x01    /* for i/o cards */
 115
 116 #define PCIC_ADDRWIN_ENABLE                     0x06    /* RW */
 117 #define PCIC_ADDRWIN_ENABLE_IO1                 0x80
 118 #define PCIC_ADDRWIN_ENABLE_IO0                 0x40
 119 #define PCIC_ADDRWIN_ENABLE_MEMCS16             0x20    /* rtfds if you care */
 120 #define PCIC_ADDRWIN_ENABLE_MEM4                0x10
 121 #define PCIC_ADDRWIN_ENABLE_MEM3                0x08
 122 #define PCIC_ADDRWIN_ENABLE_MEM2                0x04
 123 #define PCIC_ADDRWIN_ENABLE_MEM1                0x02
 124 #define PCIC_ADDRWIN_ENABLE_MEM0                0x01
 125
 126 #define PCIC_CARD_DETECT                        0x16    /* RW */
 127 #define PCIC_CARD_DETECT_RESERVED               0xC0
 128 #define PCIC_CARD_DETECT_SW_INTR                0x20
 129 #define PCIC_CARD_DETECT_RESUME_ENABLE          0x10
 130 #define PCIC_CARD_DETECT_GPI_TRANSCTL           0x08
 131 #define PCIC_CARD_DETECT_GPI_ENABLE             0x04
 132 #define PCIC_CARD_DETECT_CFGRST_ENABLE          0x02
 133 #define PCIC_CARD_DETECT_MEMDLY_INHIBIT         0x01
 134
 135 /* interrupt registers */
 136
 137 #define PCIC_INTR                               0x03    /* RW */
 138 #define PCIC_INTR_RI_ENABLE                     0x80
 139 #define PCIC_INTR_RESET                         0x40    /* active low (zero) */
 140 #define PCIC_INTR_CARDTYPE_MASK                 0x20
 141 #define PCIC_INTR_CARDTYPE_IO                   0x20
 142 #define PCIC_INTR_CARDTYPE_MEM                  0x00
 143 #define PCIC_INTR_ENABLE                        0x10
 144 #define PCIC_INTR_IRQ_MASK                      0x0F
 145 #define PCIC_INTR_IRQ_SHIFT                     0
 146 #define PCIC_INTR_IRQ_NONE                      0x00
 147 #define PCIC_INTR_IRQ_RESERVED1                 0x01
 148 #define PCIC_INTR_IRQ_RESERVED2                 0x02
 149 #define PCIC_INTR_IRQ3                          0x03
 150 #define PCIC_INTR_IRQ4                          0x04
 151 #define PCIC_INTR_IRQ5                          0x05
 152 #define PCIC_INTR_IRQ_RESERVED6                 0x06
 153 #define PCIC_INTR_IRQ7                          0x07
 154 #define PCIC_INTR_IRQ_RESERVED8                 0x08
 155 #define PCIC_INTR_IRQ9                          0x09
 156 #define PCIC_INTR_IRQ10                         0x0A
 157 #define PCIC_INTR_IRQ11                         0x0B
 158 #define PCIC_INTR_IRQ12                         0x0C
 159 #define PCIC_INTR_IRQ_RESERVED13                0x0D
 160 #define PCIC_INTR_IRQ14                         0x0E
 161 #define PCIC_INTR_IRQ15                         0x0F
 162
 163 #define PCIC_INTR_IRQ_VALIDMASK                 0xDEB8 /* 1101 1110 1011 1000 */
 164
 165 #define PCIC_CSC_INTR                           0x05    /* RW */
 166 #define PCIC_CSC_INTR_IRQ_MASK                  0xF0
 167 #define PCIC_CSC_INTR_IRQ_SHIFT                 4
 168 #define PCIC_CSC_INTR_IRQ_NONE                  0x00
 169 #define PCIC_CSC_INTR_IRQ_RESERVED1             0x10
 170 #define PCIC_CSC_INTR_IRQ_RESERVED2             0x20
 171 #define PCIC_CSC_INTR_IRQ3                      0x30
 172 #define PCIC_CSC_INTR_IRQ4                      0x40
 173 #define PCIC_CSC_INTR_IRQ5                      0x50
 174 #define PCIC_CSC_INTR_IRQ_RESERVED6             0x60
 175 #define PCIC_CSC_INTR_IRQ7                      0x70
 176 #define PCIC_CSC_INTR_IRQ_RESERVED8             0x80
 177 #define PCIC_CSC_INTR_IRQ9                      0x90
 178 #define PCIC_CSC_INTR_IRQ10                     0xA0
 179 #define PCIC_CSC_INTR_IRQ11                     0xB0
 180 #define PCIC_CSC_INTR_IRQ12                     0xC0
 181 #define PCIC_CSC_INTR_IRQ_RESERVED13            0xD0
 182 #define PCIC_CSC_INTR_IRQ14                     0xE0
 183 #define PCIC_CSC_INTR_IRQ15                     0xF0
 184 #define PCIC_CSC_INTR_CD_ENABLE                 0x08
 185 #define PCIC_CSC_INTR_READY_ENABLE              0x04
 186 #define PCIC_CSC_INTR_BATTWARN_ENABLE           0x02
 187 #define PCIC_CSC_INTR_BATTDEAD_ENABLE           0x01    /* for memory cards */
 188 #define PCIC_CSC_INTR_RI_ENABLE                 0x01    /* for I/O cards */
 189
 190 #define PCIC_CSC_INTR_IRQ_VALIDMASK             0xDEB8 /* 1101 1110 1011 1000 */
 191
 192 /* I/O registers */
 193
 194 #define PCIC_IO_WINS                            2
 195
 196 #define PCIC_IOCTL                              0x07    /* RW */
 197 #define PCIC_IOCTL_IO1_WAITSTATE                0x80
 198 #define PCIC_IOCTL_IO1_ZEROWAIT                 0x40
 199 #define PCIC_IOCTL_IO1_IOCS16SRC_MASK           0x20
 200 #define PCIC_IOCTL_IO1_IOCS16SRC_CARD           0x20
 201 #define PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE       0x00
 202 #define PCIC_IOCTL_IO1_DATASIZE_MASK            0x10
 203 #define PCIC_IOCTL_IO1_DATASIZE_16BIT           0x10
 204 #define PCIC_IOCTL_IO1_DATASIZE_8BIT            0x00
 205 #define PCIC_IOCTL_IO0_WAITSTATE                0x08
 206 #define PCIC_IOCTL_IO0_ZEROWAIT                 0x04
 207 #define PCIC_IOCTL_IO0_IOCS16SRC_MASK           0x02
 208 #define PCIC_IOCTL_IO0_IOCS16SRC_CARD           0x02
 209 #define PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE       0x00
 210 #define PCIC_IOCTL_IO0_DATASIZE_MASK            0x01
 211 #define PCIC_IOCTL_IO0_DATASIZE_16BIT           0x01
 212 #define PCIC_IOCTL_IO0_DATASIZE_8BIT            0x00
 213
 214 #define PCIC_IOADDR0_START_LSB                  0x08
 215 #define PCIC_IOADDR0_START_MSB                  0x09
 216 #define PCIC_IOADDR0_STOP_LSB                   0x0A
 217 #define PCIC_IOADDR0_STOP_MSB                   0x0B
 218 #define PCIC_IOADDR1_START_LSB                  0x0C
 219 #define PCIC_IOADDR1_START_MSB                  0x0D
 220 #define PCIC_IOADDR1_STOP_LSB                   0x0E
 221 #define PCIC_IOADDR1_STOP_MSB                   0x0F
 222
 223 /* memory registers */
 224
 225 /*
 226  * memory window addresses refer to bits A23-A12 of the ISA system memory
 227  * address.  This is a shift of 12 bits.  The LSB contains A19-A12, and the
 228  * MSB contains A23-A20, plus some other bits.
 229  */
 230
 231 #define PCIC_MEM_WINS                           5
 232
 233 #define PCIC_MEM_SHIFT                          12
 234 #define PCIC_MEM_PAGESIZE                       (1<<PCIC_MEM_SHIFT)
 235
 236 #define PCIC_SYSMEM_ADDRX_SHIFT                         PCIC_MEM_SHIFT
 237 #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK       0x80
 238 #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT      0x80
 239 #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT       0x00
 240 #define PCIC_SYSMEM_ADDRX_START_MSB_ZEROWAIT            0x40
 241 #define PCIC_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK        0x30
 242 #define PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK           0x0F
 243
 244 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK            0xC0
 245 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT0                0x00
 246 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT1                0x40
 247 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2                0x80
 248 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT3                0xC0
 249 #define PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK            0x0F
 250
 251 /*
 252  * The card side of a memory mapping consists of bits A19-A12 of the card
 253  * memory address in the LSB, and A25-A20 plus some other bits in the MSB.
 254  * Again, the shift is 12 bits.
 255  */
 256
 257 #define PCIC_CARDMEM_ADDRX_SHIFT                PCIC_MEM_SHIFT
 258 #define PCIC_CARDMEM_ADDRX_MSB_WP               0x80
 259 #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_MASK   0x40
 260 #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR   0x40
 261 #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON 0x00
 262 #define PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK        0x3F
 263
 264 #define PCIC_SYSMEM_ADDR0_START_LSB             0x10
 265 #define PCIC_SYSMEM_ADDR0_START_MSB             0x11
 266 #define PCIC_SYSMEM_ADDR0_STOP_LSB              0x12
 267 #define PCIC_SYSMEM_ADDR0_STOP_MSB              0x13
 268
 269 #define PCIC_CARDMEM_ADDR0_LSB                  0x14
 270 #define PCIC_CARDMEM_ADDR0_MSB                  0x15
 271
 272 /* #define      PCIC_RESERVED                   0x17 */
 273
 274 #define PCIC_SYSMEM_ADDR1_START_LSB             0x18
 275 #define PCIC_SYSMEM_ADDR1_START_MSB             0x19
 276 #define PCIC_SYSMEM_ADDR1_STOP_LSB              0x1A
 277 #define PCIC_SYSMEM_ADDR1_STOP_MSB              0x1B
 278
 279 #define PCIC_CARDMEM_ADDR1_LSB                  0x1C
 280 #define PCIC_CARDMEM_ADDR1_MSB                  0x1D
 281
 282 #define PCIC_SYSMEM_ADDR2_START_LSB             0x20
 283 #define PCIC_SYSMEM_ADDR2_START_MSB             0x21
 284 #define PCIC_SYSMEM_ADDR2_STOP_LSB              0x22
 285 #define PCIC_SYSMEM_ADDR2_STOP_MSB              0x23
 286
 287 #define PCIC_CARDMEM_ADDR2_LSB                  0x24
 288 #define PCIC_CARDMEM_ADDR2_MSB                  0x25
 289
 290 /* #define      PCIC_RESERVED                   0x26 */
 291 /* #define      PCIC_RESERVED                   0x27 */
 292
 293 #define PCIC_SYSMEM_ADDR3_START_LSB             0x28
 294 #define PCIC_SYSMEM_ADDR3_START_MSB             0x29
 295 #define PCIC_SYSMEM_ADDR3_STOP_LSB              0x2A
 296 #define PCIC_SYSMEM_ADDR3_STOP_MSB              0x2B
 297
 298 #define PCIC_CARDMEM_ADDR3_LSB                  0x2C
 299 #define PCIC_CARDMEM_ADDR3_MSB                  0x2D
 300
 301 /* #define      PCIC_RESERVED                   0x2E */
 302 /* #define      PCIC_RESERVED                   0x2F */
 303
 304 #define PCIC_SYSMEM_ADDR4_START_LSB             0x30
 305 #define PCIC_SYSMEM_ADDR4_START_MSB             0x31
 306 #define PCIC_SYSMEM_ADDR4_STOP_LSB              0x32
 307 #define PCIC_SYSMEM_ADDR4_STOP_MSB              0x33
 308
 309 #define PCIC_CARDMEM_ADDR4_LSB                  0x34
 310 #define PCIC_CARDMEM_ADDR4_MSB                  0x35
 311
 312 /* #define      PCIC_RESERVED                   0x36 */
 313 /* #define      PCIC_RESERVED                   0x37 */
 314 /* #define      PCIC_RESERVED                   0x38 */
 315 /* #define      PCIC_RESERVED                   0x39 */
 316 /* #define      PCIC_RESERVED                   0x3A */
 317 /* #define      PCIC_RESERVED                   0x3B */
 318 /* #define      PCIC_RESERVED                   0x3C */
 319 /* #define      PCIC_RESERVED                   0x3D */
 320 /* #define      PCIC_RESERVED                   0x3E */
 321 /* #define      PCIC_RESERVED                   0x3F */
 322
 323 /* cardbus extensions - memory window page registers */
 324
 325 #define PCIC_MEMREG_WIN_SHIFT                   24
 326 #define PCIC_SYSMEM_ADDR0_WIN                   0x40
 327 #define PCIC_SYSMEM_ADDR1_WIN                   0x41
 328 #define PCIC_SYSMEM_ADDR2_WIN                   0x42
 329 #define PCIC_SYSMEM_ADDR3_WIN                   0x43
 330 #define PCIC_SYSMEM_ADDR4_WIN                   0x44
 331
 332 /* vendor-specific registers */
 333
 334 #define PCIC_INTEL_GLOBAL_CTL                   0x1E    /* RW */
 335 #define PCIC_INTEL_GLOBAL_CTL_RESERVED          0xF0
 336 #define PCIC_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE 0x08
 337 #define PCIC_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK  0x04
 338 #define PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE   0x02
 339 #define PCIC_INTEL_GLOBAL_CTL_POWERDOWN         0x01
 340
 341 #define PCIC_CIRRUS_MISC_CTL_2                  0x1E
 342 #define PCIC_CIRRUS_MISC_CTL_2_SUSPEND          0x04
 343
 344 #define PCIC_CIRRUS_CHIP_INFO                   0x1F
 345 #define PCIC_CIRRUS_CHIP_INFO_CHIP_ID           0xC0
 346 #define PCIC_CIRRUS_CHIP_INFO_SLOTS             0x20
 347 #define PCIC_CIRRUS_CHIP_INFO_REV               0x1F
 348
 349 #define PCIC_CIRRUS_EXTENDED_INDEX              0x2E
 350 #define PCIC_CIRRUS_EXTENDED_DATA               0x2F
 351 #define PCIC_CIRRUS_EXT_CONTROL_1               0x03
 352 #define PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK 0x18
 353
 354 /* Plug and play */
 355 #define PCIC_PNP_ACTIONTEC      0x1802A904      /* AEI0218 */
 356 #define PCIC_PNP_IBM3765        0x65374d24      /* IBM3765 */
 357 #define PCIC_PNP_82365          0x000ED041      /* PNP0E00 */
 358 #define PCIC_PNP_CL_PD6720      0x010ED041      /* PNP0E01 */
 359 #define PCIC_PNP_VLSI_82C146    0x020ED041      /* PNP0E02 */
 360 #define PCIC_PNP_82365_CARDBUS  0x030ED041      /* PNP0E03 */
 361 #define PCIC_PNP_SCM_SWAPBOX    0x69046d4c      /* SMC0469 */
 362
 363 /* C-Bus PnP Definitions */
 364 #define PCIC_NEC_PC9801_102     0x9180a3b8      /* NEC8091 PC-9801-102 */
 365 #define PCIC_NEC_PC9821RA_E01   0x2181a3b8      /* NEC8121 PC-9821RA-E01 */