sys/net/i4b/layer1/ifpi2/i4b_ifpi2_pci.c

   1 /*
   2  *   Copyright (c) 2001 Gary Jennejohn. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpi2_pci.c: AVM Fritz!Card PCI hardware driver
  34  *      --------------------------------------------------
  35  *
  36  *      $Id$
  37  *
  38  * $FreeBSD: src/sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c,v 1.6.2.2 2002/05/15 08:12:42 gj Exp $
  39  *
  40  *      last edit-date: [Fri Jan 12 17:01:26 2001]
  41  *
  42  *---------------------------------------------------------------------------*/
  43
  44 #include "ifpi2.h"
  45 #include "opt_i4b.h"
  46 #include "pci.h"
  47
  48 #if (NIFPI2 > 0) && (NPCI > 0)
  49
  50 #include <sys/param.h>
  51 #include <sys/kernel.h>
  52 #include <sys/systm.h>
  53 #include <sys/mbuf.h>
  54
  55 #include <machine/bus.h>
  56 #include <sys/bus.h>
  57 #include <sys/rman.h>
  58
  59 #include <pci/pcireg.h>
  60 #include <pci/pcivar.h>
  61
  62 #include <sys/socket.h>
  63 #include <net/if.h>
  64
  65 #include <machine/i4b_debug.h>
  66 #include <machine/i4b_ioctl.h>
  67 #include <machine/i4b_trace.h>
  68
  69 #include <i4b/include/i4b_global.h>
  70 #include <i4b/include/i4b_mbuf.h>
  71
  72 #include <i4b/layer1/i4b_l1.h>
  73 #include <i4b/layer1/isic/i4b_isic.h>
  74 /*#include <i4b/layer1/isic/i4b_isac.h>*/
  75 #include <i4b/layer1/isic/i4b_hscx.h>
  76
  77 #include <i4b/layer1/ifpi2/i4b_ifpi2_ext.h>
  78 #include <i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h>
  79
  80 #define PCI_AVMA1_VID 0x1244
  81 #define PCI_AVMA1_V2_DID 0x0e00
  82
  83 /* prototypes */
  84 static void avma1pp2_disable(device_t);
  85
  86 static void avma1pp2_intr(void *);
  87 static void hscx_write_reg(int, u_int, struct l1_softc *);
  88 static u_char hscx_read_reg(int, struct l1_softc *);
  89 static u_int hscx_read_reg_int(int, struct l1_softc *);
  90 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  91 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  92 static void avma1pp2_hscx_int_handler(struct l1_softc *);
  93 static void avma1pp2_hscx_intr(int, u_int, struct l1_softc *);
  94 static void avma1pp2_init_linktab(struct l1_softc *);
  95 static void avma1pp2_bchannel_setup(int, int, int, int);
  96 static void avma1pp2_bchannel_start(int, int);
  97 static void avma1pp2_hscx_init(struct l1_softc *, int, int);
  98 static void avma1pp2_bchannel_stat(int, int, bchan_statistics_t *);
  99 static void avma1pp2_set_linktab(int, int, drvr_link_t *);
 100 static isdn_link_t * avma1pp2_ret_linktab(int, int);
 101 static int avma1pp2_pci_probe(device_t);
 102 static int avma1pp2_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
 103 int avma1pp2_attach_avma1pp(device_t);
 104 static void ifpi2_isacsx_intr(struct l1_softc *sc);
 105
 106 static device_method_t avma1pp2_pci_methods[] = {
 107         /* Device interface */
 108         DEVMETHOD(device_probe,         avma1pp2_pci_probe),
 109         DEVMETHOD(device_attach,        avma1pp2_attach_avma1pp),
 110         DEVMETHOD(device_shutdown,      avma1pp2_disable),
 111
 112         /* bus interface */
 113         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 114         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 115
 116         { 0, 0 }
 117 };
 118
 119 static driver_t avma1pp2_pci_driver = {
 120         "ifpi2-",
 121         avma1pp2_pci_methods,
 122         sizeof(struct l1_softc)
 123 };
 124
 125 static devclass_t avma1pp2_pci_devclass;
 126
 127 DRIVER_MODULE(avma1pp2, pci, avma1pp2_pci_driver, avma1pp2_pci_devclass, 0, 0);
 128
 129 /* jump table for multiplex routines */
 130
 131 struct i4b_l1mux_func avma1pp2_l1mux_func = {
 132         avma1pp2_ret_linktab,
 133         avma1pp2_set_linktab,
 134         ifpi2_mph_command_req,
 135         ifpi2_ph_data_req,
 136         ifpi2_ph_activate_req,
 137 };
 138
 139 struct l1_softc *ifpi2_scp[IFPI2_MAXUNIT];
 140
 141 /*---------------------------------------------------------------------------*
 142  *      AVM PCI Fritz!Card V. 2 special registers
 143  *---------------------------------------------------------------------------*/
 144
 145 /*
 146  *      AVM PCI Status Latch 0 read only bits
 147  */
 148 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active high */
 149 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active high */
 150 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active high */
 151 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 152 /* actually active high */
 153 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 154
 155 /*
 156  *      AVM PCI Status Latch 0 read only bits
 157  */
 158 #define ASL_TIMERRESET          0x04
 159 #define ASL_ENABLE_INT          0x08
 160
 161 /*
 162  * "HSCX" status bits
 163  */
 164 #define  HSCX_STAT_RME          0x01
 165 #define  HSCX_STAT_RDO          0x10
 166 #define  HSCX_STAT_CRCVFRRAB    0x0E
 167 #define  HSCX_STAT_CRCVFR       0x06
 168 #define  HSCX_STAT_RML_MASK     0x3f00
 169
 170 /*
 171  * "HSCX" interrupt bits
 172  */
 173 #define  HSCX_INT_XPR           0x80
 174 #define  HSCX_INT_XDU           0x40
 175 #define  HSCX_INT_RPR           0x20
 176 #define  HSCX_INT_MASK          0xE0
 177
 178 /*
 179  * "HSCX" command bits
 180  */
 181 #define  HSCX_CMD_XRS           0x80
 182 #define  HSCX_CMD_XME           0x01
 183 #define  HSCX_CMD_RRS           0x20
 184 #define  HSCX_CMD_XML_MASK      0x3f00
 185
 186 /* "HSCX" mode bits */
 187 #define HSCX_MODE_ITF_FLG       0x01
 188 #define HSCX_MODE_TRANS         0x02
 189
 190 /* offsets to various registers in the ASIC, evidently */
 191 #define  STAT0_OFFSET           0x02
 192
 193 #define  HSCX_FIFO1             0x10
 194 #define  HSCX_FIFO2             0x18
 195
 196 #define  HSCX_STAT1             0x14
 197 #define  HSCX_STAT2             0x1c
 198
 199 #define  ISACSX_INDEX           0x04
 200 #define  ISACSX_DATA            0x08
 201
 202 /*
 203  * Commands and parameters are sent to the "HSCX" as a long, but the
 204  * fields are handled as bytes.
 205  *
 206  * The long contains:
 207  *      (prot << 16)|(txl << 8)|cmd
 208  *
 209  * where:
 210  *      prot = protocol to use
 211  *      txl = transmit length
 212  *      cmd = the command to be executed
 213  *
 214  * The fields are defined as u_char in struct l1_softc.
 215  *
 216  * Macro to coalesce the byte fields into a u_int
 217  */
 218 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
 219                                         | (sc->avma1pp_prot << 16))
 220
 221 /*
 222  * to prevent deactivating the "HSCX" when both channels are active we
 223  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 224  * flag in avma1pp2_bchannel_setup upon active and cleared upon deactivation.
 225  * It is set high to allow room for new flags.
 226  */
 227 #define HSCX_AVMA1PP_ACTIVE     0x1000
 228
 229 /*---------------------------------------------------------------------------*
 230  *      AVM read fifo routines
 231  *---------------------------------------------------------------------------*/
 232
 233 static void
 234 avma1pp2_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 235 {
 236         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 237         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 238         int i;
 239
 240         switch (what) {
 241                 case ISIC_WHAT_ISAC:
 242                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, 0);
 243                         /* evidently each byte must be read as a long */
 244                         for (i = 0; i < size; i++)
 245                                 ((u_int8_t *)buf)[i] = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 246                         break;
 247                 case ISIC_WHAT_HSCXA:
 248                         hscx_read_fifo(0, buf, size, sc);
 249                         break;
 250                 case ISIC_WHAT_HSCXB:
 251                         hscx_read_fifo(1, buf, size, sc);
 252                         break;
 253         }
 254 }
 255
 256 static void
 257 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 258 {
 259         u_int32_t *ip;
 260         size_t cnt;
 261         int dataoff;
 262         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 263         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 264
 265         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 266
 267         ip = (u_int32_t *)buf;
 268         cnt = 0;
 269         /* what if len isn't a multiple of sizeof(int) and buf is */
 270         /* too small ???? */
 271         while (cnt < len)
 272         {
 273                 *ip++ = bus_space_read_4(btag, bhandle, dataoff);
 274                 cnt += 4;
 275         }
 276 }
 277
 278 /*---------------------------------------------------------------------------*
 279  *      AVM write fifo routines
 280  *---------------------------------------------------------------------------*/
 281 static void
 282 avma1pp2_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 283 {
 284         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 285         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 286         int i;
 287
 288         switch (what) {
 289                 case ISIC_WHAT_ISAC:
 290                         bus_space_write_4(btag, bhandle,  ISACSX_INDEX, 0);
 291                         /* evidently each byte must written as a long */
 292                         for (i = 0; i < size; i++)
 293                                 bus_space_write_4(btag, bhandle,  ISACSX_DATA, ((unsigned char *)buf)[i]);
 294                         break;
 295                 case ISIC_WHAT_HSCXA:
 296                         hscx_write_fifo(0, buf, size, sc);
 297                         break;
 298                 case ISIC_WHAT_HSCXB:
 299                         hscx_write_fifo(1, buf, size, sc);
 300                         break;
 301         }
 302 }
 303
 304 static void
 305 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 306 {
 307         u_int32_t *ip;
 308         size_t cnt;
 309         int dataoff;
 310         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 311         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 312         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 313
 314         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 315
 316         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 317         sc->avma1pp_txl = 0;
 318         if (Bchan->out_mbuf_cur == NULL)
 319         {
 320           if (Bchan->bprot != BPROT_NONE)
 321                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 322         }
 323         if (len != sc->sc_bfifolen)
 324                 sc->avma1pp_txl = len;
 325
 326         cnt = 0; /* borrow cnt */
 327         AVMA1PPSETCMDLONG(cnt);
 328         hscx_write_reg(chan, cnt, sc);
 329
 330         ip = (u_int32_t *)buf;
 331         cnt = 0;
 332         while (cnt < len)
 333         {
 334                 bus_space_write_4(btag, bhandle, dataoff, *ip);
 335                 ip++;
 336                 cnt += 4;
 337         }
 338 }
 339
 340 /*---------------------------------------------------------------------------*
 341  *      AVM write register routines
 342  *---------------------------------------------------------------------------*/
 343
 344 static void
 345 avma1pp2_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 346 {
 347         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 348         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 349
 350         switch (what) {
 351                 case ISIC_WHAT_ISAC:
 352                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 353                         bus_space_write_4(btag, bhandle, ISACSX_DATA, data);
 354                         break;
 355                 case ISIC_WHAT_HSCXA:
 356                         hscx_write_reg(0, data, sc);
 357                         break;
 358                 case ISIC_WHAT_HSCXB:
 359                         hscx_write_reg(1, data, sc);
 360                         break;
 361         }
 362 }
 363
 364 static void
 365 hscx_write_reg(int chan, u_int val, struct l1_softc *sc)
 366 {
 367         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 368         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 369         u_int off;
 370
 371         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 372
 373         bus_space_write_4(btag, bhandle, off, val);
 374 }
 375
 376 /*---------------------------------------------------------------------------*
 377  *      AVM read register routines
 378  *---------------------------------------------------------------------------*/
 379 static u_int8_t
 380 avma1pp2_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 381 {
 382         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 383         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 384         u_int8_t val;
 385
 386         switch (what) {
 387                 case ISIC_WHAT_ISAC:
 388                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 389                         val = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 390                         return(val);
 391                 case ISIC_WHAT_HSCXA:
 392                         return hscx_read_reg(0, sc);
 393                 case ISIC_WHAT_HSCXB:
 394                         return hscx_read_reg(1, sc);
 395         }
 396         return 0;
 397 }
 398
 399 static u_char
 400 hscx_read_reg(int chan, struct l1_softc *sc)
 401 {
 402         return(hscx_read_reg_int(chan, sc) & 0xff);
 403 }
 404
 405 /*
 406  * need to be able to return an int because the RBCH is in the 2nd
 407  * byte.
 408  */
 409 static u_int
 410 hscx_read_reg_int(int chan, struct l1_softc *sc)
 411 {
 412         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 413         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 414         u_int off;
 415
 416         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 417         return(bus_space_read_4(btag, bhandle, off));
 418 }
 419
 420 /*---------------------------------------------------------------------------*
 421  *      avma1pp2_probe - probe for a card
 422  *---------------------------------------------------------------------------*/
 423 static int
 424 avma1pp2_pci_probe(dev)
 425         device_t                dev;
 426 {
 427         u_int16_t               did, vid;
 428
 429         vid = pci_get_vendor(dev);
 430         did = pci_get_device(dev);
 431
 432         if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_V2_DID)) {
 433                 device_set_desc(dev, "AVM Fritz!Card PCI Version 2");
 434                 return(0);
 435         }
 436
 437         return(ENXIO);
 438 }
 439
 440 /*---------------------------------------------------------------------------*
 441  *      avma1pp2_attach_avma1pp - attach Fritz!Card PCI
 442  *---------------------------------------------------------------------------*/
 443 int
 444 avma1pp2_attach_avma1pp(device_t dev)
 445 {
 446         struct l1_softc *sc;
 447         u_int v;
 448         int unit, error = 0;
 449         int s;
 450         u_int16_t did, vid;
 451         void *ih = 0;
 452         bus_space_handle_t bhandle;
 453         bus_space_tag_t btag;
 454         l1_bchan_state_t *chan;
 455
 456         s = splimp();
 457
 458         vid = pci_get_vendor(dev);
 459         did = pci_get_device(dev);
 460         sc = device_get_softc(dev);
 461         unit = device_get_unit(dev);
 462         bzero(sc, sizeof(struct l1_softc));
 463
 464         /* probably not really required */
 465         if(unit > IFPI2_MAXUNIT) {
 466                 printf("ifpi2-%d: Error, unit > IFPI_MAXUNIT!\n", unit);
 467                 splx(s);
 468                 return(ENXIO);
 469         }
 470
 471         if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_V2_DID)) {
 472                 printf("ifpi2-%d: unknown device!?\n", unit);
 473                 goto fail;
 474         }
 475
 476         ifpi2_scp[unit] = sc;
 477
 478         sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
 479         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
 480                 &sc->sc_resources.io_rid[0],
 481                 0, ~0, 1, RF_ACTIVE);
 482
 483         if (sc->sc_resources.io_base[0] == NULL) {
 484                 printf("ifpi2-%d: couldn't map IO port\n", unit);
 485                 error = ENXIO;
 486                 goto fail;
 487         }
 488
 489         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 490         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 491
 492         /* Allocate interrupt */
 493         sc->sc_resources.irq_rid = 0;
 494         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 495                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 496
 497         if (sc->sc_resources.irq == NULL) {
 498                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 499                 printf("ifpi2-%d: couldn't map interrupt\n", unit);
 500                 error = ENXIO;
 501                 goto fail;
 502         }
 503
 504         error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET, avma1pp2_intr, sc, &ih);
 505
 506         if (error) {
 507                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
 508                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 509                 printf("ifpi2-%d: couldn't set up irq\n", unit);
 510                 goto fail;
 511         }
 512
 513         sc->sc_unit = unit;
 514
 515         /* end of new-bus stuff */
 516
 517         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 518
 519         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 520         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 521
 522         /* setup access routines */
 523
 524         sc->clearirq = NULL;
 525         sc->readreg = avma1pp2_read_reg;
 526         sc->writereg = avma1pp2_write_reg;
 527
 528         sc->readfifo = avma1pp2_read_fifo;
 529         sc->writefifo = avma1pp2_write_fifo;
 530
 531         /* setup card type */
 532
 533         sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI_V2;
 534
 535         /* setup IOM bus type */
 536
 537         sc->sc_bustyp = BUS_TYPE_IOM2;
 538
 539         /* set up some other miscellaneous things */
 540         sc->sc_ipac = 0;
 541         sc->sc_bfifolen = HSCX_FIFO_LEN;
 542
 543         /* reset the card */
 544         /* the Linux driver does this to clear any pending ISAC interrupts */
 545         v = 0;
 546         v = ISAC_READ(I_RMODED);
 547 #ifdef AVMA1PCI_V2_DEBUG
 548         printf("avma1pp2_attach: I_MODED %x...", v);
 549 #endif
 550         v = ISAC_READ(I_ISTAD);
 551 #ifdef AVMA1PCI_V2_DEBUG
 552         printf("avma1pp2_attach: I_ISTAD %x...", v);
 553 #endif
 554         v = ISAC_READ(I_ISTA);
 555 #ifdef AVMA1PCI_V2_DEBUG
 556         printf("avma1pp2_attach: I_ISTA %x...", v);
 557 #endif
 558         ISAC_WRITE(I_MASKD, 0xff);
 559         ISAC_WRITE(I_MASK, 0xff);
 560         /* the Linux driver does this to clear any pending HSCX interrupts */
 561         v = hscx_read_reg_int(0, sc);
 562 #ifdef AVMA1PCI_V2_DEBUG
 563         printf("avma1pp2_attach: 0 HSCX_STAT %x...", v);
 564 #endif
 565         v = hscx_read_reg_int(1, sc);
 566 #ifdef AVMA1PCI_V2_DEBUG
 567         printf("avma1pp2_attach: 1 HSCX_STAT %x\n", v);
 568 #endif
 569
 570         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET);
 571         DELAY(SEC_DELAY/100); /* 10 ms */
 572         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_ENABLE_INT);
 573         DELAY(SEC_DELAY/100); /* 10 ms */
 574
 575    /* from here to the end would normally be done in isic_pciattach */
 576
 577          printf("ifpi2-%d: ISACSX %s\n", unit, "PSB3186");
 578
 579         /* init the ISAC */
 580         ifpi2_isacsx_init(sc);
 581
 582 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 583         /* Init the channel mutexes */
 584         chan = &sc->sc_chan[HSCX_CH_A];
 585         mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp2_rx", MTX_DEF);
 586         mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp2_tx", MTX_DEF);
 587         chan = &sc->sc_chan[HSCX_CH_B];
 588         mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp2_rx", MTX_DEF);
 589         mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp2_tx", MTX_DEF);
 590 #endif
 591
 592         /* init the "HSCX" */
 593         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 594
 595         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 596
 597         /* can't use the normal B-Channel stuff */
 598         avma1pp2_init_linktab(sc);
 599
 600         /* set trace level */
 601
 602         sc->sc_trace = TRACE_OFF;
 603
 604         sc->sc_state = ISAC_IDLE;
 605
 606         sc->sc_ibuf = NULL;
 607         sc->sc_ib = NULL;
 608         sc->sc_ilen = 0;
 609
 610         sc->sc_obuf = NULL;
 611         sc->sc_op = NULL;
 612         sc->sc_ol = 0;
 613         sc->sc_freeflag = 0;
 614
 615         sc->sc_obuf2 = NULL;
 616         sc->sc_freeflag2 = 0;
 617
 618 #if defined(__FreeBSD__) && __FreeBSD__ >=3
 619         callout_handle_init(&sc->sc_T3_callout);
 620         callout_handle_init(&sc->sc_T4_callout);
 621 #endif
 622
 623         /* init higher protocol layers */
 624
 625         i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp2_l1mux_func);
 626
 627   fail:
 628         splx(s);
 629         return(error);
 630 }
 631
 632 /*
 633  * this is the real interrupt routine
 634  */
 635 static void
 636 avma1pp2_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
 637 {
 638         register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 639         int activity = -1;
 640         u_int param = 0;
 641
 642         NDBGL1(L1_H_IRQ, "%#x", stat);
 643
 644         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 645         {
 646                 chan->stat_XDU++;
 647                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 648                 /* abort the transmission */
 649                 sc->avma1pp_txl = 0;
 650                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 651                 AVMA1PPSETCMDLONG(param);
 652                 hscx_write_reg(h_chan, param, sc);
 653                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 654                 AVMA1PPSETCMDLONG(param);
 655                 hscx_write_reg(h_chan, param, sc);
 656
 657                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 658                 {
 659                         i4b_Bfreembuf(chan->out_mbuf_head);
 660                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 661                 }
 662         }
 663
 664         /*
 665          * The following is based on examination of the Linux driver.
 666          *
 667          * The logic here is different than with a "real" HSCX; all kinds
 668          * of information (interrupt/status bits) are in stat.
 669          *              HSCX_INT_RPR indicates a receive interrupt
 670          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 671          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 672          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 673          *                      CRC/framing errors are only reported in this state.
 674          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 675          *                                      CRC/framing error
 676          */
 677
 678         if(stat & HSCX_INT_RPR)
 679         {
 680                 register int fifo_data_len;
 681                 int error = 0;
 682                 /* always have to read the FIFO, so use a scratch buffer */
 683                 u_char scrbuf[HSCX_FIFO_LEN];
 684
 685                 if(stat & HSCX_STAT_RDO)
 686                 {
 687                         chan->stat_RDO++;
 688                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 689                         error++;
 690                 }
 691
 692                 /*
 693                  * check whether we're receiving data for an inactive B-channel
 694                  * and discard it. This appears to happen for telephony when
 695                  * both B-channels are active and one is deactivated. Since
 696                  * it is not really possible to deactivate the channel in that
 697                  * case (the ASIC seems to deactivate _both_ channels), the
 698                  * "deactivated" channel keeps receiving data which can lead
 699                  * to exhaustion of mbufs and a kernel panic.
 700                  *
 701                  * This is a hack, but it's the only solution I can think of
 702                  * without having the documentation for the ASIC.
 703                  * GJ - 28 Nov 1999
 704                  */
 705                  if (chan->state == HSCX_IDLE)
 706                  {
 707                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 708                         error++;
 709                  }
 710
 711                 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
 712
 713                 if(fifo_data_len == 0)
 714                         fifo_data_len = sc->sc_bfifolen;
 715
 716                 /* ALWAYS read data from HSCX fifo */
 717
 718                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 719                 chan->rxcount += fifo_data_len;
 720
 721                 /* all error conditions checked, now decide and take action */
 722
 723                 if(error == 0)
 724                 {
 725                         if(chan->in_mbuf == NULL)
 726                         {
 727                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 728                                         panic("L1 avma1pp2_hscx_intr: RME, cannot allocate mbuf!\n");
 729                                 chan->in_cbptr = chan->in_mbuf->m_data;
 730                                 chan->in_len = 0;
 731                         }
 732
 733                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 734                         {
 735                                 /* OK to copy the data */
 736                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 737                                 chan->in_cbptr += fifo_data_len;
 738                                 chan->in_len += fifo_data_len;
 739
 740                                 /* setup mbuf data length */
 741
 742                                 chan->in_mbuf->m_len = chan->in_len;
 743                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 744
 745                                 if(sc->sc_trace & TRACE_B_RX)
 746                                 {
 747                                         i4b_trace_hdr_t hdr;
 748                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 749                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 750                                         hdr.dir = FROM_NT;
 751                                         hdr.count = ++sc->sc_trace_bcount;
 752                                         MICROTIME(hdr.time);
 753                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 754                                 }
 755
 756                                 if (stat & HSCX_STAT_RME)
 757                                 {
 758                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 759                                   {
 760                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 761                                          activity = ACT_RX;
 762
 763                                          /* mark buffer ptr as unused */
 764
 765                                          chan->in_mbuf = NULL;
 766                                          chan->in_cbptr = NULL;
 767                                          chan->in_len = 0;
 768                                   }
 769                                   else
 770                                   {
 771                                                 chan->stat_CRC++;
 772                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 773                                           if (chan->in_mbuf != NULL)
 774                                           {
 775                                                   i4b_Bfreembuf(chan->in_mbuf);
 776                                                   chan->in_mbuf = NULL;
 777                                                   chan->in_cbptr = NULL;
 778                                                   chan->in_len = 0;
 779                                           }
 780                                   }
 781                                 }
 782                         } /* END enough space in mbuf */
 783                         else
 784                         {
 785                                  if(chan->bprot == BPROT_NONE)
 786                                  {
 787                                           /* setup mbuf data length */
 788
 789                                           chan->in_mbuf->m_len = chan->in_len;
 790                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 791
 792                                           if(sc->sc_trace & TRACE_B_RX)
 793                                           {
 794                                                         i4b_trace_hdr_t hdr;
 795                                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 796                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 797                                                         hdr.dir = FROM_NT;
 798                                                         hdr.count = ++sc->sc_trace_bcount;
 799                                                         MICROTIME(hdr.time);
 800                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 801                                                 }
 802
 803                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 804                                                  activity = ACT_RX;
 805
 806                                           /* move rx'd data to rx queue */
 807
 808 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 809                                           (void) IF_HANDOFF(&chan->rx_queue, chan->in_mbuf, NULL);
 810 #else
 811                                           if(!(IF_QFULL(&chan->rx_queue)))
 812                                           {
 813                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 814                                           }
 815                                           else
 816                                           {
 817                                                 i4b_Bfreembuf(chan->in_mbuf);
 818                                           }
 819 #endif
 820                                           /* signal upper layer that data are available */
 821                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 822
 823                                           /* alloc new buffer */
 824
 825                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 826                                                  panic("L1 avma1pp2_hscx_intr: RPF, cannot allocate new mbuf!\n");
 827
 828                                           /* setup new data ptr */
 829
 830                                           chan->in_cbptr = chan->in_mbuf->m_data;
 831
 832                                           /* OK to copy the data */
 833                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 834
 835                                           chan->in_cbptr += fifo_data_len;
 836                                           chan->in_len = fifo_data_len;
 837
 838                                           chan->rxcount += fifo_data_len;
 839                                         }
 840                                  else
 841                                         {
 842                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 843                                           chan->in_cbptr = chan->in_mbuf->m_data;
 844                                           chan->in_len = 0;
 845                                         }
 846                           }
 847                 } /* if(error == 0) */
 848                 else
 849                 {
 850                         /* land here for RDO */
 851                         if (chan->in_mbuf != NULL)
 852                         {
 853                                 i4b_Bfreembuf(chan->in_mbuf);
 854                                 chan->in_mbuf = NULL;
 855                                 chan->in_cbptr = NULL;
 856                                 chan->in_len = 0;
 857                         }
 858                         sc->avma1pp_txl = 0;
 859                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 860                         AVMA1PPSETCMDLONG(param);
 861                         hscx_write_reg(h_chan, param, sc);
 862                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 863                         AVMA1PPSETCMDLONG(param);
 864                         hscx_write_reg(h_chan, param, sc);
 865                 }
 866         }
 867
 868
 869         /* transmit fifo empty, new data can be written to fifo */
 870
 871         if(stat & HSCX_INT_XPR)
 872         {
 873                 /*
 874                  * for a description what is going on here, please have
 875                  * a look at isic_bchannel_start() in i4b_bchan.c !
 876                  */
 877
 878                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 879
 880                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 881                 {
 882                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 883
 884                         if(chan->out_mbuf_head == NULL)
 885                         {
 886                                 chan->state &= ~HSCX_TX_ACTIVE;
 887                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 888                         }
 889                         else
 890                         {
 891                                 chan->state |= HSCX_TX_ACTIVE;
 892                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 893                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 894                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 895
 896                                 if(sc->sc_trace & TRACE_B_TX)
 897                                 {
 898                                         i4b_trace_hdr_t hdr;
 899                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 900                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 901                                         hdr.dir = FROM_TE;
 902                                         hdr.count = ++sc->sc_trace_bcount;
 903                                         MICROTIME(hdr.time);
 904                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 905                                 }
 906
 907                                 if(chan->bprot == BPROT_NONE)
 908                                 {
 909                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 910                                                 activity = ACT_TX;
 911                                 }
 912                                 else
 913                                 {
 914                                         activity = ACT_TX;
 915                                 }
 916                         }
 917                 }
 918
 919                 avma1pp2_hscx_fifo(chan, sc);
 920         }
 921
 922         /* call timeout handling routine */
 923
 924         if(activity == ACT_RX || activity == ACT_TX)
 925                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 926 }
 927
 928 /*
 929  * this is the main routine which checks each channel and then calls
 930  * the real interrupt routine as appropriate
 931  */
 932 static void
 933 avma1pp2_hscx_int_handler(struct l1_softc *sc)
 934 {
 935         u_int stat;
 936
 937         /* has to be a u_int because the byte count is in the 2nd byte */
 938         stat = hscx_read_reg_int(0, sc);
 939         if (stat & HSCX_INT_MASK)
 940           avma1pp2_hscx_intr(0, stat, sc);
 941         stat = hscx_read_reg_int(1, sc);
 942         if (stat & HSCX_INT_MASK)
 943           avma1pp2_hscx_intr(1, stat, sc);
 944 }
 945
 946 static void
 947 avma1pp2_disable(device_t dev)
 948 {
 949         struct l1_softc *sc = device_get_softc(dev);
 950         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 951         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 952
 953         /* could still be wrong, but it seems to help */
 954         bus_space_write_1(btag, bhandle, STAT0_OFFSET, 0x00);
 955 }
 956
 957 static void
 958 avma1pp2_intr(void *xsc)
 959 {
 960         u_char stat;
 961         struct l1_softc *sc;
 962         bus_space_handle_t bhandle;
 963         bus_space_tag_t btag;
 964
 965         sc = xsc;
 966         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 967         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 968
 969         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 970         NDBGL1(L1_H_IRQ, "stat %x", stat);
 971         /* was there an interrupt from this card ? */
 972         if ((stat & ASL_IRQ_Pending) == 0)
 973                 return; /* no */
 974         /* For slow machines loop as long as an interrupt is active */
 975         for (; ((stat & ASL_IRQ_Pending) != 0) ;)
 976         {
 977                 /* interrupts are high active */
 978                 if (stat & ASL_IRQ_TIMER)
 979                         NDBGL1(L1_H_IRQ, "timer interrupt ???");
 980                 if (stat & ASL_IRQ_HSCX)
 981                 {
 982                         NDBGL1(L1_H_IRQ, "HSCX");
 983                         avma1pp2_hscx_int_handler(sc);
 984                 }
 985                 if (stat & ASL_IRQ_ISAC)
 986                 {
 987                        NDBGL1(L1_H_IRQ, "ISAC");
 988                        ifpi2_isacsx_intr(sc);
 989                 }
 990                 stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 991                 NDBGL1(L1_H_IRQ, "stat %x", stat);
 992
 993         }
 994 }
 995
 996 static void
 997 avma1pp2_hscx_init(struct l1_softc *sc, int h_chan, int activate)
 998 {
 999         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1000         u_int param = 0;
1001
1002         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1003                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1004
1005         sc->avma1pp_cmd = sc->avma1pp_prot = sc->avma1pp_txl = 0;
1006
1007         if (activate == 0)
1008         {
1009                 /* only deactivate if both channels are idle */
1010                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
1011                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
1012                 {
1013                         return;
1014                 }
1015                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1016                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1017                 AVMA1PPSETCMDLONG(param);
1018                 hscx_write_reg(h_chan, param, sc);
1019                 return;
1020         }
1021         if(chan->bprot == BPROT_RHDLC)
1022         {
1023                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1024
1025                 /* HDLC Frames, transparent mode 0 */
1026                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1027                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1028                 AVMA1PPSETCMDLONG(param);
1029                 hscx_write_reg(h_chan, param, sc);
1030                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1031                 AVMA1PPSETCMDLONG(param);
1032                 hscx_write_reg(h_chan, param, sc);
1033                 sc->avma1pp_cmd = 0;
1034         }
1035         else
1036         {
1037                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1038
1039                 /* Raw Telephony, extended transparent mode 1 */
1040                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1041                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1042                 AVMA1PPSETCMDLONG(param);
1043                 hscx_write_reg(h_chan, param, sc);
1044                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1045                 AVMA1PPSETCMDLONG(param);
1046                 hscx_write_reg(h_chan, param, sc);
1047                 sc->avma1pp_cmd = 0;
1048         }
1049 }
1050
1051 static void
1052 avma1pp2_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1053 {
1054 #ifdef __FreeBSD__
1055         struct l1_softc *sc = ifpi2_scp[unit];
1056 #else
1057         struct l1_softc *sc = isic_find_sc(unit);
1058 #endif
1059         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1060
1061         int s = SPLI4B();
1062
1063         if(activate == 0)
1064         {
1065                 /* deactivation */
1066                 chan->state = HSCX_IDLE;
1067                 avma1pp2_hscx_init(sc, h_chan, activate);
1068         }
1069
1070         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1071                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1072
1073         /* general part */
1074
1075         chan->unit = sc->sc_unit;       /* unit number */
1076         chan->channel = h_chan;         /* B channel */
1077         chan->bprot = bprot;            /* B channel protocol */
1078         chan->state = HSCX_IDLE;        /* B channel state */
1079
1080         /* receiver part */
1081
1082         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1083
1084         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1085
1086         chan->rxcount = 0;              /* reset rx counter */
1087
1088         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1089
1090         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1091         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1092         chan->in_len = 0;               /* reset mbuf data len */
1093
1094         /* transmitter part */
1095
1096         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1097
1098         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1099
1100         chan->txcount = 0;              /* reset tx counter */
1101
1102         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1103
1104         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1105         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1106         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1107         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1108
1109         if(activate != 0)
1110         {
1111                 /* activation */
1112                 avma1pp2_hscx_init(sc, h_chan, activate);
1113                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1114         }
1115
1116         splx(s);
1117 }
1118
1119 static void
1120 avma1pp2_bchannel_start(int unit, int h_chan)
1121 {
1122 #ifdef __FreeBSD__
1123         struct l1_softc *sc = ifpi2_scp[unit];
1124 #else
1125         struct l1_softc *sc = isic_find_sc(unit);
1126 #endif
1127         register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1128         int s;
1129         int activity = -1;
1130
1131         s = SPLI4B();                           /* enter critical section */
1132         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1133         {
1134                 splx(s);
1135                 return;                         /* yes, leave */
1136         }
1137
1138         /* get next mbuf from queue */
1139
1140         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1141
1142         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1143         {
1144                 splx(s);                        /* leave critical section */
1145                 return;                         /* yes, exit */
1146         }
1147
1148         /* init current mbuf values */
1149
1150         chan->out_mbuf_cur = chan->out_mbuf_head;
1151         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1152         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1153
1154         /* activity indicator for timeout handling */
1155
1156         if(chan->bprot == BPROT_NONE)
1157         {
1158                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1159                         activity = ACT_TX;
1160         }
1161         else
1162         {
1163                 activity = ACT_TX;
1164         }
1165
1166         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1167
1168         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1169         {
1170                 i4b_trace_hdr_t hdr;
1171                 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1172                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1173                 hdr.dir = FROM_TE;
1174                 hdr.count = ++sc->sc_trace_bcount;
1175                 MICROTIME(hdr.time);
1176                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1177         }
1178
1179         avma1pp2_hscx_fifo(chan, sc);
1180
1181         /* call timeout handling routine */
1182
1183         if(activity == ACT_RX || activity == ACT_TX)
1184                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1185
1186         splx(s);
1187 }
1188
1189 /*---------------------------------------------------------------------------*
1190  *      return the address of isic drivers linktab
1191  *---------------------------------------------------------------------------*/
1192 static isdn_link_t *
1193 avma1pp2_ret_linktab(int unit, int channel)
1194 {
1195 #ifdef __FreeBSD__
1196         struct l1_softc *sc = ifpi2_scp[unit];
1197 #else
1198         struct l1_softc *sc = isic_find_sc(unit);
1199 #endif
1200         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1201
1202         return(&chan->isic_isdn_linktab);
1203 }
1204
1205 /*---------------------------------------------------------------------------*
1206  *      set the driver linktab in the b channel softc
1207  *---------------------------------------------------------------------------*/
1208 static void
1209 avma1pp2_set_linktab(int unit, int channel, drvr_link_t *dlt)
1210 {
1211 #ifdef __FreeBSD__
1212         struct l1_softc *sc = ifpi2_scp[unit];
1213 #else
1214         struct l1_softc *sc = isic_find_sc(unit);
1215 #endif
1216         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1217
1218         chan->isic_drvr_linktab = dlt;
1219 }
1220
1221
1222 /*---------------------------------------------------------------------------*
1223  *      initialize our local linktab
1224  *---------------------------------------------------------------------------*/
1225 static void
1226 avma1pp2_init_linktab(struct l1_softc *sc)
1227 {
1228         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1229         isdn_link_t *lt = &chan->isic_isdn_linktab;
1230
1231         /* make sure the hardware driver is known to layer 4 */
1232         /* avoid overwriting if already set */
1233         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1234         {
1235                 ctrl_types[CTRL_PASSIVE].set_linktab = i4b_l1_set_linktab;
1236                 ctrl_types[CTRL_PASSIVE].get_linktab = i4b_l1_ret_linktab;
1237         }
1238
1239         /* local setup */
1240         lt->unit = sc->sc_unit;
1241         lt->channel = HSCX_CH_A;
1242         lt->bch_config = avma1pp2_bchannel_setup;
1243         lt->bch_tx_start = avma1pp2_bchannel_start;
1244         lt->bch_stat = avma1pp2_bchannel_stat;
1245         lt->tx_queue = &chan->tx_queue;
1246
1247         /* used by non-HDLC data transfers, i.e. telephony drivers */
1248         lt->rx_queue = &chan->rx_queue;
1249
1250         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1251         lt->rx_mbuf = &chan->in_mbuf;
1252
1253         chan = &sc->sc_chan[HSCX_CH_B];
1254         lt = &chan->isic_isdn_linktab;
1255
1256         lt->unit = sc->sc_unit;
1257         lt->channel = HSCX_CH_B;
1258         lt->bch_config = avma1pp2_bchannel_setup;
1259         lt->bch_tx_start = avma1pp2_bchannel_start;
1260         lt->bch_stat = avma1pp2_bchannel_stat;
1261         lt->tx_queue = &chan->tx_queue;
1262
1263         /* used by non-HDLC data transfers, i.e. telephony drivers */
1264         lt->rx_queue = &chan->rx_queue;
1265
1266         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1267         lt->rx_mbuf = &chan->in_mbuf;
1268 }
1269
1270 /*
1271  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1272  */
1273 static void
1274 avma1pp2_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1275 {
1276 #ifdef __FreeBSD__
1277         struct l1_softc *sc = ifpi2_scp[unit];
1278 #else
1279         struct l1_softc *sc = isic_find_sc(unit);
1280 #endif
1281         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1282         int s;
1283
1284         s = SPLI4B();
1285
1286         bsp->outbytes = chan->txcount;
1287         bsp->inbytes = chan->rxcount;
1288
1289         chan->txcount = 0;
1290         chan->rxcount = 0;
1291
1292         splx(s);
1293 }
1294
1295 /*---------------------------------------------------------------------------*
1296  *      fill HSCX fifo with data from the current mbuf
1297  *      Put this here until it can go into i4b_hscx.c
1298  *---------------------------------------------------------------------------*/
1299 static int
1300 avma1pp2_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1301 {
1302         int len;
1303         int nextlen;
1304         int i;
1305         int cmd = 0;
1306         /* using a scratch buffer simplifies writing to the FIFO */
1307         u_char scrbuf[HSCX_FIFO_LEN];
1308
1309         len = 0;
1310
1311         /*
1312          * fill the HSCX tx fifo with data from the current mbuf. if
1313          * current mbuf holds less data than HSCX fifo length, try to
1314          * get the next mbuf from (a possible) mbuf chain. if there is
1315          * not enough data in a single mbuf or in a chain, then this
1316          * is the last mbuf and we tell the HSCX that it has to send
1317          * CRC and closing flag
1318          */
1319
1320         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1321         {
1322                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1323
1324 #ifdef NOTDEF
1325                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1326                         chan->out_mbuf_head,
1327                         chan->out_mbuf_cur,
1328                         chan->out_mbuf_cur_ptr,
1329                         chan->out_mbuf_cur_len,
1330                         len,
1331                         nextlen);
1332 #endif
1333
1334                 cmd |= HSCX_CMDR_XTF;
1335                 /* collect the data in the scratch buffer */
1336                 for (i = 0; i < nextlen; i++)
1337                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1338
1339                 len += nextlen;
1340                 chan->txcount += nextlen;
1341
1342                 chan->out_mbuf_cur_ptr += nextlen;
1343                 chan->out_mbuf_cur_len -= nextlen;
1344
1345                 if(chan->out_mbuf_cur_len == 0)
1346                 {
1347                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1348                         {
1349                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1350                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1351
1352                                 if(sc->sc_trace & TRACE_B_TX)
1353                                 {
1354                                         i4b_trace_hdr_t hdr;
1355                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1356                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1357                                         hdr.dir = FROM_TE;
1358                                         hdr.count = ++sc->sc_trace_bcount;
1359                                         MICROTIME(hdr.time);
1360                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1361                                 }
1362                         }
1363                         else
1364                         {
1365                                 if (chan->bprot != BPROT_NONE)
1366                                         cmd |= HSCX_CMDR_XME;
1367                                 i4b_Bfreembuf(chan->out_mbuf_head);
1368                                 chan->out_mbuf_head = NULL;
1369                         }
1370                 }
1371         }
1372         /* write what we have from the scratch buf to the HSCX fifo */
1373         if (len != 0)
1374                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1375         return(cmd);
1376 }
1377
1378 /*---------------------------------------------------------------------------*
1379  *      ifpi2 - ISAC interrupt routine
1380  *---------------------------------------------------------------------------*/
1381 static void
1382 ifpi2_isacsx_intr(struct l1_softc *sc)
1383 {
1384         register u_char isacsx_irq_stat;
1385
1386         for(;;)
1387         {
1388                 /* get isac irq status */
1389                 /* ISTA tells us whether it was a C/I or HDLC int. */
1390                 isacsx_irq_stat = ISAC_READ(I_ISTA);
1391
1392                 if(isacsx_irq_stat)
1393                         ifpi2_isacsx_irq(sc, isacsx_irq_stat); /* isac handler */
1394                 else
1395                         break;
1396         }
1397
1398         ISAC_WRITE(I_MASKD, 0xff);
1399         ISAC_WRITE(I_MASK, 0xff);
1400
1401         DELAY(100);
1402
1403         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1404         ISAC_WRITE(I_MASK, isacsx_imask);
1405 }
1406
1407 /*---------------------------------------------------------------------------*
1408  *      ifpi2_recover - try to recover from irq lockup
1409  *---------------------------------------------------------------------------*/
1410 void
1411 ifpi2_recover(struct l1_softc *sc)
1412 {
1413         printf("ifpi2_recover %d\n", sc->sc_unit);
1414 #if 0 /* fix me later */
1415         u_char byte;
1416
1417         /* get isac irq status */
1418
1419         byte = ISAC_READ(I_ISTA);
1420
1421         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1422
1423         if(byte & ISACSX_ISTA_EXI)
1424                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1425
1426         if(byte & ISACSX_ISTA_CISQ)
1427         {
1428                 byte = ISAC_READ(I_CIRR);
1429
1430                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1431
1432                 if(byte & ISACSX_CIRR_SQC)
1433                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1434         }
1435
1436         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISACSX_IMASK);
1437
1438         ISAC_WRITE(I_MASKD, 0xff);
1439         ISAC_WRITE(I_MASK, 0xff);
1440         DELAY(100);
1441         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1442         ISAC_WRITE(I_MASK, isacsx_imask);
1443 #endif
1444 }
1445
1446
1447 #endif /* NIFPI2 > 0 */